100302QIX - Fairchild Semiconductor

August 1989

Revised August 2000

100302 Low Power Quint 2-Input OR/NOR Gate

100302

Low Power Quint 2-Input OR/NOR Gate

General Description

The 100302 is a monolithic quint 2-input OR/NOR gate with

common enable. All in puts have 50 k Ω pull-down resistors

and all outputs are buffered.

Features

■43% power reduction of the 100102

■2000V ESD protection

■Pin/function compatible with 100102

■Voltage compensated operating range = −4.2V to −5.7V

■Available to industrial grade temperature range

(PLCC pack age only )

Ordering Code:

Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the o rdering code.

Connection Diagrams

24-Pin DIP/SOIC 28-Pin PLCC

Pin Descriptions

Order Number Package Number Package Description

100302SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

100302PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

100302QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

100302QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (−40°C to +85°C)

Pin Names Description

Dna–Dne Data Inputs

E Enable Input

Oa–OeData Outputs

Oa–OeComplem ent ary Data Outpu ts

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100302

Logic Symbol Truth Table

H = HIGH Voltage Lev el L = LOW Voltage Level

D1X D2X EOXOX

LLLLH

LLHHL

LHLHL

LHHHL

HLLHL

HLHHL

HHLHL

HHHHL

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100302

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “A bsolute Maximum Ratings” are those value s beyond whic h

the saf ety of the device cannot be gu aranteed. Th e device shou ld not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rating.

The “R ecomm ended Ope rating Co ndition s” table will define the condit ions

for actu al device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version

DC Electrical Characteristics (N ote 3)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity an d gu ardband ing c an be achi eved by d ecre asin g the al l owable syste m operating ranges. Conditi ons fo r t estin g shown i n the tables are ch o-

sen to guarante e operation under “worst case” conditions.

DIP AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

Note 4: The propag at ion delay s pec ified is for s ingle output switc hing. Del ay s m ay v ary up to 100 ps w it h m ultiple out puts switc hing.

Storage Temperature (TSTG)−65°C to +150°C

Maximum Junction Temperature (TJ)+150°C

VEE Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltage (DC) VEE to +0.5V

Output Current (DC Output HIGH) −50 mA

ESD (Note 2) ≥2000V

Case Temperature (TC)

Commercial 0°C to +85°C

Industrial −40°C to +85°C

Supply Voltage (VEE)−5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage −1025 −955 −870 mV VIN = VIH(Max) or VIL(Min) Loading with

VOL Output LOW Voltage −1830 −1705 −1620 mV 50Ω to −2.0V

VOHC Output HIGH Voltage −1035 mV VIN = VIH(Min) or VIL(Max) Loading with

VOLC Output LOW Voltage −1610 mV 50Ω to −2.0V

VIH Input HIGH V olta ge −1165 −870 mV Guaranteed HIGH Signal for All Inputs

VIL Input LOW V olta ge −1830 −1475 mV Guaranteed LOW Signal for All Inputs

IIL Input LOW Current 0.50 µAV

IN = VIL(Min)

IIH Input HIGH Current 240 µAV

IN = VIH(Max)

IEE Power Supply Current −45 −36 −20 mA Inputs OPEN

Symbol Parameter TC = 0°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

tPLH Propagation Delay 0.50 1.15 0.50 1.15 0.50 1.25 ns

tPHL Data to Output Figures 1, 2

tPLH Propagation Delay 0.70 1.90 0.70 1.90 0.80 2.00 ns (Note 4)

tPHL Enable to Output

tTLH Transition Time 0.40 1.20 0.40 1.20 0.40 1.20 ns Figures 1, 2

tTHL 20% to 80%, 80% to 20%

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100302

Commercial Version (Continued)

SOIC and PLCC AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

Note 5: The prop agation delay specif ied is for single output switching. Delays may v ary up to 100 ps w ith m ult iple outputs switc hing.

Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-

aged d evice . The sp ecificatio ns appl y to an y output s swit ching in th e sam e direc tion eithe r HIGH- to-LOW (tOSHL), or LOW-to-H IGH (tOSLH), or in opp osite

direc ti ons both H L and LH (tOST). Parameters tOST and tPS guaranteed by design.

Symbol Parameter TC = 0°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

tPLH Propagation Delay 0.50 1.05 0.50 1.05 0.50 1.15 ns

tPHL Data to Output Figures 1, 2

tPLH Propagation Delay 0.70 1.80 0.70 1.80 0.80 1.90 ns (Note 5)

tPHL Enable to Output

tTLH Transition Time 0.40 1.10 0.40 1.10 0.40 1.10 ns Figures 1, 2

tTHL 20% to 80%, 80% to 20%

tOSHL Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 250 250 250 ps (Note 6)

Data to Output Path

tOSHL Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 310 310 310 ps (Note 6)

Enable to Output Path

tOSLH Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 200 200 200 ps (Note 6)

Data to Output Path

tOSLH Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 330 330 330 ps (Note 6)

Enable to Output Path

tOST Maximum Skew Opposite Edge PLCC Only

Output-to-Output Variation 250 250 250 ps (Note 6)

Data to Output Path

tOST Maximum Skew Opposite Edge PLCC Only

Output-to-Output Variation 330 330 330 ps ((Note 6)

Enable to Output Path

tPS Maximum Skew PLCC Only

Pin (Signal) Transition Variation 200 200 200 ps (Note 6)

Data to Output Path

tPS Maximum Skew PLCC Only

Pin (Signal) Transition Variation 280 280 280 ps (Note 6)

Enable to Output Path

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100302

Industri a l Version

PLCC DC Electrical Characteristics (Note 7)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C

Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity an d gu ardband ing c an be achi eved by d ecre asin g the al l owable syste m operating ranges. Conditi ons fo r t estin g shown i n the tables are ch o-

sen to guarante e operation under the “worst case” cond it ions.

PLCC AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

Note 8: The propag at ion delay s pec ified is for s ingle output switc hing. Del ay s m ay v ary up to 200 ps w it h m ultiple out puts switc hing.

Symbol Parameter TC = −40°CT

C = 0°C to +85°CUnits Conditions

MinMaxMinMax

VOH Output HIGH Voltage −1085 −870 −1025 −870 mV VIN = VIH(Max) Loading with

VOL Output LOW Voltage −1830 −1575 −1830 −1620 or VIL(Min) 50Ω to −2.0V

VOHC Output HIGH Voltage −1095 −1035 mV VIN = VIH(Min) Loading with

VOLC Output LOW Voltage −1565 −1610 or VIL(Max) 50Ω to −2.0V

VIH Input HIGH V olta ge −1170 −870 −1165 −870 mV Guaranteed HIGH Signal for ALL Inputs

VIL Input LOW V olta ge −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal for ALL Inputs

IIL Input LOW Current 0.05 0.05 µAV

IN = VIL(Min)

IIH Input HIGH Current 300 240 µAV

IN = VIH(Max)

IEE Power Supply Current −45 −20 −45 −20 mA Inputs OPEN

Symbol Parameter TC = −40°CT

C = +25°CT

C = +85°CUnits Conditions

MinMaxMinMaxMinMax

tPLH Propagation Delay 0.40 1.05 0.50 1.05 0.50 1.15 ns Figures 1, 2

(Note 8)

tPHL Data to Output

tPLH Propagation Delay 0.70 1.80 0.70 1.80 0.80 1.90 ns

tPHL Enable to Output

tTLH Transition Time 0.30 1.1 0 0.40 1 .10 0.40 1.10 ns Figures 1, 2

tTHL 20% to 80%, 80% to 20%

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100302

Test Circuitry

Notes:

VCC, VCCA = +2V, VEE = −2.5V

L1 and L2 = equal lengt h 50Ω impedance li nes

RT = 50Ω terminator internal to scope

Decoupling 0.1 µF from GND to VCC and VEE

All unus ed out put s are loade d w it h 50Ω to G ND

CL = Fixture and stray capacita nc e ≤ 3 pF

FIGURE 1. AC Test Circuit

Switching Wavefo rms

FIGURE 2. Propagation Delay and Transition Times

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100302

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100302 Low Power Quint 2-Input OR/NOR Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syste ms are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a lif e supp ort

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.