5962-8872611LA - Atmel Corporation

Features

•Advanced, High-speed Programmable Logic Device – Superset of 22V10

– Improved Performance - 7.5 ns tPD, 95 MHz External Operation

– Enhanced Logic Flexibility

– Backward Compatible with ATV750(L) Software and Hardware

•New Flip-flop Features

–D- or T-type

–Product Term or Direct Input Pin Clocking

•High-speed Erasable Programmable Logic Devices

–7.5 ns Maximum Pin-to-pin Delay

•Highest Density Programmable Logic Available in a 24-pin Package

•Increased Logic Flexibility

–42 Array Inputs, 20 Sum Terms and 20 Flip-flops

•Enhanced Output Logic Flexibility

–All 20 Flip-flops Feed Back Internally

–10 Flip-flops are Also Available as Outputs

•Full Military, Commercial and Industrial Temperature Ranges

Logic Diagram

Description

The ATV750B(L) is twice as powerful as most other 24-pin programmable logic

devices. Increased product terms, sum terms, flip-flops and output logic configurations

translate into more usable gates. High-speed logic and uniform, predictable delays

guarantee fast in-system performance.

Device ICC, Standby

ATV750B 125 mA

ATV750BL 15 mA

Rev. 0301H–03/00

High-speed UV

Erasable

Programmable

Logic Device

ATV750B

ATV750BL

Commercial and

industrial versions

are obsolete. Please

use ATF750C.

Military versions

continue to be available,

but please do not

use for new designs.

For new military

applications,

recommend multiple

ATF22V10s.

Pin Configurations

Pin Name Function

CLK Clock

IN Logic Inputs

I/O Bi-directional Buffers

* No Internal Connection

VCC +5V Supply

(continued)

DIP/SOIC

CLK/IN

GND

VCC

I/O

PLCC/LCC

I/O

GND

I/O

CLK/IN

VCC

I/O

ATV750B(L)

Each of the ATV750B(L) 22 logic pins can be used as an

input. Ten of these can be used as inputs, outputs or bi-

directional I/O pins. Each flip-flop is individually config-

urable as either D- or T-type. Each flip-flop output is fed

back into the array independently. This allows burying of all

the sum terms and flip-flops.

There are 171 total product terms available. A variable for-

mat is used to assign between four to eight product terms

per sum term. There are two sum terms per output, provid-

ing added flexibility. Much more logic can be replaced by

this device than by any other 24-pin PLD. With 20 sum

terms and flip-flops, complex state machines are easily

implemented with logic to spare.

Product terms provide individual clocks and asynchronous

resets for each flip-flop. Each flip-flop may also be individu-

ally configured to have direct input pin controlled clocking.

Each output has its own enable product term. One product

term provides a common synchronous preset for all flip-

flops. Register preload functions are provided to simplify

testing. All registers automatically reset upon power-up.

The ATV750BL is a low-power device with speeds as fast

as 15 ns. The ATV750BL provides the optimum low-power

PLD solution, with full CMOS output levels. This device

significantly reduces total system power, thereby allowing

battery-powered operation.

Logic Options

Combinatorial Output Registered Output

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Note: 1. Minimum voltage is -0.6V DC which may under-

shoot to -2.0V for pulses of less than

20 ns.Maximum output pin voltage is VCC + 0.75V

DC which may overshoot to +7.0V for pulses of

less than 20 ns.

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin with

Respect to Ground .........................................-2.0V to +7.0V(1)

Voltage on Input Pins

with Respect to Ground

During Programming.....................................-2.0V to +14.0V(1)

Programming Voltage with

Respect to Ground .......................................-2.0V to +14.0V(1)

Integrated UV Erase Dose..............................7258 W•sec/cm2

Combined Terms Separate Terms

ATV750B(L)

Clock Mux

Output Options

Note: 1. See ordering information for valid speed and temperature combination.

DC and AC Operating Conditions(1)

Commercial

-7, -10, -15

Commercial

-25 Industrial Military

Operating Temperature 0°C - 70°C

(Ambient)

0°C - 70°C

(Ambient)

-40°C - 85°C

(Ambient)

-55°C - 125°C

(Case)

VCC Power Supply 5V ± 5% 5V ± 10% 5V ± 10% 5V ± 10%

SELECT

LOGI

CELL

CLOCK

PRODUCT

TERM

CLK

CKi

CK MUX

ATV750B(L)

Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

Input Test Waveforms and

Measurement Levels

tR, tF < 3 ns (10% to 90%)

Output Test Load

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

ILI Input Load Current VIN = -0.1V to VCC + 1V 10 µA

ILO

Output Leakage

Current VOUT = -0.1V to VCC + 0.1V 10 µA

ICC

Power Supply

Current, Standby

VCC = MAX,

VIN = MAX,

Outputs Open

B-7, -10 Com. 125 180 mA

Ind., Mil. 125 190 mA

B-15, -25 Com. 125 180 mA

Ind., Mil. 125 190 mA

BL-15 Com. 15 30 mA

Ind., Mil. 15 30 mA

IOS(1) Output Short

Circuit Current VOUT = 0.5V -120 mA

VIL Input Low Voltage 4.5 ≤ VCC ≤ 5.5V -0.6 0.8 V

VIH Input High Voltage 2.0 VCC + 0.75 V

VOL

Output Low

Voltage

VIN = VIH or VIL,

VCC = MIN

IOL = 16 mA Com., Ind. 0.5 V

IOL = 12 mA Mil. 0.5 V

IOL = 24 mA Com. 0.8 V

VOH

Output High

Voltage

VIN = VIH or VIL,

VCC = MIN

IOH = -100 µA VCC - 0.3 V

IOH = -4.0 mA 2.4 V

ATV750B(L)

AC Waveforms, Product Term Clock(1)

Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.

Note: 1. See ordering information for valid part numbers.

AC Characteristics, Product Term Clock(1)

Symbol Parameter

-7 -10 B/BL-15 B/BL-25

UnitsMin Max Min Max Min Max Min Max

tPD

Input or Feedback to

Non-Registered Output 7.5 10 15 25 ns

tEA Input to Output Enable 7.5 10 15 25 ns

tER Input to Output Disable 7.5 10 15 25 ns

tCO Clock to Output 3 7.5 4 10 5 12 6 20 ns

tCF Clock to Feedback 1 5 4 7.5 5 9 5 10 ns

tSInput Setup Time 3 4 8/12 14 ns

tSF Feedback Setup Time 3 4 7 7 ns

tHHold Time 1 2 5/7 5/7 ns

tPClock Period 7 11 14 17 ns

tWClock Width 3.5 5.5 7 8.5 ns

fMAX

External Feedback 1/(tS+tCO) 95 71 50/41 29 MHz

Internal Feedback 1/(tSF+tCF) 125 86 62 58 MHz

No Feedback 1/(tP) 142 90 71 58 MHz

tAW Asynchronous Reset Width 5 10 15 20 ns

tAR Asynchronous Reset

Recovery Time 31015 20 ns

tAP Asynchronous Reset to

Registered Output Reset 812 1525ns

tSP Setup Time, Synchronous Preset 4 7 8 15 ns

ATV750B(L)

AC Waveforms, Input Pin Clock(1)

Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.

AC Characteristics, Input Pin Clock

Symbol Parameter

-7 -10

B/BL

-15

B/BL

-25

UnitsMin Max Min Max Min Max Min Max

tPD

Input or Feedback to

Non-Registered Output 7.5 10 15 25 ns

tEA Input to Output Enable 7.5 10 15 25 ns

tER Input to Output Disable 7.5 10 15 25 ns

tCOS Clock to Output 0 6.5 0 7 0 10 0 12 ns

tCFS Clock to Feedback 0 3.5 0 5 0 5.5 0 7 ns

tSS Input Setup Time 4 5 8/12.5 9/15 ns

tSFS Feedback Setup Time 4 5 7 9 ns

tHS Hold Time 0 0 0 0 ns

tPS Clock Period 7 10 12 16 ns

tWS Clock Width 3.5 5 6 8 ns

fMAXS

External Feedback 1/(tSS+tCOS) 95 83 55/44 48/37 MHz

Internal Feedback 1/(tSFS+tCFS) 133 100 80 62 MHz

No Feedback 1/(tPS) 142 100 83 62 MHz

tAW Asynchronous Reset Width 5 10 15 20 ns

tARS

Asynchronous Reset

Recovery Time

510 15 25 ns

tAP Asynchronous Reset to

Registered Output Reset

810 15 25ns

tSPS Setup Time, Synchronous Preset 5 5/9 11 15 ns

ATV750B(L)

Functional Logic Diagram ATV750B, Upper Half

ATV750B(L)

Functional Logic Diagram ATV750B, Lower Half

ATV750B(L)

Preload of Registered Outputs

The ATV750B(L) registers are provided with circuitry to

allow loading of each register asynchronously with either a

high or a low. This feature will simplify testing since any

state can be forced into the registers to control test

sequencing. A VIH level on the I/O pin will force the register

high; a VIL will force it low, independent of the output polar-

ity. The PRELOAD state is entered by placing a 10.25V to

10.75V signal on pin 8 on DIPs, and lead 10 on SMDs.

When the clock term is pulsed high, the data on the I/O

pins is placed into the register chosen by the Select Pin.

Power-up Reset

The registers in the ATV750B(L) is designed to reset during

power-up. At a point delayed slightly from VCC crossing

VRST, all registers will be reset to the low state. The output

state will depend on the polarity of the output buffer.

This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the

uncertainty of how VCC actually rises in the system, the fol-

lowing conditions are required:

1. The VCC rise must be monotonic,

2. After reset occurs, all input and feedback setup

times must be met before driving the clock terms or

pin high, and

3. The clock pin, or signals from which clock terms are

derived, must remain stable during tPR.

Level Forced on Registered

Output Pin during PRELOAD Cycle Select Pin State Register #0 State after Cycle Register #1 State after Cycle

VIH Low High X

VIL Low Low X

VIH High X High

VIL High X Low

Parameter Description Typ Max Units

tPR Power-up Reset Time 600 1000 ns

VRST Power-up Reset Voltage 3.8 4.5 V

Pin Capacitance

f = 1 MHz, T = 25°C(1)

Typ Max Units Conditions

CIN 58 pF V

IN = 0V

COUT 68 pF V

OUT = 0V

ATV750B(L)

Using the ATV750B(L) Many Advanced

Features

The ATV750B(L) advanced flexibility packs more usable

gates into 24-pins than any other logic device. The

ATV750B(L) starts with the popular 22V10 architecture,

and add several enhanced features:

•Selectable D- and T-type Registers – Each ATV750B

flip-flop can be individually configured as either D- or T-

type. Using the T-type configuration, JK and SR flip-flops

are also easily created. These options allow more

efficient product term usage.

•Selectable Asynchronous Clocks – Each of the

ATV750B(L) flip-flops may be clocked by its own clock

product term or directly from Pin 1 (SMD Lead 2). This

removes the constraint that all registers must use the

same clock. Buried state machines, counters and

registers can all coexist in one device while running on

separate clocks. Individual flip-flop clock source

selection further allows mixing higher performance pin

clocking and flexible product term clocking within one

design.

•A Full Bank of Ten More Registers – The ATV750B

provides two flip-flops per output logic cell for a total

of 20. Each register has its own sum term, its own reset

term and its own clock term.

•Independent I/O Pin and Feedback Paths – Each I/O

pin on the ATV750B has a dedicated input path. Each of

the 20 registers has its own feedback terms into the

array as well. This feature, combined with individual

product terms for each I/O’s output enable, facilitates

true bi-directional I/O design.

Programming Software Support

As with all other Atmel PLDs, several third-party develop-

ment software products support the ATV750B(L). Several

third-party programmers support the ATV750B as well.

Additionally, the ATV750B may be programmed to perform

the ATV750(L)’s functional subset (no T-type flip-flops or

pin clocking) using the ATV750(L) JEDEC file. In this case,

the ATV750B becomes a direct replacement or speed

upgrade for the ATV750(L). The ATV750(L) programming

algorithm is different from the ATV750B algorithm. Choose

the appropriate device in your programmer menu to ensure

proper programming. Please refer to the Programmable

Logic Development Tools section for a complete PLD soft-

ware and programmer listing.

Synchronous Preset and

Asynchronous Reset

One synchronous preset line is provided for all 20 registers

in the ATV750B. The appropriate input signals to cause the

internal clocks to go to a high state must be received during

a synchronous preset. Appropriate setup and hold times

must be met, as shown in the switching waveform diagram.

An individual asynchronous reset line is provided for each

of the 20 flip-flops. Both master and slave halves of the flip-

flops are reset when the input signals received force the

internal resets high.

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying

of the ATV750B fuse patterns. Once the security fuse is

programmed, all fuses will appear programmed during

verify.

The security fuse should be programmed last, as its effect

is immediate.

Erasure Characteristics

The entire memory array of an ATV750B is erased after

exposure to ultraviolet light at a wavelength of 2537 Å.

Complete erasure is assured after a minimum of 20 min-

utes exposure using 12,000 µW/cm2 intensity lamps

spaced one inch away from the chip. Minimum erase time

for lamps at other intensity ratings can be calculated from

the minimum integrated erasure dose of 15 W•sec/cm2. To

prevent unintentional erasure, an opaque label is recom-

mended to cover the clear window on any UV-erasable

PLD which will be subjected to continuous fluorescent

indoor lighting or sunlight.

Atmel CMOS PLDs

The ATV750B utilizes an advanced 0.65-micron CMOS

EPROM technology. This technology’s state-of-art features

are the optimum combination for PLDs:

•CMOS technology provides high-speed, low-power, and

high noise immunity.

•EPROM technology is the most cos-effective method for

producing PLDs – surpassing bipolar fusible link

technology in low cost, while providing the necessary

reprogrammability.

•EPROM reprogrammability, which is 100% tested before

shipment, provides inherently better programmability and

reliability than one-time fusible PLDs.

ATV750B(L)

ATV750B(L)
13
Ordering Information
tPD
(ns)
tCOS
(ns)
Ext.
fMAXS
(MHz) Ordering Code Package Operation Range
7.5 6.5 95 ATV750B-7JC(1)
ATV750B-7PC(1)
28J
24P3
Commercial
(0°C to 70°C)
10 7 83 ATV750B-10JC(1)
ATV750B-10PC(1)
ATV750B-10SC(1)
28J
24P3
24S
Commercial
(0°C to 70°C)
ATV750B-10JI(1)
ATV750B-10PI(1)
ATV750B-10SI(1)
28J
24P3
24S
Industrial
(-40°C to 85°C)
ATV750B-10DM/883(2)
ATV750B-10LM/883(2)
24DW3
28LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
15 10 58 ATV750B-15JC(1)
ATV750B-15PC(1)
ATV750B-15SC(1)
28J
24P3
24S
Commercial
(0°C to 70°C)
ATV750B-15JI(1)
ATV750B-15PI(1)
ATV750B-15SI(1)
28J
24P3
24S
Industrial
(-40°C to 85°C)
ATV750B-15DM/883(2)
ATV750B-15LM/883(2)
24DW3
28LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
25 15 41 ATV750B-25JC(1)
ATV750B-25PC(1)
ATV750B-25SC(1)
28J
24P3
24S
Commercial
(0°C to 70°C)
ATV750B-25JI(1)
ATV750B-25PI(1)
ATV750B-25SI(1)
28J
24P3
24S
Industrial
(-40°C to 85°C)
Note: 1. Obsolete, please use ATF750C versions.
2. Continue to be available, but please do not use for new designs. For new designs recommend multiple ATF22V10s.
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
24DW3 24-lead, 0.300" Wide, Windowed, Ceramic Dual Inline Package (Cerdip)
28J 28-lead, Plastic J-leaded Chip Carrier OTP (PLCC)
28LW 28-pad, Windowed, Ceramic Leadless Chip Carrier (LCC)
24P3 24-lead, 0.300" Wide, Plastic Dual Inline Package OTP (PDIP)
24S 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline OTP (SOIC)

ATV750B(L)
14
10 7 83 5962-88726 08 LA(2)
5962-88726 08 3X(2)
24DW3
28LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
15 9 58 5962-88726 09 LA(2)
5962-88726 09 3X(2)
24DW3
28LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
15 9 92 ATV750BL-15JC(1)
ATV750BL-15PC(1)
ATV750BL-15SC(1)
28J
24P3
24S
Commercial
(0°C to 70°C)
ATV750BL-15JI(1)
ATV750BL-15PI(1)
ATV750BL-15SI(1)
28J
24P3
24S
Industrial
(-40°C to 85°C)
ATV750BL-15DM/883(2)
ATV750BL-15LM/883(2)
24DW3
28LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
25 15 37 ATV750BL-25JC(1)
ATV750BL-25PC(1)
ATV750BL-25SC(1)
28J
24P3
24S
Commercial
(0°C to 70°C)
ATV750BL-25JI17
ATV750BL-25PI(1)
ATV750BL-25SI(1)
28J
24P3
24S
Industrial
(-40°C to 85°C)
15 9 92 5962-88726 11 LX(2)
5962-88726 11 3X(2)
24DW3
28LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
Ordering Information (Continued)
tPD
(ns)
tCOS
(ns)
Ext.
fMAXS
(MHz) Ordering Code Package Operation Range
Note: 1. Obsolete, please use ATF750C versions.
2. Continue to be available, but please do not use for new designs. For new designs recommend multiple ATF22V10s.
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
24DW3 24-lead, 0.300" Wide, Windowed, Ceramic Dual Inline Package (Cerdip)
28J 28-lead, Plastic J-leaded Chip Carrier OTP (PLCC)
28LW 28-pad, Windowed, Ceramic Leadless Chip Carrier (LCC)
24P3 24-lead, 0.300" Wide, Plastic Dual Inline Package OTP (PDIP)
24S 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline OTP (SOIC)

ATV750B(L)

Packaging Information

.045(1.14) X 45°PIN NO. 1

IDENTIFY

.032(.813)

.026(.660)

.050(1.27) TYP

.300(7.62) REF SQ

.045

(

1.14

)

X 30° - 45°

.022(.559) X 45° MAX (3X)

.012(.305)

.008(.203)

.021(.533)

.013(.330)

.430(10.9)

.390(9.91)SQ

.043(1.09)

.020(.508)

.120(3.05)

.090(2.29)

.180(4.57)

.165(4.19)

.456(11.6)

.450(11.4)

.495(12.6)

.485(12.3)

*Controlling dimension: millimeters

1.27(32.3)

1.25(31.7) PIN

.266(6.76)

.250(6.35)

.090(2.29)

MAX

.005(.127)

MIN

.070(1.78)

.020(.508)

.023(.584)

.014(.356)

.065(1.65)

.040(1.02)

.325(8.26)

.300(7.62)

15 REF

.400(10.2) MAX

.012(.305)

.008(.203)

.110(2.79)

.090(2.29)

.151(3.84)

.125(3.18)

SEATING

PLANE

.200(5.06)

MAX

1.100(27.94) REF

24DW3, 24-lead, 0.300" Wide, WIndowed, Ceramic

Dual Inline Package (Cerdip)

Dimensions in Inches and (Millimeters)

MIL-STD-1835 D-9 CONFIG A

28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-018 AB

28LW, 28-pad, Windowed, Ceramic Leadless Chip

Carrier (LCC)

Dimensions in Inches and (Millimeters)*

MIL-STD-1835 C-4

24P3, 24-lead, 0.300" Wide, Plastic Dual Inline

Package (PDIP)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-001 AF

ATV750B(L)

Packaging Information

.020(.508)

.013(.330)

.299(7.60)

.291(7.39)

.420(10.7)

.393(9.98)

.105(2.67)

.092(2.34)

.050(1.27) BSC

.616(15.6)

.598(15.2)

.012(.305)

.003(.076)

.013(.330)

.009(.229)

.050(1.27)

.015(.381)

0REF

PIN 1 ID

24S, 24-lead, 0.300" Wide, Plastic Gull Wing Small

Outline (SOIC)

Dimensions in Inches and (Millimeters)

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