Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
http://www.cirrus.com DS734F5
OCT '11
CS485xx Family Data Sheet
Features
Cost-effective, High-performance 32-bit DSP
300,000,000 MAC/S (multiply accumulates per second )
Dual MAC cycles per clock
72-bit accumulators are the most accurate in the industry
24k x 32 SRAM, 2k blocks - assignable to data or program
Internal ROM contains a variety of configurable sound
enhancement feature sets
8-channel internal DMA
Internal watch-dog DSP lock-up prevention
DSP Tool Set w/ Private Keys for Protecting Customer IP
Configurable Serial Audio Inputs/ Outputs
Configurable for all input/output types
Maximum 32-bit @ 192 kHz
Supports 32-bit audio sample I/O between DSP chips
TDM input modes (multiple chan nels on same line)
192 kHz SPDIF transmitter
Multi-channel DSD direct stream digital SACD input
Supports Two Different Input Fs Sample Rates
Output can be master or slave
Dual processing path capability
Input supports dual domain slave clocking
Hardware assist time sampling for sample rate conversion
Integrated Clock Manager/PLL
Can operate from external crystal, external oscillator
Input Fs Auto Detection
Host & Boot via Serial Interface
Configurable GPIOs and External Interrupt Input
1.8V Core and a 3.3V I/O that is tolerant to 5V input
Low-power Mode
“Energy Star® Ready” in low-power mode, 268 µW in standby
Differentiating from the legacy Cirrus multi-standard, multi-channel
decoders, this new CS485xx family is still based on the same
high-performance 32-bit fixed point Digital Signal Processor core
but instead is equippe d wit h much l ess memory, tailoring it f or more
cost-eff ective applications associated with multi-channel and
virtual-channel sound enhancements. Target applications are:
Digital Telev isions
Multimedia Peripherals
iPod® Docking Stations
Automotive Head Units
Automotive Outb oard Amplifiers
HD-DVD™ and Blu-ray Disc® DVD Receivers
PC Speakers
There are also a wide variety of licensable DSP codes available
today as seen by the following examples:
Cirrus also has developed, or is developing their own royalty-free
versions of popular features sets like Cirrus Bass Manager, Cirrus
Dynamic Volume Leveler, Cirrus Original Multichannel Surround,
Cirrus Virtual Speaker & Cirrus 3D-Audio.
The CS485xx family is programmed using the Cirrus propri etary
DSP Composer™ GUI development tool. Process ing chains may be
designed using a drag-and-drop interface to place/utilize functional
macro audio DSP primitives. The end result is a software image that
is down-loaded to the DSP via serial host or serial boo t modes.
See Section 6 for ordering information.
CS485xx Block Diagram
32-bit
DSP
D
M
A
P X Y
Serial
Control 1
12 Ch PCM
Audio Out
GPIO Debug
Watchdog
TMR1
TMR2
PLL
S/PDIF
12 Ch. Audio In /
6 Ch. SACD In
CS485xx
DS734F5 2
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change
withou t n oti c e and is pr ov i de d “A S I S” wi t h out war r an ty o f a ny k i n d (ex p res s o r impl i ed ). Cus t ome r s ar e adv is ed to obtai n the latest version of relevant information to verify,
before placing orders, t hat information being relied on i s current and complete. All product s are sold subject to the t erms and co nd it io ns of sal e suppl i ed at t he ti me of or der
acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information,
including use of this information as the basis for manufacture or sal e o f an y items, or for infring ement of patents or othe r r ights of third pa rties. This docum en t is the p rop er ty
of Cirrus a nd by fu rn i shi ng thi s i nf or mati on , Cir r us gr ant s n o license, express or implied under any patents, mask work rights, copyrights , tr ad emar ks , t r a de se cr et s or ot he r
intellec tua l pr oper ty rig hts. Cirr us owns the copy ri ghts ass ociat ed wit h the i nfor mati on co nta ined h ere in and giv es co nsent for copies to be made of the information only for
use within your organization with res pect to Cirrus integrated circuit s or other product s of Cirrus. This con sent does not extend to other copying such as copying for general
distribution, adve rtisin g o r pr omotional purposes, or for creating an y wor k for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRI TICAL APPLICATIO NS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS
SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISC LAIMS AND MAKES
NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR
PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS
THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, C USTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIR ECTORS,
EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR
ARISE IN CONNECTION WITH THESE US ES .
Cirrus Logic, Cirrus , and the Cirrus Logi c logo design s, DSP Com poser, an d Cirrus Fram ework are trade marks of Cirrus Logic, Inc. All other brand and product names in this
document may be tradem arks o r service marks of their respective owne rs.
Dolby, Dolby Digitaol, Dolby Headphone, Virtual Speaker, and Pro Logic are registered trademarks of Dolby Laboratories, Inc. Supply of an implementation of Dolby
Technolog y does not convey a license no r imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation
in any finished end- user or ready-to-use fina l pro d uct. It is hereb y no tified that a li cen se for such u s e is re qu ir ed from Dolby Laboratories .
DTS and DTS Neo:6 are registered trademarks of Digital Theat er Systems, Inc. It is hereby notified that a third-party license from DTS is necessary to distribute software of
DTS in any finish ed en d- use r or rea dy- to- use final pro du ct.
SRS, Cir cle Surround and Trusurround XT are regis tered trademarks of SRS Labs, Inc. Circle Surround II i s a trademark of SRS Labs, Inc. The Circle Surround technology
is incorporated under license from SRS Labs, Inc. The Circle Surround technology rights incorporated in the CS485xx are owned by SRS Labs, a U.S. Corporation and
licensed to Cirrus Logic, Inc. Purchaser of CS485xx must sign a license for use of the chip and display of the SRS Labs trademarks. Any products incorporating the CS485xx
must be sent to SRS Labs for review. The Circle Surround technology is protected under US and foreign patents issued and/or pending. Circle Surrou nd, SRS and (O) symb ol
are trademarks of SRS Labs, Inc. in the United States and selected foreign coun tries. Neither the purchase of the CS485xx, no r the corresponding sale of audio enhancement
equipment conveys the right to sell commercialized recordings made with any SRS technology/solution. SRS Labs requires all set makers to comply with all rules and
regulations as outli ne d in the S R S Trad emark Usage Manual.
SPI is a trademark of Motorola, Inc.
I²C is a trademark of Philips Semiconductor.
iPod is a registered trad emark of Apple Computer, Inc.
HD DVD is a trade m a rk of DV D Form a t/Log o L icen sin g Corporation.
Blu-Ray Disc is a registered trademark of SONY KABUSHIKI KAISHA CORPORATION.
Energy Star is a registered trademark of the Environmental Protection Agency, a federal agency of the United States government.
3DS734F5
TABLE OF CONTENTS
1 Documentation Strategy ........................................................................................................................................... 1-5
2 Overview ..................................................................................................................................................................... 2-5
2.1 Licensing ............................................................................................................................................................ 2-5
3 Code Overlays ............................................................................................................................................................ 3-6
4 Hardware Functional Description ............................................................................................................................ 4-7
4.1 DSP Core ........................................................................................................................................................... 4-7
4.1.1 DSP Memory ............................................................................................................................................. 4-7
4.1.2 DMA Controller .......................................................................................................................................... 4-7
4.2 On-chip DSP Peripherals ...................................................................................................................................4-7
4.2.1 Digital Audio Input Port (DAI) ................... ... ... .................... ... ................... .... ... ..........................................4-7
4.2.2 Digital Audio Output Port (DAO) ................................................................................................................ 4-8
4.2.3 Serial Con tr ol Por t (I2C™ or SPI™) ................. ............. ............. ............. .......... ............. ............. ............. ...4-8
4.2.4 GPIO ......................................................................................................................................................... 4-8
4.2.5 PLL-based Clock Generator ......................................................................................................................4-8
4.2.6 Hardware Watchdog Timer ....................................................................................................................... 4-8
4.3 DSP I/O Description ...........................................................................................................................................4-8
4.3.1 Multiplexed Pins ........................................................................................................................................ 4-8
4.3.2 Termination Requirements ........................................................................................................................ 4-8
4.3.3 Pads .......................................................................................................................................................... 4-9
4.4 Application Code Security .................................................................................................................................. 4-9
5 Characteristics and Specifications .......................................................................................................................... 5-9
5.1 Absolute Maximum Ratings ................................................................................................................................ 5-9
5.2 Recommended Operations Conditions .............. ............. ............. ............. ............. ......... ............. .......................5-9
5.3 Digital DC Characteristics ...................................................................................................................................5-9
5.4 Power Supply Characteristics .. ................ ................ ................. ................ ............. ...........................................5-10
5.5 Thermal Data (48-pin LQFP) ............................................................................................................................5-10
5.6 Switching Characteristics—RESET .................................................................................................................. 5-11
5.7 Switching Characteristics—XTI ........................................................................................................................5-11
5.8 Switching Characteristics—Internal Clock ........................................................................................................5-11
5.9 Switching Characteristics—Serial Control Port–SPI Slave Mode ..................................................................... 5-12
5.10 Switching Characteristics—Serial Control Port–SPI Master Mode .................................................................5-13
5.11 Switching Characteristics— Ser ial Co nt ro l Port– I2C Slave Mode ...................................................................5-13
5.12 Switching Characteristics— Ser ial Co nt ro l Port– I2C Master Mode ................................................................. 5-14
5.13 Switching Characteristics—Digital Audio Slave Input Port .............. .... ... ... ................... .................... ..............5-15
5.14 Switching Characteristics—DSD Slave Input Port . .................... ... ... .................... ... ... ................... .................. 5-15
5.15 Switching Characteristics—Digital Audio Output (DAO ) Port .......... .... ... ................... ... .... ................... ...........5-16
6 Ordering Information ............................................................................................................................................... 6-18
7 Environmental, Manufacturing, and Handling Information ................................................................................. 7-18
8 Device Pinout Diagrams .......................................................................................................................................... 8-19
8.1 CS48520, 48-pin LQFP Pinout Diagram .......................................................................................................... 8-19
8.2 CS48540, 48-pin LQFP Pinout Diagram .......................................................................................................... 8-20
8.3 CS48560, 48-pin LQFP Pinout Diagram .......................................................................................................... 8-21
9 Package Mechanical Drawings ............................................................................................................................... 9-22
9.1 48-pin LQFP Package Drawing ........................................................................................................................ 9-22
10 Revision History ........ ... ... ... .... ... ... .................... ... ... ... ... .... ... ... .................... ... ... ... ... .... ......................................... 10-23
4DS734F5
LIST OF FIGURES
Figure 5-1. RESET Timing ......................................................................................................................................5-11
Figure 5-2. XTI Timing............................................................................................................................................. 5-11
Figure 5-3. Serial Control Port–SPI Slave Mode Timing......................................................................................... 5-12
Figure 5-4. Serial Control Port–SPI Master Mode Timing.......................................................................................5-13
Figure 5-5. Serial Control Port–I2C Slave Mode Timing..........................................................................................5-14
Figure 5-6. Serial Control Port–I2C Master Mode Timing........................................................................................5-15
Figure 5-7. Digital Audio Input (DAI) Port Timing Diagram. ... ... ... .... ... ... ... .... ... ... ... ... .... ... ................... ... .................. 5-15
Figure 5-8. Direct Stream Digital–Serial Audio Input Timing.................... .... ... ... ... ... .... ... ... ... .... ... ...........................5-15
Figure 5-9. Digital Audio Output Port Timing, Master Mode....................................................................................5-17
Figure 5-10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) .........................................5-17
Figure 8-1. CS48520, 48-pin LQFP Pinout..............................................................................................................8-19
Figure 8-2. CS48540, 48-pin LQFP Pinout..............................................................................................................8-20
Figure 8-3. CS48560, 48-pin LQFP......................................................................................................................... 8-21
Figure 9-1. 48-pin LQFP Package Drawing.............................................................................................................8-22
LIST OF TABLES
Table 1-1. CS485xx Family Related Document at ion.......................... ................... .................... ................................ 1-5
Table 3-1. Device and Firmware Selection Guide.............. ... ... ... .... ................... ... ... .................... ... ... ....................... 3-6
Table 5-1. Master Mode (Output A1 Mode)............................................................................................................. 5-16
Table 5-2. Slave Mode (Output A0 Mode)...............................................................................................................5-17
Table 6-1. Ordering Information ..............................................................................................................................6-18
Table 7-1. Environmental, Manufacturing, and Handling Information .....................................................................7-18
5DS734F5
1 Documentation Strategy
1 Documentation Strategy
The CS485xx Family Data Sheet describes the CS485 xx family of multichannel audio processors. This docu ment should
be used in conjunction with the following docum ents when evaluating or designing a system around the CS485xx family
of processors.
The scope of the CS485xx Family Data Sheet is primarily the hardware specifications of the CS485xx family of devices.
This includes hardware functionality, characteristic data, pinout, and packaging information.
The intended audience for the CS485xx Family Data Sheet is the system PCB designer, MCU programmer, and the quality
control engineer.
2 Overview
The CS485xx DSP Family is designed to provide high- performance post- processing and mixing of digital audio. The dual
clock domain provided on the PCM inputs allows for the mixing of audio streams with different sampling frequencies. The
low-power standby preser ves battery life for applications which are always o n, but not necessarily processing audio, such
as automotive audio systems.
There are three de vices comprising the CS485xx fa mily. The CS485 20, CS48540 and CS48560 are differentiated by the
number of inputs and outputs available. All DSPs support dual input clock domains and dual audio processing paths. All
DSPs are available in a 48-pin QFP package. Refer to Table 3-1 for the input, output, firmware features of each device.
2.1 Licensing
Licenses are required for all of the third party audio processing algorithms listed in Section 3. Contact your local
Cirrus Logic Sales representative for more information.
Table 1-1. CS485xx Family Related D ocumen tation
Document Name Description
CS485xx Family Data Sheet This document
CS485xx Family Hardware User’s Manual Includes detailed system design information including Typical Connection Diagrams,
Boot-Procedures, Pin Descriptions, etc.
AN298–CS485xx Family Firmware User’s Manual Includes detailed firmware design information including signal processing flow
diagrams and control API information
DSP Composer User’s Manual Includes detailed configuration and usage information for the GUI development tool.
6DS734F5
3 Code Overlays
3 Code Overlays
The suite of software a vailable for the CS485xx fa mily consists of an operating system (OS) and a library of overlays. The
overlays have been divided into three main groups called Matrix-processors, Virtualizer-processors, and Post-processors.
All software components are defined below:
1. OS/Kernel—Encompasses all non-audio processing tasks, including loading data from external memory,
processing host messages, calling audio-processing subroutines, error concealment, etc.
2. Matrix-processor—Any Mod ule that performs a matrix decode on PCM data to produce more output channels
than input channels (2n cha nnels) . Examples ar e Do lby ProLogic IIx and DTS Neo:6 . Gener ally speaking, these
modules incre as e th e nu m be r of valid ch an ne ls in the au dio I/ O buffer.
3. Virtualizer-processor—Any module that encodes PCM dat a into fewer output channels than input channe ls (n2
channels) with the effect of providing “phantom” speakers to represent the physical audio channels that were
eliminated. Examples are Dolby Headphone® and Dolby Virtual Speaker®. Generally speaking, these modules
reduce the number of valid chann els in the audio I/O buffer.
4. Post-processors—Any module that processes audio I/O buf fe r PCM data in-place after the matrix- or
virtualizer-processors. Examples are bass management, audio manager, tone control, EQ, delay,
customer-specific effects, etc.
The bulk of each overlay is stored in ROM within the CS485xx, but a small imag e is required to configure the overlays and
boot the DSP. This small image can either be stored in an external serial FLASH/EEPROM, or downloaded via a host
controller through the SPI™/I2C™ serial port.
The overlay structure reduces the time required to reconfigure the DSP when a proces sin g cha nge is requ e ste d . Each
overlay can be reloaded independ ently without disturbing th e other overla ys. For example, when a new matrix-processor
is selected, th e OS, vir tua lize r- , an d post-processors do not need to be reloaded — only the new matrix-processor (the
same is true for the other overlays).
Table 3-1 lists the firmware available based on device selection. Refer AN298, CS485xx Firmware User’s
Manual for the latest listing of application codes and Cirrus Framework™ modules available.
Table 3-1. Device and Firmware Selection Guide
Device Suggested Applicatio n Channel Count Input/Output Package
CS48520-CQZ Digital TV, port able audio docking station, portable DVD, DVD mini/
receiver, multimedia PC speakers Up to 4-channel in/4-chan nel out 48-pin QFP
CS48540-CQZ
CS48540-DQZ CS48520 features plus 8-channel car audio, DVD receiver Up to 8-channel in/8-chan nel out 48-pin QFP
CS48560-CQZ
CS48560-DQZ CS48540 features p lus 12-channel car audio, high-end digit al TV , dual
source/dual zone SACD Up to 12-channel in/12-channel out 48-pin QFP
7DS734F5
4 Hardware Functional Description
4 Hardware Functional Description
4.1 DSP Core
The CS485xx family DSPs are single-core DSP with separate X and Y data and P code memory spaces. The DSP core
is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two
multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has eigh t 72-bit accumulato rs, four X- and four
Y-data registers, and 12 index registers.
The DSP core is coupled to a flexible DMA engine. The DMA engine can move data between peripherals such as the serial
control port (SCP), digital audio input (DAI) and digital audio output (DAO), or any DSP core memory, all without the
intervention of the DSP. The DMA engine off loads data move instructions from the DSP core, leaving more MIPS available
for signal processing instructions.
CS485xx family functionality is controlled by application codes that are stored in on-board ROM or downloaded to the
CS485xx from a host controller or external serial FLASH/EEPROM.
Users can develop their applications using DSP Composer to create the processing chain and then compile the image into
a series of commands that are sent to the CS485xx through the SCP. The processing application can either load modules
(matrix-processors, virtualizers, post-proce ssors) from the DSPs on-board ROM, or custo m firmware can be downloaded
through the SCP.
The CS485xx is suitable for a variety of audio post-processing ap plications such as automotive head-ends, automotive
amplifiers, and boom boxes.
4.1.1 DSP Memory
The DSP core has its own on-chip data and program RAM and ROM and does not require external memory for
post-processing applications.
The Y-RAM and P-RAM share a single block of memory that can be configured to make Y and P equal in size, or more
memory can be allocated for Y-RAM in 2kword blocks.
4.1.2 DMA Controller
The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter:
X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start
address and increment controls. The service intervals for each DMA channel, as well as up to 6 interrupt events, are
programmable.
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI)
Each version of the CS485xx supports a different number of input channels. Refer to Table 3-1 for more details.
The DAI port suppo rts a wide variety of data input formats a t sample rates (Fs) as high as 192 kHz. The port is capable o f
accepting PCM or DSD formats. Up to 32-bit word lengths are supported. DSD is supported and internally converted to
PCM before processing. The DAI also supports a time division multiplexed (TDM) one-line data mode, that packs PCM
audio on a single d ata line (the total number possible de pends on the ratio of SCLK to LRCLK and the version of chip. For
example on the CS48520 on ly 4 ch of PCM are supported in one line mode and on the CS48560 up to 8 channels are
supported.).
The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock
domain. The sample rate o f the inpu t clo ck domain s can be d eter mined au tomatically by the DSP, off- loa ding th e task of
monitoring the SPDIF receiver from the host. A time-stamping feature allows the input data to be sample-rate converted
via software.
8DS734F5
4.3 DSP I/O Description
4.2.2 Digital Audio Output Port (DAO)
Each version of the CS485xx supports a different number of output channels. Refer to Table 3-1 for more details.
DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as 192 kHz. The port
can be configured as an independent clock domain mastered by the DSP, or as a clock slave if an external MCLK or SCLK/
LRCLK source is available. One of the serial audio pins can be re-configured as a S/PDIF transmitter that drives a biphase
encoded S/PDIF signal (data with embedd ed clock on a single line).
The DAO also supports a time division multiplexed (TDM) o ne-line data mode, th at packs multiple channels of PCM audio
on a single data line.
4.2.3 Serial Control Port (I2C™ or SPI™)
The on-chip serial control port is capable of operating as master or slave in eith er SPI™ or I2C™ modes. Master/
Slave operation is chosen by mode select pins when the CS485xx comes out of Reset. The serial clock pin can
support frequencies as high as 25 MHz in SPI mode (SPI clock speed must always be ≤ (Fdclk/2)). The CS485xx
serial control port also includes a pin for flow control of the communications interface (SCP_ BSY) and a pin to
indicate when the DSP has a message for the host (SCP_IRQ).
4.2.4 GPIO
Many of the CS485xx pe ripheral pins ar e multiplexed with GPIO. Each GPIO can be configured as an output, an input, o r
an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high.
4.2.5 PLL-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core
and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving
audio converters. The CS485 xx defaults to running from the externa l reference freq uency an d is switched to use the PLL
output after overlays have been loaded and configured , either through master boot from an external FLASH or through
host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is
selectable between 1:1 (default) or 2:1 .
4.2.6 Hardware Watchdog Timer
The CS485xx has an integrated watchdog timer that acts as a “health” monitor for the DSP. The watchdog timer must be
reset by the DSP before the counter expires, or the entire chip is reset. This peripheral ensures that the CS485xx will reset
itself in the event of a temporary system failure. In stand-alone mode (that is, no host MCU), the DSP will reboot from
external FLASH. In slave mode (that is, host MCU present) a GPIO will be used to signal the host that the watchdog has
expired and the DSP should be rebooted and re-configured.
4.3 DSP I/O Description
4.3.1 Multiplexed Pins
Many of the CS485xx family pins are multi-functional. For details on pin fu nctionality, refer to the CS485xx Hardware
User’s Manual.
4.3.2 Termination Requirements
Open-drain pins on the CS485xx must be pulled high for proper operation. Refer to the CS485xx Hardware User’s Manual
to identify which pins are open-dr ain and what value of pull-up resistor is required for proper operation.
Mode select pins in the CS485xx family are used to select the boot mode upon the rising edge from reset. A detailed
explanation of termination requirements for each co mmunication mode select pi n can be foun d in the CS485xx Hardware
User’s Manual.
9DS734F5
4.4 Application Code Security
4.3.3 Pads
The CS485xx I/Os operate from the 3.3 V supply and are 5 V to lerant.
4.4 Application Code Security
The external program code may be encrypted by the programmer to protect any intellectual property it may contain. A
secret, customer-speci fic key is used to encrypt the program code th at is to be stored external to the device. Contact your
local Cirrus representative for details.
5 Characteristics and Specifications
Note: All data sheet minimum and maximum timing parameters a re guaranteed over the rated voltage and temperatur e.
All data sheet typical parameters are measured under the following conditions: T = 25° C, CL = 20 pF,
VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.
5.1 Absolute Maximum Ratings
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not
guaranteed at these extremes.
5.2 Recommended Operations Conditions
(GNDD = GNDIO = GN DA = 0 V; all voltages with respect to 0 V)
Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.
5.3 Digital DC Characteristics
(Measurements performed under static conditions.)
Parameter Symbol Min Max Unit
DC power supplies: Core supply VDD –0.3 2.0 V
PLL supply VDDA –0.3 3.6 V
I/O supply VDDIO –0.3 3.6 V
|VDDA–VDDIO| — — 0.3 V
Input pin current, any pin except supplies Iin —±10mA
Input voltage on PLL_REF_RES Vfilt –0.3 3.6 V
Input voltage on I/O pins Vinio –0.3 5.0 V
Storage temperature Tstg –65 150 °C
Parameter Symbol Min Typ Max Unit
DC power supplies: Core supply VDD 1.71 1.8 1.89 V
PLL supply VDDA 3.13 3.3 3.46 V
I/O supply VDDIO 3.13 3.3 3.46 V
|VDDA–VDDIO| — — 0 — V
Ambient operating temperature TA——— °C
–CQZ — 0 — +70 —
–DQZ — –40 — +85 —
10 DS734F5
5.4 Power Supply Characteristi cs
5.4 Power Supply Characteristics
(Measurements performed under operating conditions)
5.5 Thermal Data (48-pin LQFP)
Parameter Symbol Min Typ Max Unit
High-level input voltage VIH 2.0 — — V
Low-level input voltage, except XTI VIL ——0.8V
Low-level input voltage, XTI VILXTI ——0.6V
Input hys teresis Vhys —0.4— V
High-level output voltage (IO = –2 mA), except XTI VOH VDDIO*0.9 — — V
Low-level output voltage (IO = 2 mA), except XTI VOL ——VDDIO*0.1V
Input leakage XTI ILXTI —— 5 µA
Input leakage current (a ll digita l pins with internal pull-up resistors enabled) ILEAK ——70µA
Parameter Min Typ Max Unit
Operational Power Supply Current:
VDD: Core and I/O operating1
1.Dependent on application firmware and DSP clock speed.
— 203 — mA
VDDA: PLL operating —8—mA
VDDIO: With most ports operating —27—mA
Total Operational Power Dissipation: — 480 — mW
Standby Power Supply Current:
VDD: Core and I/O not clocked — 100 — µA
VDDA: PLL halted —1—µA
VDDIO: All connected I/O pins 3-stated by other ICs in system — 50 — µA
Total Standby Power Dissipation — 348 — µW
Parameter Symbol Min Typ Max Unit
Junction Temperature Tj——125 °C
Thermal Resist ance (Junction to Ambient) Two-layer board1
Four-layer board2
1.Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1 oz. copper covering 20% of the top and bottom layers.
2.Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1 oz. copper covering 20% of the top and bottom layers and 0.5
oz. copper covering 90 % of the internal power plane and ground plane layers.
θja — 63.5 — °C/Watt
—54 —
Thermal Resistance (Junction to Top of Package) Two-layer board3
Four-layer board4
3.To calculate the die temperature for a given power dissipation
Tj = Ambient Temperature + [(Power Dissipation in Watts)*θja]
4.To calculate the case temperature for a given power dissipation
Tc = Tj – [(Power Dissipation in Watts)*ψjt]
ψjt — 0.70 — °C/Watt
—0.64—
11 DS734F5
5.6 Switching Characteristics—RESET
5.6 Switching Characteristics—RESET
Figure 5-1. RESET Timing
5.7 Switching Characteristics—XTI
Figure 5-2. XTI Timi ng
5.8 Switching Characteristics—Internal Clock
Parameter Symbol Min Max Unit
RESET# minimum pulse width low Trstl 1—ms
All bidirectional pins high-Z after RESET# low T rst2z — 100 ns
Configuration pins setup before RESET# high Trstsu 50 — ns
Configuration pins hold after RESET# high Trsthld 20 — ns
Parameter Symbol Min Max Unit
External Cryst al operating frequency1
1.Part characterized with the following crystal frequency values: 11.2896, 12.288, 18.432, 24.576, & 27 MH.z
Fxtal 11.2896 27 MHz
XTI period Tclki 33.3 100 ns
XTI high time Tclkih 13.3 — ns
XTI low time Tclkil 13.3 — ns
External Crystal Load Capacitance (parallel resonant)2
2.CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals that require a CL outside this range should be avoided. The
crystal oscillator circuit design should follow the crystal manufacturer’s recommendation for load capacitor selection.
CL10 18 pF
External Crystal Equivalent Series Resistance ESR — 50 Ω
Parameter Symbol Min Max Unit
Internal DCLK frequency1Fdclk ——MHz
CS4852x-CQZ
CS4854x-CQZ
CS4856x-CQZ
CS4854x-DQZ
CS4856x-DQZ
Fxtal
Fxtal
Fxtal
Fxtal
Fxtal
150
150
150
150
150
RESET#
Trst2z
Trstl
Trstsu Trsthld
HS[3:0]
All Bidirectional
Pins
tclkih tclkil
Tclki
XTI
12 DS734F5
5.9 Switching Characteristics—Serial Control Port–SPI Slave Mode
5.9 Switching Characteristics—Serial Control Port–SPI Slave Mode
Figure 5-3. Serial Control Port–SPI Slave Mode Timing
Internal DCLK period1DCLKP — — ns
CS4852x-CQZ
CS4854x-CQZ
CS4856x-CQZ
CS4854x-DQZ
CS4856x-DQZ
6.7
6.7
6.7
6.7
6.7
1/Fxtal
1/Fxtal
1/Fxtal
1/Fxtal
1/Fxtal
1.After initial power-on reset, Fdclk = Fxtal. After initial kick-start commands, the PLL is locked to max Fdclk and remains locked until the next power-on
reset.
Parameter Symbol Min Typical Max Units
SCP_CLK frequency1
1.The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the
communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of
the input data buffer. At boot the maximum speed is Fxtal/3.
fspisck ——25MHz
SCP_CS# falling to SCP_CLK rising tspicss 24 — — ns
SCP_CLK low time tspickl 20 — — ns
SCP_CLK hi gh time tspickh 20 — — ns
Setup time SCP_MOSI input tspidsu 5——ns
Hold time SCP_MOSI input tspidh 5——ns
SCP_CLK lo w to SCP_MISO output valid tspidov ——11ns
SCP_CLK fa lling to SCP_IRQ# rising tspiirqh — — 20 ns
SCP_CS# rising to SCP_IRQ# falling tspiirql 0——ns
SCP_CLK low to SCP_CS# rising tspicsh 24 — — ns
SCP_CS# rising to SCP_MISO output high-Z tspicsdz —20—ns
SCP_CLK rising to SCP_BSY# falling tspicbsyl —3*DCLKP+20— ns
Parameter Symbol Min Max Unit
SCP_BSY#
SCP_CS#
SCP_CLK
SCP_MOSI
SCP_MISO
SCP_IRQ#
012670567
tspicss
tspickl
tspickh
tspidsu tspidh tspidov
A6 A5 A0 R/W MSB LSB
MSB LSB
tspicsh
tspibsyl
tspiirql
tspiirqh
fspisck
tspicsdz
13 DS734F5
5.10 Switching Characteristics—Serial Control Port–SPI Master Mode
5.10 Switching Characteristics—Serial Control Port–SPI Master Mode
Figure 5-4. Serial Control Port–SPI Master Mode Timing
5.11 Switching Characteristics—Serial Control Port–I2C Slave Mode
Parameter Symbol Min Typical Max Units
SCP_CLK frequency1
1.The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the
communication port may be limited by the firmware application.
fspisck ——F
xtal/22
2.See Section 5.7.
MHz
SCP_CS# falling to SCP_CLK rising3
3.SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter.
tspicss — 11*DCLKP + (SCP_CLK PERIOD)/2 — ns
SCP_CLK low time tspickl 20 — — ns
SCP_CLK hi gh time tspickh 20 — — ns
Setup time SCP_MISO input tspidsu 13 — — ns
Hold time SCP_MISO input tspidh 5— —ns
SCP_CLK lo w to SCP_MOSI output valid tspidov —— 8ns
SCP_CLK low to SCP_CS# fa lling tspicsl 7— —ns
SCP_CLK low to SCP_CS# rising tspicsh — 11*DCLKP + (SCP_CLK PERIOD)/2 — ns
Bus free time between active SCP_CS# tspicsx — 3*DCLKP — ns
SCP_CLK falling to SCP_MOSI output high-Z tspidz — — 20 ns
Parameter Symbol Min Typical Max Units
SCP_CLK frequency1fiicck —— 400kHz
SCP_CLK low time tiicckl 1.25 — — µs
SCP_CLK hi gh time tiicckh 1.25 — — µs
SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition tiicckcmd 1.25 — — µs
START condition to SCP_CLK falling tiicstscl 1.25 — — µs
SCP_CLK falling to STOP condition tiicstp 2.5 — — µs
Bus free time between STOP and START conditions tiicbft 3— —µs
Setup time SCP_SDA input valid to SCP_CLK rising tiicsu 100 — — ns
Hold time SCP_SDA input after SCP_CLK falling tiich 20 — — ns
EE_CS#
SCP_CLK
SCP_MISO
SCP_MOSI
012670567
tspicss
tspickl
tspickh
tspidsu tspidh tspidov
A6 A5 A0 R/W MSB LSB
MSB LSB
tspicsh
tspicsx
fspisck
tspidz
tspicsl
14 DS734F5
5.12 Switching Characteristics—Serial Contro l Port–I2C Master Mode
Figure 5-5. Serial Control Port–I2C Slave Mode Timing
5.12 Switching Characteristics—Serial Control Port–I2C Master Mode
SCP_CLK low to SCP_SDA out valid tiicdov — — 18 ns
SCP_CLK fa lling to SCP_IRQ# rising tiicirqh — — 3*DCLKP + 40 ns
NAK condition to SCP_IRQ# low tiicirql — 3*DCLKP + 20 — ns
SCP_CLK rising to SCB_BSY# low tiicbsyl — 3*DCLKP + 20 — ns
1.The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the
communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of
the input data buffer.
Parameter Symbol Min Max Units
SCP_CLK frequency1
1.The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the
communication port may be limited by the firmware application.
fiicck —400kHz
SCP_CLK low time tiicckl 1.25 — µs
SCP_CLK hi gh time tiicckh 1.25 — µs
SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition tiicckcmd 1.25 — µs
START condition to SCP_CLK falling tiicstscl 1.25 — µs
SCP_CLK falling to STOP condition tiicstp 2.5 — µs
Bus free time between STOP and START conditions tiicbft 3— µs
Setup time SCP_SDA input valid to SCP_CLK rising tiicsu 100 — ns
Hold time SCP_SDA input after SCP_CLK falling tiich 20 — ns
SCP_CLK low to SCP_SDA out valid tiicdov —18 ns
Parameter Symbol Min Typical Max Units
SCP_BSY#
SCP_CLK
SCP_SDA
SCP_IRQ#
01 67801 7
tiicckl
tiicckh
tiicsu tiich
A6 A0 R/W ACK LSB
tiicirqh tiicirql
8
ACK
MSB
tiicstp
6
tiiccbsyl
tiicdov tiicbft
tiicstscl
tiicckcmd
fiicck
tiicckcmd
tiicf
tiicr
15 DS734F5
5.13 Switching Characteristics—Digital Audio Slave Input Port
Figure 5-6. Serial Control Port–I2C Master Mode Timing
5.13 Switching Characteristics—Digital Audio Slave Input Port
Figure 5-7. Digital Audio Input (DAI) Port Timing Diagram
5.14 Switching Characteristics—DSD Slave Input Port
Figure 5-8. Direct Stream Digital–Serial Audio Input Timing
Parameter Symbol Min Max Unit
DAI_SCLK period Tdaiclkp 40 — ns
DAI_SCLK duty cycle — 45 55 %
Setup time DAI_DATAn tdaidsu 10 — ns
Hold time DAI_DATAn tdaidh 5—ns
Parameter Symbol Min Typ Max Unit
DSD_SCLK Pulse Width Low tsclkl 78 — — ns
DSD_SCLK Pulse Width High tsclkh 78 — — ns
DSD_SCLK Frequency (64x Oversampled) — 1.024 — 3.2 MHz
DSD_A/B valid to DSD_SCLK rising setup time tsdlrs 20 — — ns
DSD_SCLK rising to DSD_A or DSD_B hold time tsdh 20 — — ns
SCP_CLK
SCP_SDA
01 67801 7
tiicckl
tiicckh
tiicsu tiich
A6 A0 R/W ACK LSB
8
ACK
MSB
tiicstp
6
tiicdov tiicbft
tiicstscl
tiicckcmd
fiicck
tiicckcmd
tiicf
tiicr
DAI_SCLK
DAI_DATAn
tdaidh
tdaidsu
16 DS734F5
5.15 Switching Characteristics—Digital Audio Output ( DAO) Port
5.15 Switching Characteristics—Digital Audio Output (DAO) Port
Figure 5-9. Digital Audio Output Port Timing, Master Mode
Parameter Symbol Min Max Unit
DAO_MCLK period Tdaomclk 40 — ns
DAO_MCLK duty cycle — 45 55 %
DAO_SCLK period for Master or Slave mode1
1.Master mode timing specifications are characterized, not production tested.
Tdaosclk 40 — ns
DAO_SCLK duty cycle for Master or Slave mode1—4060%
Table 5-1. Master Mode (Output A1 Mode)1,2
1.Master mode timing specifications are characterized, not production tested.
2.Master mode is defined as the CS48xx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_
LRCLK.
Parameter Symbol Min Max Unit
DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an input tdaomsck —19ns
DAO_LRCLK delay from DAO_SCLK transition, respectively3
3.This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the data is valid.
tdaomstlr —8ns
DAO_SCLK delay from DAO_LRCLK transition, respectively3tdaomlrts —8ns
DAO1_DATA[3:0], DAO2_DATA[1:0] delay from DAO_SCLK transition3tdaomdv —10ns
DAO_MCLK
DAO_SCLK
DAO_LRCLK
DAOn_DATAn
tdaomclk
tdaomsck
tdaomstlr
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK.
17 DS734F5
5.15 Switching Characteristics—Digital Audio Output ( DAO) Port
Figure 5-10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)
Table 5-2. Slave Mode (Output A0 Mode)1
1.Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
Parameter Symbol Min Max Unit
DAO_SCLK active edge to DAO_LRCLK transition tdaosstlr 10 — ns
DAO_LRCLK transition to DAO_SCLK acti ve edge tdaoslrts 10 — ns
DAO_Dx delay from DAO_SCLK inactive edge tdaosdv —11ns
DAO_SCLK
DAO_LRCLK
DAOn_DATAn
tdaosstlr
tdaosclk
DAO_SCLK
DAO_LRCLK
t
daoslrts
t
daosdv
t
daosclk
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK.
18 DS734F5
6 Ordering Information
6 Ordering Information
The CS485xx family part number is CS485NI-XYZR where:
• N–Product Number Variant
• I–ROM ID Number
• X–Product Grade
• Y–Package Type
• Z–Lead (Pb) Free
• R–Tape and Reel Packaging
Note: Contact the factory for availability of the automotive grade package.
7 Environmental, Manufacturing, and Handling Information
Table 6-1. Ordering Information
Part No. Grade Temp. Range Package
CS48520-CQZ Commercial 0 to +70° C 48-pin LQFP
CS48540-CQZ Commercial 0 to +70° C
CS48540-DQZ Automotive –40 to +85° C
CS48560-CQZ Commercial 0 to +70° C
CS48560-DQZ Automotive –40 to +85° C
Table 7-1. Environmental, Manufacturing, and Handling Information
Model Number Peak Reflow Temp MSL Rating1
1.MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
Max Floor Life
CS48520-CQZ 260° C 3 7 days
CS48540-CQZ
CS48540-DQZ
CS48560-CQZ
CS48560-DQZ
19 DS734F5
8 Device Pinout Diagrams
8 Device Pinout Diagrams
8.1 CS48520, 48-pin LQFP Pinout Diagram
Figure 8-1. CS48520, 48-pin LQFP Pinout
XTO
XTI
GNDA
PLL_REF_RES
VDDA (3.3V) GPIO1
GPIO2
GPIO16, DAI1_DATA0
GPIO0
38
40
41
42
43
45
46
GPIO13, SCP_BSY#, EE_CS#
GPOI12, SCP_IRQ#
GPIO10, SCP__MISO / SDA
GPIO9, SCP_MOSI
GPIO11, SCP_CLK
35
33
31
30
28
26
25
GND4
GNDIO4
VDD3
GND3
VDDIO3
GNDIO3
23
22
21
19
17
15
1
GPIO5, XMTA
GPIO3, HS1
DAO1_DATA0, HS0
DAO_LRCLK
DAI1_LRCLK
GPIO18, DAO_MCLK
DAI1_SCLK
VDD1
GND1
DAO_SCLK
GPIO4, HS2
RESET#
VDDIO1
GNDIO1
GPIO6, DAO2 _DATA0, HS3
GPIO7, HS4
VDD2
GND2
VDDIO2
GNDIO2
2
3
4
5
6
7
9
10
11
12
GPIO8, SCP_CS#
TEST
DBDA
DBCK
XTAL_OUT GPIO15, DAI2_SCLK
GPIO14, DAI2_LRCLK
GPIO17, DAI2_DATA0
CS48520
48-Pin LQFP
8
13
14
16
18
20
24
27
29
32
34
36
37
39
44
47
48
20 DS734F5
8.2 CS48540, 48-pin LQFP Pinout Diagram
8.2 CS48540, 48-pin LQFP Pinout Diagram
Figure 8-2. CS48540, 48-pin LQFP Pinout
XTO
XTI
GNDA
PLL_REF_RES
VDDA (3.3V) GPIO1, DAI1_DATA2
GPIO2
GPIO16, DAI1_DATA0
GPIO0, DAI1_DATA1
38
40
41
42
43
45
46
GPIO13, SCP_BSY#, EE_CS#
GPOI12, SCP_IRQ#
GPIO10, SCP__MISO / SDA
GPIO9, SCP_MOSI
GPIO11, SCP_CLK
35
33
31
30
28
26
25
GND4
GNDIO4
VDD3
GND3
VDDIO3
GNDIO3
23
22
21
19
17
15
1
GPIO5, XMTA
GPIO3, DAO1_ DATA1, HS1
DAO1_DATA0, HS0
DAO_LRCLK
DAI1_LRCLK
GPIO18, DAO_MCLK
DAI1_SCLK
VDD1
GND1
DAO_SCLK
GPIO4, DAO1_ DATA2, HS2
RESET#
VDDIO1
GNDIO1
GPIO6, DAO2_DATA0, HS3
GPIO7, HS4
VDD2GND2
VDDIO2
GNDIO2
2
3
4
5
6
7
9
10
11
12
GPIO8, SCP_CS#
TEST
DBDA
DBCK
XTAL_OUT GPIO15, DAI2_SCLK
GPIO14, DAI2_LRCLK
GPIO17,
DAI2_DATA0
CS48540
48-Pin LQFP
8
13
14
16
18
20
24
27
29
32
34
36
37
39
44
47
48
21 DS734F5
8.3 CS48560, 48-pin LQFP Pinout Diagram
8.3 CS48560, 48-pin LQFP Pinout Diagram
Figure 8-3 . CS485 60, 48-pin LQFP
XTO
XTI
GNDA
PLL_REF_RES
VDDA (3.3V) GPIO1, DAI1_DATA2, TM2, DSD2
GPIO2, DAI1_DATA3, TM3, DSD3
GPIO16, DAI1_DATA0, TM0, DSD0
GPIO0, DAI1_DATA1, TM1, DSD1
38
40
41
42
43
45
46
GPIO13, SCP_BSY#, EE_CS#
GPOI12, SCP_IRQ#
GPIO10, SCP__MISO / SDA
GPIO9, SCP_MOSI
GPIO11, SCP_CLK
35
33
31
30
28
26
25
GND4
GNDIO4
VDD3
GND3
VDDIO3
GNDIO3
23
22
21
19
17
15
1
GPIO5, DAO1_DATA3, X MTA
GPIO3, DAO1_ DATA1, HS1
DAO1_DATA0, HS0
DAO_LRCLK
DAI1_LRCLK, DAI1_DATA4, DSD5
GPIO18, DAO_MCLK
DAI1_SCLK, DSD-CLK
VDD1
GND1
DAO_SCLK
GPIO4, DAO1_ DATA2, HS2
RESET#
VDDIO1
GNDIO1
GPIO6, DAO2 _DATA0, HS3
GPIO7, DAO2_D ATA1, HS4
VDD2GND2
VDDIO2
GNDIO2
2
3
4
5
6
7
9
10
11
12
GPIO8, SCP_CS#
TEST
DBDA
DBCK
XTAL_OUT GPIO15, DAI2_SCLK
GPIO14, DAI2_LRCLK
GPIO17, DAI2_DATA0, DSD4
CS48560
48-Pin LQFP
8
13
14
16
18
20
24
27
29
32
34
36
37
39
44
47
48
22 DS734F5
9 Package Mechanical Drawings
9 Package Mechanical Drawings
9.1 48-pin LQFP Package Drawing
Figure 9-1. 48-pin LQFP Package Drawing
48 LD LQFP (7 x 7 x 1.4 mm body)
Number of Leads
48
MIN NOM MAX
A1.60
A1 0.05 0.15
A2 1.35 1.40 1.45
b 0.17 0.22 0.27
D9.00BSC
D1 7.00 BSC
e0.50BSC
E9.00BSC
E1 7.00 BSC
theta 0 7
L 0.45 0.60 0.75
L1 1.00 REF
NOTES:
1) Reference document: JEDEC MS-026
2) All dimensions are in millimeters and controlling dimension is in millimeters.
3) D1 and E1 do not include mold flash which is 0.25 mm max. per side.A1
4) Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.
23 DS734F5
10 Revision History
10Revision History
Revision Date Changes
A1 July, 2006 Advance release.
A2 July, 2006 Updated pinout definition for pins 26 and 27. Updated typical power numbers.
A3 December 5, 2006 Updated sections 2.0, 4.21, 5.8, Table 3, Table 4, to show new device numbering scheme. Updated
sections 8.1, 8.2, 8.3.
PP1 March 12, 2007 Preliminary Release
PP2 December 18, 2007 Changed title of data sheet from CS48500 Data Sheet to CS485xx Family Data Sheet to cover all CS485xx
family products. Updated Standby Powe r spec if ica tion i n Section 5.4. Upd ated DAO t i ming spec ific ati ons
and timing diagrams in Section 5.15.
F1 April 21, 2007 Removed DSD Phase Modulation Mode fro m Section 5.14. Removed reference to MCLK in Section 5.14.
Redefined Master mode clock speed for SCP_CLK in Section 5.10. Redefined DC leakage
characterization data in Section 5.3. Added typi cal crystal frequency values in Table Footnote 1 under
Section 5.7. Modified Footnote 1 under Section 5.9. Modified power supply characteristics in Section 5.4,
F2 July 14, 2008 Added reference to support for time division multiplexed (TDM) one-line data mode for DAO port in
Section 4.2.2.
F3 February 16, 2009 Updated Section 5.5, adding Junction Temperature specification.
F4 June 29, 2011 Updated Section 5.10; changed Tspidsu value to 13 ns.
F5 October, 2011 Updated Section 5.15 DAO output slave mode specifi cations.
