HD6417750F167V - Renesas Electronics

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please

confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to

additional and different information to be disclose d by Renesa s Electronics such as that disclosed through our website.

2. Renesas Electronics does not assum e any liability for inf ringement of patents, co pyrights, or other int ellectual property rights

of third parties by or arising from the use of Renesas Elec tronics products or technical information described in this document.

No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights

of Renesas Electronics or others.

3. You should not alter, m odify, copy, or otherw ise misappropriate an y Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of

semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,

and information in the design of your equipment. Renesas Electronics assumes no responsi bility for any losse s incurred by

you or third parties arising from the use of these circuits, software, or information.

5. When exporting the products or technol ogy described in this document, you should comply with the applicable export control

laws and regulations and follow the procedures required by such law s and regulations. You should not use Renesas

Electronics products or the technology described in this docum ent for any purpose rela ting to military applications or use by

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incurred by you resulting from errors in or omissions from the information included herein.

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expressly specified in a Renesas Electronics data sheets or data books, etc.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

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“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-

crime systems; safety equipment; and medical equipment not specifically designed for life support.

“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or

systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare

intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,

especially with respect to the m aximum rating , opera ting supply voltag e range, movement power voltage ra nge, heat radiation

characteristics, installation and other product characteristic s. Re nesas Electronics shall have no liabil ity for malfunctions or

damages arising out of the use of Re nesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliabili ty of its products, semiconductor products have

specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,

Renesas Electronics products are not subject to radiation res istance design. Pleas e be sure to implement saf ety measures to

guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a

Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire

control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because

the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system

manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental

compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable

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Directive. Renesas Electronics assum es no liability for damage s or losses occurring as a result of your noncom pliance with

applicable laws and regulatio ns.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas

Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions re garding the information conta ined in this

document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-

owned subsidiaries.

(Note 2) “Re nesas Electronics produc t(s)” means any product develope d or manufactured by or for Re nesas Electronics.

SH7750, SH7750S,

SH7750R Group

Hardware Manual

User’s Manual

Rev.7.00 2008.10

Renesas 32-Bit RISC

Microcomputer

SuperH™ RISC engine Family/

SH7750 Series

Rev.7.00 Oct. 10, 2008 Page ii of lxxxiv

REJ09B0366-0700

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate

Renesas products for their use. Renesas neither makes warranties or representations with respect to the

accuracy or completeness of the information contained in this document nor grants any license to any

intellectual property rights or any other rights of Renesas or any third party with respect to the information in

this document.

2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising

out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,

programs, algorithms, and application circuit examples.

3. You should not use the products or the technology described in this document for the purpose of military

applications such as the development of weapons of mass destruction or for the purpose of any other military

use. When exporting the products or technology described herein, you should follow the applicable export

control laws and regulations, and procedures required by such laws and regulations.

4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and

application circuit examples, is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas products listed in this

document, please confirm the latest product information with a Renesas sales office. Also, please pay regular

and careful attention to additional and different information to be disclosed by Renesas such as that disclosed

through our website. (http://www.renesas.com )

5. Renesas has used reasonable care in compiling the information included in this document, but Renesas

assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information

included in this document.

6. When using or otherwise relying on the information in this document, you should evaluate the information in

light of the total system before deciding about the applicability of such information to the intended application.

Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any

particular application and specifically disclaims any liability arising out of the application and use of the

information in this document or Renesas products.

7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas

products are not designed, manufactured or tested for applications or otherwise in systems the failure or

malfunction of which may cause a direct threat to human life or create a risk of human injury or which require

especially high quality and reliability such as safety systems, or equipment or systems for transportation and

traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication

transmission. If you are considering the use of our products for such purposes, please contact a Renesas

sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.

8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:

(1) artificial life support devices or systems

(2) surgical implantations

(3) healthcare intervention (e.g., excision, administration of medication, etc.)

(4) any other purposes that pose a direct threat to human life

Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who

elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas

Technology Corp., its affiliated companies and their officers, directors, and employees against any and all

damages arising out of such applications.

9. You should use the products described herein within the range specified by Renesas, especially with respect

to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation

characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or

damages arising out of the use of Renesas products beyond such specified ranges.

10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific

characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use

conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and

injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for

hardware and software including but not limited to redundancy, fire control and malfunction prevention,

appropriate treatment for aging degradation or any other applicable measures. Among others, since the

evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or

system manufactured by you.

11. In case Renesas products listed in this document are detached from the products to which the Renesas

products are attached or affixed, the risk of accident such as swallowing by infants and small children is very

high. You should implement safety measures so that Renesas products may not be easily detached from your

products. Renesas shall have no liability for damages arising out of such detachment.

12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written

approval from Renesas.

13. Please contact a Renesas sales office if you have any questions regarding the information contained in this

document, Renesas semiconductor products, or if you have any other inquiries.

Notes regarding these materials

Rev.7.00 Oct. 10, 2008 Page iii of lxxxiv

REJ09B0366-0700

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes

on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under

General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each

other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in

the manual.

⎯ The input pins of CMOS products are generally in the high-impedance state. In

operation with an unused pin in the open-circuit state, extra electromagnetic noise is

induced in the vicinity of LSI, an associated shoot-through current flows internally, and

malfunctions may occur due to the false recognition of the pin state as an input signal.

Unused pins should be handled as described under Handling of Unused Pins in the

manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

⎯ The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the

states of pins are not guaranteed from the moment when power is supplied until the

reset process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on

reset function are not guaranteed from the moment when power is supplied until the

power reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

⎯ The reserved addresses are provided for the possible future expansion of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are

accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has

become stable. When switching the clock signal during program execution, wait until the

target clock signal has stabilized.

⎯ When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization

of the clock signal. Moreover, when switching to a clock signal produced with an

external resonator (or by an external oscillator) while program execution is in progress,

wait until the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different type number,

confirm that the change will not lead to problems.

⎯ The characteristics of MPU/MCU in the same group but having different type numbers

may differ because of the differences in internal memory capacity and layout pattern.

When changing to products of different type numbers, implement a system-evaluation

test for each of the products.

Rev.7.00 Oct. 10, 2008 Page iv of lxxxiv

REJ09B0366-0700

Rev.7.00 Oct. 10, 2008 Page v of lxxxiv

REJ09B0366-0700

Preface

The SH-4 (SH7750 Group: SH7750, SH7750S, SH7750R) microprocessor incorporates the 32-bit

SH-4 CPU and is also equipped with peripheral functions necessary for configuring a user system.

The SH7750 Group is built in with a variety of peripheral functions such as cache memory,

memory management unit (MMU), interrupt controller, timers, two serial communication

interfaces (SCI, SCIF), real-tim1e clock (RTC), user break controller (UBC), bus state controller

(BSC) and smart card interface. This LSI can be used in a wide range of multimedia equipment.

The bus controller is compatible with ROM, SRAM, DRAM, synchronous DRAM and PCMCIA,

as well as 64-bit synchronous DRAM 4-bank system and 64-bit data bus.

Target Readers: This manual is designed for use by people who design application systems using

the SH7750, SH7750S, or SH7750R.

To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is

required.

Purpose: This manual provides the information of the hardware functions and electrical

characteristics of the SH7750, SH7750S, and SH7750R.

The SH-4 Software Manual contains detailed information of executable instructions. Please read

the Software Manual together with this manual.

How to Use the Book:

• To understand general functions

→ Read the manual from the beginning.

The manual explains the CPU, system control functions, peripheral functions and electrical

characteristics in that order.

• To understanding CPU functions

→ Refer to the separate SH-4 Software Manual.

Explanatory Note: Bit sequence: upper bit at left, and lower bit at right

List of Related Documents: The latest documents are available on our Web site. Please make

sure that you have the latest version.

(http://www.renesas.com/)

• User manuals for SH7750, SH7750S, and SH7750R

Name of Document Document No.

SH7750, SH7750S, SH7750R Group Hardware Manual This manual

SH-4 Software Manual REJ09B0318-0600

Rev.7.00 Oct. 10, 2008 Page vi of lxxxiv

REJ09B0366-0700

• User manuals for development tools

Name of Document Document No.

SuperH™ RISC engine C/C++ Compiler, Assembler, Optimizing Linkage

Editor User's Manual

REJ10J1571-0100

SuperH™ RISC engine Simulator/Debugger User's Manual REJ10B0210-0400

High-performance Embedded Workshop User's Manual REJ10J1737-0100

Rev.7.00 Oct. 10, 2008 Page vii of lxxxiv

REJ09B0366-0700

Main Revisions for This Edition

Item Page Revision (See Manual for Details)

All ⎯ • Notification of change in company name amended

(Before) Hitachi, Ltd. → (After) Renesas Technology Corp.

Description amended

Iφ → Ick

Bφ → Bck

Pφ → Pck

1.1 SH7750, SH7750S,

SH7750R Groups

Features

1 Description amended

This LSI (SH7750, SH7750S, and SH7750R Groups) is a 32-bit

RISC (reduced instruction set computer) microprocessor with a

SH-4 CPU core and features upward compatibility with SH-1,

SH-2, and SH-3 microcomputers at the instruction set level.

Table 1.1 LSI Features 1 to 3, 8 Table amended

SH-1, SH-2, and SH-3)

Item Features

LSI

• Superscalar architecture: Parallel execution of two instructions

• External buses

⎯ Separate 26-bit address and 64-bit data buses

⎯ External bus frequency of 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus

frequency

CPU • RISC-type instruction set (upward-compatible with

FPU • Floating-point registers: 32 bits × 16 × 2 banks

(single-precision 32 bits × 16 or double-precision 64 bits × 8 )

× 2 banks

Product lineup Abbre-

viation

Voltage

(Internal)

Operating

Frequency Model No. Package

SH7750 1.95 V 200 MHz HD6417750BP200M 256-pin BGA

1.8 V 167 MHz HD6417750F167

1.5 V 128 MHz HD6417750VF128

208-pin QFP

SH7750S 1.95 V 200 MHz HD6417750SBP200 256-pin BGA

HD6417750SF200

1.8 V 167 MHz HD6417750SF167

1.5 V 133 MHz HD6417750SVF133

208-pin QFP

HD6417750SVBT133 264-pin CSP

SH7750R 1.5 V 240 M

200 MHz

Hz HD6417750RBG240 292-pin BGA

HD6417750RBP240 256-pin BGA

HD6417750RF240 208-pin QFP

HD6417750RBG200 292-pin BGA

HD6417750RBP200 256-pin BGA

HD6417750RF200 208-pin QFP

Rev.7.00 Oct. 10, 2008 Page viii of lxxxiv

REJ09B0366-0700

Item Page Revision (See Manual for Details)

1.2 Block Diagram

Figure 1.1 Block

Diagram of SH7750/

SH7750S/SH7750R

Group Functions

9 Figure amended

CPG

INTC

SCI

(SCIF)

RTC

TMU

External

bus interface

BSC DMAC

Address 29-bit address

64-bit data

32-bit data

Upper 32-bit data

32-bit address (instructions)

32-bit data (instructions)

32-bit address (data)

Peripheral address bus

26-bit

address 64-bit

data

16-bit peripheral data bus

UBC

Lower 32-bit data

32-bit data (load)

32-bit data (store)

CPU

I cache O cacheITLB UTLB

Cache and

TLB

controller

FPU

64-bit data (store)

SH-4 Core

Rev.7.00 Oct. 10, 2008 Page ix of lxxxiv

REJ09B0366-0700

Item Page Revision (See Manual for Details)

1.3 Pin Arrangement

Figure 1.4 Pin

Arrangement (264-Pin

CSP)

12 Figure amended

VSS-CPG XTAL EXTAL VDD-CPG TRST TDO MD6/IOIS16 A0 VDDQ VDDQ A20 VDD TCLK VSS-RTC XTAL2 EXTAL2 IRL2

RESET CS4 VDD-PLL2 VSS STATUS0 DACK0 A24 VDDQ MD7/TXD CA IRL3

RDY VSS-PLL2 VSS-PLL1 VDD-PLL1 TCK VSSQ VSSQ MD3/CE2A A22 A18 VDDQ VDDQ VDD-RTC MD1/TXD2 NMI

CS0 VSSQ CKIO2ENB TDI VDD A1 MD5/RAS2 A23 VSS MD8/RTS2 CTS2 VSSQ IRL0 IRL1

BS CS1 CS5 CS6 TMS ASEBRK/

BRKACK VDDQ VDDQ MD4/CE2B VSSQ VSSQ SCK2/

MRESET D48 RD/WR2 MD2/RXD2 VSSQ

VDD D47 VDDQ RD2 D32 D33 STATUS1 DACK1 VSSQ A25 A21 A19 D49 VDDQ D63 MD0/SCK D62

D45 VDDQ D46 VSS VSSQ D34 D50 VDDQ VDD VSSQ VSS D61

VDDQ D43 D44 D35 VSSQ D36 D52 VDDQ D51 VSSQ D60 D59

VDDQ D38 D42 D41 D37 VSSQ VSSQ D57 D53 D54 D58 VDDQ

D39 D0 VSSQ D15 VDDQ D40 D56 VSSQ D31 D16 D55 VDDQ

D1 VSS VSSQ VDD VDDQ D14 D30 VSSQ VSS D18 VDDQ D17

D2 D4 D3 VDDQ D13 A14 A9 VDDQ A6 A2 D29 D28 D27 VDDQ D19 VDD

VSSQ D5 D11 D12 A16 VDDQ VDDQ A7 A4 DRAK0 VSSQ VSS D26 D21 VDDQ D20

VSSQ VDDQ VDDQ

WE4/CAS4/

DQM4

WE0/CAS0/

DQM0

VDD A11 VSSQ VSSQ CS2 RD/CASS/

FRAME VSSQ VSSQ D25 DREQ1

D6 BREQ/

BSACK D10 CKE WE5/CAS5/

DQM5 A17 VSS A12 A8 VDDQ VDDQ RAS

WE3/CAS3/

DQM3/ICIOWR

WE6/CAS6/

DQM6

WE2/CAS2/

DQM2/ICIORD

RXD

BACK/

BSREQ VSSQ D8 VDDQ VSSQ A13 VSSQ CKIO2 A3 VDD RD/WR D24 D22 VSSQ DREQ0

D9 D7 WE1/CAS1/

DQM1 A15 VSSQ A10 CKIO A5 DRAK1 CS3 VDDQ VDDQ WE7/CAS7/

DQM7/REG D23 VSSQ

234567891011121314151617

CSP264

(Top view)

Figure 1.5 Pin

Arrangement (292-Pin

BGA)

13 Newly added

1.4.1 Pin Functions

(256-Pin BGA)

Table 1.2 Pin

Functions

17, 20,

Table and notes amended

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

92 Y11 CKIO O Clock output CKIO CKIO CKIO

93 V10 VDDQ Power IO VDD (3.3 V)

94 U10 VSSQ Power IO GND (0 V)

95 W11 CKIO2 O CKIO*

CKIO CKIO CKIO

115 W16 RD/WR RD/WR RD/WR RD/WR RD/WR RD/WRO Read/write

RD/WR2 RD/WR RD/WR RD/WR RD/WR RD/WRO RD/WR

178 E18

Notes: ... VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG

are connected inside the package.

NC pins must be left completely open, and not

connected to a power supply, GND, etc.

Rev.7.00 Oct. 10, 2008 Page x of lxxxiv

REJ09B0366-0700

Item Page Revision (See Manual for Details)

1.4.2 Pin Functions

(208-Pin QFP)

Table 1.3 Pin

Functions

26, 27,

Table and notes amended

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

77 CKIO O Clock output CKIO CKIO CKIO

RD/WR RD/WR RD/WR RD/WR RD/WR RD/WRO Read/write

Notes: ... VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG

are connected inside the package.

The RD2, RD/WR2, CKIO2, and CKIO2ENB pins are not

provided on the QFP package.

1.4.3 Pin Functions

(264-Pin CSP)

Table 1.4 Pin

Functions

35, 38,

Table and notes amended

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

90 U9 CKIO O Clock output CKIO CKIO CKIO

91 M9 VDDQ Power IO VDD (3.3 V)

92 P9 VSSQ Power IO GND (0 V)

93 T9 CKIO2 O CKIO* CKIO CKIO CKIO

RD/WR RD/WR RD/WR RD/WR RD/WR RD/WRO Read/write

113 T12

RD/WR2 RD/WR RD/WR RD/WR RD/WR RD/WRO RD/WR

175 E14

Notes: ... Power must be supplied to VDD-RTC and VSS-RTC

regardless of whether or not the on-chip RTC is used.

NC pins must be left completely open, and not

connected to a power supply, GND, etc.

1.4.4 Pin Functions

(292-Pin BGA)

42 to 52 Newly added

2.2.1 Privileged Mode

and Banks

Table 2.1 Initial

55 Table amended

Type Registers Initial Value*

SR MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0,

IMASK = 1111 (H'F), reserved bits = 0, others

undefined

Control registers

2.6 Processor States

Figure 2.6 Processor

State Transitions

68 Figure amended

RESET = 0,

MRESET = 1

Power-on reset state Manual reset state

From any state when

RESET = 0 and MRESET = 1 RESET = 0 and MRESET = 0

Reset state

3.8 Usage Notes 109 Newly added

4.3.1 Configuration

• LRU (SH7750R only)

119 Description amended

Rev.7.00 Oct. 10, 2008 Page xi of lxxxiv

REJ09B0366-0700

Item Page Revision (See Manual for Details)

4.3.10 Notes on Using

Cache Enhanced Mode

(SH7750R Only)

125 to

127

Newly added

4.4.1 Configuration

• LRU (SH7750R only)

130 Description amended

• LRU (SH7750R only)

In a 2-way set-associative cache, up to 2 items of data can

be registered in the cache at each entry address. When an

entry is registered, the LRU bit indicates which of the 2 ways

it is to be registered in. The LRU bit is a single bit of each

entry, and its value is controlled by hardware.

5.3.2 Exception

Handling Vector

Addresses

151 Description amended

The reset vector address is fixed at H'A000 0000. General

exception and interrupt vector addresses are determined by

adding the offset for the specific event to the vector base

address, which is set by software in the vector base register

(VBR).

5.5.3 Exception

Requests and BL Bit

158 Description amended

When the BL bit in SR is 0, general exception and interrupts are

accepted.

When the BL bit in SR is 1 and a general exception other than a

user break is generated, the CPU's internal registers and the

registers of the other modules are set to their states following a

manual reset, and the CPU branches to the same address as in

a reset (H'A000 0000).

5.6.1 Resets

(1) Power-On Reset

159 Description amended

In the initialization processing, the VBR register is set to H'0000

0000, and in SR, the MD, RB, and BL bits are set to 1, the FD

bit is cleared to 0, and the interrupt mask bits (IMASK) are set

to B'1111.

...

SR.IMASK = B'1111;

(2) Manual Reset 160 Description amended

In the initialization processing, the VBR register is set to H'0000

0000, and in SR, the MD, RB, and BL bits are set to 1, the FD

bit is cleared to 0, and the interrupt mask bits (IMASK) are set

to B'1111.

...

SR.IMASK = B'1111;

Rev.7.00 Oct. 10, 2008 Page xii of lxxxiv

REJ09B0366-0700

Item Page Revision (See Manual for Details)

5.6.1 Resets

(3) H-UDI Reset

161 Description amended

In the initialization processing, the VBR register is set to H'0000

0000, and in SR, the MD, RB, and BL bits are set to 1, the FD

bit is cleared to 0, and the interrupt mask bits (IMASK) are set

to B'1111.

...

SR.IMASK = B'1111;

(4) Instruction TLB

Multiple-Hit Exception

162 Description amended

In the initialization processing, the VBR register is set to H'0000

0000, and in SR, the MD, RB, and BL bits are set to 1, the FD

bit is cleared to 0, and the interrupt mask bits (IMASK) are set

to B'1111.

...

SR.IMASK = B'1111;

(5) Operand TLB

Multiple-Hit Exception

163 Description amended

In the initialization processing, the VBR register is set to H'0000

0000, and in SR, the MD, RB, and BL bits are set to 1, the FD

bit is cleared to 0, and the interrupt mask bits (IMASK) are set

to B'1111.

...

SR.IMASK = B'1111;

5.6.2 General

Exceptions

(11) General FPU

Disable Exception

174 Note amended

Note: * FPU instructions are instructions in which the first 4 bits

of the instruction code are H'F (but excluding undefined

instruction H'FFFD), and the LDS, STS, LDS.L, and

STS.L instructions corresponding to FPUL and FPSCR.

5.6.3 Interrupts

(3) Peripheral Module

Interrupts

180 Description amended

INTEVT = H'00000400 ~ H'00000B80;

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5.7 Usage Notes 182 Description amended

2. If a general exception or interrupt occurs when SR.BL = 1

a. General exception

When a general exception other than a user break occurs, a

manual reset is executed. The value in EXPEVT at this time

is H'0000 0020; the value of the SPC and SSR registers is

undefined.

...

3. SPC when an exception occurs

a. Re-execution type general exception

The PC value for the instruction in which the general

exception occurred is set in SPC, and the instruction is re-

executed after returning from exception handling. If an

exception occurs in a delay slot instruction, however, the PC

value for the delay slot instruction is saved in SPC regardless

of whether or not the preceding delayed branch instruction

condition is satisfied.

b. Completion type general exception or interrupt

The PC value for the instruction following that in which the

general exception occurred is set in SPC. If an exception

occurs in a branch instruction with delay slot, however, the

PC value for the branch destination is saved in SPC.

6.5 Floating-Point

Exceptions

• Enable/disable

exception handling

194 Description amended

For information on these possibilities, see the individual

instruction descriptions in chapter 9 of the SH-4 Software

Manual. The particulars differ demanding on the instruction. All

exception events that originate in the FPU are assigned as the

same exception event. The meaning of an exception is

determined by software by reading system register FPSCR and

interpreting the information it contains.

6.6.2 Pair Single-

Precision Data Transfer

196 Description amended

In addition to the geometric operation instructions, the FPU

also supports high-speed data transfer instructions.

When FPSCR.SZ = 1, the FPU can perform data transfer by

means of pair single-precision data transfer instructions.

6.7 Usage Notes 197 to

207

Newly added

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7.3 Instruction Set

Table 7.12 Floating-

Point Graphics

Acceleration Instructions

227 Table amended

Instruction Operation

FRCHG ~FPSCR.FR → FPSCR.FR

FSCHG ~FPSCR.SZ → FPSCR.SZ

7.4 Usage Notes 227 to

229

Newly added

8.4 Usage Notes 258 Newly added

9.1.1 Types of Power-

Down Modes

259 Description amended

• Module standby function (TMU, RTC, SCI/SCIF, DMAC,

SQ*, and UBC* )

9.2.4 Standby Control

266 Description amended

Bit 6 —STATUS Pin High-Impedance Control (STHZ): This bit

selects whether the STATUS0 and STATUS1 pins are set to

high-impedance when in hardware standby mode.

Bit 6: STHZ Description

0 Sets STATUS0, 1 pins to high-impedance when in hardware standby mode

(Initial value)

1 Drives STATUS0, 1 pins to LH when in hardware standby mode

9.5.2 Exit from Standby

Mode

271 Notes amended

Notes: 1. Only when the RTC clock (32.768 kHz) is operating

(see section 19.2.2, IRL Interrupts), standby mode

can be exited by means of IRL3–IRL0 (when the

IRL3–IRL0 level is higher than the SR register IMASK

mask level).

2. GPIO can be used to cancel standby mode when the

RTC clock (32.768 kHz) is operating (when the GPIO

level is higher than the SR register IMASK mask

level).

9.7.1 Transition to

Hardware Standby

Mode

274 Description amended

3. On the SH7750S, the RTC continues to operate even when

no power is supplied to power pins other than the RTC power

supply pin.

The state of the STATUS pin reflects the setting of the STHZ

bit. Refer to appendix E, Pin Functions, for details on output

pin states.

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9.7.2 Exit from

Hardware Standby

Mode

274 Description amended

Setting the CA pin level high after the RESET pin level has

been set low and the SCK2 pin high starts the clock to oscillate.

The RESET pin level should be kept low until the clock has

stabilized, then set high so that the CPU starts the power-on

reset exiting procedure.

9.7.3 Usage Notes 275 Description amended

1. The CA pin level must be kept high when the RTC power

supply is started (figure 9.15).

2. On the SH7750R, power must be supplied to the other power

supply pins (VDD, VDDQ, VDD−CPG, VDD−PLL1, and VDD−PLL2), in addition

to the RTC power supply pin, in hardware standby mode.

9.8.1 In Reset

Figure 9.2 STATUS

Output in Manual Reset

276 Figure amended

CKIO

RESET*

STATUS Normal Reset Normal

SCK2

0–30 Bcyc

≥ 0 Bcyc

Note: * In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting

until the end of the currently executing bus cycle.

Must be asserted for

RESW

or longer

9.8.5 Hardware

Standby Mode Timing

(SH7750S, SH7750R

Only)

Figure 9.15 Timing

When VDD-RTC Power

is Off → On

285 Figure amended

VDD-RTC

SCK2

RESET

VDD, VDDQ

Min 0s

Note: * V

DD, VDD-PLL1/2, VDDQ, VDD-CPG

Power-on oscillation

setting time

9.9 Usage Notes 286 Newly added

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10.1.1 Features 287 Description amended

• Three clocks

The CPG can generate the CPU clock (Ick) used by the

CPU, FPU, caches, and TLB, the peripheral module clock

(Pck) used by the peripheral modules, and the bus clock

(Bck) used by the external bus interface.

10.3 Clock Operating

Modes

Table 10.4 FRQCR

Settings and Internal

Clock Frequencies

294 Table amended

Frequency Division Ratio of Frequency Divider 2

10.11 Usage Notes 309 Newly added

11.1 Overview 311 Description amended

This LSI includes an on-chip realtime clock (RTC) and a 32.768

kHz crystal oscillation circuit for use by the RTC.

11.2.16 RTC Control

Bit 3— Oscillation

Circuit Enable (RTCEN):

326 Description amended

Controls the operation of the RTC crystal oscillation circuit.

Bit 3: RTCEN Description

0 RTC crystal oscillation circuit halted

1 RTC crystal oscillation circuit operating (Initial value)

11.5.4 RTC Register

Settings (SH7750 only)

334 to

336

Newly added

12.1.2 Block Diagram

Figure 12.1 Block

Diagram of TMU

338 Figure amended

Pck/4,16, 64

Prescaler

To each

channel

12.2.7 Input Capture

350 Title amended

12.5.2 Underflow Flag

Writes (SH7750 only)

356 Newly added

12.5.5 External Clock

Frequency

Description amended

Ensure that the external clock frequency for any channel does

not exceed Pck/8.

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13.1.2 Block Diagram

Figure 13.1 Block

Diagram of BSC

359 Figure amended

RD/FRAME

RD/WR

WE7–WE0

RAS

CAS7–CAS0, CASS

CKE

ICIORD, ICIOWR

REG

IOIS16

Memory

control unit

13.1.3 Pin

Configuration

Table 13.1 BSC Pins

360 Table amended

Name Signals I/O Description

Data bus D63−D52,

D31−D0

I/O Data input/output

When port functions are used and DDT mode is

selected, input the DTR format. Otherwise, when

port functions are used, D63−D52 cannot be used

and should be left open.

13.1.6 PCMCIA

Support

Table 13.5 PCMCIA

Support Interfaces

371 Table and notes amended

IC Memory Card Interface I/O Card Interface

Signal

Name I/O Function

Signal

Name I/O Function

Corresponding

LSI Pin

59 WAIT O Wait request WAIT O Wait request RDY*

Note: 1. WP is not supported.

2. Input an external wait request with correct polarity.

13.2.1 Bus Control

372 Bit table amended

Bit: 31 30 29 28 27 26

ENDIAN MASTER A0MPX

— — DPUP*

Initial value: 0/1*

0/1*

000

R/W: R R R R R R/W

13.2.7 Wait Control

400 Description amended

Bits 4n+3⎯Area n (4 or 1) Read-Strobe Negate Timing

(AnRDH) (Setting Only Possible in the SH7750R): When

reading, these bits specify the timing for the negation of read

strobe. These bits should be cleared to 0 when a byte control

SRAM setting is made. Valid only for the SRAM interface.

Bit 4n + 3: AnRDH Read-Strobe Negate Timing

0 Read strobe negated after hold wait cycles specified by WCR3.AnH bits

(Initial value)

1 Read strobe negated according to data sampling timing

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13.2.8 Memory Control

Bit 31—RAS Down

(RASD):

402 Description and table amended

Do not set RAS down mode in slave mode or partial-sharing

mode, or when areas 2 and 3 are both designated as

synchronous DRAM interface. See Connecting a 128-Mbit/256-

Mbit Synchronous DRAM with 64-bit Bus Width (SH7750R

Only): in section 13.3.5, Synchronous DRAM Interface.

Bit 31: RASD Description

0(Initial value)

Auto-precharge mode

Bits 29 to 27—RAS

Precharge Time at End

of Refresh (TRC2–

TRC0)

402 Note added

Note: For setting values and the period during which no

command is issued, see 22.3.3, Bus Timing.

Bits 21 to 19—RAS

Precharge Period

(TPC2–TPC0):

403 Description amended and note added

When the DRAM interface is selected, these bits specify the

minimum number of cycles until RAS is asserted again after

being negated. When the synchronous DRAM interface is

selected, these bits specify the minimum number of cycles until

the next bank active command after precharging.

Note: For setting values and the period during which no

command is issued, see 22.3.3, Bus Timing.

Bits 15 to 13—Write

Precharge Delay

(TRWL2–TRWL0):

404 Description amended and note added

After a write cycle, the next active command is not issued for a

period equivalent to the setting values of the TPC[2:0] and

TRWL[2:0] bits.* ...

Note: * For setting values and the period during which no

command is issued, see 22.3.3, Bus Timing.

Bits 12 to 10—CAS-

Before-RAS Refresh

RAS Assertion Period

(TRAS2–TRAS0):

405 Description amended and note added

When the DRAM interface is set, these bits set the RAS

assertion period in CAS-before-RAS refreshing. When the

synchronous DRAM interface is set, the bank active command

is not issued for the period set by the TRC[2:0]* and TRAS[2:0]

bits after an auto-refresh command is issued.

Note: For setting values and the period during which no

command is issued, see 22.3.3, Bus Timing.

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13.3.4 DRAM Interface

Refresh Timing:

• Self-Refresh

463 Description deleted

After the self-refresh is cleared, the refresh controller

immediately generates a refresh request. The RAS precharge

time immediately after the end of the self-refreshing can be set

by bits TRC2–TRC0 in MCR.

CAS-before-RAS refreshing is performed in normal operation,

in sleep mode, and in the case of a manual reset.

13.3.5 Synchronous

DRAM Interface

465 Description amended

With this LSI, burst read/burst write mode is supported as the

synchronous DRAM operating mode. The data bus width is 32

or 64 bits, and the SZ size bits in MCR must be set to 00 or 11.

The burst enable bit (BE) in MCR is ignored, a 32-byte burst

transfer is performed in a cache fill/copy-back cycle, and in a

write-through area write or a non-cacheable area read/write,

32-byte data is read even in a single read in order to access

synchronous DRAM with a burst read/write access. 32-byte

data transfer is also performed in a single write, but DQMn is

not asserted when unnecessary data is transferred. For details

on the burst length, see section 13.2.10, Synchronous DRAM

Mode Register (SDMR), and Power-On Sequence in section

13.3.5, Synchronous DRAM Interface. The SH7750R Group

supports burst read and burst write operations with a burst

length of 4 as a synchronous DRAM operating mode when

using a 32-bit data bus. The burst enable (BE) bit in MCR is

ignored, and a 32-byte burst transfer is performed in a cache fill

or copy-back cycle. In write-through area write operations and

non-cacheable area read or write operations, 16 bytes of data

is read even in a single read because burst read or write

accesses to synchronous DRAM use a burst length of 4.

Sixteen bytes of data is transferred in the case of a single write

also, but DQMn is not asserted when unnecessary data is

transferred.

For changing the burst length (a function only available in the

SH7750R) for a 32-bit bus, see Notes on Changing the Burst

Length (SH7750R Only) in section 13.3.5, Synchronous DRAM

Interface.

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13.3.5 Synchronous

DRAM Interface

Figure 13.26 Example

of 64-Bit Data Width

Synchronous DRAM

Connection (Area 3)

466 Figure amended

A12–A3

CKIO

CKE

CS3

RAS

CASS

RD/WR

D63–D48

DQM7

DQM6

SH7750, SH7750S, SH7750R

Figure 13.27 Example

of 32-Bit Data Width

Synchronous DRAM

Connection (Area 3)

467 Figure amended

A11–A2

CKIO

CKE

CS3

RAS

CASS

RD/WR

D31–D16

DQM3

DQM2

SH7750, SH7750S, SH7750R

Figure 13.37 Burst

Write Timing (Different

Row Addresses)

481 Figure amended

Tpr Tr Trw Tc1 Tc2 Tc3Tpc

H/LH/L

Tc4 Trwl Trwl Trwl

CKIO

Bank

Precharge-sel

Address

CSn

RD/WR

Row

Power-On Sequence:

Figure 13.42 (1)

Synchronous DRAM

Mode Write Timing

(PALL)

490 Figure amended

CASS

D63–D0

CKE (High)

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13.3.5 Synchronous

DRAM Interface

Figure 13.42 (2)

Synchronous DRAM

Mode Write Timing

(Mode Register Set)

491 Figure amended

CASS

D63–D0

CKE (High)

Connecting a 128-

Mbit/256-Mbit

Synchronous DRAM

with 64-bit Bus Width

(SH7750R Only):

494, 495 Description amended

• In the auto-refresh operation, the REF command is issued

twice continuously in response to a single refresh request.

The interval cycle number between the first and second REF

commands issuance is specified by the setting of the

TRAS2−TRAS0 bits in MCR, which is 4 to 11 CKIO cycles.

The interval cycle number between the second REF

command and the next ACTV command issuance is specified

by the settings of both the TRAS2−TRAS0 bits and the

TRC2−TRC0 bits in MCR in the sum total, which is 4 to 32

CKIO cycles. Set RTCOR and bits CKS2−CKS0, and MCR so

as to satisfy the refresh-interval rating of the synchronous

DRAM which you are using. The synchronous DRAM auto-

refresh timing with 64-bit bus width is shown below figure.

Figure 13.46

Synchronous DRAM

Auto-Refresh Timing

with 64-Bit Bus Width

(TRAS [2:0] = 001, TRC

[2:0] = 001))

496 Figure newly added

13.3.7 PCMCIA

Interface

Figure 13.51 Basic

Timing for PCMCIA

Memory Card Interface

505 Figure amended

D15–D0

(write)

WE1

(write)

Figure 13.52 Wait

Timing for PCMCIA

Memory Card Interface

506 Figure amended

D15–D0

(write)

WE1

(write)

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13.3.7 PCMCIA

Interface

Figure 13.54 Basic

Timing for PCMCIA I/O

Card Interface

508 Figure amended

ICIOWR

(write)

D15–D0

(write)

Figure 13.55 Wait

Timing for PCMCIA I/O

Card Interface

509 Figure amended

ICIOWR

(write)

D15–D0

(write)

13.3.8 MPX Interface

Figure 13.57 Example

of 64-Bit Data Width

MPX Connection

512 Figure amended

CKIO

CSn

RD/FRAME

RD/WR

D63–D0

RDY

SH7750, SH7750S, SH7750R

Figure 13.66 MPX

Interface Timing 9

(Burst Read Cycle, AnW

= 0, No External Wait,

Bus Width: 32 Bits,

Transfer Data Size: 64

Bits)

521 Title amended

Figure 13.67 MPX

Interface Timing 10

(Burst Read Cycle, AnW

= 0, One External Wait

Inserted, Bus Width: 32

Bits, Transfer Data Size:

64 Bits)

522 Title amended

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13.3.8 MPX Interface

Figure 13.68 MPX

Interface Timing 11

(Burst Write Cycle, AnW

= 0, No External Wait,

Bus Width: 32 Bits,

Transfer Data Size: 64

Bits)

523 Title amended

Figure 13.69 MPX

Interface Timing 12

(Burst Write Cycle, AnW

= 1, One External Wait

Inserted, Bus Width: 32

Bits, Transfer Data Size:

64 Bits)

524 Title amended

13.3.16 Notes on

Usage

Synchronous DRAM

Mode Register Setting

(SH7750, SH7750S

Only):

543 Notes amended

3. If synchronous DRAM mode register setting is performed

immediately following write access to the on-chip peripheral

modules*2, the values written to the on-chip peripheral modules

cannot be guaranteed. Note that following power-on,

synchronous DRAM mode register settings should be

performed before accessing synchronous DRAM. After making

mode register settings, do not change them.

BSREQ Output in

Partial-Sharing Master

Mode

543, 544 Newly added

14.2.1 DMA Source

Address Registers 0–3

(SAR0–SAR3)

552 Description deleted

When transfer is performed from memory to an external device

with DACK in DDT mode, DTR format [31:0] is set in SAR0

[31:0]. For details, see Data Transfer Request Format in section

14.5.2, Pin in DDT Mode.

14.2.4 DMA Channel

Control Registers 0−3

(CHCR0−CHCR3)

Bits 13 and 12⎯Source

Address Mode 1 and 0

(SM1, SM0):

560 Description amended

These bits specify incrementing/decrementing of the DMA

transfer source address. The specification of these bits is

ignored when data is transferred from an external device to

external memory in single address mode. For channel 0, in

DDT mode these bits are set to SM1 = 0 and SM0 = 1 with the

DTR format.

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14.3.2 DMA Transfer

Requests

569 Description amended

The DS bit in CHCR0/CHCR1 is used to select either falling

edge detection or low level detection for the DREQ signal (level

detection when DS = 0, edge detection when DS = 1).

DREQ is accepted after a power-on reset if TE = 0, NMIF = 0,

and AE = 0, but transfer is not executed if DMA transfer is not

enabled (DE = 0 or DME = 0).

14.3.4 Types of DMA

Transfer

Table 14.7

Relationship between

DMA Transfer Type,

Request Mode, and Bus

Mode

582 Notes amended

Notes: 2. Auto-request, or on-chip peripheral module request

possible. If the transfer request source is the SCI

(SCIF), either the transfer source must be SCRDR1

(SCFRDR2) or the transfer destination must be

SCTDR1 (SCFTDR2).

Table 14.8 External

Request Transfer

Sources and

Destinations in Normal

DMA Mode

583 Title ameded

14.3.5 Number of Bus

Cycle States and DREQ

Pin Sampling Timing

585 Description added

DREQ Pin Sampling Timing: In external request mode, the

DREQ pin is sampled at the rising edge of CKIO clock pulses.

When DREQ input is detected, a DMAC bus cycle is generated

and DMA transfer executed after four CKIO cycles at the

earliest.

When falling edge detection is selected for DREQ, the DMAC

will recognize DREQ two cycles (CKIO) later because the

signal must pass through the asynchronous input

synchronization circuit. (There is a 1-cycle (CKIO) delay when

low-level detection is selected.)

The second and subsequent DREQ sampling operations are

performed one cycle after the start of the first DMAC transfer

bus cycle (in the case of single address mode).

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14.5.2 Pins in DDT

Mode

Figure 14.24 System

Configuration in On-

Demand Data Transfer

Mode

Figure amended

Synchronous

DRAM

DBREQ/DREQ0

BAVL/DRAK0

TR/DREQ1

TDACK/DACK0

ID1, ID0/DRAK1, DACK1

CKIO

D63–D0=DTR

External device

SH7750, SH7750S, SH7750R

A25–A0, RAS, CAS, WE, DQMn, CKE

• TR: Transfer request

signal

605

Description amended

Assertion of TR has the following different meanings.

⎯ In normal data transfer mode (channel 0, except channel 0),

TR is asserted, and at the same time the DTR format is

output, two cycles after BAVL is asserted.

608 Notes amended

7. For DTR format transfer when ID[1:0] = 00, input MD[1:0]

and SZ ≠ 101, 110.

14.8.3 Transfer

Channel Notification in

DDT Mode

Description amended

When the DMAC is set up for eight-channel external request

acceptance in DDT mode (DMAOR.DBL = 1), the ID [1:0] bits

and the simultaneous (on the timing of TDACK assertion)

assertion of ID2 from the BAVL (data bus available) pin are

used to notify the external device of the DMAC channel that is

to be used (see table 14.15).

Table 14.16 Function

of BAVL

648

Table amended

Function of B

BAVL

TDACK = High Bus available

14.9 Usage Notes

10. [SH7750 Only]

653 Newly added

15.1 Overview 655 Description amended

The SCI supports a smart card interface. This is a serial

communication function supporting a subset of the ISO/IEC

7816-3 (identification cards) standard. For details, see section

17, Smart Card Interface.

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15.3.3 Multiprocessor

Communication

Function

Multiprocessor Serial

Data Reception:

Figure 15.15 Sample

Multiprocessor Serial

Reception Flowchart (1)

702 to

704

Description of 1. and 2. added, and figure replaced

Figure 15.16 Example

of SCI Receive

Operation (Example with

8-Bit Data,

Multiprocessor Bit, One

Stop Bit)

706 Figure amended

0 D0 D1 D7 1 1 0 D0 D1 D7 0 1

MPB

MPIE

RDRF

ID1 ID2 Data2

0 D0 D1 D7 1 1 0 D0 D1 D7 0 1

MPB MPB

MPIE

RDRF

SCRDR1

value ID1

Serial

data

Start

bit Data (ID1) Stop

bit

Start

bit

Idle state

(mark state)

Data

(Data1)

Stop

bit

(b) Data matches station's ID

RXI interrupt request

(multiprocessor

interrupt)

MPIE = 0

SCRDR1 data read

and RDRF flag

cleared to 0 by RXI

interrupt handler

As data is not this

station's ID, MPIE

bit is set to 1 again

RXI interrupt

request

MPIE = 1

The RDRF flag

is cleared to 0

by the RXI

interrupt handler.

MPB

Serial

data

Start

bit Data (ID2) Stop

bit

Start

bit

Data

(Data2)

Stop

bit

Idle state

(mark state)

(a) Data does not match station's ID

SCRDR1

value

RXI interrupt request

(multiprocessor interrupt)

MPIE = 0

SCRDR1 data read

and RDRF flag

cleared to 0 by RXI

interrupt handler

As data matches this

station's ID, reception

continues and data is

received by RXI

interrupt handler

MPIE bit set

to 1 again

15.5 Usage Notes

Handling of TEND Flag

and TE Bit

720 Newly added

SH7750 Only 722 to

724

Newly added

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16.1.3 Pin

Configuration

Table 16.1 SCIF Pins

728 Note amended

Note: After a power-on reset, these pins function as mode input

pins MD1, MD2 and MD8. These pins can function as

serial pins by setting the SCIF operation with the TE, RE,

and CKE1 bits in SCSCR2 and the MCE bit in SCFCR2.

These pins are made to function as serial pins by

performing SCIF operation settings with the TE, RE, and

CKE1 bits in SCSCR2 and the MCE bit in SCFCR2.

Break state transmission and detection can be set in the

SCIF's SCSPTR2 register.

16.2.9 FIFO Control

Bits 5 and 4—Transmit

FIFO Data Number

Trigger (TTRG1,

TTRG0):

747 Description amended

• SH7750

Bit 5: TTRG1 Bit 4: TTRG0 Transmit Trigger Number

0 0 7 (9) (Initial value)

3 (13)

(15)

0 (16)

Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set.

• SH7750S/SH7750R

Bit 5: TTRG1 Bit 4: TTRG0 Transmit Trigger Number

0 0 8 (8) (Initial value)

4 (12)

1 2

(14)

1 (15)

Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set.

16.2.11 Serial Port

750, 751 Description amended

Bit: 7 6 5 4 3 2 1 0

RTSIO RTSDT CTSIO CTSDT — — SPB2IO

SPB2DT

Initial value: 0 — 0 — 0 — 0 —

R/W: R/W R/W R/W R/W R R R/W R/W

Bit 3—Reserved: This bit is always read as 0, and should only

be written with 0.

Bit 2—Reserved: The value of this bit is undefined when read.

The write value should always be 0.

17.1 Overview 775 Description amended

The serial communication interface (SCI) supports a subset of

the ISO/IEC 7816-3 (identification cards) standard as an

extended function.

17.1.3 Pin

Configuration

Table 17.1 Smart Card

Interface Pins

777 Note added

Note: The serial clock pin and transmit data pin function as

mode input pins MD0 and MD7 after a power-on reset

Rev.7.00 Oct. 10, 2008 Page xxviii of lxxxiv

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19.1.2 Block Diagram

Figure 19.1 Block

Diagram of INTC

826 Figure amended

Interrupt

request

IMASK

CPU

19.1.3 Pin

Configuration

Table 19.1 INTC Pins

827 Table amended

Pin Name Abbreviation I/O Function

Nonmaskable interrupt

input pin

NMI Input Input of nonmaskable interrupt request

signal

Interrupt input pins IRL3–IRL0Input Input of interrupt request signals

(maskable by IMASK in SR)

19.2.1 NMI Interrupt 828 Description amended

NMI interrupt exception handling does not affect the interrupt

mask level bits (IMASK) in the status register (SR).

19.2.2 IRL Interrupts 830 Description amended

The interrupt mask bits (IMASK) in the status register (SR) are

not affected by IRL interrupt handling.

19.2.3 On-Chip

Peripheral Module

Interrupts

831 Description amended

The interrupt mask bits (IMASK) in the status register (SR) are

not affected by on-chip peripheral module interrupt handling.

Rev.7.00 Oct. 10, 2008 Page xxix of lxxxiv

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19.4.1 Interrupt

Operation Sequence

843 Description and notes amended

3. The priority level of the interrupt selected by the interrupt

controller is compared with the interrupt mask bits (IMASK) in

the status register (SR) of the CPU. If the request priority

level is higher that the level in bits IMASK, the interrupt

controller accepts the interrupt and sends an interrupt

request signal to the CPU.

...

Notes: 1. The interrupt mask bits (IMASK) in the status register

(SR) are not changed by acceptance of an interrupt in

this LSI.

2. The interrupt source flag should be cleared in the

interrupt handler. To ensure that an interrupt request

that should have been cleared is not inadvertently

accepted again, read the interrupt source flag after it

has been cleared, then wait for the interval shown in

table 19.9 (Time for priority decision and SR mask bit

comparison) before clearing the BL bit or executing

an RTE instruction.

Figure 19.3 Interrupt

Operation Flowchart

844 Figure amended

Yes

Yes No

Yes

Save SR to SSR;

save PC to SPC

Set interrupt source

in INTEVT

Set BL, MD, RB bits

in SR to 1

Branch to exception

handler

Level 14

interrupt?

Level 1

interrupt?

IMASK =

level 13 or

lower?

IMASK =

level 0?

Yes

Level 15

interrupt?

IMASK* =

level 14 or

lower?

Note: * IMASK: Interrupt mask bits in status register (SR)

19.6 Usage Notes 847 to

849

Newly added

Rev.7.00 Oct. 10, 2008 Page xxx of lxxxiv

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20.2.1 Access to UBC

Control Registers

854 Description amended

2. Execute instructions requiring 5 states for execution after the

memory store instruction that updated the register. As the

CPU executes two instructions in parallel and a minimum of

0.5 state is required for execution of one instruction, 11

instructions must be inserted. The updated value will be valid

from the 6th state onward.

21.1.1 Features 879 Description amended

The high-performance user debug interface (H-UDI) is a serial

input/output interface supporting a subset of the JTAG, IEEE

1149.1, IEEE Standard Test Access Port and Boundary-Scan

Architecture.

21.1.3 Pin

Configuration

Table 21.1 H-UDI Pins

881, 882 Note amended

3. Fixed to the ground or connected to the same signal line as

RESET, or to a signal line that behaves in the same way.

However, there is a problem when this pin is fixed to the

ground. TRST is pulled up in the chip so, when this pin is fixed

to the ground via external connection, a minute current will flow.

The size of this current is determined by the rating of the pull-up

resistor . Although this current has no effect on the chip's

operation, unnecessary current will be dissipated.

Rev.7.00 Oct. 10, 2008 Page xxxi of lxxxiv

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21.2.5 Boundary Scan

(SH7750R Only)

887 Description amended

The boundary scan register (SDBSR) is a shift register that is

placed on the pads to control the chip's I/O pins. This register

can perform a boundary scan test equivalent to the JTAG (IEEE

Std 1149.1) standard using EXTEST, SAMPLE, and PRELOAD

commands.

888 Table amended

No. Pin Name Type

to TDO

Table 21.3

Configuration of the

Boundary Scan Register

345 CKIO2ENB IN

344 MD6/IOIS16 IN

890 Table amended

No. Pin Name Type

2 CS0 OUT

1 RDY IN

from TDI

21.3.4 Boundary Scan

(EXTEST,

SAMPLE/PRELOAD,

BYPASS) (SH7750R

Only)

893 Description amended

In the SH7750R, setting a command from the H-UDI in SDIR

can place the H-UDI pins in the boundary scan mode .

However, the following limitations apply.

...

4. With EXTEST, assert the MRESET pin (low), the RESET pin

(low), and the CA pin (high). With SAMPLE/PRELOAD,

assert the CA pin (high).

6. Deleted

21.4 Usage Notes 894 Description added

6. In BYPASS mode on the SH7750 or SH7750S, the contents

of the bypass register (SDBPR) are undefined in the

Capture-DR state. On the SH7750R, SDBPR has a value of

Rev.7.00 Oct. 10, 2008 Page xxxii of lxxxiv

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Section 22 Electrical

Characteristics

895 to

1016

Description of lead-free products added

HD6417750RBP240 (V)

HD6417750RF240 (V)

HD6417750RBG240 (V)

HD6417750RBP200 (V)

HD6417750RF200 (V)

HD6417750RBG200 (V)

HD6417750SBP200 (V)

HD6417750SF200 (V)

HD6417750BP200M (V)

HD6417750SF167 (V)

HD6417750F167 (V)

HD6417750SVF133 (V)

HD6417750SVBF133 (V)

HD6417750VF128 (V)

22.1 Absolute

Maximum Ratings

Table 22.1 Absolute

Maximum Ratings

895 Table and notes amended

Item Symbol Value Unit

I/O, PLL, RTC, CPG power supply

voltage

DDQ

DD-PLL1/2

DD-RTC

DD-CPG

–0.3 to 4.2, –0.3 to 4.6* V

Internal power supply voltage V

–0.3 to 2.5, –0.3 to 2.1* V

Operating temperature T

opr

–20 to 75 °C

Notes:

* HD6417750R only

22.2 DC

Characteristics

Table 22.2 DC

Characteristics

(HD6417750RBP240

(V),

HD6417750RBG240

(V))

896, 897 Title and table amended

= –2 mA Output

voltage

All output

pins V

= 2 mA

Item Symbol Test Conditions

Normal

operation

Ick = 240 MHz

Sleep mode

Current

dissipation

Table 22.3 DC

Characteristics

(HD6417750RF240 (V))

899 Table amended

Item Symbol Test Conditions

VOH I

OH = –2 mA Output

voltage

All output

pins VOL I

OL = 2 mA

Rev.7.00 Oct. 10, 2008 Page xxxiii of lxxxiv

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22.2 DC

Characteristics

Table 22.4 DC

Characteristics

(HD6417750RBP200

(V),

HD6417750RBG200

(V))

900, 901 Title and table amended

Item Symbol Test Conditions

= –2 mA Output

voltage

All output

pins V

= 2 mA

Table 22.5 DC

Characteristics

(HD6417750RF200 (V))

903 Table amended

Item Symbol Test Conditions

= –2 mA Output

voltage

All output

pins V

= 2 mA

Table 22.6 DC

Characteristics

(HD6417750SBP200

(V))

904 Table amended

Item Symbol Test Conditions

VOH I

OH = –2 mA Output

voltage

All output

pins VOL I

OL = 2 mA

Table 22.7 DC

Characteristics

(HD6417750SF200 (V))

906 Table amended

Item Symbol Test Conditions

VOH I

OH = –2 mA Output

voltage

All output

pins VOL I

OL = 2 mA

Table 22.8 DC

Characteristics

(HD6417750BP200M

(V))

908 Table amended

Item Symbol Test Conditions

= –2 mA Output

voltage

All output

pins V

= 2 mA

Table 22.9 DC

Characteristics

(HD6417750SF167 (V))

910 Table amended

Item Symbol Test Conditions

= –2 mA Output

voltage

All output

pins V

= 2 mA

Table 22.10 DC

Characteristics

(HD6417750SF167I (V))

— Deleted

Rev.7.00 Oct. 10, 2008 Page xxxiv of lxxxiv

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22.2 DC

Characteristics

Table 22.10 DC

Characteristics

(HD6417750F167 (V))

912 Table amended

Item Symbol Test Conditions

= –2 mA Output

voltage

All output

pins V

= 2 mA

Table 22.12 DC

Characteristics

(HD6417750F167I (V))

— Deleted

Table 22.11 DC

Characteristics

(HD6417750SVF133

(V))

914 Table amended

VOH I

OH = –2 mA Output

voltage

All output

pins VOL I

OL = 2 mA

Item Symbol Test Conditions

Normal

operation

= 133 MHz,

Bck

Ick

= 67 MHz

Current

dissipation

IDD

Table 22.12 DC

Characteristics

(HD6417750SVBT133

(V))

916 Table amended

Item Symbol Test Conditions

= –2 mA Output

voltage

All output

pins V

= 2 mA

Table 22.13 DC

Characteristics

(HD6417750VF128 (V))

918 Table amended

Item Symbol Test Conditions

VOH I

OH = –2 mA Output

voltage

All output

pins VOL I

OL = 2 mA

22.3 AC

Characteristics

Table 22.15 Clock

Timing

(HD6417750RBP240

(V),

HD6417750RBG240

(V))

920 Title amended

Rev.7.00 Oct. 10, 2008 Page xxxv of lxxxiv

REJ09B0366-0700

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22.3 AC

Characteristics

Table 22.17 Clock

Timing

(HD6417750BP200M

(V), HD6417750SBP200

(V), HD6417750RBP200

(V),

HD6417750RBG200

(V))

920 Title amended

Table 22.20 Clock

Timing

(HD6417750F167 (V),

HD6417750SF167 (V)

)

921 Title amended

22.3.1 Clock and

Control Signal Timing

Table 22.23 Clock and

Control Signal Timing

(HD6417750RBP240

(V),

HD6417750RBG240

(V))

922 Title amended

Table 22.25 Clock and

Control Signal Timing

(HD6417750RBP200

(V),

HD6417750RBG200

(V))

926 Title amended

Table 22.27 Clock and

Control Signal Timing

(HD6417750BP200M

(V), HD6417750SBP200

(V))

930 Description amended

VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF

Table 22.29 Clock and

Control Signal Timing

(HD6417750F167 (V),

HD6417750SF167 (V)

)

934, 935 Title, description, notes amended

HD6417750SF167 (V), HD6417750F167 (V):

VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF

Notes: When a crystal resonator is connected to EXTAL and

XTAL, the maximum frequency is 34 MHz. When a 3rd

overtone crystal resonator is used, an external tank

circuit is necessary.

Rev.7.00 Oct. 10, 2008 Page xxxvi of lxxxiv

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22.3.1 Clock and

Control Signal Timing

Table 22.30 Clock and

Control Signal Timing

(HD6417750SVF133,

HD6417750SVBT133

(V))

936, 937 Description and notes amended

HD6417750SVBT133 (V): VDDQ = 3.0 to 3.6 V, VDD = 1.5 V ,

Ta = –30 to +70°C, CL = 30 pF

HD6417750SVF133 (V): VDDQ = 3.0 to 3.6 V, VDD = 1.5 V,

Ta = –20 to +75°C, CL = 30 pF

Notes: When a crystal resonator is connected to EXTAL and

XTAL, the maximum frequency is 34 MHz. When a 3rd

overtone crystal resonator is used, an external tank

circuit is necessary.

Table 22.31 Clock and

Control Signal Timing

(HD6417750VF128)

939 Notes amended

Notes: When a crystal resonator is connected to EXTAL and

XTAL, the maximum frequency is 34 MHz. When a 3rd

overtone crystal resonator is used, an external tank

circuit is necessary.

Figure 22.11 Manual

Reset Input Timing

945 Figure amended

CKIO

SCK2

RESET

tSCK2RS tSCK2RH

tRESW

Bus idle

22.3.2 Control Signal

Timing

Table 22.32 Control

Signal Timing (1)

946 Table and note amended

HD6417750

RF240 (V)

HD6417750

RF200 (V)

* * * *

Item Symbol Min Max Min Max Min Max Min Max Unit Figure Notes

Bus tri-state

delay time

to standby

mode

BOFF2

— 2 — 2 — 2 — 2 t

cyc

22.14

(2)

Bus buffer

on time

BON1

— 12 — 12 — 12 — 12 ns 22.13

Bus buffer

on time from

standby

BON2

— 2 — 2 — 2 — 2 t

cyc

22.14

(2)

STATUS0/1

delay time

STD1

— 6 — 6 — 6 — 6 ns 22.14

(1)

STD2

— 2 — 2 — 2 — 2 t

cyc

22.14

(1), (2)

STD3

— 2 — 2 — 2 — 2 t

cyc

22.14

(2)

HD6417750

RBP240 (V)

HD6417750

RBG240 (V)

HD6417750

RBP200 (V)

HD6417750

RBG200 (V)

Note: * VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

Rev.7.00 Oct. 10, 2008 Page xxxvii of lxxxiv

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22.3.2 Control Signal

Timing

Table 22.32 Control

Signal Timing (2)

947 Table and notes amended

HD6417750

VF128 (V)

HD6417750

SVF133 (V)

HD6417750

SVBT133 (V)

HD6417750

F167 (V)

HD6417750

SF167 (V)

HD6417750

SF200 (V)

HD6417750

BP200M (V)

HD6417750

SBP200 (V)

Item Symbol Min Max Min Max Min Max Min Max Unit Figure Notes

Bus tri-state

delay time

to standby

mode

BOFF2

— 2 — 2 — 2 — 2 t

cyc

22.14

(2)

Bus buffer

on time

BON1

— 12 — 12 — 12 — 12 ns 22.13

Bus buffer

on time from

standby

BON2

— 2 — 2 — 2 — 2 t

cyc

22.14

(2)

STATUS0/1

delay time

STD1

— 6 — 6 — 6 — 6 ns 22.14

(1)

STD2

— 2 — 2 — 2 — 2 t

cyc

22.14

(1), (2)

STD3

— 2 — 2 — 2 — 2 t

cyc

22.14

(2)

Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

2. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

Figure 22.14 (1) Pin

Drive Timing for Reset

or Sleep Mode

948 Title amended and figure replaced

Figure 22.14 (2) Pin

Drive Timing for

Software Standby Mode

949 Figure replaced

22.3.3 Bus Timing

Table 22.33 Bus

Timing (1)

950, 951 Table and note amended

HD6417750

RBP240 (V)

HD6417750

RBG240 (V)

HD6417750

RBP200 (V)

HD6417750

RBG200 (V)

Item Symbol Min Max Min

Max

Note: * VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

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22.3.3 Bus Timing

Table 22.33 Bus

Timing (2)

952, 953 Table and notes amended

HD6417750S

VF133 (V)

HD6417750S

VBT133 (V)

HD6417750S

F167 (V)

HD6417750S

F200 (V)

Item Symbol Min Max Min Max

Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

2. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

Table 22.33 Bus

Timing (3)

954, 955 Table and notes amended

HD6417750

VF128 (V)

HD6417750

F167 (V)

Item Symbol Min Max Min Max

Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

2. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

Rev.7.00 Oct. 10, 2008 Page xxxix of lxxxiv

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22.3.3 Bus Timing

Figure 22.25

Synchronous DRAM

Normal Read Bus Cycle:

ACT + READ

Commands,

Burst (RASD = 1,

RCD[1:0] = 01, CAS

Latency = 3)

966 Title amended

Figure 22.26

Synchronous DRAM

Normal Read Bus Cycle:

PRE + ACT + READ

Commands, Burst

(RASD = 1, RCD[1:0] =

01, TPC[2:0] = 001,

CAS Latency = 3)

967 Title amended

Figure 22.27

Synchronous DRAM

Normal Read Bus Cycle:

READ Command, Burst

(RASD = 1, CAS

Latency = 3)

968 Title amended

Figure 22.30

Synchronous DRAM

Normal Write Bus Cycle:

ACT + WRITE

Commands, Burst

(RASD = 1, RCD[1:0] =

01, TRWL[2:0] = 010)

971 Title amended

Figure 22.31

Synchronous DRAM

Normal Write Bus Cycle:

PRE + ACT + WRITE

Commands, Burst

(RASD = 1, RCD[1:0] =

01, TPC[2:0] = 001,

TRWL[2:0] = 010)

972 Title amended

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22.3.3 Bus Timing

Figure 22.32

Synchronous DRAM

Normal Write Bus Cycle:

WRITE Command,

Burst (RASD = 1,

TRWL[2:0] = 010)

973 Title amended

Figure 22.52 PCMCIA

Memory Bus Cycle

(1) TED[2:0] = 000,

TEH[2:0] = 000, No Wait

(2) TED[2:0] = 001,

TEH[2:0] = 001, One

Internal Wait + One

External Wait

994 Notes amended

Note: *: SH7750S and SH7750R only

22.3.4 Peripheral

Module Signal Timing

Table 22.34 Peripheral

Module Signal Timing

(1)

1003,

1004

Table amended

HD6417750

RBP240 (V)

HD6417750

RBG240 (V)

HD6417750

RBP200 (V)

HD6417750

RBG200 (V)

Module Item Symbol Min Max Min Max

Table 22.34 Peripheral

Module Signal Timing

(2)

1005,

1006

Table and notes amended

HD6417750S

VF133 (V)

HD6417750S

VBT133 (V)

HD6417750

SF167 (V)

HD6417750

SF200 (V)

Module Item Symbol Min Max Min Max

Notes: 1. Pcyc: P clock cycles

2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

4. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

Rev.7.00 Oct. 10, 2008 Page xli of lxxxiv

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22.3.4 Peripheral

Module Signal Timing

Table 22.34 Peripheral

Module Signal Timing

(3)

1007 Table and notes amended

HD6417750S

VF133 (V)

HD6417750S

VBT133 (V)

HD6417750

SF167 (V)

HD6417750

SF200 (V)

Module Item Symbol Min Max Min Max

Notes: 1. Pcyc: P clock cycles

2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

4. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

Table 22.34 Peripheral

Module Signal Timing

(4)

1008,

1009

Table and notes amended

HD6417750

VF128 (V)

HD6417750

F167 (V)

Module Item Symbol Min Max Min Max

Notes: 1. Pcyc: P clock cycles

2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

4. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

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22.3.4 Peripheral

Module Signal Timing

Table 22.34 Peripheral

Module Signal Timing

(5)

1010 Table and notes amended

HD6417750

VF128 (V)

HD6417750

F167 (V)

*2*3

Module Item Symbol Min Max Min Max

Notes: 1. Pcyc: P clock cycles

2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

4. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C,

CL = 30 pF, PLL2 on

Appendix A Address

List

Table A.1 Address List

1017 to

1022

Table amended

Synchronization Clock

lclk → lck

Bclk → Bck

Pclk → Pck

Appendix B Package

Dimensions

Figure B.2 Package

Dimensions (256-Pin

BGA)

⎯ Package Dimensions deleted (Combined with figure B.1)

Figure B.4 Package

Dimensions (292-Pin

BGA)

1026 Newly added

Rev.7.00 Oct. 10, 2008 Page xliii of lxxxiv

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E.1 Pin States

Table E.1 Pin States in

Reset, Power-Down

State, and Bus-

Released State

1033 Table and notes amended

Reset

(Power-On)

Reset

(Manual)

Signal Name I/O Master Slave Master Slave Standby

Bus

Released

Hardware

Standby

D0–D7 I/

O Z Z Z*

D8–D15 O Z Z Z*

D16–D23 O Z Z Z*

D24–D31 O Z Z Z*

D32–D51 O Z Z Z*

D52–D55 O Z Z Z*

D56–D63 O Z Z Z*

A0, A1, A18–A25 O

P P Z*

A2–A17 P P Z*

RESET I I I I I I I

BACK/BSREQ O H H H H H O Z

BREQ/BSACK P P I*

BS O H PZ H Z*

CKE H H O O L O Z

CS6–CS0H PZ H Z*

RAS H PZ O Z*

RD/CASS/FRAME H PZ O Z*

RD/WR O H PZ H Z*

RDY PI PI I*

WE7/CAS7/DQM7 H PZ O Z*

WE6/CAS6/DQM6 H PZ O Z*

WE5/CAS5/DQM5 H PZ O Z*

WE4/CAS4/DQM4 H PZ O Z*

WE3/CAS3/DQM3 H PZ O Z*

WE2/CAS2/DQM2 H PZ O Z*

Rev.7.00 Oct. 10, 2008 Page xliv of lxxxiv

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E.1 Pin States

Table E.1 Pin States in

Reset, Power-Down

State, and Bus-

Released State

1034

Reset

(Power-On)

Reset

(Manual)

Signal Name I/O Master Slave Master Slave Standby

Bus

Released

Hardware

Standby

WE1/CAS1/DQM1 H PZ O Z*13 Z

*13O*4 Z

*13O*4

WE0/CAS0/DQM0 H PZ O Z*13 Z

*13O*4 Z

*13O*4

DACK1–DACK0 O L L L L Z*11O*7 O

MD7/TXD I/O

I/O

PI*14 PI*14 Z

*11 Z

*11K*18O*7Z*11K*18O*7

MD6/IOIS16 I PI*14 PI*14 I

*12 I

*12 Z

*12 I

*12

MD5/RAS2I/O *1 PI*14 PI*14 Z

*13O*5 Z

*13 Z

*13O*4 Z

*13O*4

MD4/CE2BI/O *3 PI*14 PI*14 Z

*13H*6 Z

*13 Z

*13H*6 Z

*13

MD3/CE2AI/O

I/O

I/O*2 PI*14 PI*14 Z

*13H*6 Z

*13 Z

*13H*6 Z

*13

CKIO O O O O*10Z*10 O

*10Z*10 PZ O*10Z*10

STATUS1–STATUS0 O O O O O O O *16

IRL3–IRL0 I

PI PI I*12 I

*12 I

*12

NMI PI PI I*12 I

*12 I

*12

DREQ1–DREQ0 PI PI I*11 I

*11 Z

*11 I

*11

DRAK1–DRAK0 O L L L L Z*11O*7 O

MD0/SCK PI*14 PI*14 I

*11 I

*11KZ *18O*7*11OK*18

RXD PI PI I*11 I

*11 Z

*11 I

*11

SCK2/MRESET PI PI I*11 I

*11 I

*11

MD1/TXD2 I/O PI*14 PI*14 Z

*11 Z

*11 K*18

O*7 O

Z*11 K*18

MD2/RXD2 PI*14 PI*14 I

*11 I

*11 Z

*11 I

*11

CTS2 I/O PI PI I*11 I

*11 Z

*11K*18 I

*11K*18

MD8/RTS2 I/O PI*14 PI*14 I

*11 I

*11 Z

*11K*18 I

*11K*18

TCLK I/O PI PI I*11 I

*11 K

*11O*17 I

*11O*17

TDO O O O O O O

TMS I PI PI PI PZ PI

TCK I PI PI PI PZ PI

TDI I PI PI PI PZ PI

TRST I PI PI PI

PI PZ PI

CKIO2*21 OPZ

*20O*9PZ*20O*9PZ*20

920

PZ*20

920

PZ PZ*20O*9*20

1035

Reset

(Power-On)

Reset

(Manual)

Signal Name I/O Master Slave Master Slave Standby

Bus

Released

Hardware

Standby

RD2*

PZ*

RD/WR2*

PZ*

CKIO2ENB I PI PI PI PI PI PI Z

CA I I I I I I I

ASEBRK/BRKACK I/O PI*

PI*

Legend:

I: Input (not Pulled Up)

O: Output

Z: High-impedance (not Pulled Up)

H: High-level output

L: Low-level output

K: Output state held

Rev.7.00 Oct. 10, 2008 Page xlv of lxxxiv

REJ09B0366-0700

Item Page Revision (See Manual for Details)

E.1 Pin States

Table E.1 Pin States in

Reset, Power-Down

State, and Bus-

Released State

1035,

1036

PI: Input (Pulled Up)

PZ: High-impedance (Pulled Up)

Notes: 1. Output when area 2 is used as DRAM.

2. Output when area 5 is used as PCMCIA.

3. Output when area 6 is used as PCMCIA.

4. Z (I) or O on refresh operations, depending on

5. Depends on refresh operations.

6. Z (I) or H (state held), depending on register setting

(BCR1.HIZMEM).

7. Z or O, depending on register setting (STBCR.PHZ).

8. Output when refreshing is set.

9. Operation in respective state when CKIO2ENB = 0

(SH7750/SH7750S) (High-level outputs as

SH7750R).

10. PZ or O, depending on register setting

(FRQCR.CKOEN).

11. Pulled up or not pulled up, depending on register

setting (STBCR.PPU).

12. Pulled up or not pulled up, depending on register

setting (BCR1.IPUP).

13. Pulled up or not pulled up, depending on register

setting (BCR1.OPUP).

14. Pulled up with a built-in pull-up resistance. However

it, cannot use for fixation of an input MD pin at the

time of power-on reset. Pull up or down outside this

LSI.

15. Output when refreshing is set (SH7750R only).

16. Z or O, depending on register setting

(STBCR2.STHZ) (SH7750R only).

17. Z or O, depending on register setting (TOCR,

TCOE)

18. Output state held when used as port.

19. Pulled up or not pulled up, depending on register

setting (BCR1.DPUP) (SH7750R only).

20. Z when CKIO2ENB = 1

21. BGA Package only.

22. Depends on Emulator operations.

Rev.7.00 Oct. 10, 2008 Page xlvi of lxxxiv

REJ09B0366-0700

Item Page Revision (See Manual for Details)

E.2 Handling of

Unused Pins

1036 Note added

Note: To prevent unwanted effects on other pins when using

external pull-up or pull-down resistors, use independent pull-up

or pull-down resistors for individual pins.

Appendix F

Synchronous DRAM

Address Multiplexing

Tables

(17) BUS 64 (128 M: 4

M × 8 b × 4) × 8*

(SH7750R only)

1053 Title amended

Appendix H Power-On

and Power-Off

Procedures

1061 to

1063

Replaced

Appendix I Product

Lineup

Table I.1 SH7750/

SH7750S/SH7750R

Product Lineup

1065 Table amended and note added

Appendix J Version

Registers

1067 Newly added

All trademarks and registered trademarks are the property of their respective owners.

Rev.7.00 Oct. 10, 2008 Page xlvii of lxxxiv

REJ09B0366-0700

Contents

Section 1 Overview............................................................................................................. 1

1.1 SH7750, SH7750S, SH7750R Groups Features ............................................................... 1

1.2 Block Diagram .................................................................................................................. 9

1.3 Pin Arrangement ............................................................................................................... 10

1.4 Pin Functions .................................................................................................................... 14

1.4.1 Pin Functions (256-Pin BGA).............................................................................. 14

1.4.2 Pin Functions (208-Pin QFP)............................................................................... 24

1.4.3 Pin Functions (264-Pin CSP) ............................................................................... 32

1.4.4 Pin Functions (292-Pin BGA).............................................................................. 42

Section 2 Programming Model........................................................................................ 53

2.1 Data Formats..................................................................................................................... 53

2.2 Register Configuration...................................................................................................... 54

2.2.1 Privileged Mode and Banks ................................................................................. 54

2.2.2 General Registers................................................................................................. 57

2.2.3 Floating-Point Registers....................................................................................... 59

2.2.4 Control Registers ................................................................................................. 62

2.2.5 System Registers.................................................................................................. 63

2.3 Memory-Mapped Registers............................................................................................... 65

2.4 Data Format in Registers................................................................................................... 66

2.5 Data Formats in Memory .................................................................................................. 66

2.6 Processor States................................................................................................................. 67

2.7 Processor Modes ............................................................................................................... 69

Section 3 Memory Management Unit (MMU) ........................................................... 71

3.1 Overview........................................................................................................................... 71

3.1.1 Features................................................................................................................ 71

3.1.2 Role of the MMU................................................................................................. 71

3.1.3 Register Configuration......................................................................................... 74

3.1.4 Caution................................................................................................................. 74

3.2 Register Descriptions ........................................................................................................ 75

3.3 Address Space................................................................................................................... 79

3.3.1 Physical Address Space ....................................................................................... 79

3.3.2 External Memory Space....................................................................................... 82

3.3.3 Virtual Address Space.......................................................................................... 83

3.3.4 On-Chip RAM Space........................................................................................... 84

3.3.5 Address Translation ............................................................................................. 85

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REJ09B0366-0700

3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode ................... 85

3.3.7 Address Space Identifier (ASID) ......................................................................... 85

3.4 TLB Functions .................................................................................................................. 86

3.4.1 Unified TLB (UTLB) Configuration ................................................................... 86

3.4.2 Instruction TLB (ITLB) Configuration................................................................ 90

3.4.3 Address Translation Method................................................................................ 90

3.5 MMU Functions................................................................................................................ 93

3.5.1 MMU Hardware Management............................................................................. 93

3.5.2 MMU Software Management .............................................................................. 93

3.5.3 MMU Instruction (LDTLB)................................................................................. 93

3.5.4 Hardware ITLB Miss Handling ........................................................................... 94

3.5.5 Avoiding Synonym Problems.............................................................................. 95

3.6 MMU Exceptions.............................................................................................................. 96

3.6.1 Instruction TLB Multiple Hit Exception.............................................................. 96

3.6.2 Instruction TLB Miss Exception.......................................................................... 96

3.6.3 Instruction TLB Protection Violation Exception ................................................. 98

3.6.4 Data TLB Multiple Hit Exception ....................................................................... 98

3.6.5 Data TLB Miss Exception ................................................................................... 99

3.6.6 Data TLB Protection Violation Exception........................................................... 100

3.6.7 Initial Page Write Exception................................................................................ 101

3.7 Memory-Mapped TLB Configuration............................................................................... 102

3.7.1 ITLB Address Array ............................................................................................ 103

3.7.2 ITLB Data Array 1............................................................................................... 104

3.7.3 ITLB Data Array 2............................................................................................... 105

3.7.4 UTLB Address Array........................................................................................... 106

3.7.5 UTLB Data Array 1 ............................................................................................. 107

3.7.6 UTLB Data Array 2 ............................................................................................. 108

3.8 Usage Notes ...................................................................................................................... 109

Section 4 Caches.................................................................................................................. 111

4.1 Overview........................................................................................................................... 111

4.1.1 Features................................................................................................................ 111

4.1.2 Register Configuration......................................................................................... 113

4.2 Register Descriptions........................................................................................................ 114

4.3 Operand Cache (OC)......................................................................................................... 116

4.3.1 Configuration....................................................................................................... 116

4.3.2 Read Operation .................................................................................................... 120

4.3.3 Write Operation ................................................................................................... 121

4.3.4 Write-Back Buffer ............................................................................................... 122

4.3.5 Write-Through Buffer.......................................................................................... 122

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REJ09B0366-0700

4.3.6 RAM Mode.......................................................................................................... 123

4.3.7 OC Index Mode.................................................................................................... 124

4.3.8 Coherency between Cache and External Memory ............................................... 125

4.3.9 Prefetch Operation ............................................................................................... 125

4.3.10 Notes on Using Cache Enhanced Mode (SH7750R Only)................................... 125

4.4 Instruction Cache (IC)....................................................................................................... 128

4.4.1 Configuration....................................................................................................... 128

4.4.2 Read Operation .................................................................................................... 130

4.4.3 IC Index Mode ..................................................................................................... 131

4.5 Memory-Mapped Cache Configuration (SH7750, SH7750S) .......................................... 131

4.5.1 IC Address Array ................................................................................................. 131

4.5.2 IC Data Array....................................................................................................... 132

4.5.3 OC Address Array................................................................................................ 133

4.5.4 OC Data Array ..................................................................................................... 135

4.6 Memory-Mapped Cache Configuration (SH7750R)......................................................... 136

4.6.1 IC Address Array ................................................................................................. 137

4.6.2 IC Data Array....................................................................................................... 138

4.6.3 OC Address Array................................................................................................ 139

4.6.4 OC Data Array ..................................................................................................... 141

4.6.5 Summary of the Memory-Mapping of the OC..................................................... 142

4.7 Store Queues ..................................................................................................................... 142

4.7.1 SQ Configuration................................................................................................. 142

4.7.2 SQ Writes............................................................................................................. 143

4.7.3 Transfer to External Memory............................................................................... 143

4.7.4 SQ Protection....................................................................................................... 145

4.7.5 Reading the SQs (SH7750R Only) ...................................................................... 145

4.7.6 SQ Usage Notes ................................................................................................... 146

Section 5 Exceptions........................................................................................................... 149

5.1 Overview........................................................................................................................... 149

5.1.1 Features................................................................................................................ 149

5.1.2 Register Configuration......................................................................................... 149

5.2 Register Descriptions ........................................................................................................ 150

5.3 Exception Handling Functions.......................................................................................... 151

5.3.1 Exception Handling Flow .................................................................................... 151

5.3.2 Exception Handling Vector Addresses ................................................................ 151

5.4 Exception Types and Priorities ......................................................................................... 152

5.5 Exception Flow ................................................................................................................. 155

5.5.1 Exception Flow .................................................................................................... 155

5.5.2 Exception Source Acceptance.............................................................................. 156

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REJ09B0366-0700

5.5.3 Exception Requests and BL Bit ........................................................................... 158

5.5.4 Return from Exception Handling......................................................................... 158

5.6 Description of Exceptions................................................................................................. 158

5.6.1 Resets................................................................................................................... 159

5.6.2 General Exceptions .............................................................................................. 164

5.6.3 Interrupts.............................................................................................................. 178

5.6.4 Priority Order with Multiple Exceptions.............................................................. 181

5.7 Usage Notes ...................................................................................................................... 182

5.8 Restrictions ....................................................................................................................... 183

Section 6 Floating-Point Unit (FPU) ............................................................................. 185

6.1 Overview........................................................................................................................... 185

6.2 Data Formats..................................................................................................................... 185

6.2.1 Floating-Point Format.......................................................................................... 185

6.2.2 Non-Numbers (NaN) ........................................................................................... 187

6.2.3 Denormalized Numbers ....................................................................................... 188

6.3 Registers............................................................................................................................ 189

6.3.1 Floating-Point Registers....................................................................................... 189

6.3.2 Floating-Point Status/Control Register (FPSCR)................................................. 191

6.3.3 Floating-Point Communication Register (FPUL) ................................................ 192

6.4 Rounding........................................................................................................................... 193

6.5 Floating-Point Exceptions................................................................................................. 193

6.6 Graphics Support Functions.............................................................................................. 195

6.6.1 Geometric Operation Instructions ........................................................................ 195

6.6.2 Pair Single-Precision Data Transfer..................................................................... 196

6.7 Usage Notes ...................................................................................................................... 197

6.7.1 Rounding Mode and Underflow Flag .................................................................. 197

6.7.2 Setting of Overflow Flag by FIPR or FTRV Instruction ..................................... 198

6.7.3 Sign of Operation Result when Using FIPR or FTRV Instruction....................... 199

6.7.4 Notes on Double-Precision FADD and FSUB Instructions ................................. 199

6.7.5 Notes on FPU Double-Precision Operation Instructions (SH7750 Only)............ 200

Section 7 Instruction Set.................................................................................................... 209

7.1 Execution Environment..................................................................................................... 209

7.2 Addressing Modes ............................................................................................................ 211

7.3 Instruction Set................................................................................................................... 215

7.4 Usage Notes ...................................................................................................................... 227

7.4.1 Notes on TRAPA Instruction, SLEEP Instruction, and Undefined Instruction

(H'FFFD).............................................................................................................. 227

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REJ09B0366-0700

Section 8 Pipelining ............................................................................................................ 231

8.1 Pipelines............................................................................................................................ 231

8.2 Parallel-Executability........................................................................................................ 238

8.3 Execution Cycles and Pipeline Stalling ............................................................................ 242

8.4 Usage Notes ...................................................................................................................... 258

Section 9 Power-Down Modes ........................................................................................ 259

9.1 Overview........................................................................................................................... 259

9.1.1 Types of Power-Down Modes ............................................................................. 259

9.1.2 Register Configuration......................................................................................... 261

9.1.3 Pin Configuration................................................................................................. 261

9.2 Register Descriptions ........................................................................................................ 262

9.2.1 Standby Control Register (STBCR)..................................................................... 262

9.2.2 Peripheral Module Pin High Impedance Control................................................. 264

9.2.3 Peripheral Module Pin Pull-Up Control............................................................... 265

9.2.4 Standby Control Register 2 (STBCR2)................................................................ 265

9.2.5 Clock-Stop Register 00 (CLKSTP00) (SH7750R Only) ..................................... 267

9.2.6 Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only) .................... 268

9.3 Sleep Mode ....................................................................................................................... 268

9.3.1 Transition to Sleep Mode..................................................................................... 268

9.3.2 Exit from Sleep Mode.......................................................................................... 269

9.4 Deep Sleep Mode.............................................................................................................. 269

9.4.1 Transition to Deep Sleep Mode............................................................................ 269

9.4.2 Exit from Deep Sleep Mode................................................................................. 269

9.5 Standby Mode ................................................................................................................... 270

9.5.1 Transition to Standby Mode................................................................................. 270

9.5.2 Exit from Standby Mode...................................................................................... 271

9.5.3 Clock Pause Function .......................................................................................... 271

9.6 Module Standby Function................................................................................................. 272

9.6.1 Transition to Module Standby Function .............................................................. 272

9.6.2 Exit from Module Standby Function.................................................................... 273

9.7 Hardware Standby Mode (SH7750S, SH7750R Only) ..................................................... 274

9.7.1 Transition to Hardware Standby Mode................................................................ 274

9.7.2 Exit from Hardware Standby Mode ..................................................................... 274

9.7.3 Usage Notes ......................................................................................................... 275

9.8 STATUS Pin Change Timing ........................................................................................... 275

9.8.1 In Reset ................................................................................................................ 276

9.8.2 In Exit from Standby Mode ................................................................................. 277

9.8.3 In Exit from Sleep Mode...................................................................................... 279

9.8.4 In Exit from Deep Sleep Mode ............................................................................ 281

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REJ09B0366-0700

9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only) ........................... 283

9.9 Usage Notes ...................................................................................................................... 286

9.9.1 Note on Current Consumption ............................................................................. 286

Section 10 Clock Oscillation Circuits ........................................................................... 287

10.1 Overview........................................................................................................................... 287

10.1.1 Features................................................................................................................ 287

10.2 Overview of CPG.............................................................................................................. 289

10.2.1 Block Diagram of CPG........................................................................................ 289

10.2.2 CPG Pin Configuration........................................................................................ 292

10.2.3 CPG Register Configuration ................................................................................ 292

10.3 Clock Operating Modes .................................................................................................... 293

10.4 CPG Register Description................................................................................................. 295

10.4.1 Frequency Control Register (FRQCR)................................................................. 295

10.5 Changing the Frequency ................................................................................................... 298

10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off) ........... 298

10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)............ 298

10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On) ...................... 299

10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off) ..................... 299

10.5.5 Changing CPU or Peripheral Module Clock Division Ratio ............................... 299

10.6 Output Clock Control........................................................................................................ 299

10.7 Overview of Watchdog Timer .......................................................................................... 300

10.7.1 Block Diagram..................................................................................................... 300

10.7.2 Register Configuration......................................................................................... 301

10.8 WDT Register Descriptions .............................................................................................. 301

10.8.1 Watchdog Timer Counter (WTCNT)................................................................... 301

10.8.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 302

10.8.3 Notes on Register Access..................................................................................... 305

10.9 Using the WDT ................................................................................................................. 305

10.9.1 Standby Clearing Procedure ................................................................................ 305

10.9.2 Frequency Changing Procedure........................................................................... 306

10.9.3 Using Watchdog Timer Mode.............................................................................. 306

10.9.4 Using Interval Timer Mode ................................................................................. 307

10.10 Notes on Board Design ..................................................................................................... 307

10.11 Usage Notes ...................................................................................................................... 309

10.11.1 Invalid Manual Reset Triggered by Watchdog Timer (SH7750 and SH7750S).. 309

Section 11 Realtime Clock (RTC).................................................................................. 311

11.1 Overview........................................................................................................................... 311

11.1.1 Features................................................................................................................ 311

Rev.7.00 Oct. 10, 2008 Page liii of lxxxiv

REJ09B0366-0700

11.1.2 Block Diagram..................................................................................................... 312

11.1.3 Pin Configuration................................................................................................. 313

11.1.4 Register Configuration......................................................................................... 313

11.2 Register Descriptions ........................................................................................................ 315

11.2.1 64 Hz Counter (R64CNT).................................................................................... 315

11.2.2 Second Counter (RSECCNT) .............................................................................. 316

11.2.3 Minute Counter (RMINCNT) .............................................................................. 316

11.2.4 Hour Counter (RHRCNT).................................................................................... 317

11.2.5 Day-of-Week Counter (RWKCNT)..................................................................... 317

11.2.6 Day Counter (RDAYCNT) .................................................................................. 318

11.2.7 Month Counter (RMONCNT) ............................................................................. 318

11.2.8 Year Counter (RYRCNT) .................................................................................... 319

11.2.9 Second Alarm Register (RSECAR) ..................................................................... 320

11.2.10 Minute Alarm Register (RMINAR)..................................................................... 320

11.2.11 Hour Alarm Register (RHRAR)........................................................................... 321

11.2.12 Day-of-Week Alarm Register (RWKAR)............................................................ 321

11.2.13 Day Alarm Register (RDAYAR)......................................................................... 322

11.2.14 Month Alarm Register (RMONAR) .................................................................... 323

11.2.15 RTC Control Register 1 (RCR1).......................................................................... 323

11.2.16 RTC Control Register 2 (RCR2).......................................................................... 325

11.2.17 RTC Control Register 3 (RCR3) and Year-Alarm Register (RYRAR)

(SH7750R Only) .................................................................................................. 327

11.3 Operation........................................................................................................................... 329

11.3.1 Time Setting Procedures...................................................................................... 329

11.3.2 Time Reading Procedures .................................................................................... 330

11.3.3 Alarm Function .................................................................................................... 332

11.4 Interrupts........................................................................................................................... 333

11.5 Usage Notes ...................................................................................................................... 333

11.5.1 Register Initialization........................................................................................... 333

11.5.2 Carry Flag and Interrupt Flag in Standby Mode .................................................. 333

11.5.3 Crystal Oscillator Circuit ..................................................................................... 333

11.5.4 RTC Register Settings (SH7750 only)................................................................. 334

Section 12 Timer Unit (TMU) ......................................................................................... 337

12.1 Overview........................................................................................................................... 337

12.1.1 Features................................................................................................................ 337

12.1.2 Block Diagram..................................................................................................... 338

12.1.3 Pin Configuration................................................................................................. 338

12.1.4 Register Configuration......................................................................................... 339

12.2 Register Descriptions ........................................................................................................ 341

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REJ09B0366-0700

12.2.1 Timer Output Control Register (TOCR).............................................................. 341

12.2.2 Timer Start Register (TSTR) ............................................................................... 342

12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only) .............................................. 343

12.2.4 Timer Constant Registers (TCOR) ...................................................................... 344

12.2.5 Timer Counters (TCNT) ...................................................................................... 344

12.2.6 Timer Control Registers (TCR) ........................................................................... 345

12.2.7 Input Capture Register 2 (TCPR2)....................................................................... 350

12.3 Operation .......................................................................................................................... 350

12.3.1 Counter Operation................................................................................................ 350

12.3.2 Input Capture Function ........................................................................................ 353

12.4 Interrupts........................................................................................................................... 355

12.5 Usage Notes ...................................................................................................................... 355

12.5.1 Register Writes .................................................................................................... 355

12.5.2 Underflow Flag Writes (SH7750 only)................................................................ 356

12.5.3 TCNT Register Reads.......................................................................................... 356

12.5.4 Resetting the RTC Frequency Divider................................................................. 356

12.5.5 External Clock Frequency.................................................................................... 356

Section 13 Bus State Controller (BSC)......................................................................... 357

13.1 Overview........................................................................................................................... 357

13.1.1 Features................................................................................................................ 357

13.1.2 Block Diagram..................................................................................................... 359

13.1.3 Pin Configuration................................................................................................. 360

13.1.4 Register Configuration......................................................................................... 364

13.1.5 Overview of Areas............................................................................................... 365

13.1.6 PCMCIA Support ................................................................................................ 368

13.2 Register Descriptions........................................................................................................ 372

13.2.1 Bus Control Register 1 (BCR1) ........................................................................... 372

13.2.2 Bus Control Register 2 (BCR2) ........................................................................... 381

13.2.3 Bus Control Register 3 (BCR3) (SH7750R Only)............................................... 383

13.2.4 Bus Control Register 4 (BCR4) (SH7750R Only)............................................... 384

13.2.5 Wait Control Register 1 (WCR1)......................................................................... 388

13.2.6 Wait Control Register 2 (WCR2)......................................................................... 391

13.2.7 Wait Control Register 3 (WCR3)......................................................................... 399

13.2.8 Memory Control Register (MCR)........................................................................ 401

13.2.9 PCMCIA Control Register (PCR)........................................................................ 409

13.2.10 Synchronous DRAM Mode Register (SDMR) .................................................... 413

13.2.11 Refresh Timer Control/Status Register (RTCSR)................................................ 415

13.2.12 Refresh Timer Counter (RTCNT)........................................................................ 418

13.2.13 Refresh Time Constant Register (RTCOR) ......................................................... 419

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13.2.14 Refresh Count Register (RFCR) .......................................................................... 420

13.2.15 Notes on Accessing Refresh Control Registers.................................................... 420

13.3 Operation........................................................................................................................... 421

13.3.1 Endian/Access Size and Data Alignment............................................................. 421

13.3.2 Areas .................................................................................................................... 433

13.3.3 SRAM Interface................................................................................................... 438

13.3.4 DRAM Interface .................................................................................................. 447

13.3.5 Synchronous DRAM Interface............................................................................. 465

13.3.6 Burst ROM Interface............................................................................................ 497

13.3.7 PCMCIA Interface ............................................................................................... 500

13.3.8 MPX Interface...................................................................................................... 511

13.3.9 Byte Control SRAM Interface ............................................................................. 529

13.3.10 Waits between Access Cycles.............................................................................. 534

13.3.11 Bus Arbitration..................................................................................................... 536

13.3.12 Master Mode ........................................................................................................ 539

13.3.13 Slave Mode .......................................................................................................... 540

13.3.14 Partial-Sharing Master Mode ............................................................................... 541

13.3.15 Cooperation between Master and Slave............................................................... 542

13.3.16 Notes on Usage .................................................................................................... 543

Section 14 Direct Memory Access Controller (DMAC).......................................... 545

14.1 Overview........................................................................................................................... 545

14.1.1 Features................................................................................................................ 545

14.1.2 Block Diagram (SH7750, SH7750S) ................................................................... 547

14.1.3 Pin Configuration (SH7750, SH7750S)............................................................... 549

14.1.4 Register Configuration (SH7750, SH7750S)....................................................... 550

14.2 Register Descriptions (SH7750, SH7750S) ...................................................................... 552

14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 552

14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3).................................. 553

14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......................... 554

14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... 555

14.2.5 DMA Operation Register (DMAOR)................................................................... 564

14.3 Operation........................................................................................................................... 567

14.3.1 DMA Transfer Procedure..................................................................................... 567

14.3.2 DMA Transfer Requests ...................................................................................... 569

14.3.3 Channel Priorities................................................................................................. 573

14.3.4 Types of DMA Transfer....................................................................................... 576

14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing .......................... 585

14.3.6 Ending DMA Transfer ......................................................................................... 599

14.4 Examples of Use ............................................................................................................... 602

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14.4.1 Examples of Transfer between External Memory and an External Device with

DACK.................................................................................................................. 602

14.5 On-Demand Data Transfer Mode (DDT Mode)................................................................ 603

14.5.1 Operation ............................................................................................................. 603

14.5.2 Pins in DDT Mode............................................................................................... 605

14.5.3 Transfer Request Acceptance on Each Channel .................................................. 608

14.5.4 Notes on Use of DDT Module ............................................................................. 631

14.6 Configuration of the DMAC (SH7750R).......................................................................... 634

14.6.1 Block Diagram of the DMAC.............................................................................. 634

14.6.2 Pin Configuration (SH7750R) ............................................................................. 636

14.6.3 Register Configuration (SH7750R) ..................................................................... 637

14.7 Register Descriptions (SH7750R)..................................................................................... 640

14.7.1 DMA Source Address Registers 0–7 (SAR0–SAR7) .......................................... 640

14.7.2 DMA Destination Address Registers 0–7 (DAR0–DAR7).................................. 640

14.7.3 DMA Transfer Count Registers 0–7 (DMATCR0–DMATCR7)......................... 641

14.7.4 DMA Channel Control Registers 0–7 (CHCR0–CHCR7)................................... 641

14.7.5 DMA Operation Register (DMAOR) .................................................................. 645

14.8 Operation (SH7750R) ....................................................................................................... 647

14.8.1 Channel Specification for a Normal DMA Transfer............................................ 647

14.8.2 Channel Specification for DDT-Mode DMA Transfer ........................................ 647

14.8.3 Transfer Channel Notification in DDT Mode...................................................... 648

14.8.4 Clearing Request Queues by DTR Format........................................................... 649

14.8.5 Interrupt-Request Codes ...................................................................................... 649

14.9 Usage Notes ...................................................................................................................... 652

Section 15 Serial Communication Interface (SCI) .................................................... 655

15.1 Overview........................................................................................................................... 655

15.1.1 Features................................................................................................................ 655

15.1.2 Block Diagram..................................................................................................... 657

15.1.3 Pin Configuration................................................................................................. 658

15.1.4 Register Configuration......................................................................................... 658

15.2 Register Descriptions........................................................................................................ 659

15.2.1 Receive Shift Register (SCRSR1)........................................................................ 659

15.2.2 Receive Data Register (SCRDR1) ....................................................................... 660

15.2.3 Transmit Shift Register (SCTSR1) ...................................................................... 660

15.2.4 Transmit Data Register (SCTDR1)...................................................................... 661

15.2.5 Serial Mode Register (SCSMR1)......................................................................... 661

15.2.6 Serial Control Register (SCSCR1)....................................................................... 664

15.2.7 Serial Status Register (SCSSR1).......................................................................... 667

15.2.8 Serial Port Register (SCSPTR1) .......................................................................... 671

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15.2.9 Bit Rate Register (SCBRR1)................................................................................ 676

15.3 Operation........................................................................................................................... 684

15.3.1 Overview.............................................................................................................. 684

15.3.2 Operation in Asynchronous Mode ....................................................................... 686

15.3.3 Multiprocessor Communication Function............................................................ 698

15.3.4 Operation in Synchronous Mode ......................................................................... 707

15.4 SCI Interrupt Sources and DMAC .................................................................................... 717

15.5 Usage Notes ...................................................................................................................... 718

Section 16 Serial Communication Interface with FIFO (SCIF)............................. 725

16.1 Overview........................................................................................................................... 725

16.1.1 Features................................................................................................................ 725

16.1.2 Block Diagram..................................................................................................... 727

16.1.3 Pin Configuration................................................................................................. 728

16.1.4 Register Configuration......................................................................................... 729

16.2 Register Descriptions ........................................................................................................ 729

16.2.1 Receive Shift Register (SCRSR2)........................................................................ 729

16.2.2 Receive FIFO Data Register (SCFRDR2) ........................................................... 730

16.2.3 Transmit Shift Register (SCTSR2) ...................................................................... 730

16.2.4 Transmit FIFO Data Register (SCFTDR2) .......................................................... 731

16.2.5 Serial Mode Register (SCSMR2)......................................................................... 731

16.2.6 Serial Control Register (SCSCR2)....................................................................... 734

16.2.7 Serial Status Register (SCFSR2).......................................................................... 737

16.2.8 Bit Rate Register (SCBRR2)................................................................................ 744

16.2.9 FIFO Control Register (SCFCR2) ....................................................................... 745

16.2.10 FIFO Data Count Register (SCFDR2) ................................................................. 749

16.2.11 Serial Port Register (SCSPTR2) .......................................................................... 750

16.2.12 Line Status Register (SCLSR2) ........................................................................... 756

16.3 Operation........................................................................................................................... 757

16.3.1 Overview.............................................................................................................. 757

16.3.2 Serial Operation ................................................................................................... 758

16.4 SCIF Interrupt Sources and the DMAC ............................................................................ 769

16.5 Usage Notes ...................................................................................................................... 770

Section 17 Smart Card Interface ..................................................................................... 775

17.1 Overview........................................................................................................................... 775

17.1.1 Features................................................................................................................ 775

17.1.2 Block Diagram..................................................................................................... 776

17.1.3 Pin Configuration................................................................................................. 777

17.1.4 Register Configuration......................................................................................... 777

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17.2 Register Descriptions........................................................................................................ 778

17.2.1 Smart Card Mode Register (SCSCMR1) ............................................................. 778

17.2.2 Serial Mode Register (SCSMR1)......................................................................... 779

17.2.3 Serial Control Register (SCSCR1)....................................................................... 780

17.2.4 Serial Status Register (SCSSR1).......................................................................... 781

17.3 Operation .......................................................................................................................... 782

17.3.1 Overview.............................................................................................................. 782

17.3.2 Pin Connections ................................................................................................... 783

17.3.3 Data Format ......................................................................................................... 784

17.3.4 Register Settings .................................................................................................. 785

17.3.5 Clock.................................................................................................................... 787

17.3.6 Data Transmit/Receive Operations ...................................................................... 790

17.4 Usage Notes ...................................................................................................................... 797

Section 18 I/O Ports............................................................................................................ 803

18.1 Overview........................................................................................................................... 803

18.1.1 Features................................................................................................................ 803

18.1.2 Block Diagrams ................................................................................................... 804

18.1.3 Pin Configuration................................................................................................. 811

18.1.4 Register Configuration......................................................................................... 813

18.2 Register Descriptions........................................................................................................ 814

18.2.1 Port Control Register A (PCTRA)....................................................................... 814

18.2.2 Port Data Register A (PDTRA) ........................................................................... 815

18.2.3 Port Control Register B (PCTRB) ....................................................................... 816

18.2.4 Port Data Register B (PDTRB)............................................................................ 817

18.2.5 GPIO Interrupt Control Register (GPIOIC)......................................................... 818

18.2.6 Serial Port Register (SCSPTR1) .......................................................................... 819

18.2.7 Serial Port Register (SCSPTR2) .......................................................................... 821

Section 19 Interrupt Controller (INTC) ........................................................................ 825

19.1 Overview........................................................................................................................... 825

19.1.1 Features................................................................................................................ 825

19.1.2 Block Diagram..................................................................................................... 825

19.1.3 Pin Configuration................................................................................................. 827

19.1.4 Register Configuration......................................................................................... 827

19.2 Interrupt Sources............................................................................................................... 828

19.2.1 NMI Interrupt....................................................................................................... 828

19.2.2 IRL Interrupts ...................................................................................................... 829

19.2.3 On-Chip Peripheral Module Interrupts ................................................................ 831

19.2.4 Interrupt Exception Handling and Priority........................................................... 832

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19.3 Register Descriptions ........................................................................................................ 835

19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) ............................................... 835

19.3.2 Interrupt Control Register (ICR).......................................................................... 837

19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only)........ 839

19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only).............................. 840

19.3.5 Interrupt Mask Register 00 (INTMSK00) (SH7750R Only) ............................... 841

19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only) .............. 842

19.3.7 Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00

(SH7750R Only) .................................................................................................. 842

19.4 INTC Operation ................................................................................................................ 843

19.4.1 Interrupt Operation Sequence .............................................................................. 843

19.4.2 Multiple Interrupts ............................................................................................... 845

19.4.3 Interrupt Masking with MAI Bit .......................................................................... 845

19.5 Interrupt Response Time................................................................................................... 846

19.6 Usage Notes ...................................................................................................................... 847

19.6.1 NMI Interrupts (SH7750 and SH7750S Only)..................................................... 847

Section 20 User Break Controller (UBC)..................................................................... 851

20.1 Overview........................................................................................................................... 851

20.1.1 Features................................................................................................................ 851

20.1.2 Block Diagram..................................................................................................... 852

20.2 Register Descriptions ........................................................................................................ 854

20.2.1 Access to UBC Control Registers........................................................................ 854

20.2.2 Break Address Register A (BARA) ..................................................................... 855

20.2.3 Break ASID Register A (BASRA)....................................................................... 856

20.2.4 Break Address Mask Register A (BAMRA)........................................................ 856

20.2.5 Break Bus Cycle Register A (BBRA).................................................................. 857

20.2.6 Break Address Register B (BARB)...................................................................... 859

20.2.7 Break ASID Register B (BASRB) ....................................................................... 859

20.2.8 Break Address Mask Register B (BAMRB) ........................................................ 859

20.2.9 Break Data Register B (BDRB) ........................................................................... 859

20.2.10 Break Data Mask Register B (BDMRB).............................................................. 860

20.2.11 Break Bus Cycle Register B (BBRB) .................................................................. 861

20.2.12 Break Control Register (BRCR) .......................................................................... 861

20.3 Operation........................................................................................................................... 864

20.3.1 Explanation of Terms Relating to Accesses......................................................... 864

20.3.2 Explanation of Terms Relating to Instruction Intervals ....................................... 864

20.3.3 User Break Operation Sequence .......................................................................... 865

20.3.4 Instruction Access Cycle Break ........................................................................... 866

20.3.5 Operand Access Cycle Break............................................................................... 867

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20.3.6 Condition Match Flag Setting.............................................................................. 868

20.3.7 Program Counter (PC) Value Saved .................................................................... 868

20.3.8 Contiguous A and B Settings for Sequential Conditions ..................................... 869

20.3.9 Usage Notes ......................................................................................................... 870

20.4 User Break Debug Support Function ................................................................................ 872

20.5 Examples of Use ............................................................................................................... 874

20.6 User Break Controller Stop Function................................................................................ 876

20.6.1 Transition to User Break Controller Stopped State.............................................. 876

20.6.2 Cancelling the User Break Controller Stopped State ........................................... 876

20.6.3 Examples of Stopping and Restarting the User Break Controller........................ 877

Section 21 High-performance User Debug Interface (H-UDI).............................. 879

21.1 Overview........................................................................................................................... 879

21.1.1 Features................................................................................................................ 879

21.1.2 Block Diagram..................................................................................................... 879

21.1.3 Pin Configuration................................................................................................. 881

21.1.4 Register Configuration......................................................................................... 882

21.2 Register Descriptions........................................................................................................ 883

21.2.1 Instruction Register (SDIR) ................................................................................. 883

21.2.2 Data Register (SDDR) ......................................................................................... 885

21.2.3 Bypass Register (SDBPR) ................................................................................... 885

21.2.4 Interrupt Source Register (SDINT) (SH7750R Only).......................................... 886

21.2.5 Boundary Scan Register (SDBSR) (SH7750R Only) .......................................... 887

21.3 Operation .......................................................................................................................... 891

21.3.1 TAP Control......................................................................................................... 891

21.3.2 H-UDI Reset ........................................................................................................ 892

21.3.3 H-UDI Interrupt ................................................................................................... 892

21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS)

(SH7750R Only) .................................................................................................. 893

21.4 Usage Notes ...................................................................................................................... 893

Section 22 Electrical Characteristics ............................................................................. 895

22.1 Absolute Maximum Ratings ............................................................................................. 895

22.2 DC Characteristics ............................................................................................................ 896

22.3 AC Characteristics ............................................................................................................ 920

22.3.1 Clock and Control Signal Timing ........................................................................ 922

22.3.2 Control Signal Timing ......................................................................................... 946

22.3.3 Bus Timing .......................................................................................................... 950

22.3.4 Peripheral Module Signal Timing...................................................................... 1003

22.3.5 AC Characteristic Test Conditions .................................................................... 1015

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22.3.6 Delay Time Variation Due to Load Capacitance ............................................... 1016

Appendix A Address List................................................................................................ 1017

Appendix B Package Dimensions................................................................................. 1023

Appendix C Mode Pin Settings ..................................................................................... 1027

Appendix D CKIO2ENB Pin Configuration............................................................. 1031

Appendix E Pin Functions .............................................................................................. 1033

E.1 Pin States......................................................................................................................... 1033

E.2 Handling of Unused Pins ................................................................................................ 1036

Appendix F Synchronous DRAM Address Multiplexing Tables....................... 1037

Appendix G Prefetching of Instructions and its Side Effects ............................... 1059

Appendix H Power-On and Power-Off Procedures................................................. 1061

H.1 Power-On Stipulations .................................................................................................... 1061

H.2 Power-Off Stipulations ................................................................................................... 1061

H.3 Common Stipulations for Power-On and Power-Off ...................................................... 1062

Appendix I Product Lineup............................................................................................. 1065

Appendix J Version Registers........................................................................................ 1067

Index ........................................................................................................................... 1069

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Figures

Section 1 Overview

Figure 1.1 Block Diagram of SH7750/SH7750S/SH7750R Group Functions ........................ 9

Figure 1.2 Pin Arrangement (256-Pin BGA)........................................................................... 10

Figure 1.3 Pin Arrangement (208-Pin QFP)............................................................................ 11

Figure 1.4 Pin Arrangement (264-Pin CSP) ............................................................................ 12

Figure 1.5 Pin Arrangement (292-Pin BGA)........................................................................... 13

Section 2 Programming Model

Figure 2.1 Data Formats .......................................................................................................... 53

Figure 2.2 CPU Register Configuration in Each Processor Mode........................................... 56

Figure 2.3 General Registers ................................................................................................... 58

Figure 2.4 Floating-Point Registers......................................................................................... 61

Figure 2.5 Data Formats In Memory ....................................................................................... 67

Figure 2.6 Processor State Transitions .................................................................................... 68

Section 3 Memory Management Unit (MMU)

Figure 3.1 Role of the MMU ................................................................................................... 73

Figure 3.2 MMU-Related Registers......................................................................................... 75

Figure 3.3 Physical Address Space (MMUCR.AT = 0) .......................................................... 79

Figure 3.4 P4 Area................................................................................................................... 81

Figure 3.5 External Memory Space ......................................................................................... 82

Figure 3.6 Virtual Address Space (MMUCR.AT = 1)............................................................. 83

Figure 3.7 UTLB Configuration .............................................................................................. 86

Figure 3.8 Relationship between Page Size and Address Format............................................ 87

Figure 3.9 ITLB Configuration................................................................................................ 90

Figure 3.10 Flowchart of Memory Access Using UTLB........................................................... 91

Figure 3.11 Flowchart of Memory Access Using ITLB ............................................................ 92

Figure 3.12 Operation of LDTLB Instruction............................................................................ 94

Figure 3.13 Memory-Mapped ITLB Address Array.................................................................. 103

Figure 3.14 Memory-Mapped ITLB Data Array 1 .................................................................... 104

Figure 3.15 Memory-Mapped ITLB Data Array 2 .................................................................... 105

Figure 3.16 Memory-Mapped UTLB Address Array ................................................................ 107

Figure 3.17 Memory-Mapped UTLB Data Array 1................................................................... 108

Figure 3.18 Memory-Mapped UTLB Data Array 2................................................................... 109

Section 4 Caches

Figure 4.1 Cache and Store Queue Control Registers ............................................................. 114

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Figure 4.2 Configuration of Operand Cache (SH7750, SH7750S).......................................... 117

Figure 4.3 Configuration of Operand Cache (SH7750R) ........................................................ 118

Figure 4.4 Configuration of Write-Back Buffer ...................................................................... 122

Figure 4.5 Configuration of Write-Through Buffer................................................................. 122

Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S) ...................................... 128

Figure 4.7 Configuration of Instruction Cache (SH7750R)..................................................... 129

Figure 4.8 Memory-Mapped IC Address Array ...................................................................... 132

Figure 4.9 Memory-Mapped IC Data Array............................................................................ 133

Figure 4.10 Memory-Mapped OC Address Array..................................................................... 135

Figure 4.11 Memory-Mapped OC Data Array .......................................................................... 136

Figure 4.12 Memory-Mapped IC Address Array ...................................................................... 138

Figure 4.13 Memory-Mapped IC Data Array............................................................................ 139

Figure 4.14 Memory-Mapped OC Address Array..................................................................... 140

Figure 4.15 Memory-Mapped OC Data Array .......................................................................... 141

Figure 4.16 Store Queue Configuration..................................................................................... 143

Section 5 Exceptions

Figure 5.1 Register Bit Configurations.................................................................................... 150

Figure 5.2 Instruction Execution and Exception Handling...................................................... 155

Figure 5.3 Example of General Exception Acceptance Order................................................. 157

Section 6 Floating-Point Unit (FPU)

Figure 6.1 Format of Single-Precision Floating-Point Number............................................... 185

Figure 6.2 Format of Double-Precision Floating-Point Number ............................................. 186

Figure 6.3 Single-Precision NaN Bit Pattern........................................................................... 188

Figure 6.4 Floating-Point Registers......................................................................................... 190

Section 8 Pipelining

Figure 8.1 Basic Pipelines ....................................................................................................... 232

Figure 8.2 Instruction Execution Patterns................................................................................ 233

Figure 8.3 Examples of Pipelined Execution........................................................................... 245

Section 9 Power-Down Modes

Figure 9.1 STATUS Output in Power-On Reset ..................................................................... 276

Figure 9.2 STATUS Output in Manual Reset.......................................................................... 276

Figure 9.3 STATUS Output in Standby → Interrupt Sequence............................................... 277

Figure 9.4 STATUS Output in Standby → Power-On Reset Sequence .................................. 277

Figure 9.5 STATUS Output in Standby → Manual Reset Sequence ...................................... 278

Figure 9.6 STATUS Output in Sleep → Interrupt Sequence................................................... 279

Figure 9.7 STATUS Output in Sleep → Power-On Reset Sequence ...................................... 279

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Figure 9.8 STATUS Output in Sleep → Manual Reset Sequence........................................... 280

Figure 9.9 STATUS Output in Deep Sleep → Interrupt Sequence ......................................... 281

Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence ............................. 281

Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence ................................. 282

Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation) .......... 283

Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation) ............. 284

Figure 9.14 Timing When Power Other than VDD-RTC Is Off................................................ 285

Figure 9.15 Timing When VDD-RTC Power Is Off → On....................................................... 285

Section 10 Clock Oscillation Circuits

Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S) ................................................... 289

Figure 10.1 (2) Block Diagram of CPG (SH7750R).................................................................. 290

Figure 10.2 Block Diagram of WDT......................................................................................... 300

Figure 10.3 Writing to WTCNT and WTCSR........................................................................... 305

Figure 10.4 Points for Attention when Using Crystal Resonator............................................... 307

Figure 10.5 Points for Attention when Using PLL Oscillator Circuit ....................................... 308

Section 11 Realtime Clock (RTC)

Figure 11.1 Block Diagram of RTC .......................................................................................... 312

Figure 11.2 Examples of Time Setting Procedures.................................................................... 329

Figure 11.3 Examples of Time Reading Procedures.................................................................. 331

Figure 11.4 Example of Use of Alarm Function........................................................................ 332

Figure 11.5 Example of Crystal Oscillator Circuit Connection................................................. 334

Section 12 Timer Unit (TMU)

Figure 12.1 Block Diagram of TMU ......................................................................................... 338

Figure 12.2 Example of Count Operation Setting Procedure .................................................... 351

Figure 12.3 TCNT Auto-Reload Operation............................................................................... 352

Figure 12.4 Count Timing when Operating on Internal Clock .................................................. 352

Figure 12.5 Count Timing when Operating on External Clock................................................. 353

Figure 12.6 Count Timing when Operating on On-Chip RTC Output Clock............................ 353

Figure 12.7 Operation Timing when Using Input Capture Function ......................................... 354

Section 13 Bus State Controller (BSC)

Figure 13.1 Block Diagram of BSC........................................................................................... 359

Figure 13.2 Correspondence between Virtual Address Space and External Memory Space..... 365

Figure 13.3 External Memory Space Allocation ....................................................................... 367

Figure 13.4 Example of RDY Sampling Timing at which BCR4 Is Set

(Two Wait Cycles Are Inserted by WCR2)............................................................ 385

Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR................................................. 421

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Figure 13.6 Basic Timing of SRAM Interface........................................................................... 439

Figure 13.7 Example of 64-Bit Data Width SRAM Connection ............................................... 440

Figure 13.8 Example of 32-Bit Data Width SRAM Connection ............................................... 441

Figure 13.9 Example of 16-Bit Data Width SRAM Connection ............................................... 442

Figure 13.10 Example of 8-Bit Data Width SRAM Connection ................................................. 443

Figure 13.11 SRAM Interface Wait Timing (Software Wait Only) ............................................ 444

Figure 13.12 SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal) .......... 445

Figure 13.13 SRAM Interface Read-Strobe Negate Timing (AnS = 1, AnW = 4, AnH = 2) ...... 446

Figure 13.14 Example of DRAM Connection (64-Bit Data Width, Area 3) ............................... 448

Figure 13.15 Example of DRAM Connection (32-Bit Data Width, Area 3) ............................... 449

Figure 13.16 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3).................... 450

Figure 13.17 Basic DRAM Access Timing ................................................................................. 452

Figure 13.18 DRAM Wait State Timing ..................................................................................... 453

Figure 13.19 DRAM Burst Access Timing ................................................................................. 454

Figure 13.20 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1)............................ 455

Figure 13.21 Burst Access Timing in DRAM EDO Mode.......................................................... 456

Figure 13.22 (1) DRAM Burst Bus Cycle, RAS Down Mode Start

(Fast Page Mode, RCD = 0, AnW = 0) .......................................................... 457

Figure 13.22 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation

(Fast Page Mode, RCD = 0, AnW = 0) .......................................................... 458

Figure 13.22 (3) DRAM Burst Bus Cycle, RAS Down Mode Start

(EDO Mode, RCD = 0, AnW = 0).................................................................. 459

Figure 13.22 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation

(EDO Mode, RCD = 0, AnW = 0).................................................................. 460

Figure 13.23 CAS-Before-RAS Refresh Operation..................................................................... 461

Figure 13.24 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1).............. 462

Figure 13.25 DRAM Self-Refresh Cycle Timing........................................................................ 464

Figure 13.26 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3) .......... 466

Figure 13.27 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) .......... 467

Figure 13.28 Basic Timing for Synchronous DRAM Burst Read ............................................... 469

Figure 13.29 Basic Timing for Synchronous DRAM Single Read.............................................. 471

Figure 13.30 Basic Timing for Synchronous DRAM Burst Write .............................................. 473

Figure 13.31 Basic Timing for Synchronous DRAM Single Write............................................. 474

Figure 13.32 Burst Read Timing ................................................................................................. 476

Figure 13.33 Burst Read Timing (RAS Down, Same Row Address).......................................... 477

Figure 13.34 Burst Read Timing (RAS Down, Different Row Addresses)................................. 478

Figure 13.35 Burst Write Timing ................................................................................................ 479

Figure 13.36 Burst Write Timing (Same Row Address) ............................................................. 480

Figure 13.37 Burst Write Timing (Different Row Addresses) .................................................... 481

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Figure 13.38 Burst Read Cycle for Different Bank and Row Address Following Preceding

Burst Read Cycle.................................................................................................... 483

Figure 13.39 Auto-Refresh Operation ......................................................................................... 485

Figure 13.40 Synchronous DRAM Auto-Refresh Timing........................................................... 486

Figure 13.41 Synchronous DRAM Self-Refresh Timing ............................................................ 487

Figure 13.42 (1) Synchronous DRAM Mode Write Timing (PALL) ........................................ 490

Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set)..................... 491

Figure 13.43 Basic Timing of Synchronous DRAM Burst Read (Burst Length = 4).................. 492

Figure 13.44 Basic Timing of a Burst Write to Synchronous DRAM......................................... 494

Figure 13.45 Example of the Connection of Synchronous DRAM with 64-bit Bus Width

(256 Mbits)............................................................................................................. 495

Figure 13.46 Synchronous DRAM Auto-Refresh Timing with 64-Bit Bus Width

(TRAS[2:0] = 001, TRC[2:0] = 001)...................................................................... 496

Figure 13.47 Burst ROM Basic Access Timing .......................................................................... 498

Figure 13.48 Burst ROM Wait Access Timing ........................................................................... 499

Figure 13.49 Burst ROM Wait Access Timing ........................................................................... 500

Figure 13.50 Example of PCMCIA Interface.............................................................................. 504

Figure 13.51 Basic Timing for PCMCIA Memory Card Interface.............................................. 505

Figure 13.52 Wait Timing for PCMCIA Memory Card Interface ............................................... 506

Figure 13.53 PCMCIA Space Allocation .................................................................................... 507

Figure 13.54 Basic Timing for PCMCIA I/O Card Interface ...................................................... 508

Figure 13.55 Wait Timing for PCMCIA I/O Card Interface ....................................................... 509

Figure 13.56 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface .............................. 510

Figure 13.57 Example of 64-Bit Data Width MPX Connection.................................................. 512

Figure 13.58 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait,

Bus Width: 64 Bits)................................................................................................ 513

Figure 13.59 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted,

Bus Width: 64 Bits)................................................................................................ 514

Figure 13.60 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No Wait,

Bus Width: 64 Bits)................................................................................................ 515

Figure 13.61 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted,

Bus Width: 64 Bits)................................................................................................ 516

Figure 13.62 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait,

Bus Width: 64 Bits, Transfer Data Size: 32 Bytes)............................................... 517

Figure 13.63 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control,

Bus Width: 64 Bits, Transfer Data Size: 32 Bytes)............................................... 518

Figure 13.64 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait,

Bus Width: 64 Bits, Transfer Data Size: 32 Bytes)............................................... 519

Figure 13.65 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control,

Bus Width: 64 Bits, Transfer Data Size: 32 Bytes)............................................... 520

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Figure 13.66 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait,

Bus Width: 32 Bits, Transfer Data Size: 64 Bits).................................................. 521

Figure 13.67 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0, One External Wait

Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)................................... 522

Figure 13.68 MPX Interface Timing 11 (Burst Write Cycle, AnW = 0, No External Wait,

Bus Width: 32 Bits, Transfer Data Size: 64 Bits).................................................. 523

Figure 13.69 MPX Interface Timing 12 (Burst Write Cycle, AnW = 1, One External Wait

Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)................................... 524

Figure 13.70 MPX Interface Timing 13 (Burst Read Cycle, AnW = 0, No External Wait,

Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)................................................ 525

Figure 13.71 MPX Interface Timing 14 (Burst Read Cycle, AnW = 0, External Wait Control,

Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)............................................... 526

Figure 13.72 MPX Interface Timing 15 (Burst Write Cycle, AnW = 0, No External Wait,

Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)............................................... 527

Figure 13.73 MPX Interface Timing 16 (Burst Write Cycle, AnW = 1, External Wait Control,

Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)............................................... 528

Figure 13.74 Example of 64-Bit Data Width Byte Control SRAM............................................. 530

Figure 13.75 Byte Control SRAM Basic Read Cycle (No Wait) ................................................ 531

Figure 13.76 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) ....................... 532

Figure 13.77 Byte Control SRAM Basic Read Cycle

(One Internal Wait + One External Wait) .............................................................. 533

Figure 13.78 Waits between Access Cycles ................................................................................ 535

Figure 13.79 Arbitration Sequence.............................................................................................. 538

Section 14 Direct Memory Access Controller (DMAC)

Figure 14.1 Block Diagram of DMAC ...................................................................................... 548

Figure 14.2 DMAC Transfer Flowchart .................................................................................... 568

Figure 14.3 Round Robin Mode ................................................................................................ 574

Figure 14.4 Example of Changes in Priority Order in Round Robin Mode............................... 575

Figure 14.5 Data Flow in Single Address Mode ....................................................................... 577

Figure 14.6 DMA Transfer Timing in Single Address Mode.................................................... 578

Figure 14.7 Operation in Dual Address Mode........................................................................... 579

Figure 14.8 Example of Transfer Timing in Dual Address Mode ............................................. 580

Figure 14.9 Example of DMA Transfer in Cycle Steal Mode................................................... 581

Figure 14.10 Example of DMA Transfer in Burst Mode............................................................. 581

Figure 14.11 Bus Handling with Two DMAC Channels Operating............................................ 585

Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ

(Level Detection), DACK (Read Cycle) ................................................................ 588

Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ

(Edge Detection), DACK (Read Cycle) ................................................................. 589

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Figure 14.14 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ

(Level Detection), DACK (Read Cycle) ................................................................ 590

Figure 14.15 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ

(Edge Detection), DACK (Read Cycle) ................................................................. 591

Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) →

External Bus ........................................................................................................... 592

Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus → On-Chip SCI

(Level Detection).................................................................................................... 593

Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ

(Level Detection).................................................................................................... 594

Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ

(Edge Detection) .................................................................................................... 595

Figure 14.20 Single Address Mode/Burst Mode External Bus → External Bus/DREQ

(Level Detection).................................................................................................... 596

Figure 14.21 Single Address Mode/Burst Mode External Bus → External Bus/DREQ

(Edge Detection) .................................................................................................... 597

Figure 14.22 Single Address Mode/Burst Mode External Bus → External Bus/DREQ

(Level Detection)/32-Byte Block Transfer (Bus Width: 64 Bits, SDRAM:

Row Hit Write)....................................................................................................... 598

Figure 14.23 On-Demand Transfer Mode Block Diagram .......................................................... 603

Figure 14.24 System Configuration in On-Demand Data Transfer Mode................................... 605

Figure 14.25 Data Transfer Request Format................................................................................ 606

Figure 14.26 Single Address Mode: Synchronous DRAM → External Device Longword Transfer

SDRAM auto-precharge Read bus cycle, burst (RCD[1:0] = 01, CAS latency = 3,

TPC[2:0] = 001)....................................................................................................... 609

Figure 14.27 Single Address Mode: External Device → Synchronous DRAM Longword Transfer

SDRAM auto-precharge Write bus cycle, burst (RCD[1:0] = 01, TRWL[2:0] = 101,

TPC[2:0] = 001)....................................................................................................... 610

Figure 14.28 Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer............ 611

Figure 14.29 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte

Block Transfer/Channel 0 On-Demand Data Transfer........................................... 612

Figure 14.30 Single Address Mode/Burst Mode/External Device → External Bus 32-Byte

Block Transfer/Channel 0 On-Demand Data Transfer........................................... 613

Figure 14.31 Single Address Mode/Burst Mode/External Bus → External Device 32-Bit

Transfer/Channel 0 On-Demand Data Transfer ..................................................... 614

Figure 14.32 Single Address Mode/Burst Mode/External Device → External Bus 32-Bit

Transfer/Channel 0 On-Demand Data Transfer ..................................................... 615

Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) ..... 616

Figure 14.34 Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data

Transfer)................................................................................................................. 617

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Figure 14.35 Read from Synchronous DRAM Precharge Bank.................................................. 618

Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss)...................... 618

Figure 14.37 Read from Synchronous DRAM (Row Hit) ........................................................... 619

Figure 14.38 Write to Synchronous DRAM Precharge Bank...................................................... 619

Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss).......................... 620

Figure 14.40 Write to Synchronous DRAM (Row Hit)............................................................... 620

Figure 14.41 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte

Block Transfer/Channel 0 On-Demand Data Transfer........................................... 621

Figure 14.42 DDT Mode Setting ................................................................................................. 622

Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device

→ External Bus Data Transfer ............................................................................... 622

Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus

→ External Device Data Transfer .......................................................................... 623

Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,

Quadword/External Bus → External Device Data Transfer................................... 624

Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,

Quadword/External Device → External Bus Data Transfer................................... 625

Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer

Request to Channels 1–3 Using Data Bus.............................................................. 626

Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus

→ External Device Data Transfer/ Direct Data Transfer Request to Channel 2

without Using Data Bus ......................................................................................... 627

Figure 14.49 Single Address Mode/Burst Mode/External Bus → External Device Data

Transfer/Direct Data Transfer Request to Channel 2 ............................................. 628

Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data

Transfer/Direct Data Transfer Request to Channel 2 ............................................. 629

Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data

Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2........ 630

Figure 14.52 Single Address Mode/Burst Mode/External Device → External Bus Data

Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2........ 631

Figure 14.53 Block Diagram of the DMAC ................................................................................ 635

Figure 14.54 DTR Format (Transfer Request Format) (SH7750R)............................................. 646

Figure 14.55 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte

Block Transfer/Channel 0 On-Demand Data Transfer........................................... 650

Figure 14.56 Single Address Mode/Burst Mode/External Bus → External Device/32-Byte

Block Transfer/On-Demand Data Transfer on Channel 4...................................... 651

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Section 15 Serial Communication Interface (SCI)

Figure 15.1 Block Diagram of SCI............................................................................................ 657

Figure 15.2 MD0/SCK Pin ........................................................................................................ 674

Figure 15.3 MD7/TxD Pin......................................................................................................... 675

Figure 15.4 RxD Pin .................................................................................................................. 675

Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data,

Parity, Two Stop Bits) ............................................................................................ 687

Figure 15.6 Relation between Output Clock and Transfer Data Phase

(Asynchronous Mode)............................................................................................ 689

Figure 15.7 Sample SCI Initialization Flowchart ...................................................................... 690

Figure 15.8 Sample Serial Transmission Flowchart .................................................................. 691

Figure 15.9 Example of Transmit Operation in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 693

Figure 15.10 Sample Serial Reception Flowchart (1).................................................................. 694

Figure 15.10 Sample Serial Reception Flowchart (2).................................................................. 695

Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity,

One Stop Bit).......................................................................................................... 697

Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A) ........................................... 699

Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart ......................................... 700

Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor

Bit, One Stop Bit)................................................................................................... 702

Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1)......................................... 704

Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (2)......................................... 705

Figure 15.16 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor

Bit, One Stop Bit)................................................................................................... 706

Figure 15.17 Data Format in Synchronous Communication ....................................................... 707

Figure 15.18 Sample SCI Initialization Flowchart ...................................................................... 709

Figure 15.19 Sample Serial Transmission Flowchart .................................................................. 710

Figure 15.20 Example of SCI Transmit Operation...................................................................... 712

Figure 15.21 Sample Serial Reception Flowchart (1).................................................................. 713

Figure 15.21 Sample Serial Reception Flowchart (2).................................................................. 714

Figure 15.22 Example of SCI Receive Operation........................................................................ 715

Figure 15.23 Sample Flowchart for Serial Data Transmission and Reception ............................ 716

Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode ....................................... 720

Figure 15.25 Example of Synchronous Transmission by DMAC ............................................... 721

Figure 15.26 Example Countermeasure on SH7750.................................................................... 723

Figure 15.27 Clock Input Timing of SCK Pin............................................................................. 723

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Section 16 Serial Communication Interface with FIFO (SCIF)

Figure 16.1 Block Diagram of SCIF.......................................................................................... 727

Figure 16.2 MD8/RTS2 Pin....................................................................................................... 753

Figure 16.3 CTS2 Pin ................................................................................................................ 754

Figure 16.4 MD1/TxD2 Pin....................................................................................................... 755

Figure 16.5 MD2/RxD2 Pin ...................................................................................................... 755

Figure 16.6 Sample SCIF Initialization Flowchart.................................................................... 761

Figure 16.7 Sample Serial Transmission Flowchart.................................................................. 762

Figure 16.8 Example of Transmit Operation (Example with 8-Bit Data, Parity,

One Stop Bit).......................................................................................................... 764

Figure 16.9 Example of Operation Using Modem Control (CTS2)........................................... 764

Figure 16.10 Sample Serial Reception Flowchart (1).................................................................. 765

Figure 16.10 Sample Serial Reception Flowchart (2).................................................................. 766

Figure 16.11 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity,

One Stop Bit).......................................................................................................... 768

Figure 16.12 Example of Operation Using Modem Control (RTS2)........................................... 769

Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode ....................................... 772

Figure 16.14 Overrun Error Flag................................................................................................. 774

Section 17 Smart Card Interface

Figure 17.1 Block Diagram of Smart Card Interface................................................................. 776

Figure 17.2 Schematic Diagram of Smart Card Interface Pin Connections............................... 783

Figure 17.3 Smart Card Interface Data Format ......................................................................... 784

Figure 17.4 TEND Generation Timing...................................................................................... 786

Figure 17.5 Sample Start Character Waveforms ....................................................................... 787

Figure 17.6 Difference in Clock Output According to GM Bit Setting..................................... 790

Figure 17.7 Sample Initialization Flowchart ............................................................................. 791

Figure 17.8 Sample Transmission Processing Flowchart .......................................................... 793

Figure 17.9 Sample Reception Processing Flowchart ............................................................... 795

Figure 17.10 Receive Data Sampling Timing in Smart Card Mode ............................................ 797

Figure 17.11 Retransfer Operation in SCI Receive Mode........................................................... 799

Figure 17.12 Retransfer Operation in SCI Transmit Mode ......................................................... 799

Figure 17.13 Procedure for Stopping and Restarting the Clock .................................................. 800

Section 18 I/O Ports

Figure 18.1 16-Bit Port.............................................................................................................. 804

Figure 18.2 4-Bit Port................................................................................................................ 805

Figure 18.3 MD0/SCK Pin ........................................................................................................ 806

Figure 18.4 MD7/TxD Pin......................................................................................................... 807

Figure 18.5 RxD Pin.................................................................................................................. 807

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Figure 18.6 MD1/TxD2 Pin....................................................................................................... 808

Figure 18.7 MD2/RxD2 Pin ...................................................................................................... 808

Figure 18.8 CTS2 Pin ................................................................................................................ 809

Figure 18.9 MD8/RTS2 Pin....................................................................................................... 810

Section 19 Interrupt Controller (INTC)

Figure 19.1 Block Diagram of INTC......................................................................................... 826

Figure 19.2 Example of IRL Interrupt Connection.................................................................... 829

Figure 19.3 Interrupt Operation Flowchart................................................................................ 844

Section 20 User Break Controller (UBC)

Figure 20.1 Block Diagram of User Break Controller............................................................... 852

Figure 20.2 User Break Debug Support Function Flowchart .................................................... 873

Section 21 High-performance User Debug Interface (H-UDI)

Figure 21.1 Block Diagram of H-UDI Circuit........................................................................... 880

Figure 21.2 TAP Control State Transition Diagram.................................................................. 891

Figure 21.3 H-UDI Reset........................................................................................................... 892

Section 22 Electrical Characteristics

Figure 22.1 EXTAL Clock Input Timing .................................................................................. 940

Figure 22.2 (1) CKIO Clock Output Timing ............................................................................. 940

Figure 22.2 (2) CKIO Clock Output Timing ............................................................................. 940

Figure 22.3 Power-On Oscillation Settling Time ...................................................................... 941

Figure 22.4 Standby Return Oscillation Settling Time (Return by RESET) ............................. 941

Figure 22.5 Power-On Oscillation Settling Time ...................................................................... 942

Figure 22.6 Standby Return Oscillation Settling Time (Return by RESET) ............................. 942

Figure 22.7 Standby Return Oscillation Settling Time (Return by NMI).................................. 943

Figure 22.8 Standby Return Oscillation Settling Time (Return by IRL3 to IRL0).................... 943

Figure 22.9 PLL Synchronization Settling Time in Case of RESET or NMI Interrupt............. 944

Figure 22.10 PLL Synchronization Settling Time in Case of IRL Interrupt................................ 944

Figure 22.11 Manual Reset Input Timing.................................................................................... 945

Figure 22.12 Mode Input Timing ................................................................................................ 945

Figure 22.13 Control Signal Timing............................................................................................ 948

Figure 22.14 (1) Pin Drive Timing for Reset or Sleep Mode .................................................... 948

Figure 22.14 (2) Pin Drive Timing for Software Standby Mode ............................................... 949

Figure 22.15 SRAM Bus Cycle: Basic Bus Cycle (No Wait)...................................................... 956

Figure 22.16 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) ...................................... 957

Figure 22.17 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait) .... 958

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Figure 22.18 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time

Insertion, AnS = 1, AnH = 1) ................................................................................. 959

Figure 22.19 Burst ROM Bus Cycle (No Wait) .......................................................................... 960

Figure 22.20 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait;

2nd/3rd/4th Data: One Internal Wait)..................................................................... 961

Figure 22.21 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1,

AnH = 1) ................................................................................................................ 962

Figure 22.22 Burst ROM Bus Cycle (One Internal Wait + One External Wait) ......................... 963

Figure 22.23 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD[1:0] = 01,

CAS Latency = 3, TPC[2:0] = 011) ....................................................................... 964

Figure 22.24 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD[1:0] = 01,

CAS Latency = 3, TPC[2:0] = 011) ....................................................................... 965

Figure 22.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands,

Burst (RASD = 1, RCD[1:0] = 01, CAS Latency = 3)........................................... 966

Figure 22.26 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands,

Burst ((RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, CAS Latency = 3) .............. 967

Figure 22.27 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst

((RASD = 1, CAS Latency = 3) ............................................................................. 968

Figure 22.28 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD[1:0] = 01,

TPC[2:0] = 001, TRWL[2:0] = 010) ...................................................................... 969

Figure 22.29 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD[1:0] = 01,

TPC[2:0] = 001, TRWL[2:0] = 010) ...................................................................... 970

Figure 22.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands,

Burst (RASD = 1, RCD[1:0] = 01, TRWL[2:0] = 010) ......................................... 971

Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands,

Burst (RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) .............. 972

Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst

(RASD = 1, TRWL[2:0] = 010)............................................................................. 973

Figure 22.33 Synchronous DRAM Bus Cycle: Synchronous DRAM Precharge Command

(RASD = 1, TPC[2:0] = 001) ................................................................................. 974

Figure 22.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh

(TRAS = 1, TRC[2:0] = 001)................................................................................. 975

Figure 22.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh

(TRC[2:0] = 001) ................................................................................................... 976

Figure 22.36 (a) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register

Setting (PALL)....................................................................................................... 977

Figure 22.36 (b) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register

Setting (SET).......................................................................................................... 978

Figure 22.37 DRAM Bus Cycles (1) RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001

(2) RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 010 .......................................... 979

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Figure 22.38 DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000,

TPC[2:0] = 001) ..................................................................................................... 980

Figure 22.39 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000,

TPC[2:0] = 001) ..................................................................................................... 981

Figure 22.40 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001,

TPC[2:0] = 001) ..................................................................................................... 982

Figure 22.41 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001,

TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width) ............................................. 983

Figure 22.42 DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode, RCD[1:0] = 00,

AnW[2:0] = 000).................................................................................................... 984

Figure 22.43 DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode,

RCD[1:0] = 00, AnW[2:0] = 000).......................................................................... 985

Figure 22.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000,

TPC[2:0] = 001) ..................................................................................................... 986

Figure 22.45 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001,

TPC[2:0] = 001) ..................................................................................................... 987

Figure 22.46 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001,

TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width) ............................................. 988

Figure 22.47 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode,

RCD[1:0] = 00, AnW[2:0] = 000).......................................................................... 989

Figure 22.48 DRAM Burst Bus Cycle: RAS Down Mode Continuation (Fast Page Mode,

RCD[1:0] = 00, AnW[2:0] = 000).......................................................................... 990

Figure 22.49 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 000,

TRC[2:0] = 001)..................................................................................................... 991

Figure 22.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 001,

TRC[2:0] = 001)..................................................................................................... 992

Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001) .................................. 993

Figure 22.52 PCMCIA Memory Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait

(2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait .... 994

Figure 22.53 PCMCIA I/O Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait

(2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait .... 995

Figure 22.54 PCMCIA I/O Bus Cycle (TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait,

Bus Sizing) ............................................................................................................. 996

Figure 22.55 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait) (2) 1st Data

(One Internal Wait + One External Wait) .............................................................. 997

Figure 22.56 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait) (2) 1st Data (One Internal

Wait) (3) 1st Data (One Internal Wait + One External Wait)................................. 998

Figure 22.57 MPX Bus Cycle: Burst Read (1) 1st Data (One Internal Wait), 2nd to 8th Data

(One Internal Wait) (2) 1st Data (One Internal Wait), 2nd to 4th Data

(One Internal Wait + One External Wait) .............................................................. 999

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Figure 22.58 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data (One Internal Wait),

2nd to 4th Data (No Internal Wait + External Wait Control)................................ 1000

Figure 22.59 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (No Wait)

(2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal

Wait + One External Wait).................................................................................... 1001

Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address

Setup/Hold Time Insertion, AnS[0] = 1, AnH[1:0] =0 1) ..................................... 1002

Figure 22.61 TCLK Input Timing .............................................................................................. 1011

Figure 22.62 RTC Oscillation Settling Time at Power-On......................................................... 1011

Figure 22.63 SCK Input Clock Timing ...................................................................................... 1011

Figure 22.64 SCI I/O Synchronous Mode Clock Timing........................................................... 1012

Figure 22.65 I/O Port Input/Output Timing................................................................................ 1012

Figure 22.66 (a) DREQ/DRAK Timing.................................................................................... 1012

Figure 22.66 (b) DBREQ/TR Input Timing and BAVL Output Timing .................................. 1013

Figure 22.67 TCK Input Timing................................................................................................. 1013

Figure 22.68 RESET Hold Timing............................................................................................. 1014

Figure 22.69 H-UDI Data Transfer Timing................................................................................ 1014

Figure 22.70 Pin Break Timing .................................................................................................. 1014

Figure 22.71 NMI Input Timing................................................................................................. 1014

Figure 22.72 Output Load Circuit .............................................................................................. 1015

Figure 22.73 Load Capacitance vs. Delay Time......................................................................... 1016

Appendix B Package Dimensions

Figure B.1 Package Dimensions (256-Pin BGA).................................................................... 1023

Figure B.2 Package Dimensions (208-Pin QFP)..................................................................... 1024

Figure B.3 Package Dimensions (264-Pin CSP) ..................................................................... 1025

Figure B.4 Package Dimensions (292-Pin BGA).................................................................... 1026

Appendix D CKIO2ENB Pin Configuration

Figure D.1 CKIO2ENB Pin Configuration ............................................................................. 1031

Appendix G Prefetching of Instructions and its Side Effects

Figure G.1 Instruction Prefetch ............................................................................................... 1059

Appendix H Power-On and Power-Off Procedures

Figure H.1 Power-On Procedure 1 .......................................................................................... 1062

Figure H.2 Power-On Procedure 2 .......................................................................................... 1063

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Tables

Section 1 Overview

Table 1.1 LSI Features ........................................................................................................... 1

Table 1.2 Pin Functions.......................................................................................................... 14

Table 1.3 Pin Functions.......................................................................................................... 24

Table 1.4 Pin Functions.......................................................................................................... 32

Table 1.5 Pin Functions.......................................................................................................... 42

Section 2 Programming Model

Table 2.1 Initial Register Values............................................................................................ 55

Section 3 Memory Management Unit (MMU)

Table 3.1 MMU Registers...................................................................................................... 74

Section 4 Caches

Table 4.1 Cache Features (SH7750, SH7750S)...................................................................... 111

Table 4.2 Cache Features (SH7750R) .................................................................................... 112

Table 4.3 Features of Store Queues........................................................................................ 112

Table 4.4 Cache Control Registers......................................................................................... 113

Section 5 Exceptions

Table 5.1 Exception-Related Registers .................................................................................. 149

Table 5.2 Exceptions.............................................................................................................. 152

Table 5.3 Types of Reset........................................................................................................ 161

Section 6 Floating-Point Unit (FPU)

Table 6.1 Floating-Point Number Formats and Parameters ................................................... 186

Table 6.2 Floating-Point Ranges ............................................................................................ 187

Table 6.3 Incorrect Operation Result ..................................................................................... 203

Table 6.4 FDIV DRm, DRn (DRn/DRm → DRn) ................................................................ 204

Table 6.5 FADD DRm, DRn (DRn + DRm → DRn) FSUB DRm, DRn

(DRn − DRm → DRn) ........................................................................................... 205

Table 6.6 FMUL DRm, DRn (DRn*DRm → DRn).............................................................. 205

Table 6.7 TRAP Routine Processing...................................................................................... 207

Section 7 Instruction Set

Table 7.1 Addressing Modes and Effective Addresses .......................................................... 211

Table 7.2 Notation Used in Instruction List ........................................................................... 215

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Table 7.3 Fixed-Point Transfer Instructions........................................................................... 216

Table 7.4 Arithmetic Operation Instructions.......................................................................... 218

Table 7.5 Logic Operation Instructions.................................................................................. 220

Table 7.6 Shift Instructions .................................................................................................... 221

Table 7.7 Branch Instructions ................................................................................................ 222

Table 7.8 System Control Instructions ................................................................................... 223

Table 7.9 Floating-Point Single-Precision Instructions.......................................................... 225

Table 7.10 Floating-Point Double-Precision Instructions ........................................................ 226

Table 7.11 Floating-Point Control Instructions........................................................................ 226

Table 7.12 Floating-Point Graphics Acceleration Instructions ................................................ 227

Section 8 Pipelining

Table 8.1 Instruction Groups.................................................................................................. 238

Table 8.2 Parallel-Executability............................................................................................. 242

Table 8.3 Execution Cycles.................................................................................................... 249

Section 9 Power-Down Modes

Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes............................ 260

Table 9.2 Power-Down Mode Registers ................................................................................ 261

Table 9.3 Power-Down Mode Pins ........................................................................................ 261

Table 9.4 State of Registers in Standby Mode ....................................................................... 270

Section 10 Clock Oscillation Circuits

Table 10.1 CPG Pins ................................................................................................................ 292

Table 10.2 CPG Register.......................................................................................................... 292

Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S).................................................... 293

Table 10.3 (2) Clock Operating Modes (SH7750R) .................................................................. 293

Table 10.4 FRQCR Settings and Internal Clock Frequencies .................................................. 294

Table 10.5 WDT Registers....................................................................................................... 301

Section 11 Realtime Clock (RTC)

Table 11.1 RTC Pins ................................................................................................................ 313

Table 11.2 RTC Registers ........................................................................................................ 313

Table 11.3 Crystal Oscillator Circuit Constants (Recommended Values) ............................... 333

Section 12 Timer Unit (TMU)

Table 12.1 TMU Pins............................................................................................................... 338

Table 12.2 TMU Registers....................................................................................................... 339

Table 12.3 TMU Interrupt Sources .......................................................................................... 355

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REJ09B0366-0700

Section 13 Bus State Controller (BSC)

Table 13.1 BSC Pins ................................................................................................................ 360

Table 13.2 BSC Registers ........................................................................................................ 364

Table 13.3 External Memory Space Map................................................................................. 366

Table 13.4 PCMCIA Interface Features................................................................................... 368

Table 13.5 PCMCIA Support Interfaces .................................................................................. 369

Table 13.6 MPX Interface is Selected (Areas 0 to 6) ............................................................... 398

Table 13.7 (1) 64-Bit External Device/Big-Endian Access and Data Alignment...................... 423

Table 13.7 (2) 64-Bit External Device/Big-Endian Access and Data Alignment...................... 424

Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment .......................... 425

Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment .......................... 426

Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment ............................ 427

Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment ................. 428

Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment ................. 429

Table 13.12 32-Bit External Device/Little-Endian Access and Data Alignment ....................... 430

Table 13.13 16-Bit External Device/Little-Endian Access and Data Alignment ....................... 431

Table 13.14 8-Bit External Device/Little-Endian Access and Data Alignment ......................... 432

Table 13.15 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing... 451

Table 13.16 Example of Correspondence between this LSI and Synchronous DRAM Address

Pins (64-Bit Bus Width, AMX2–AMX0 = 011, AMXEXT = 0) ........................... 468

Table 13.17 Cycles for which Pipeline Access is Possible......................................................... 484

Table 13.18 Relationship between Address and CE when Using PCMCIA Interface ............... 502

Section 14 Direct Memory Access Controller (DMAC)

Table 14.1 DMAC Pins............................................................................................................ 549

Table 14.2 DMAC Pins in DDT Mode .................................................................................... 550

Table 14.3 DMAC Registers.................................................................................................... 550

Table 14.4 Selecting External Request Mode with RS Bits ..................................................... 570

Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits ...................... 572

Table 14.6 Supported DMA Transfers ..................................................................................... 576

Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode ......... 582

Table 14.8 External Request Transfer Sources and Destinations in Normal DMA Mode ....... 583

Table 14.9 External Request Transfer Sources and Destinations in DDT Mode ..................... 584

Table 14.10 Conditions for Transfer between External Memory and an External Device with

DACK, and Corresponding Register Settings ........................................................ 602

Table 14.11 DMAC Pins............................................................................................................ 636

Table 14.12 DMAC Pins in DDT Mode .................................................................................... 637

Table 14.13 Register Configuration ........................................................................................... 638

Table 14.14 Channel Selection by DTR Format (DMAOR.DBL = 1)....................................... 646

Table 14.15 Notification of Transfer Channel in Eight-Channel DDT Mode............................ 648

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REJ09B0366-0700

Table 14.16 Function of BAVL ................................................................................................. 648

Table 14.17 DTR Format for Clearing Request Queues ............................................................ 649

Table 14.18 DMAC Interrupt-Request Codes............................................................................ 650

Section 15 Serial Communication Interface (SCI)

Table 15.1 SCI Pins.................................................................................................................. 658

Table 15.2 SCI Registers.......................................................................................................... 659

Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode ................. 677

Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode.................... 681

Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator

(Asynchronous Mode)............................................................................................ 682

Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. 683

Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode).................... 683

Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection ........................................ 685

Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection.......................... 686

Table 15.10 Serial Transfer Formats (Asynchronous Mode) ..................................................... 688

Table 15.11 Receive Error Conditions....................................................................................... 696

Table 15.12 SCI Interrupt Sources............................................................................................. 718

Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data.............................................. 719

Table 15.14 Peripheral Module Signal Timing .......................................................................... 724

Section 16 Serial Communication Interface with FIFO (SCIF)

Table 16.1 SCIF Pins ............................................................................................................... 728

Table 16.2 SCIF Registers ....................................................................................................... 729

Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection ........................................ 758

Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection .............................................. 758

Table 16.5 Serial Transmit/Receive Formats ........................................................................... 759

Table 16.6 SCIF Interrupt Sources........................................................................................... 770

Section 17 Smart Card Interface

Table 17.1 Smart Card Interface Pins ...................................................................................... 777

Table 17.2 Smart Card Interface Registers............................................................................... 777

Table 17.3 Smart Card Interface Register Settings .................................................................. 785

Table 17.4 Values of n and Corresponding CKS1 and CKS0 Settings .................................... 788

Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0)....... 788

Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) .................... 788

Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) ............ 789

Table 17.8 Register Settings and SCK Pin State...................................................................... 789

Table 17.9 Smart Card Mode Operating States and Interrupt Sources..................................... 796

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Section 18 I/O Ports

Table 18.1 20-Bit General-Purpose I/O Port Pins .................................................................... 811

Table 18.2 SCI I/O Port Pins.................................................................................................... 812

Table 18.3 SCIF I/O Port Pins.................................................................................................. 812

Table 18.4 I/O Port Registers ................................................................................................... 813

Section 19 Interrupt Controller (INTC)

Table 19.1 INTC Pins............................................................................................................... 827

Table 19.2 INTC Registers....................................................................................................... 827

Table 19.3 IRL3–IRL0 Pins and Interrupt Levels.................................................................... 830

Table 19.4 SH7750 IRL3–IRL0 Pins and Interrupt Levels (When IRLM = 1)........................ 831

Table 19.5 Interrupt Exception Handling Sources and Priority Order ..................................... 833

Table 19.6 Interrupt Request Sources and IPRA–IPRD Registers........................................... 836

Table 19.7 Interrupt Request Sources and the Bits of the INTPRI00 Register ........................ 839

Table 19.8 Bit Assignments ..................................................................................................... 842

Table 19.9 Interrupt Response Time ........................................................................................ 846

Section 20 User Break Controller (UBC)

Table 20.1 UBC Registers........................................................................................................ 853

Section 21 High-performance User Debug Interface (H-UDI)

Table 21.1 H-UDI Pins............................................................................................................. 881

Table 21.2 H-UDI Registers..................................................................................................... 882

Table 21.3 Configuration of the Boundary Scan Register........................................................ 888

Section 22 Electrical Characteristics

Table 22.1 Absolute Maximum Ratings................................................................................... 895

Table 22.2 DC Characteristics (HD6417750RBP240 (V), HD6417750RBG240 (V)) ............ 896

Table 22.3 DC Characteristics (HD6417750RF240 (V)) ......................................................... 898

Table 22.4 DC Characteristics (HD6417750RBP200 (V), HD6417750RBG200 (V)) ............ 900

Table 22.5 DC Characteristics (HD6417750RF200 (V)) ......................................................... 902

Table 22.6 DC Characteristics (HD6417750SBP200 (V))....................................................... 904

Table 22.7 DC Characteristics (HD6417750SF200 (V)).......................................................... 906

Table 22.8 DC Characteristics (HD6417750BP200M (V))...................................................... 908

Table 22.9 DC Characteristics (HD6417750SF167 (V)).......................................................... 910

Table 22.10 DC Characteristics (HD6417750F167 (V))............................................................ 912

Table 22.11 DC Characteristics (HD6417750SVF133 (V))....................................................... 914

Table 22.12 DC Characteristics (HD6417750SVBT133 (V)).................................................... 916

Table 22.13 DC Characteristics (HD6417750VF128 (V))......................................................... 918

Table 22.14 Permissible Output Currents................................................................................... 919

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Table 22.15 Clock Timing (HD6417750RBP240 (V), HD6417750RBG240 (V)).................... 920

Table 22.16 Clock Timing (HD6417750RF240 (V))................................................................. 920

Table 22.17 Clock Timing (HD6417750BP200M (V), HD6417750SBP200 (V),

HD6417750RBP200 (V), HD6417750RBG200 (V))............................................. 920

Table 22.18 Clock Timing (HD6417750RF200 (V))................................................................. 920

Table 22.19 Clock Timing (HD6417750SF200 (V)) ................................................................. 921

Table 22.20 Clock Timing (HD6417750F167 (V), HD6417750SF167 (V)) ............................. 921

Table 22.21 Clock Timing (HD6417750SVF133 (V), HD6417750SVBT133 (V)) .................. 921

Table 22.22 Clock Timing (HD6417750VF128 (V))................................................................. 921

Table 22.23 Clock and Control Signal Timing (HD6417750RBP240 (V),

HD6417750RBG240 (V)) ...................................................................................... 922

Table 22.24 Clock and Control Signal Timing (HD6417750RF240 (V)).................................. 924

Table 22.25 Clock and Control Signal Timing (HD6417750RBP200 (V),

HD6417750RBG200 (V)) ...................................................................................... 926

Table 22.26 Clock and Control Signal Timing (HD6417750RF200 (V)).................................. 928

Table 22.27 Clock and Control Signal Timing (HD6417750BP200M (V),

HD6417750SBP200 (V)) ....................................................................................... 930

Table 22.28 Clock and Control Signal Timing (HD6417750SF200 (V)) .................................. 932

Table 22.29 Clock and Control Signal Timing (HD6417750F167 (V),

HD6417750SF167 (V)).......................................................................................... 934

Table 22.30 Clock and Control Signal Timing (HD6417750SVF133 (V),

HD6417750SVBT133 (V)) .................................................................................... 936

Table 22.31 Clock and Control Signal Timing (HD6417750VF128 (V)).................................. 938

Table 22.32 Control Signal Timing (1) ...................................................................................... 946

Table 22.32 Control Signal Timing (2) ...................................................................................... 947

Table 22.33 Bus Timing (1) ....................................................................................................... 950

Table 22.33 Bus Timing (2) ....................................................................................................... 952

Table 22.33 Bus Timing (3) ....................................................................................................... 954

Table 22.34 Peripheral Module Signal Timing (1)................................................................... 1003

Table 22.34 Peripheral Module Signal Timing (2)................................................................... 1005

Table 22.34 Peripheral Module Signal Timing (3)................................................................... 1007

Table 22.34 Peripheral Module Signal Timing (4)................................................................... 1008

Table 22.34 Peripheral Module Signal Timing (5)................................................................... 1010

Appendix A Address List

Table A.1 Address List ......................................................................................................... 1017

Appendix E Pin Functions

Table E.1 Pin States in Reset, Power-Down State, and Bus-Released State ........................ 1033

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Appendix I Product Lineup

Table I.1 SH7750/SH7750S/SH7750R Product Lineup ...................................................... 1065

Appendix J Version Registers

Table J.1 Register Configuration ......................................................................................... 1067

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Section 1 Overview

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Section 1 Overview

1.1 SH7750, SH7750S, SH7750R Groups Features

This LSI (SH7750, SH7750S, and SH7750R Groups) is a 32-bit RISC (reduced instruction set

computer) microprocessor with a SH-4 CPU core and features upward compatibility with SH-1,

SH-2, and SH-3 microcomputers at the instruction set level. It includes an instruction cache, an

operand cache with a choice of copy-back or write-through mode, and an MMU (memory

management unit) with a 64-entry fully-associative unified TLB (translation lookaside buffer).

The SH7750 and SH7750S have an 8-Kbyte instruction cache and a 16-Kbyte data cache. The

SH7750R has a 16-Kbyte instruction cache and a 32-Kbyte data cache.

This LSI has an on-chip bus state controller (BSC) that allows connection to DRAM and

synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be

reduced by almost 50% compared with 32-bit instructions.

The features of this LSI are summarized in table 1.1.

Table 1.1 LSI Features

Item Features

LSI • Superscalar architecture: Parallel execution of two instructions

• External buses

⎯ Separate 26-bit address and 64-bit data buses

⎯ External bus frequency of 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus

frequency

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Item Features

CPU • Renesas Technology original SuperH architecture

• 32-bit internal data bus

• General register file:

⎯ Sixteen 32-bit general registers (and eight 32-bit shadow registers)

⎯ Seven 32-bit control registers

⎯ Four 32-bit system registers

• RISC-type instruction set (upward-compatible with SH-1, SH-2, and SH-3)

⎯ Fixed 16-bit instruction length for improved code efficiency

⎯ Load-store architecture

⎯ Delayed branch instructions

⎯ Conditional execution

⎯ C-based instruction set

• Superscalar architecture (providing simultaneous execution of two

instructions) including FPU

• Instruction execution time: Maximum 2 instructions/cycle

• Virtual address space: 4 Gbytes (448-Mbyte external memory space)

• Space identifier ASIDs: 8 bits, 256 virtual address spaces

• On-chip multiplier

• Five-stage pipeline

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Item Features

FPU • On-chip floating-point coprocessor

• Supports single-precision (32 bits) and double-precision (64 bits)

• Supports IEEE754-compliant data types and exceptions

• Two rounding modes: Round to Nearest and Round to Zero

• Handling of denormalized numbers: Truncation to zero or interrupt

generation for compliance with IEEE754

• Floating-point registers: 32 bits × 16 × 2 banks

(single-precision 32 bits × 16 or double-precision 64 bits × 8) × 2 banks

• 32-bit CPU-FPU floating-point communication register (FPUL)

• Supports FMAC (multiply-and-accumulate) instruction

• Supports FDIV (divide) and FSQRT (square root) instructions

• Supports FLDI0/FLDI1 (load constant 0/1) instructions

• Instruction execution times

⎯ Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8

cycles (double-precision)

⎯ Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6 cycles

(double-precision)

Note: FMAC is supported for single-precision only.

• 3-D graphics instructions (single-precision only):

⎯ 4-dimensional vector conversion and matrix operations (FTRV): 4

cycles (pitch), 7 cycles (latency)

⎯ 4-dimensional vector inner product (FIPR): 1 cycle (pitch), 4 cycles

(latency)

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Item Features

Clock pulse

generator (CPG)

• Choice of main clock:

⎯ SH7750, SH7750S: 1/2, 1, 3, or 6 times EXTAL

⎯ SH7750R: 1, 6, or 12 times EXTAL

• Clock modes:

⎯ CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock

⎯ Bus frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock

⎯ Peripheral frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock

Note: Maximum frequency varies with models.

• Power-down modes

⎯ Sleep mode

⎯ Standby mode

⎯ Module standby function

• Single-channel watchdog timer

Memory

management

unit (MMU)

• 4-Gbyte address space, 256 address space identifiers (8-bit ASIDs)

• Single virtual mode and multiple virtual memory mode

• Supports multiple page sizes: 1 Kbyte, 4 Kbytes, 64 Kbytes, 1 Mbyte

• 4-entry fully-associative TLB for instructions

• 64-entry fully-associative TLB for instructions and operands

• Supports software-controlled replacement and random-counter

replacement algorithm

• TLB contents can be accessed directly by address mapping

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Item Features

Cache memory

[SH7750, SH7750S]

• Instruction cache (IC)

⎯ 8 Kbytes, direct mapping

⎯ 256 entries, 32-byte block length

⎯ Normal mode (8-Kbyte cache)

⎯ Index mode

• Operand cache (OC)

⎯ 16 Kbytes, direct mapping

⎯ 512 entries, 32-byte block length

⎯ Normal mode (16-Kbyte cache)

⎯ Index mode

⎯ RAM mode (8-Kbyte cache + 8-Kbyte RAM)

⎯ Choice of write method (copy-back or write-through)

• Single-stage copy-back buffer, single-stage write-through buffer

• Cache memory contents can be accessed directly by address mapping

(usable as on-chip memory)

• Store queue (32 bytes × 2 entries)

Cache memory

[SH7750R]

• Instruction cache (IC)

⎯ 16 Kbytes, 2-way set associative

⎯ 256 entries/way, 32-byte block length

⎯ Cache-double-mode (16-Kbyte cache)

⎯ Index mode

⎯ SH7750/SH7750S-compatible mode (8 Kbytes, direct mapping)

• Operand cache (OC)

⎯ 32 Kbytes, 2-way set associative

⎯ 512 entries/way, 32-byte block length

⎯ Cache-double-mode (32-Kbyte cache)

⎯ Index mode

⎯ RAM mode (16-Kbyte cache + 16-Kbyte RAM)

⎯ SH7750/SH7750S-compatible mode (16 Kbytes, direct mapping)

• Single-stage copy-back buffer, single-stage write-through buffer

• Cache memory contents can be accessed directly by address mapping

(usable as on-chip memory)

• Store queue (32 bytes × 2 entries)

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Item Features

Interrupt controller

(INTC)

• Five independent external interrupts: NMI, IRL3 to IRL0

• 15-level encoded external interrupts: IRL3 to IRL0

• On-chip peripheral module interrupts: Priority level can be set for each

module

User break

controller (UBC)

• Supports debugging by means of user break interrupts

• Two break channels

• Address, data value, access type, and data size can all be set as break

conditions

• Supports sequential break function

Bus state

controller (BSC)

• Supports external memory access

⎯ 64/32/16/8-bit external data bus

• External memory space divided into seven areas, each of up to 64

Mbytes, with the following parameters settable for each area:

⎯ Bus size (8, 16, 32, or 64 bits)

⎯ Number of wait cycles (hardware wait function also supported)

⎯ Connection of DRAM, synchronous DRAM, and burst ROM possible

by setting space type

⎯ Supports fast page mode and DRAM EDO

⎯ Supports PCMCIA interface

⎯ Chip select signals (CS0 to CS6) output for relevant areas

• DRAM/synchronous DRAM refresh functions

⎯ Programmable refresh interval

⎯ Supports CAS-before-RAS refresh mode and self-refresh mode

• DRAM/synchronous DRAM burst access function

• Big endian or little endian mode can be set

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Item Features

Direct memory

access controller

(DMAC)

• Physical address DMA controller:

⎯ SH7750, SH7750S: 4-channel

⎯ SH7750R: 8-channel

• Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes

• Address modes:

⎯ Single address mode

⎯ Dual address mode

• Transfer requests: External, on-chip module, or auto-requests

• Bus modes: Cycle-steal or burst mode

• Supports on-demand data transfer

Timer unit (TMU) • Auto-reload 32-bit timer:

⎯ SH7750, SH7750S: 3-channel

⎯ SH7750R: 5-channel

• Input capture function

• Choice of seven counter input clocks

Realtime clock

(RTC)

• On-chip clock and calendar functions

• Built-in 32 kHz crystal oscillator with maximum 1/256 second resolution

(cycle interrupts)

Serial

communication

interface

(SCI, SCIF)

• Two full-duplex communication channels (SCI, SCIF)

• Channel 1 (SCI):

⎯ Choice of asynchronous mode or synchronous mode

⎯ Supports smart card interface

• Channel 2 (SCIF):

⎯ Supports asynchronous mode

⎯ Separate 16-byte FIFOs provided for transmitter and receiver

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Item Features

Product lineup Abbre-

viation

Voltage

(Internal)

Operating

Frequency

Model No.

Package

SH7750 1.95 V 200 MHz HD6417750BP200M 256-pin BGA

1.8 V 167 MHz HD6417750F167

1.5 V 128 MHz HD6417750VF128

208-pin QFP

SH7750S 1.95 V 200 MHz HD6417750SBP200 256-pin BGA

HD6417750SF200

1.8 V 167 MHz HD6417750SF167

1.5 V 133 MHz HD6417750SVF133

208-pin QFP

HD6417750SVBT133 264-pin CSP

SH7750R 1.5 V 240 MHz HD6417750RBG240 292-pin BGA

HD6417750RBP240 256-pin BGA

HD6417750RF240 208-pin QFP

200 MHz HD6417750RBG200 292-pin BGA

HD6417750RBP200 256-pin BGA

HD6417750RF200 208-pin QFP

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1.2 Block Diagram

Figure 1.1 shows an internal block diagram of this LSI.

CPG

INTC

SCI

(SCIF)

RTC

TMU

External

bus interface

BSC DMAC

Address 29-bit address

64-bit data

32-bit data

Upper 32-bit data

32-bit address (instructions)

32-bit data (instructions)

32-bit address (data)

Peripheral address bus

26-bit

address 64-bit

data

16-bit peripheral data bus

UBC

Lower 32-bit data

32-bit data (load)

32-bit data (store)

CPU

I cache O cacheITLB UTLB

Cache and

TLB

controller

FPU

SH-4 Core

64-bit data (store)

Legend:

BSC: Bus state controller

CPG: Clock pulse generator

DMAC: Direct memory access controller

FPU: Floating-point unit

INTC: Interrupt controller

ITLB: Instruction TLB (translation lookaside buffer)

UTLB: Unified TLB (translation lookaside buffer)

RTC: Realtime clock

SCI: Serial communication interface

SCIF: Serial communication interface with FIFO

TMU: Timer unit

UBC: User break controller

Figure 1.1 Block Diagram of SH7750/SH7750S/SH7750R Group Functions

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1.3 Pin Arrangement

NMI

IRL3

IRL2

IRL1

IRL0

MD1/TXD2

MD0/SCK

D50

D51

D52

D53

D63

D62

D61

D57

D56

D31

D30

D29

D28

D27

D26

D25

D54

D55

D16

D17

D18

D19

D20

D21

D48

D49

D60

D59

D58

RDY

RESET

CS0

CS1

CS6

EXTAL

CKIO2ENB

XTAL

VSS-CPG

VDD-CPG(3.3V)

VDD-PLL1(3.3V)

VDD-PLL2(3.3V)

TDI

TCK

TMS

TDO

ASEBRK/BRKACK

MD6/IOIS16

STATUS1

STATUS0

DACK1

DACK0

MD5/RAS2

MD4/CE2B

MD3/CE2A

A25

A24

A23

A22

A21

A20

A19

A18

MD7/TXD

SCK2/MRESET

MD8/RTS2

TCLK

VDD-RTC(3.3V)

VSS-RTC

EXTAL2

XTAL2

CKE

WE5/CAS5/DQM5

WE4/CAS4/DQM4

WE1/CAS1/DQM1

WE0/CAS0/DQM0

A17

A16

A15

A14

A13

A12

A11

A10

CKIO

CKIO2

CS3

CS2

RAS

RD/CASS/FRAME

RD/WR

WE2/CAS2/DQM2/ICIORD

WE3/CAS3/DQM3/ICIOWR

WE6/CAS6/DQM6

WE7/CAS7/DQM7/REG

D23

D24

D22

1234567891011121314151617 192018

D47

D46

D45

D44

D43

D42

D32

D33

D34

D35

D36

D37

CS4

TRST

CTS2

DRAK0

DRAK1

VSS-PLL1

VSS-PLL2

CS5

RD2

RD/WR2

BGA256

(Top view)

MD2/RXD2

DREQ1

DREQ0

RXD

BACK/BSREQ

D41

D40

D15

D14

D13

D12

D11

D10

D38

D39

BREQ/BSACK

VDDQ (IO)

VSSQ (IO)

VDD (internal)

VSS (internal)

CA*

Notes: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2,

VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation

circuit, and RTC are used.

* Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V.

Figure 1.2 Pin Arrangement (256-Pin BGA)

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 11 of 1074

REJ09B0366-0700

RDY

RESET

CS0

CS1

CS4

CS5

CS6

D47

D32

D46

D33

D45

D34

D44

D35

D43

D36

D42

D37

D41

D38

D40

D39

D15

D14

D13

D12

D11

D10

BACK/BSREQ

BREQ/BSACK

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

NMI

IRL3

IRL2

IRL1

IRL0

MD2/RXD2

MD1/TXD2

MD0/SCK

D63

D48

D62

D49

D61

D50

D60

D51

D59

D52

D58

D53

D57

D54

D56

D55

D31

D16

D30

D17

D29

D18

D28

D19

D27

D20

D26

D21

D25

DREQ1

DREQ0

RXD

100

101

102

103

104

CKE

WE5/CAS5/DQM5

WE4/CAS4/DQM4

WE1/CAS1/DQM1

WE0/CAS0/DQM0

A17

A16

A15

A14

A13

A12

A11

A10

CKIO

DRAK1

DRAK0

CS3

CS2

RAS

RD/CASS/FRAME

RD/WR

WE2/CAS2/DQM2/IOICRD

WE3/CAS3/DQM3/IOICWR

WE6/CAS6/DQM6

WE7/CAS7/DQM7/REG

D23

D24

D22

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

EXTAL

XTAL

VSS-CPG

VDD-CPG(3.3V)

VSS-PLL1

VDD-PLL1(3.3V)

VSS-PLL2

VDD-PLL2(3.3V)

TRST

TDI

TCK

TMS

TDO

ASEBRK/BRKACK

MD6/IOIS16

STATUS1

STATUS0

DACK1

DACK0

MD5/RAS2

MD4/CE2B

MD3/CE2A

A25

A24

A23

A22

A21

A20

A19

A18

SCK2/MRESET

MD7/TXD

MD8/RTS2

TCLK

CTS2

CA*

VDD-RTC(3.3V)

VSS-RTC

EXTAL2

XTAL2

QFP208

Top view

VDD (internal)

VSS (internal)

VDDQ (IO)

VSSQ (IO)

Notes: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2,

VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation

circuit, and RTC are used.

* Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V.

Figure 1.3 Pin Arrangement (208-Pin QFP)

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 12 of 1074

REJ09B0366-0700

VDDQ (IO)

VSSQ (IO)

VDD (internal)

VSS (internal)

VSS-CPG XTAL EXTAL VDD-CPG TRST TDO MD6/IOIS16 A0 VDDQ VDDQ A20 VDD TCLK VSS-RTC XTAL2 EXTAL2 IRL2

RESET CS4 VDD-PLL2 VSS STATUS0 DACK0 A24 VDDQ MD7/TXD CA IRL3

RDY VSS-PLL2 VSS-PLL1 VDD-PLL1 TCK VSSQ VSSQ MD3/CE2A A22 A18 VDDQ VDDQ VDD-RTC MD1/TXD2 NMI

CS0 VSSQ CKIO2ENB TDI VDD A1 MD5/RAS2 A23 VSS MD8/RTS2 CTS2 VSSQ IRL0 IRL1

BS CS1 CS5 CS6 TMS ASEBRK/

BRKACK VDDQ VDDQ MD4/CE2B VSSQ VSSQ SCK2/

MRESET D48 RD/WR2 MD2/RXD2 VSSQ

VDD D47 VDDQ RD2 D32 D33 STATUS1 DACK1 VSSQ A25 A21 A19 D49 VDDQ D63 MD0/SCK D62

D45 VDDQ D46 VSS VSSQ D34 D50 VDDQ VDD VSSQ VSS D61

VDDQ D43 D44 D35 VSSQ D36 D52 VDDQ D51 VSSQ D60 D59

VDDQ D38 D42 D41 D37 VSSQ VSSQ D57 D53 D54 D58 VDDQ

D39 D0 VSSQ D15 VDDQ D40 D56 VSSQ D31 D16 D55 VDDQ

D1 VSS VSSQ VDD VDDQ D14 D30 VSSQ VSS D18 VDDQ D17

D2 D4 D3 VDDQ D13 A14 A9 VDDQ A6 A2 D29 D28 D27 VDDQ D19 VDD

VSSQ D5 D11 D12 A16 VDDQ VDDQ A7 A4 DRAK0 VSSQ VSS D26 D21 VDDQ D20

VSSQ VDDQ VDDQ

WE4/CAS4/

DQM4

WE0/CAS0/

DQM0

VDD A11 VSSQ VSSQ CS2 RD/CASS/

FRAME VSSQ VSSQ D25 DREQ1

D6 BREQ/

BSACK D10 CKE WE5/CAS5/

DQM5 A17 VSS A12 A8 VDDQ VDDQ RAS

WE3/CAS3/

DQM3/ICIOWR

WE6/CAS6/

DQM6

WE2/CAS2/

DQM2/ICIORD

RXD

BACK/

BSREQ VSSQ D8 VDDQ VSSQ A13 VSSQ CKIO2 A3 VDD RD/WR D24 D22 VSSQ DREQ0

D9 D7 WE1/CAS1/

DQM1 A15 VSSQ A10 CKIO A5 DRAK1 CS3 VDDQ VDDQ WE7/CAS7/

DQM7/REG D23 VSSQ

234567891011121314151617

CSP264

(Top view)

Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2,

VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation

circuit, and RTC are used.

Figure 1.4 Pin Arrangement (264-Pin CSP)

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 13 of 1074

REJ09B0366-0700

XTAL2

VSS-RTC

NMI

IRL1

IRL2

MD2/RXD2

IRL0

D49

D50

D51

D52

RD/WR2

D62

D61

D57

D56

D31

D30

D29

D28

D27

D21

DREQ1

D54

D55

D16

D17

D18

D19

D20

D25

MD0/SCK

D48

D60

D59

D58

RDY

RESET

CS0

CS1

CS5

CS6

EXTAL

VSS-PLL1

XTAL

VDD-CPG(3.3V)

VSS-CPG

VSS-PLL2

VDD-PLL1(3.3V)

TRST

VDD-PLL2(3.3V)

TMS

TCK

MD6/IOIS16

ASEBRK/BRKACK

STATUS0

STATUS1

DACK0

DACK1

MD5/RAS2

MD4/CE2B

MD3/CE2A

A25

A24

A23

A22

A21

A20

A19

A18

SCK2/MRESET

MD7/TXD

TCLK

CTS2

VDD-RTC(3.3V)

VSS-RTC

EXTAL2

IRL3

CKE

WE5/CAS5/DQM5

WE1/CAS1/DQM1

WE0/CAS0/DQM0

A17

A16

A15

A14

A13

A12

A11

A10

CKIO

DRAK1

CS3

DRAK0

RAS

CS2

RD/WR

RD/CASS/FRAME

WE6/CAS6/DQM6

WE3/CAS3/DQM3/ICIOWR

D24

D23

D22

DREQ0

RXD

1234567891011121314151617 192018

RD2

D32

D33

D34

D35

D36

D47

D46

D45

D44

D43

D42

CKIO2ENB

MD8/

RTS2

CKIO2

TDI

TDO

CS4

D37

D53

D63

BGA292

(Top view)

MD1/TXD2

D26

WE2/CAS2/

DQM2/ICIORD

D11

D41

D40

D15

D14

D13

D12

BACK/

BSREQ

BREQ/

BSACK

D38

D39

D10

WE4/CAS4/DQM4

VDDQ (IO)

VDD (internal)

VSS

WE7/CAS7/DQM7

REG

Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2,

VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation

circuit, and RTC are used.

Figure 1.5 Pin Arrangement (292-Pin BGA)

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 14 of 1074

REJ09B0366-0700

1.4 Pin Functions

1.4.1 Pin Functions (256-Pin BGA)

Table 1.2 Pin Functions

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

1 B2 RDY I Bus ready RDY RDY RDY

2 B1 RESET I Reset RESET

3 C2 CS0 O Chip select 0 CS0 CS0

4 C1 CS1 O Chip select 1 CS1 CS1

5 D4 CS4 O Chip select 4 CS4 CS4

6 D3 CS5 O Chip select 5 CS5 CE1A CS5

7 D2 CS6 O Chip select 6 CS6 CE1B CS6

8 D1 BS O Bust start (BS) (BS) (BS) (BS) (BS)

9 E4 VSSQ Power IO GND (0 V)

10 E3 RD2 O RD/CASS/

FRAME

OE CAS OE FRAME

11 F3 VDDQ Power IO VDD (3.3 V)

12 F4 VSSQ Power IO GND (0 V)

13 E2 D47 I/O Data/port (Port) (Port) (Port) (Port) (Port)

14 E1 D32 I/O Data/port (Port) (Port) (Port) (Port) (Port)

15 G3 VDD Power Internal VDD

(1.8 V)

16 G4 VSS Power Internal GND

(0 V)

17 F2 D46 I/O Data/port (Port) (Port) (Port) (Port) (Port)

18 F1 D33 I/O Data/port (Port) (Port) (Port) (Port) (Port)

19 H3 VDDQ Power IO VDD (3.3 V)

20 H4 VSSQ Power IO GND (0 V)

21 G2 D45 I/O Data/port (Port) (Port) (Port) (Port) (Port)

22 G1 D34 I/O Data/port (Port) (Port) (Port) (Port) (Port)

23 H2 D44 I/O Data/port (Port) (Port) (Port) (Port) (Port)

24 H1 D35 I/O Data/port (Port) (Port) (Port) (Port) (Port)

25 J3 VDDQ Power IO VDD (3.3 V)

26 J4 VSSQ Power IO GND (0 V)

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 15 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

27 J2 D43 I/O Data/port (Port) (Port) (Port) (Port) (Port)

28 J1 D36 I/O Data/port (Port) (Port) (Port) (Port) (Port)

29 K2 D42 I/O Data/port (Port) (Port) (Port) (Port) (Port)

30 K1 D37 I/O Data/port (Port) (Port) (Port) (Port) (Port)

31 K3 VDDQ Power IO VDD (3.3 V)

32 K4 VSSQ Power IO GND (0 V)

33 L1 D41 I/O Data/port (Port) (Port) (Port) (Port) (Port)

34 L2 D38 I/O Data/port (Port) (Port) (Port) (Port) (Port)

35 M1 D40 I/O Data/port (Port) (Port) (Port) (Port) (Port)

36 M2 D39 I/O Data/port (Port) (Port) (Port) (Port) (Port)

37 L3 VDDQ Power IO VDD (3.3 V)

38 L4 VSSQ Power IO GND (0 V)

39 N1 D15 I/O Data A15

40 N2 D0 I/O Data A0

41 P1 D14 I/O Data A14

42 P2 D1 I/O Data A1

43 M3 VDDQ Power IO VDD (3.3 V)

44 M4 VSSQ Power IO GND (0 V)

45 R1 D13 I/O Data A13

46 R2 D2 I/O Data A2

47 P3 VDD Power Internal VDD

48 P4 VSS Power Internal GND

(0 V)

49 T1 D12 I/O Data A12

50 T2 D3 I/O Data A3

51 R3 VDDQ Power IO VDD (3.3 V)

52 R4 VSSQ Power IO GND (0 V)

53 U1 D11 I/O Data A11

54 U2 D4 I/O Data A4

55 V1 D10 I/O Data A10

56 V2 D5 I/O Data A5

57 T3 VDDQ Power IO VDD (3.3 V)

58 T4 VSSQ Power IO GND (0 V)

59 W1 D9 I/O Data A9

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 16 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

60 Y1 D6 I/O Data A6

61 U3 BACK/

BSREQ

O Bus

acknowledge/

bus request

62 V3 BREQ/

BSACK

I Bus

request/bus

acknowledge

63 W2 D8 I/O Data A8

64 Y2 D7 I/O Data A7

65 W3 CKE O Clock output

enable

CKE

66 V5 VDDQ Power IO VDD (3.3 V)

67 U5 VSSQ Power IO GND (0 V)

68 Y3 WE5/CAS5/

DQM5

O D47–D40 select

signal

WE5 CAS5 DQM5

69 W4 WE4/CAS4/

DQM4

O D39–D32 select

signal

WE4 CAS4 DQM4

70 Y4 WE1/CAS1/

DQM1

O D15–D8 select

signal

WE1 CAS1 DQM1 WE1

71 W5 WE0/CAS0/

DQM0

O D7–D0 select

signal

WE0 CAS0 DQM0

72 Y5 A17 O Address

73 V6 VDDQ Power IO VDD (3.3 V)

74 U6 VSSQ Power IO GND (0 V)

75 W6 A16 O Address

76 Y6 A15 O Address

77 V7 VDD Power Internal VDD

78 U7 VSS Power Internal GND

(0 V)

79 W7 A14 O Address

80 Y7 A13 O Address

81 V8 VDDQ Power IO VDD (3.3 V)

82 U8 VSSQ Power IO GND (0 V)

83 V4 NC

84 W8 A12 O Address

85 Y8 A11 O Address

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 17 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

86 W9 A10 O Address

87 V9 VDDQ Power IO VDD (3.3 V)

88 U9 VSSQ Power IO GND (0 V)

89 Y9 A9 O Address

90 W10 A8 O Address

91 Y10 A7 O Address

92 Y11 CKIO O Clock output CKIO CKIO CKIO

93 V10 VDDQ Power IO VDD (3.3 V)

94 U10 VSSQ Power IO GND (0 V)

95 W11 CKIO2 O CKIO*1 CKIO CKIO CKIO

96 Y12 A6 O Address

97 W12 A5 O Address

98 Y13 A4 O Address

99 V11 VDDQ Power IO VDD (3.3 V)

100 U11 VSSQ Power IO GND (0 V)

101 W13 A3 O Address

102 Y14 A2 O Address

103 V12 DRAK1 O DMAC1 request

acknowledge

104 U13 DRAK0 O DMAC0 request

acknowledge

105 V13 VDDQ Power IO VDD (3.3 V)

106 U12 VSSQ Power IO GND (0 V)

107 W14 CS3 O Chip select 3 CS3 (CS3) CS3 CS3

108 Y15 CS2 O Chip select 2 CS2 (CS2) CS2 CS2

109 V14 VDD Power Internal VDD

110 U14 VSS Power Internal GND

(0 V)

111 W15 RAS O RAS RAS RAS

112 Y16 RD/CASS/

FRAME

O Read/CAS/

FRAME

OE CAS OE FRAME

113 V15 VDDQ Power IO VDD (3.3 V)

114 U15 VSSQ Power IO GND (0 V)

115 W16 RD/WR O Read/write RD/WR RD/WR RD/WR RD/WR RD/WR

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 18 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

116 Y17 WE2/CAS2/

DQM2/

ICIORD

O D23–D16 select

signal

WE2 CAS2 DQM2 ICIORD

117 W17 WE3/CAS3/

DQM3/

ICIOWR

O D31–D24 select

signal

WE3 CAS3 DQM3 ICIOWR

118 Y18 WE6/CAS6/

DQM6

O D55–D48 select

signal

WE6 CAS6 DQM6

119 V16 VDDQ Power IO VDD (3.3 V)

120 U16 VSSQ Power IO GND (0 V)

121 W18 WE7/CAS7/

DQM7/REG

O D63–D56 select

signal

WE7 CAS7 DQM7 REG

122 Y19 D23 I/O Data A23

123 W19 D24 I/O Data A24

124 Y20 D22 I/O Data A22

125 V17 RXD I SCI data input

126 U17 DREQ0 I Request from

DMAC0

127 U18 DREQ1 I Request from

DMAC1

128 W20 D25 I/O Data A25

129 T18 VDDQ Power IO VDD (3.3 V)

130 T17 VSSQ Power IO GND (0 V)

131 V19 D21 I/O Data A21

132 V20 D26 I/O Data

133 U19 D20 I/O Data A20

134 U20 D27 I/O Data

135 R18 VDDQ Power IO VDD (3.3 V)

136 R17 VSSQ Power IO GND (0 V)

137 T19 D19 I/O Data A19

138 T20 D28 I/O Data

139 P18 VDD Power Internal VDD

140 P17 VSS Power Internal GND

(0 V)

141 R19 D18 I/O Data A18

142 R20 D29 I/O Data

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 19 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

143 N18 VDDQ Power IO VDD (3.3 V)

144 N17 VSSQ Power IO GND (0 V)

145 P19 D17 I/O Data A17

146 P20 D30 I/O Data

147 N19 D16 I/O Data A16

148 N20 D31 I/O Data

149 M18 VDDQ Power IO VDD (3.3 V)

150 M17 VSSQ Power IO GND (0 V)

151 M19 D55 I/O Data

152 M20 D56 I/O Data

153 L19 D54 I/O Data

154 L20 D57 I/O Data

155 L18 VDDQ Power IO VDD (3.3 V)

156 L17 VSSQ Power IO GND (0 V)

157 K20 D53 I/O Data

158 K19 D58 I/O Data

159 J20 D52 I/O Data

160 J19 D59 I/O Data

161 K18 VDDQ Power IO VDD (3.3 V)

162 K17 VSSQ Power IO GND (0 V)

163 H20 D51 I/O Data/port (Port) (Port) (Port) (Port) (Port)

164 H19 D60 I/O Data

165 G20 D50 I/O Data/port (Port) (Port) (Port) (Port) (Port)

166 G19 D61 I/O Data ACCSIZE0

167 J18 VDDQ Power IO VDD (3.3 V)

168 J17 VSSQ Power IO GND (0 V)

169 F20 D49 I/O Data/port (Port) (Port) (Port) (Port) (Port)

170 F19 D62 I/O Data ACCSIZE1

171 G18 VDD Power Internal VDD

172 G17 VSS Power Internal GND

(0 V)

173 E20 D48 I/O Data/port (Port) (Port) (Port) (Port) (Port)

174 E19 D63 I/O Data ACCSIZE2

175 F18 VDDQ Power IO VDD (3.3 V)

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 20 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

176 F17 VSSQ Power IO GND (0 V)

177 E17 VSSQ Power IO GND (0 V)

178 E18 RD/WR2 O RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR

179 D20 MD0/SCK I/O Mode/SCI

clock

MD0 SCK SCK SCK SCK SCK

180 D19 MD1/TXD2 I/O Mode SCIF

data output

MD1 TXD2 TXD2 TXD2 TXD2 TXD2

181 D18 MD2/RXD2 I Mode/SCIF

data input

MD2 RXD2 RXD2 RXD2 RXD2 RXD2

182 C20 IRL0 I Interrupt 0

183 C19 IRL1 I Interrupt 1

184 B20 IRL2 I Interrupt 2

185 C18 IRL3 I Interrupt 3

186 A20 NMI I Nonmaskable

interrupt

187 B19 XTAL2 O RTC crystal

resonator pin

188 A19 EXTAL2 I RTC crystal

resonator pin

189 B18 VSS-RTC Power RTC GND

(0 V)

190 A18 VDD-RTC Power RTC VDD

(3.3 V)

191 D17 CA I *2

192 C17 VSS Power Internal GND

(0 V)

193 B17 VDDQ Power IO VDD (3.3 V)

194 C16 CTS2 I/O SCIF data

control (CTS)

195 A17 TCLK I/O RTC/TMU

clock

196 B16 MD8/RTS2 I/O Mode/SCIF

data control

(RTS)

MD8 RTS2 RTS2 RTS2 RTS2 RTS2

197 C15 VDDQ Power IO VDD (3.3 V)

198 D15 VSSQ Power IO GND (0 V)

199 B15 MD7/TXD I/O Mode/SCI

data output

MD7 TXD TXD TXD TXD TXD

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 21 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

200 A16 SCK2/

MRESET

I SCIF clock/

manual reset

MRESET SCK2 SCK2 SCK2 SCK2 SCK2

201 C14 VDD Power Internal VDD

202 D14 VSS Power Internal GND

(0 V)

203 A15 A18 O Address

204 B14 A19 O Address

205 C13 VDDQ Power IO VDD (3.3 V)

206 D13 VSSQ Power IO GND (0 V)

207 A14 A20 O Address

208 B13 A21 O Address

209 A13 A22 O Address

210 B12 A23 O Address

211 C12 VDDQ Power IO VDD (3.3 V)

212 D12 VSSQ Power IO GND (0 V)

213 A12 A24 O Address

214 B11 A25 O Address

215 A11 MD3/CE2A I/O Mode/

PCMCIA-CE

MD3 CE2A

216 A10 MD4/CE2B I/O Mode/

PCMCIA-CE

MD4 CE2B

217 C11 VDDQ Power IO VDD (3.3 V)

218 D11 VSSQ Power IO GND (0 V)

219 B10 MD5/RAS2 I/O Mode/RAS

(DRAM)

MD5 RAS2

220 A9 DACK0 O DMAC0 bus

acknowledge

221 B9 DACK1 O DMAC1 bus

acknowledge

222 C8 A0 O Address

223 C10 VDDQ Power IO VDD (3.3 V)

224 D10 VSSQ Power IO GND (0 V)

225 D8 A1 O Address

226 A8 STATUS0 O Status

227 B8 STATUS1 O Status

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 22 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

228 A7 MD6/

IOIS16

I Mode/IOIS16

(PCMCIA)

MD6 IOIS16

229 C9 VDDQ Power IO VDD (3.3 V)

230 D9 VSSQ Power IO GND (0 V)

231 B7 ASEBRK/

BRKACK

I/O Pin break/

acknowledge

(H-UDI)

232 A6 TDO O Data out

(H-UDI)

233 C7 VDD Power Internal VDD

234 D7 VSS Power Internal GND

(0 V)

235 B6 TMS I Mode

(H-UDI)

236 A5 TCK I Clock

(H-UDI)

237 B5 TDI I Data in

(H-UDI)

238 C4 TRST I Reset

(H-UDI)

239 C3 CKIO2ENB I CKIO2, RD2,

RD/WR2

enable

240 C6 NC

241 A4 VDD-PLL2 Power PLL2 VDD

(3.3V)

242 D6 VSS-PLL2 Power PLL2 GND (0V)

243 B4 VDD-PLL1 Power PLL1 VDD

(3.3V)

244 D5 VSS-PLL1 Power PLL1 GND (0V)

245 A3 VDD-CPG Power CPG VDD

(3.3V)

246 B3 VSS-CPG Power CPG GND (0V)

247 A2 XTAL O Crystal

resonator

248 A1 EXTAL I External input

clock/crystal

resonator

249 C5 NC

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REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

250 D16 NC

251 H17 NC

252 H18 NC

253 N3 NC

254 N4 NC

255 U4 NC

256 V18 NC

Legend:

I: Input

O: Output

I/O: Input/output

Power: Power supply

Notes: Supply power to all power pins. For the SH7750S, supply power to RTC at a minimum in

hardware standby mode.

Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the

on-chip PLL circuits are used.

Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-

chip crystal oscillation circuit is used.

Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-

chip RTC is used.

VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG are connected inside the package.

NC pins must be left completely open, and not connected to a power supply, GND, etc.

1. CKIO2 is not connected to PLL2.

2. Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V.

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 24 of 1074

REJ09B0366-0700

1.4.2 Pin Functions (208-Pin QFP)

Table 1.3 Pin Functions

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

1 RDY I Bus ready RDY RDY RDY

2 RESET I Reset RESET

3 CS0 O Chip select 0 CS0 CS0

4 CS1 O Chip select 1 CS1 CS1

5 CS4 O Chip select 4 CS4 CS4

6 CS5 O Chip select 5 CS5 CE1A CS5

7 CS6 O Chip select 6 CS6 CE1B CS6

8 BS O Bust start (BS) (BS) (BS) (BS) (BS)

9 VDDQ Power IO VDD (3.3 V)

10 VSSQ Power IO GND (0 V)

11 D47 I/O Data/port (Port) (Port) (Port) (Port) (Port)

12 D32 I/O Data/port (Port) (Port) (Port) (Port) (Port)

13 VDD Power Internal VDD

14 VSS Power Internal GND

(0 V)

15 D46 I/O Data/port (Port) (Port) (Port) (Port) (Port)

16 D33 I/O Data/port (Port) (Port) (Port) (Port) (Port)

17 D45 I/O Data/port (Port) (Port) (Port) (Port) (Port)

18 D34 I/O Data/port (Port) (Port) (Port) (Port) (Port)

19 D44 I/O Data/port (Port) (Port) (Port) (Port) (Port)

20 D35 I/O Data/port (Port) (Port) (Port) (Port) (Port)

21 VDDQ Power IO VDD (3.3 V)

22 VSSQ Power IO GND (0 V)

23 D43 I/O Data/port (Port) (Port) (Port) (Port) (Port)

24 D36 I/O Data/port (Port) (Port) (Port) (Port) (Port)

25 D42 I/O Data/port (Port) (Port) (Port) (Port) (Port)

26 D37 I/O Data/port (Port) (Port) (Port) (Port) (Port)

27 D41 I/O Data/port (Port) (Port) (Port) (Port) (Port)

28 D38 I/O Data/port (Port) (Port) (Port) (Port) (Port)

29 D40 I/O Data/port (Port) (Port) (Port) (Port) (Port)

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REJ09B0366-0700

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

30 D39 I/O Data/port (Port) (Port) (Port) (Port) (Port)

31 VDDQ Power IO VDD (3.3 V)

32 VSSQ Power IO GND (0 V)

33 D15 I/O Data A15

34 D0 I/O Data A0

35 D14 I/O Data A14

36 D1 I/O Data A1

37 D13 I/O Data A13

38 D2 I/O Data A2

39 VDD Power Internal VDD

(1.8 V)

40 VSS Power Internal GND

(0 V)

41 D12 I/O Data A12

42 D3 I/O Data A3

43 VDDQ Power IO VDD (3.3 V)

44 VSSQ Power IO GND (0 V)

45 D11 I/O Data A11

46 D4 I/O Data A4

47 D10 I/O Data A10

48 D5 I/O Data A5

49 D9 I/O Data A9

50 D6 I/O Data A6

51 BACK/

BSREQ

O Bus

acknowledge/

bus request

52 BREQ/

BSACK

I Bus request/bus

acknowledge

53 D8 I/O Data A8

54 D7 I/O Data A7

55 CKE O Clock output

enable

CKE

56 VDDQ Power IO VDD (3.3 V)

57 VSSQ Power IO GND (0 V)

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 26 of 1074

REJ09B0366-0700

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

58 WE5/CAS5/

DQM5

O D47–D40 select

signal

WE5 CAS5 DQM5

59 WE4/CAS4/

DQM4

O D39–D32 select

signal

WE4 CAS4 DQM4

60 WE1/CAS1/

DQM1

O D15–D8 select

signal

WE1 CAS1 DQM1 WE1

61 WE0/CAS0/

DQM0

O D7–D0 select

signal

WE0 CAS0 DQM0

62 A17 O Address

63 A16 O Address

64 A15 O Address

65 VDD Power Internal VDD

66 VSS Power Internal GND

(0 V)

67 A14 O Address

68 A13 O Address

69 VDDQ Power IO VDD (3.3 V)

70 VSSQ Power IO GND (0 V)

71 A12 O Address

72 A11 O Address

73 A10 O Address

74 A9 O Address

75 A8 O Address

76 A7 O Address

77 CKIO O Clock output CKIO CKIO CKIO

78 VDDQ Power IO VDD (3.3 V)

79 VSSQ Power IO GND (0 V)

80 A6 O Address

81 A5 O Address

82 A4 O Address

83 A3 O Address

84 A2 O Address

85 DRAK1 O DMAC1 request

acknowledge

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 27 of 1074

REJ09B0366-0700

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

86 DRAK0 O DMAC0 request

acknowledge

87 VDDQ Power IO VDD (3.3 V)

88 VSSQ Power IO GND (0 V)

89 CS3 O Chip select 3 CS3 (CS3) CS3 CS3

90 CS2 O Chip select 2 CS2 (CS2) CS2 CS2

91 VDD Power Internal VDD

92 VSS Power Internal GND

(0 V)

93 RAS O RAS RAS RAS

94 RD/CASS/

FRAME

O Read/CAS/

FRAME

OE CAS OE FRAME

95 RD/WR O Read/write RD/WR RD/WR RD/WR RD/WR RD/WR

96 WE2/CAS2/

DQM2/

ICIORD

O D23–D16 select

signal

WE2 CAS2 DQM2 ICIORD

97 WE3/CAS3/

DQM3/

ICIOWR

O D31–D24 select

signal

WE3 CAS3 DQM3 ICIOWR

98 WE6/CAS6/

DQM6

O D55–D48 select

signal

WE6 CAS6 DQM6

99 VDDQ Power IO VDD (3.3 V)

100 VSSQ Power IO GND (0 V)

101 WE7/CAS7/

DQM7/REG

O D63–D56 select

signal

WE7 CAS7 DQM7 REG

102 D23 I/O Data A23

103 D24 I/O Data A24

104 D22 I/O Data A22

105 RXD I SCI Data input

106 DREQ0 I Request from

DMAC0

107 DREQ1 I Request from

DMAC1

108 D25 I/O Data A25

109 D21 I/O Data A21

110 D26 I/O Data

111 D20 I/O Data A20

Section 1 Overview

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REJ09B0366-0700

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

112 D27 I/O Data

113 VDDQ Power IO VDD (3.3 V)

114 VSSQ Power IO GND (0 V)

115 D19 I/O Data A19

116 D28 I/O Data

117 VDD Power Internal VDD

118 VSS Power Internal GND

(0 V)

119 D18 I/O Data A18

120 D29 I/O Data

121 D17 I/O Data A17

122 D30 I/O Data

123 D16 I/O Data A16

124 D31 I/O Data

125 VDDQ Power IO VDD (3.3 V)

126 VSSQ Power IO GND (0 V)

127 D55 I/O Data

128 D56 I/O Data

129 D54 I/O Data

130 D57 I/O Data

131 D53 I/O Data

132 D58 I/O Data

133 D52 I/O Data

134 D59 I/O Data

135 VDDQ Power IO VDD (3.3 V)

136 VSSQ Power IO GND (0 V)

137 D51 I/O Data/port (Port) (Port) (Port) (Port) (Port)

138 D60 I/O Data

139 D50 I/O Data/port (Port) (Port) (Port) (Port) (Port)

140 D61 I/O Data ACCSIZE0

141 D49 I/O Data/port (Port) (Port) (Port) (Port) (Port)

142 D62 I/O Data ACCSIZE1

143 VDD Power Internal VDD

Section 1 Overview

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REJ09B0366-0700

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

144 VSS Power Internal GND

(0 V)

145 D48 I/O Data/port (Port) (Port) (Port) (Port) (Port)

146 D63 I/O Data ACCSIZE2

147 VDDQ Power IO VDD (3.3 V)

148 VSSQ Power IO GND (0 V)

149 MD0/SCK I/O Mode/SCI clock MD0 SCK SCK SCK SCK SCK

150 MD1/TXD2 I/O Mode SCIF data

output

MD1 TXD2 TXD2 TXD2 TXD2 TXD2

151 MD2/RXD2 I Mode/SCIF data

input

MD2 RXD2 RXD2 RXD2 RXD2 RXD2

152 IRL0 I Interrupt 0

153 IRL1 I Interrupt 1

154 IRL2 I Interrupt 2

155 IRL3 I Interrupt 3

156 NMI I Nonmaskable

interrupt

157 XTAL2 O RTC crystal

resonator pin

158 EXTAL2 I RTC crystal

resonator pin

159 VSS-RTC Power RTC GND

(0 V)

160 VDD-RTC Power RTC VDD

(3.3 V)

161 CA I *

162 VSS Power Internal GND

(0 V)

163 VDDQ Power IO VDD (3.3 V)

164 CTS2 I/O SCIF data control

(CTS)

165 TCLK I/O RTC/TMU

clock

166 MD8/RTS2 I/O Mode/SCIF data

control (RTS)

MD8 RTS2 RTS2 RTS2 RTS2 RTS2

167 MD7/TXD I/O Mode/SCI data

output

MD7 TXD TXD TXD TXD TXD

Section 1 Overview

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REJ09B0366-0700

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

168 SCK2/

MRESET

I SCIF clock/

manual reset

MRESET SCK2 SCK2 SCK2 SCK2 SCK2

169 VDD Power Internal VDD

170 VSS Power Internal GND

(0 V)

171 A18 O Address

172 A19 O Address

173 A20 O Address

174 A21 O Address

175 A22 O Address

176 A23 O Address

177 VDDQ Power IO VDD (3.3 V)

178 VSSQ Power IO GND (0 V)

179 A24 O Address

180 A25 O Address

181 MD3/CE2A I/O Mode/

PCMCIA-CE

MD3 CE2A

182 MD4/CE2B I/O Mode/

PCMCIA-CE

MD4 CE2B

183 MD5/RAS2 I/O Mode/RAS

(DRAM)

MD5 RAS2

184 DACK0 O DMAC0 bus

acknowledge

185 DACK1 O DMAC1 bus

acknowledge

186 A0 O Address

187 VDDQ Power IO VDD (3.3 V)

188 VSSQ Power IO GND (0 V)

189 A1 O Address

190 STATUS0 O Status

191 STATUS1 O Status

192 MD6/

IOIS16

I Mode/IOIS16

(PCMCIA)

MD6 IOIS16

193 ASEBRK/

BRKACK

I/O Pin break/

acknowledge

(H-UDI)

Section 1 Overview

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REJ09B0366-0700

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

194 TDO O Data out

(H-UDI)

195 VDD Power Internal VDD

196 VSS Power Internal GND

(0 V)

197 TMS I Mode (H-UDI)

198 TCK I Clock (H-UDI)

199 TDI I Data in (H-UDI)

200 TRST I Reset (H-UDI)

201 VDD-PLL2 Power PLL2 VDD (3.3V)

202 VSS-PLL2 Power PLL2 GND (0V)

203 VDD-PLL1 Power PLL1 VDD (3.3V)

204 VSS-PLL1 Power PLL1 GND (0V)

205 VDD-CPG Power CPG VDD (3.3V)

206 VSS-CPG Power CPG GND (0V)

207 XTAL O Crystal resonator

208 EXTAL I External input

clock/crystal

resonator

Legend:

I: Input

O: Output

I/O: Input/output

Power: Power supply

Notes: Supply power to all power pins. For the SH7750S, supply power to RTC at a minimum in

hardware standby mode.

Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the

on-chip PLL circuits are used.

Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-

chip crystal oscillation circuit is used.

Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-

chip RTC is used.

VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG are connected inside the package.

The RD2, RD/WR2, CKIO2, and CKIO2ENB pins are not provided on the QFP package.

For a QFP package, the maximum operating frequency of the external bus is 84 MHz.

* Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V.

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 32 of 1074

REJ09B0366-0700

1.4.3 Pin Functions (264-Pin CSP)

Table 1.4 Pin Functions

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

1 C2 RDY I Bus ready RDY RDY RDY

2 B1 RESET I Reset RESET

3 D3 CS0 O Chip select 0 CS0 CS0

4 E2 CS1 O Chip select 1 CS1 CS1

5 B2 CS4 O Chip select 4 CS4 CS4

6 E3 CS5 O Chip select 5 CS5 CE1A CS5

7 E4 CS6 O Chip select 6 CS6 CE1B CS6

8 E1 BS O Bus start (BS) (BS) (BS) (BS) (BS)

9 F4 RD2 O RD/CASS/

FRAME

OE CAS OE FRAME

10 F3 VDDQ Power IO VDD (3.3 V)

11 D4 VSSQ Power IO GND (0 V)

12 F2 D47 I/O Data/port (Port) (Port) (Port) (Port) (Port)

13 F5 D32 I/O Data/port (Port) (Port) (Port) (Port) (Port)

14 F1 VDD Power Internal VDD

(1.5 V)

15 G4 VSS Power Internal GND

(0 V)

16 G3 D46 I/O Data/port (Port) (Port) (Port) (Port) (Port)

17 F6 D33 I/O Data/port (Port) (Port) (Port) (Port) (Port)

18 G2 VDDQ Power IO VDD (3.3 V)

19 G5 VSSQ Power IO GND (0 V)

20 G1 D45 I/O Data/port (Port) (Port) (Port) (Port) (Port)

21 G6 D34 I/O Data/port (Port) (Port) (Port) (Port) (Port)

22 H3 D44 I/O Data/port (Port) (Port) (Port) (Port) (Port)

23 H4 D35 I/O Data/port (Port) (Port) (Port) (Port) (Port)

24 H1 VDDQ Power IO VDD (3.3 V)

25 H5 VSSQ Power IO GND (0 V)

26 H2 D43 I/O Data/port (Port) (Port) (Port) (Port) (Port)

27 H6 D36 I/O Data/port (Port) (Port) (Port) (Port) (Port)

28 J3 D42 I/O Data/port (Port) (Port) (Port) (Port) (Port)

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 33 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

29 J5 D37 I/O Data/port (Port) (Port) (Port) (Port) (Port)

30 J1 VDDQ Power IO VDD (3.3 V)

31 J6 VSSQ Power IO GND (0 V)

32 J4 D41 I/O Data/port (Port) (Port) (Port) (Port) (Port)

33 J2 D38 I/O Data/port (Port) (Port) (Port) (Port) (Port)

34 K6 D40 I/O Data/port (Port) (Port) (Port) (Port) (Port)

35 K1 D39 I/O Data/port (Port) (Port) (Port) (Port) (Port)

36 K5 VDDQ Power IO VDD (3.3 V)

37 K3 VSSQ Power IO GND (0 V)

38 K4 D15 I/O Data A15

39 K2 D0 I/O Data A0

40 L6 D14 I/O Data A14

41 L1 D1 I/O Data A1

42 L5 VDDQ Power IO VDD (3.3 V)

43 L3 VSSQ Power IO GND (0 V)

44 M5 D13 I/O Data A13

45 M1 D2 I/O Data A2

46 L4 VDD Power Internal VDD

(1.5 V)

47 L2 VSS Power Internal GND

(0 V)

48 N5 D12 I/O Data A12

49 M3 D3 I/O Data A3

50 M4 VDDQ Power IO VDD (3.3 V)

51 N1 VSSQ Power IO GND (0 V)

52 N4 D11 I/O Data A11

53 M2 D4 I/O Data A4

54 R3 D10 I/O Data A10

55 N3 D5 I/O Data A5

56 P3 VDDQ Power IO VDD (3.3 V)

57 P1 VSSQ Power IO GND (0 V)

58 U1 D9 I/O Data A9

59 R1 D6 I/O Data A6

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 34 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

60 T1 BACK/

BSREQ

O Bus

acknowledge/

bus request

61 R2 BREQ/

BSACK

I Bus request/bus

acknowledge

62 T3 D8 I/O Data A8

63 U2 D7 I/O Data A7

64 R4 CKE O Clock output

enable

CKE

65 T5 VDDQ Power IO VDD (3.3 V)

66 T2 VSSQ Power IO GND (0 V)

67 R5 WE5/CAS5/

DQM5

O D47–D40 select

signal

WE5 CAS5 DQM5

68 P5 WE4/CAS4/

DQM4

O D39–D32 select

signal

WE4 CAS4 DQM4

69 U5 WE1/CAS1/

DQM1

O D15–D8 select

signal

WE1 CAS1 DQM1 WE1

70 P6 WE0/CAS0/

DQM0

O D7–D0 select

signal

WE0 CAS0 DQM0

71 R6 A17 O Address

72 P4 VDDQ Power IO VDD (3.3 V)

73 T6 VSSQ Power IO GND (0 V)

74 N6 A16 O Address

75 U6 A15 O Address

76 P7 VDD Power Internal VDD

(1.5 V)

77 R7 VSS Power Internal GND

(0 V)

78 M6 A14 O Address

79 T7 A13 O Address

80 N7 VDDQ Power IO VDD (3.3 V)

81 U7 VSSQ Power IO GND (0 V)

82 R8 A12 O Address

83 P8 A11 O Address

84 U8 A10 O Address

85 N8 VDDQ Power IO VDD (3.3 V)

Section 1 Overview

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REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

86 T8 VSSQ Power IO GND (0 V)

87 M8 A9 O Address

88 R9 A8 O Address

89 N9 A7 O Address

90 U9 CKIO O Clock output CKIO CKIO CKIO

91 M9 VDDQ Power IO VDD (3.3 V)

92 P9 VSSQ Power IO GND (0 V)

93 T9 CKIO2 O CKIO* CKIO CKIO CKIO

94 M10 A6 O Address

95 U10 A5 O Address

96 N10 A4 O Address

97 R10 VDDQ Power IO VDD (3.3 V)

98 P10 VSSQ Power IO GND (0 V)

99 T10 A3 O Address

100 M11 A2 O Address

101 U11 DRAK1 O DMAC1 request

acknowledge

102 N11 DRAK0 O DMAC0 request

acknowledge

103 R11 VDDQ Power IO VDD (3.3 V)

104 N12 VSSQ Power IO GND (0 V)

105 U12 CS3 O Chip select 3 CS3 (CS3) CS3 CS3

106 P11 CS2 O Chip select 2 CS2 (CS2) CS2 CS2

107 T11 VDD Power Internal VDD

(1.5 V)

108 N13 VSS Power Internal GND

(0 V)

109 R12 RAS O RAS RAS RAS

110 P12 RD/CASS/

FRAME

O Read/CAS/

FRAME

OE CAS OE FRAME

111 U13 VDDQ Power IO VDD (3.3 V)

112 P13 VSSQ Power IO GND (0 V)

113 T12 RD/WR O Read/write RD/WR RD/WR RD/WR RD/WR RD/WR

114 R15 WE2/CAS2/

DQM2/

ICIORD

O D23–D16 select

signal

WE2 CAS2 DQM2 ICIORD

Section 1 Overview

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REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

115 R13 WE3/CAS3/

DQM3/

ICIOWR

O D31–D24 select

signal

WE3 CAS3 DQM3 ICIOWR

116 R14 WE6/CAS6/

DQM6

O D55–D48 select

signal

WE6 CAS6 DQM6

117 U14 VDDQ Power IO VDD (3.3 V)

118 U17 VSSQ Power IO GND (0 V)

119 U15 WE7/CAS7/

DQM7/REG

O D63–D56 select

signal

WE7 CAS7 DQM7 REG

120 U16 D23 I/O Data A23

121 T13 D24 I/O Data A24

122 T15 D22 I/O Data A22

123 R16 RXD I SCI1 data input

124 T17 DREQ0 I Request from

DMAC0

125 P17 DREQ1 I Request from

DMAC1

126 P15 D25 I/O Data A25

127 N16 VDDQ Power IO VDD (3.3 V)

128 T16 VSSQ Power IO GND (0 V)

129 N15 D21 I/O Data A21

130 N14 D26 I/O Data

131 N17 D20 I/O Data A20

132 M14 D27 I/O Data

133 M15 VDDQ Power IO VDD (3.3 V)

134 P14 VSSQ Power IO GND (0 V)

135 M16 D19 I/O Data A19

136 M13 D28 I/O Data

137 M17 VDD Power Internal VDD

(1.5 V)

138 L14 VSS Power Internal GND

(0 V)

139 L15 D18 I/O Data A18

140 M12 D29 I/O Data

141 L16 VDDQ Power IO VDD (3.3 V)

142 L13 VSSQ Power IO GND (0 V)

Section 1 Overview

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REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

143 L17 D17 I/O Data A17

144 L12 D30 I/O Data

145 K15 D16 I/O Data A16

146 K14 D31 I/O Data

147 K17 VDDQ Power IO VDD (3.3 V)

148 K13 VSSQ Power IO GND (0 V)

149 K16 D55 I/O Data

150 K12 D56 I/O Data

151 J15 D54 I/O Data

152 J13 D57 I/O Data

153 J17 VDDQ Power IO VDD (3.3 V)

154 J12 VSSQ Power IO GND (0 V)

155 J14 D53 I/O Data

156 J16 D58 I/O Data

157 H12 D52 I/O Data

158 H17 D59 I/O Data

159 H13 VDDQ Power IO VDD (3.3 V)

160 H15 VSSQ Power IO GND (0 V)

161 H14 D51 I/O Data/port (Port) (Port) (Port) (Port) (Port)

162 H16 D60 I/O Data

163 G12 D50 I/O Data/port (Port) (Port) (Port) (Port) (Port)

164 G17 D61 I/O Data ACCSIZE0

165 G13 VDDQ Power IO VDD (3.3 V)

166 G15 VSSQ Power IO GND (0 V)

167 F13 D49 I/O Data/port (Port) (Port) (Port) (Port) (Port)

168 F17 D62 I/O Data ACCSIZE1

169 G14 VDD Power Internal VDD

(1.5 V)

170 G16 VSS Power Internal GND

(0 V)

171 E13 D48 I/O Data/port (Port) (Port) (Port) (Port) (Port)

172 F15 D63 I/O Data ACCSIZE2

173 F14 VDDQ Power IO VDD (3.3 V)

174 E17 VSSQ Power IO GND (0 V)

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 38 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

175 E14 RD/WR2 O RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR

176 F16 MD0/SCK I/O Mode/SCI1

clock

MD0 SCK SCK SCK SCK SCK

177 C15 MD1/TXD2 I/O Mode/SCIF

data output

MD1 TXD2 TXD2 TXD2 TXD2 TXD2

178 E15 MD2/RXD2 I Mode/SCIF

data input

MD2 RXD2 RXD2 RXD2 RXD2 RXD2

179 D15 IRL0 I Interrupt 0

180 D17 IRL1 I Interrupt 1

181 A17 IRL2 I Interrupt 2

182 B17 IRL3 I Interrupt 3

183 C16 NMI I Nonmaskable

interrupt

184 A15 XTAL2 O RTC crystal

resonator pin

185 A16 EXTAL2 I RTC crystal

resonator pin

186 A14 VSS-RTC Power RTC GND

(0 V)

187 C14 VDD-RTC Power RTC VDD

(3.3 V)

188 B13 CA I Hardware

standby request

189 C13 VDDQ Power IO VDD (3.3 V)

190 D13 CTS2 I/O SCIF data control

(CTS)

191 A13 TCLK I/O RTC/TMU

clock

192 D12 MD8/RTS2 I/O Mode/SCIF data

control (RTS)

MD8 RTS2 RTS2 RTS2 RTS2 RTS2

193 C12 VDDQ Power IO VDD (3.3 V)

194 D14 VSSQ Power IO GND (0 V)

195 B12 MD7/TXD I/O Mode/SCI1 data

output

MD7 TXD TXD TXD TXD TXD

196 E12 SCK2/

MRESET

I SCIF clock/

manual reset

MRESET SCK2 SCK2 SCK2 SCK2 SCK2

197 A12 VDD Power Internal VDD

(1.5 V)

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Rev.7.00 Oct. 10, 2008 Page 39 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

198 D11 VSS Power Internal GND

(0 V)

199 C11 A18 O Address

200 F12 A19 O Address

201 B11 VDDQ Power IO VDD (3.3 V)

202 E11 VSSQ Power IO GND (0 V)

203 A11 A20 O Address

204 F11 A21 O Address

205 C10 A22 O Address

206 D10 A23 O Address

207 A10 VDDQ Power IO VDD (3.3 V)

208 E10 VSSQ Power IO GND (0 V)

209 B10 A24 O Address

210 F10 A25 O Address

211 C9 MD3/CE2A I/O Mode/

PCMCIA-CE

MD3 CE2A

212 E9 MD4/CE2B I/O Mode/

PCMCIA-CE

MD4 CE2B

213 A9 VDDQ Power IO VDD (3.3 V)

214 F9 VSSQ Power IO GND (0 V)

215 D9 MD5/RAS2 I/O Mode/RAS

(DRAM)

MD5 RAS2

216 B9 DACK0 O DMAC0 bus

acknowledge

217 F8 DACK1 O DMAC1 bus

acknowledge

218 A8 A0 O Address

219 E8 VDDQ Power IO VDD (3.3 V)

220 C8 VSSQ Power IO GND (0 V)

221 D8 A1 O Address

222 B8 STATUS0 O Status

223 F7 STATUS1 O Status

224 A7 MD6/

IOIS16

I Mode/IOIS16

(PCMCIA)

MD6 IOIS16

225 E7 VDDQ Power IO VDD (3.3 V)

226 C7 VSSQ Power IO GND (0 V)

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 40 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

227 E6 ASEBRK/

BRKACK

I/O Pin break/

acknowledge

(H-UDI)

228 A6 TDO O Data out

(H-UDI)

229 D7 VDD Power Internal VDD

(1.5 V)

230 B7 VSS Power Internal GND

(0 V)

231 E5 TMS I Mode (H-UDI)

232 C6 TCK I Clock (H-UDI)

233 D6 TDI I Data in (H-UDI)

234 A5 TRST I Reset (H-UDI)

235 D5 CKIO2ENB I CKIO2, RD2,

RD/WR2 enable

236 B6 VDD-PLL2 Power PLL2 VDD (3.3V)

237 C3 VSS-PLL2 Power PLL2 GND (0V)

238 C5 VDD-PLL1 Power PLL1 VDD (3.3V)

239 C4 VSS-PLL1 Power PLL1 GND (0V)

240 A4 VDD-CPG Power CPG VDD (3.3V)

241 A1 VSS-CPG Power CPG GND (0V)

242 A2 XTAL O Crystal resonator

243 A3 EXTAL I External clock/

crystal resonator

244 B3 NC-1

245 B4 NC-2

246 B5 NC-3

247 B14 NC-4

248 B15 NC-5

249 B16 NC-6

250 C1 NC-7

251 C17 NC-8

252 D1 NC-9

253 D2 NC-10

254 D16 NC-11

255 E16 NC-12

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 41 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

256 M7 NC-13

257 N2 NC-14

258 P2 NC-15

259 P16 NC-16

260 R17 NC-17

261 T4 NC-18

262 T14 NC-19

263 U3 NC-20

264 U4 NC-21

Legend:

I: Input

O: Output

I/O: Input/output

Power: Power supply

Notes: Supply power to all power pins. For the SH7750S, supply power to RTC at a minimum in

hardware standby mode.

Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the

on-chip PLL circuits are used.

Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-

chip crystal oscillation circuit is used.

Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-

chip RTC is used.

NC pins must be left completely open, and not connected to a power supply, GND, etc.

* CKIO2 is not connected to PLL2.

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 42 of 1074

REJ09B0366-0700

1.4.4 Pin Functions (292-Pin BGA)

Table 1.5 Pin Functions

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

1 B2 RDY I Bus ready RDY RDY RDY

2 B1 RESET I Reset RESET

3 C2 CS0 O Chip select 0 CS0 CS0

4 C1 CS1 O Chip select 1 CS1 CS1

5 D3 CS4 O Chip select 4 CS4 CS4

6 D2 CS5 O Chip select 5 CS5 CE1A CS5

7 D1 CS6 O Chip select 6 CS6 CE1B CS6

8 E3 BS O Bus start (BS) (BS) (BS) (BS) (BS)

9 E4 VSS Power GND (0 V)

10 E2 RD2 O RD/CASS/

FRAME

OE CAS OE FRAME

11 F3 VDDQ Power IO VDD (3.3 V)

12 F4 VSS Power GND (0 V)

13 E1 D47 I/O Data/port (Port) (Port) (Port) (Port) (Port)

14 F2 D32 I/O Data/port (Port) (Port) (Port) (Port) (Port)

15 G3 VDD Power Internal VDD

16 G4 VSS Power GND (0 V)

17 F1 D46 I/O Data/port (Port) (Port) (Port) (Port) (Port)

18 G2 D33 I/O Data/port (Port) (Port) (Port) (Port) (Port)

19 H3 VDDQ Power IO VDD (3.3 V)

20 H4 VSS Power GND (0 V)

21 G1 D45 I/O Data/port (Port) (Port) (Port) (Port) (Port)

22 H2 D34 I/O Data/port (Port) (Port) (Port) (Port) (Port)

23 H1 D44 I/O Data/port (Port) (Port) (Port) (Port) (Port)

24 J2 D35 I/O Data/port (Port) (Port) (Port) (Port) (Port)

25 J3 VDDQ Power IO VDD (3.3 V)

26 J4 VSS Power GND (0 V)

27 J1 D43 I/O Data/port (Port) (Port) (Port) (Port) (Port)

28 K2 D36 I/O Data/port (Port) (Port) (Port) (Port) (Port)

29 K1 D42 I/O Data/port (Port) (Port) (Port) (Port) (Port)

Section 1 Overview

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REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

30 L3 D37 I/O Data/port (Port) (Port) (Port) (Port) (Port)

31 K3 VDDQ Power IO VDD (3.3 V)

32 K4 VSS Power GND (0 V)

33 L2 D41 I/O Data/port (Port) (Port) (Port) (Port) (Port)

34 L1 D38 I/O Data/port (Port) (Port) (Port) (Port) (Port)

35 M2 D40 I/O Data/port (Port) (Port) (Port) (Port) (Port)

36 M1 D39 I/O Data/port (Port) (Port) (Port) (Port) (Port)

37 M3 VDDQ Power IO VDD (3.3 V)

38 L4 VSS Power GND (0 V)

39 N2 D15 I/O Data A15

40 N1 D0 I/O Data A0

41 P2 D14 I/O Data A14

42 P1 D1 I/O Data A1

43 N3 VDDQ Power IO VDD (3.3 V)

44 M4 VSS Power GND (0 V)

45 R2 D13 I/O Data A13

46 R1 D2 I/O Data A2

47 P3 VDD Power Internal VDD

48 P4 VSS Power GND (0 V)

49 T2 D12 I/O Data A12

50 T1 D3 I/O Data A3

51 R3 VDDQ Power IO VDD (3.3 V)

52 R4 VSS Power GND (0 V)

53 U3 D11 I/O Data A11

54 U2 D4 I/O Data A4

55 U1 D10 I/O Data A10

56 V2 D5 I/O Data A5

57 T3 VDDQ Power IO VDD (3.3 V)

58 T4 VSS Power GND (0 V)

59 V1 D9 I/O Data A9

60 W2 D6 I/O Data A6

61 W1 BACK/

BSREQ

O Bus

acknowledge/

bus request

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 44 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

62 Y1 BREQ/

BSACK

I Bus request/

bus acknowledge

63 Y2 D8 I/O Data A8

64 V3 D7 I/O Data A7

65 W3 CKE O Clock output

enable

CKE

66 V5 VDDQ Power IO VDD (3.3 V)

67 U5 VSS Power GND (0 V)

68 Y3 WE5/CAS5/

DQM5

O D47–D40 select

signal

WE5 CAS5 DQM5

69 V4 WE4/CAS4/

DQM4

O D39–D32 select

signal

WE4 CAS4 DQM4

70 W4 WE1/CAS1/

DQM1

O D15–D8 select

signal

WE1 CAS1 DQM1 WE1

71 Y4 WE0/CAS0/

DQM0

O D7–D0 select

signal

WE0 CAS0 DQM0

72 W5 A17 O Address

73 V6 VDDQ Power IO VDD (3.3 V)

74 U6 VSS Power GND (0 V)

75 Y5 A16 O Address

76 W6 A15 O Address

77 V7 VDD Power Internal VDD

78 U7 VSS Power GND (0 V)

79 Y6 A14 O Address

80 W7 A13 O Address

81 V8 VDDQ Power IO VDD (3.3 V)

82 U8 VSS Power GND (0 V)

83 U4 VSS Power GND (0 V)

84 Y7 A12 O Address

85 W8 A11 O Address

86 Y8 A10 O Address

87 V9 VDDQ Power IO VDD (3.3 V)

88 U9 VSS Power GND (0 V)

89 W9 A9 O Address

90 Y9 A8 O Address

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 45 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

91 W10 A7 O Address

92 Y10 CKIO O Clock output CKIO CKIO CKIO

93 V10 VDDQ Power IO VDD (3.3 V)

94 U10 VSS Power GND (0 V)

95 V11 CKIO2 O CKIO* CKIO CKIO CKIO

96 W11 A6 O Address

97 Y11 A5 O Address

98 W12 A4 O Address

99 V12 VDDQ Power IO VDD (3.3 V)

100 U12 VSS Power GND (0 V)

101 Y12 A3 O Address

102 W13 A2 O Address

103 Y13 DRAK1

O DMAC1 request

acknowledge

104 W14 DRAK0

O DMAC0 request

acknowledge

105 V13 VDDQ Power IO VDD (3.3 V)

106 U13 VSS Power GND (0 V)

107 Y14 CS3 O Chip select 3 CS3 (CS3) CS3 CS3

108 W15 CS2 O Chip select 2 CS2 (CS2) CS2 CS2

109 V14 VDD Power Internal VDD

110 U14 VSS Power GND (0 V)

111 Y15 RAS O RAS RAS RAS

112 W16 RD/CASS/

FRAME

O Read/CAS/

FRAME

OE CAS OE FRAME

113 V15 VDDQ Power IO VDD (3.3 V)

114 U15 VSS Power GND (0 V)

115 Y16 RD/WR O Read/write RD/WR RD/WR RD/WR RD/WR RD/WR

116 V17 WE2/CAS2/

DQM2/

ICIORD

O D23–D16 select

signal

WE2 CAS2 DQM2 ICIORD

117 W17 WE3/CAS3/

DQM3/

ICIOWR

O D31–D24 select

signal

WE3 CAS3 DQM3 ICIOWR

118 Y17 WE6/CAS6/

DQM6

O D55–D48 select

signal

WE6 CAS6 DQM6

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 46 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

119 V16 VDDQ Power IO VDD (3.3 V)

120 U16 VSS Power GND (0 V)

121 V18 WE7/CAS7/

DQM7/REG

O D63–D56 select

signal

WE7 CAS7 DQM7 REG

122 W18 D23 I/O Data A23

123 Y18 D24 I/O Data A24

124 Y19 D22 I/O Data A22

125 Y20 RXD I SCI data input

126 W19 DREQ0 I Request from

DMAC0

127 W20 DREQ1 I Request from

DMAC1

128 V19 D25 I/O Data A25

129 T18 VDDQ Power IO VDD (3.3 V)

130 T17 VSS Power GND (0 V)

131 V20 D21 I/O Data A21

132 U18 D26 I/O Data

133 U19 D20 I/O Data A20

134 U20 D27 I/O Data

135 R18 VDDQ Power IO VDD (3.3 V)

136 R17 VSS Power GND (0 V)

137 T19 D19 I/O Data A19

138 T20 D28 I/O Data

139 P18 VDD Power Internal VDD

140 P17 VSS Power GND (0 V)

141 R19 D18 I/O Data A18

142 R20 D29 I/O Data

143 N18 VDDQ Power IO VDD (3.3 V)

144 N17 VSS Power GND (0 V)

145 P19 D17 I/O Data A17

146 P20 D30 I/O Data

147 N19 D16 I/O Data A16

148 N20 D31 I/O Data

149 M18 VDDQ Power IO VDD (3.3 V)

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 47 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

150 M17 VSS Power GND (0 V)

151 M19 D55 I/O Data

152 M20 D56 I/O Data

153 L19 D54 I/O Data

154 L20 D57 I/O Data

155 L18 VDDQ Power IO VDD (3.3 V)

156 L17 VSS Power GND (0 V)

157 K18 D53 I/O Data

158 K19 D58 I/O Data

159 K20 D52 I/O Data

160 J19 D59 I/O Data

161 J18 VDDQ Power IO VDD (3.3 V)

162 K17 VSS Power GND (0 V)

163 J20 D51 I/O Data/port (Port) (Port) (Port) (Port) (Port)

164 H19 D60 I/O Data

165 H20 D50 I/O Data/port (Port) (Port) (Port) (Port) (Port)

166 G19 D61 I/O Data ACCSIZE0

167 H18 VDDQ Power IO VDD (3.3 V)

168 J17 VSS Power GND (0 V)

169 G20 D49 I/O Data/port (Port) (Port) (Port) (Port) (Port)

170 F19 D62 I/O Data ACCSIZE1

171 G18 VDD Power Internal VDD

172 G17 VSS Power GND (0 V)

173 F20 D48 I/O Data/port (Port) (Port) (Port) (Port) (Port)

174 E18 D63 I/O Data ACCSIZE2

175 F18 VDDQ Power IO VDD (3.3 V)

176 F17 VSS Power GND (0 V)

177 E17 VSS Power GND (0 V)

178 E19 RD/WR2 O RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR

179 E20 MD0/SCK I/O Mode/SCI Clock MD0 SCK SCK SCK SCK SCK

180 D18 MD1/TXD2 I/O Mode/SCIF data

output

MD1 TXD2 TXD2 TXD2 TXD2 TXD2

181 D19 MD2/RXD2 I Mode/SCIF data

input

MD2 RXD2 RXD2 RXD2 RXD2 RXD2

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 48 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

182 D20 IRL0 I Interrupt 0

183 C19 IRL1 I Interrupt 1

184 C20 IRL2 I Interrupt 2

185 B19 IRL3 I Interrupt 3

186 B20 NMI I Nonmaskable

interrupt

187 A20 XTAL2 O RTC crystal

resonator pin

188 A19 EXTAL2 I RTC crystal

resonator pin

189 B18 VSS-RTC Power RTC GND (0 V)

190 A18 VDD-RTC Power RTC VDD (3.3 V)

191 D17 CA I Hardware

standby

192 C17 VDDQ Power IO VDD (3.3 V)

193 C18 VSS-RTC Power RTC GND (0 V)

194 B17 CTS2 I/O SCIF data control

(CTS)

195 A17 TCLK I/O RTC/TMU clock

196 C16 MD8/RTS2 I/O Mode/SCIF data

control (RTS)

MD8 RTS2 RTS2 RTS2 RTS2 RTS2

197 C15 VDDQ Power IO VDD (3.3 V)

198 D15 VSS Power GND (0 V)

199 B16 MD7/TXD I/O Mode/SCI1 data

output

MD7 TXD TXD TXD TXD TXD

200 A16 SCK2/

MRESET

I SCIF clock/

manual reset

MRESET SCK2 SCK2 SCK2 SCK2 SCK2

201 C14 VDD Power Internal VDD

202 D14 VSS Power GND (0 V)

203 B15 A18 O Address

204 A15 A19 O Address

205 C13 VDDQ Power IO VDD (3.3 V)

206 D13 VSS Power GND (0 V)

207 B14 A20 O Address

208 A14 A21 O Address

209 B13 A22 O Address

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 49 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

210 A13 A23 O Address

211 C12 VDDQ Power IO VDD (3.3 V)

212 D12 VSS Power GND (0 V)

213 B12 A24 O Address

214 A12 A25 O Address

215 B11 MD3/CE2A I/O Mode/

PCMCIA-CE

MD3 CE2A

216 A11 MD4/CE2B I/O Mode/

PCMCIA-CE

MD4 CE2B

217 C11 VDDQ Power IO VDD (3.3 V)

218 D11 VSS Power GND (0 V)

219 C10 MD5/RAS2 I/O Mode/RAS

(DRAM)

MD5 RAS2

220 B10 DACK0 O DMAC0 bus

acknowledge

221 A10 DACK1 O DMAC1

acknowledge

222 B9 A0 O Address

223 C8 VDDQ Power IO VDD (3.3 V)

224 D8 VSS Power GND (0 V)

225 A9 A1 O Address

226 B8 STATUS0 O Status

227 A8 STATUS1 O Status

228 B7 MD6/IOIS16 I Mode/IOIS16

(PCMCIA)

MD6 IOIS16

229 C9 VDDQ Power IO VDD (3.3 V)

230 D9 VSS Power GND (0 V)

231 A7 ASEBRK/

BRKACK

I/O Pin break/

acknowledge

(H-UDI)

232 C6 TDO O Data out (H-UDI)

233 C7 VDD Power Internal VDD

234 D7 VSS Power GND (0 V)

235 B6 TMS I Mode (H-UDI)

236 A6 TCK I Clock (H-UDI)

237 C5 TDI I Data in (H-UDI)

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 50 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

238 B5 TRST I Reset (H-UDI)

239 C4 CKIO2ENB I CKIO2, RD2,

RD/WR2 enable

240 D6 VSS Power GND (0 V)

241 A5 VDD-PLL2 Power PLL2 VDD

(3.3 V)

242 B4 VSS-PLL2 Power PLL2 GND (0 V)

243 A4 VDD-PLL1 Power PLL1 VDD

(3.3 V)

244 C3 VSS-PLL1 Power PLL1 GND (0 V)

245 B3 VDD-CPG Power CPG VDD (3.3 V)

246 A3 VSS-CPG Power CPG GND (0 V)

247 A2 XTAL O Crystal resonator

248 A1 EXTAL I External clock/

crystal resonator

249 N4 VSS Power GND (0 V)

250 U11 VSS Power GND (0 V)

251 U17 VSS Power GND (0 V)

252 H17 VSS Power GND (0 V)

253 D16 VSS Power GND (0 V)

254 D10 VSS Power GND (0 V)

255 D5 VSS Power GND (0 V)

256 D4 VSS Power GND (0 V)

257 H8 VSS Power GND (0 V)

258 J8 VSS Power GND (0 V)

259 K8 VSS Power GND (0 V)

260 L8 VSS Power GND (0 V)

261 M8 VSS Power GND (0 V)

262 N8 VSS Power GND (0 V)

263 N9 VSS Power GND (0 V)

264 N10 VSS Power GND (0 V)

265 N11 VSS Power GND (0 V)

266 N12 VSS Power GND (0 V)

267 N13 VSS Power GND (0 V)

268 M13 VSS Power GND (0 V)

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 51 of 1074

REJ09B0366-0700

Memory Interface

No.

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

269 L13 VSS Power GND (0 V)

270 K13 VSS Power GND (0 V)

271 J13 VSS Power GND (0 V)

272 H13 VSS Power GND (0 V)

273 H12 VSS Power GND (0 V)

274 H11 VSS Power GND (0 V)

275 H10 VSS Power GND (0 V)

276 H9 VSS Power GND (0 V)

277 J9 VSS Power GND (0 V)

278 K9 VSS Power GND (0 V)

279 L9 VSS Power GND (0 V)

280 M9 VSS Power GND (0 V)

281 M10 VSS Power GND (0 V)

282 M11 VSS Power GND (0 V)

283 M12 VSS Power GND (0 V)

284 L12 VSS Power GND (0 V)

285 K12 VSS Power GND (0 V)

286 J12 VSS Power GND (0 V)

287 J11 VSS Power GND (0 V)

288 J10 VSS Power GND (0 V)

289 K10 VSS Power GND (0 V)

290 L10 VSS Power GND (0 V)

291 L11 VSS Power GND (0 V)

292 K11 VSS Power GND (0 V)

Legend:

I: Input

O: Output

I/O: Input/output

Power: Power supply

Notes: Supply power to all power pins.

Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the

on-chip PLL circuits are used.

Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-

chip crystal oscillation circuit is used.

Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 52 of 1074

REJ09B0366-0700

Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-

chip RTC is used.

NC pins must be left completely open, and not connected to a power supply, GND, etc.

* CKIO2 is not connected to PLL2.

Section 2 Programming Model

Rev.7.00 Oct. 10, 2008 Page 53 of 1074

REJ09B0366-0700

Section 2 Programming Model

2.1 Data Formats

The data formats handled by the SH-4 are shown in figure 2.1.

Byte (8 bits)

Word (16 bits)

Longword (32 bits)

Single-precision floating-point (32 bits)

Double-precision floating-point (64 bits)

015

31 30 22

fractionexp

63 62 51

exps fraction

Figure 2.1 Data Formats

Section 2 Programming Model

Rev.7.00 Oct. 10, 2008 Page 54 of 1074

REJ09B0366-0700

2.2 Register Configuration

2.2.1 Privileged Mode and Banks

Processor Modes: The SH-4 has two processor modes, user mode and privileged mode. The SH-4

normally operates in user mode, and switches to privileged mode when an exception occurs or an

interrupt is accepted. There are four kinds of registers—general registers, system registers, control

registers, and floating-point registers—and the registers that can be accessed differ in the two

processor modes.

General Registers: There are 16 general registers, designated R0 to R15. General registers R0 to

R7 are banked registers which are switched by a processor mode change.

In privileged mode, the register bank bit (RB) in the status register (SR) defines which banked

When the RB bit is 1 (that is, when bank 1 is selected), the 16 registers comprising bank 1 general

registers R0_BANK1 to R7_BANK1 and non-banked general registers R8 to R15 can be accessed

as general registers R0 to R15. In this case, the eight registers comprising bank 0 general registers

R0_BANK0 to R7_BANK0 are accessed by the LDC/STC instructions. When the RB bit is 0 (that

is, when bank 0 is selected), the 16 registers comprising bank 0 general registers R0_BANK0 to

R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0

to R15. In this case, the eight registers comprising bank 1 general registers R0_BANK1 to

R7_BANK1 are accessed by the LDC/STC instructions.

In user mode, the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and

non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. The eight

registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 cannot be accessed.

Control Registers: Control registers comprise the global base register (GBR) and status register

(SR), which can be accessed in both processor modes, and the saved status register (SSR), saved

program counter (SPC), vector base register (VBR), saved general register 15 (SGR), and debug

base register (DBR), which can only be accessed in privileged mode. Some bits of the status

System Registers: System registers comprise the multiply-and-accumulate registers

(MACH/MACL), the procedure register (PR), the program counter (PC), the floating-point

status/control register (FPSCR), and the floating-point communication register (FPUL). Access to

these registers does not depend on the processor mode.

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Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0–

XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0–

FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1).

FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating-

point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0–

XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix

XMTRX.

Table 2.1 Initial Register Values

Type Registers Initial Value*

General registers R0_BANK0–R7_BANK0,

R0_BANK1–R7_BANK1,

R8–R15

Undefined

SR MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0,

IMASK = 1111 (H'F), reserved bits = 0, others

undefined

GBR, SSR, SPC, SGR,

DBR

Undefined

Control registers

VBR H'00000000

MACH, MACL, PR, FPUL Undefined

PC H'A0000000

System registers

FPSCR H'00040001

Floating-point

registers

FR0–FR15, XF0–XF15 Undefined

Note: * Initialized by a power-on reset and manual reset.

The register configuration in each processor is shown in figure 2.2.

Switching between user mode and privileged mode is controlled by the processor mode bit (MD)

in the status register.

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31 0

R0_BANK0*1 *2

R1_BANK0*2

R2_BANK0*2

R3_BANK0*2

R4_BANK0*2

R5_BANK0*2

R6_BANK0*2

R7_BANK0*2

R10

R11

R12

R13

R14

R15

GBR

MACH

MACL

(a) Register configuration

in user mode

31 0

R0_BANK1*1 *3

R1_BANK1*3

R2_BANK1*3

R3_BANK1*3

R4_BANK1*3

R5_BANK1*3

R6_BANK1*3

R7_BANK1*3

R10

R11

R12

R13

R14

R15

R0_BANK0*1 *4

R1_BANK0*4

R2_BANK0*4

R3_BANK0*4

R4_BANK0*4

R5_BANK0*4

R6_BANK0*4

R7_BANK0*4

(b) Register configuration in

privileged mode (RB = 1)

GBR

MACH

MACL

VBR

SSR

SPC

31 0

R0_BANK1*1 *3

R1_BANK1*3

R2_BANK1*3

R3_BANK1*3

R4_BANK1*3

R5_BANK1*3

R6_BANK1*3

R7_BANK1*3

R10

R11

R12

R13

R14

R15

R0_BANK0*1 *4

R1_BANK0*4

R2_BANK0*4

R3_BANK0*4

R4_BANK0*4

R5_BANK0*4

R6_BANK0*4

R7_BANK0*4

privileged mode (RB = 0)

GBR

MACH

MACL

VBR

SSR

SPC

SGR

DBR

SGR

DBR

Notes: 1. The R0 register is used as the index register in indexed register-indirect addressing mode and

indexed GBR indirect addressing mode.

2. Banked registers

3. Banked registers

Accessed as general registers when the RB bit is set to 1 in the SR register. Accessed only by

LDC/STC instructions when the RB bit is cleared to 0.

4. Banked registers

Accessed as general registers when the RB bit is cleared to 0 in the SR register. Accessed only by

LDC/STC instructions when the RB bit is set to 1.

Figure 2.2 CPU Register Configuration in Each Processor Mode

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2.2.2 General Registers

Figure 2.3 shows the relationship between the processor modes and general registers. The SH-4

has twenty-four 32-bit general registers (R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1,

and R8–R15). However, only 16 of these can be accessed as general registers R0–R15 in one

processor mode. The SH-4 has two processor modes, user mode and privileged mode, in which

R0–R7 are assigned as shown below.

• R0_BANK0–R7_BANK0

In user mode (SR.MD = 0), R0–R7 are always assigned to R0_BANK0–R7_BANK0.

In privileged mode (SR.MD = 1), R0–R7 are assigned to R0_BANK0–R7_BANK0 only when

SR.RB = 0.

• R0_BANK1–R7_BANK1

In user mode, R0_BANK1–R7_BANK1 cannot be accessed.

In privileged mode, R0–R7 are assigned to R0_BANK1–R7_BANK1 only when SR.RB = 1.

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SR.MD = 0 or

(SR.MD = 1, SR.RB = 0)

R0_BANK0

R1_BANK0

R2_BANK0

R3_BANK0

R4_BANK0

R5_BANK0

R6_BANK0

R7_BANK0

R0_BANK0

R1_BANK0

R2_BANK0

R3_BANK0

R4_BANK0

R5_BANK0

R6_BANK0

R7_BANK0

R0_BANK1

R1_BANK1

R2_BANK1

R3_BANK1

R4_BANK1

R5_BANK1

R6_BANK1

R7_BANK1

R0_BANK1

R1_BANK1

R2_BANK1

R3_BANK1

R4_BANK1

R5_BANK1

R6_BANK1

R7_BANK1

R10

R11

R12

R13

R14

R15

R10

R11

R12

R13

R14

R15

R10

R11

R12

R13

R14

R15

(SR.MD = 1, SR.RB = 1)

Figure 2.3 General Registers

Programming Note: As the user's R0–R7 are assigned to R0_BANK0–R7_BANK0, and after an

exception or interrupt R0–R7 are assigned to R0_BANK1–R7_BANK1, it is not necessary for the

interrupt handler to save and restore the user's R0–R7 (R0_BANK0–R7_BANK0).

After a reset, the values of R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, and R8–R15 are

undefined.

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2.2.3 Floating-Point Registers

Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers,

divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1).

These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15,

XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference

name is determined by the FR bit in FPSCR (see figure 2.4).

• Floating-point registers, FPRn_BANKi (32 registers)

FPR0_BANK0, FPR1_BANK0, FPR2_BANK0, FPR3_BANK0, FPR4_BANK0,

FPR5_BANK0, FPR6_BANK0, FPR7_BANK0, FPR8_BANK0, FPR9_BANK0,

FPR10_BANK0, FPR11_BANK0, FPR12_BANK0, FPR13_BANK0, FPR14_BANK0,

FPR15_BANK0

FPR0_BANK1, FPR1_BANK1, FPR2_BANK1, FPR3_BANK1, FPR4_BANK1,

FPR5_BANK1, FPR6_BANK1, FPR7_BANK1, FPR8_BANK1, FPR9_BANK1,

FPR10_BANK1, FPR11_BANK1, FPR12_BANK1, FPR13_BANK1, FPR14_BANK1,

FPR15_BANK1

• Single-precision floating-point registers, FRi (16 registers)

When FPSCR.FR = 0, FR0–FR15 are assigned to FPR0_BANK0–FPR15_BANK0.

When FPSCR.FR = 1, FR0–FR15 are assigned to FPR0_BANK1–FPR15_BANK1.

• Double-precision floating-point registers or single-precision floating-point register pairs, DRi

(8 registers): A DR register comprises two FR registers.

DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7},

DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15}

• Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises

four FR registers

FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7},

FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15}

• Single-precision floating-point extended registers, XFi (16 registers)

When FPSCR.FR = 0, XF0–XF15 are assigned to FPR0_BANK1–FPR15_BANK1.

When FPSCR.FR = 1, XF0–XF15 are assigned to FPR0_BANK0–FPR15_BANK0.

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• Single-precision floating-point extended register pairs, XDi (8 registers): An XD register

comprises two XF registers

XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7},

XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15}

• Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16

XF registers

XMTRX = XF0 XF4 XF8 XF12

XF1 XF5 XF9 XF13

XF2 XF6 XF10 XF14

XF3 XF7 XF11 XF15

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FPR0_BANK0

FPR1_BANK0

FPR2_BANK0

FPR3_BANK0

FPR4_BANK0

FPR5_BANK0

FPR6_BANK0

FPR7_BANK0

FPR8_BANK0

FPR9_BANK0

FPR10_BANK0

FPR11_BANK0

FPR12_BANK0

FPR13_BANK0

FPR14_BANK0

FPR15_BANK0

XF0

XF1

XF2

XF3

XF4

XF5

XF6

XF7

XF8

XF9

XF10

XF11

XF12

XF13

XF14

XF15

FR0

FR1

FR2

FR3

FR4

FR5

FR6

FR7

FR8

FR9

FR10

FR11

FR12

FR13

FR14

FR15

DR0

DR2

DR4

DR6

DR8

DR10

DR12

DR14

FV0

FV4

FV8

FV12

XD0 XMTRX

XD2

XD4

XD6

XD8

XD10

XD12

XD14

FPR0_BANK1

FPR1_BANK1

FPR2_BANK1

FPR3_BANK1

FPR4_BANK1

FPR5_BANK1

FPR6_BANK1

FPR7_BANK1

FPR8_BANK1

FPR9_BANK1

FPR10_BANK1

FPR11_BANK1

FPR12_BANK1

FPR13_BANK1

FPR14_BANK1

FPR15_BANK1

XF0

XF1

XF2

XF3

XF4

XF5

XF6

XF7

XF8

XF9

XF10

XF11

XF12

XF13

XF14

XF15

FR0

FR1

FR2

FR3

FR4

FR5

FR6

FR7

FR8

FR9

FR10

FR11

FR12

FR13

FR14

FR15

DR0

DR2

DR4

DR6

DR8

DR10

DR12

DR14

FV0

FV4

FV8

FV12

XD0XMTRX

XD2

XD4

XD6

XD8

XD10

XD12

XD14

FPSCR.FR = 0 FPSCR.FR = 1

Figure 2.4 Floating-Point Registers

Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and

FPR0_BANK1–FPR15_BANK1 are undefined.

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2.2.4 Control Registers

Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000

00XX 1111 00XX (X: undefined))

31 30 29 28 27 16 15 14 10 9 8 7 4 3 2 1 0

— MD RB BL — FD — M Q IMASK — S T

Note: —: Reserved. These bits are always read as 0, and should only be written with 0.

• MD: Processor mode

MD = 0: User mode (some instructions cannot be executed, and some resources cannot be

accessed)

MD = 1: Privileged mode

• RB: General register bank specifier in privileged mode (set to 1 by a reset, exception, or

interrupt)

RB = 0: R0_BANK0–R7_BANK0 are accessed as general registers R0–R7. (R0_BANK1–

R7_BANK1 can be accessed using LDC/STC R0_BANK–R7_BANK instructions.)

RB = 1: R0_BANK1–R7_BANK1 are accessed as general registers R0–R7. (R0_BANK0–

R7_BANK0 can be accessed using LDC/STC R0_BANK–R7_BANK instructions.)

• BL: Exception/interrupt block bit (set to 1 by a reset, exception, or interrupt)

BL = 1: Interrupt requests are masked. If a general exception other than a user break occurs

while BL = 1, the processor switches to the reset state.

• FD: FPU disable bit (cleared to 0 by a reset)

FD = 1: An FPU instruction causes a general FPU disable exception, and if the FPU instruction

is in a delay slot, a slot FPU disable exception is generated. (FPU instructions: H'F***

instructions, LDC(.L)/STS(.L) instructions for FPUL/FPSCR)

• M, Q: Used by the DIV0S, DIV0U, and DIV1 instructions.

• IMASK: Interrupt mask level

External interrupts of a same level or a lower level than IMASK are masked.

• S: Specifies a saturation operation for a MAC instruction.

• T: True/false condition or carry/borrow bit

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Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current

contents of SR are saved to SSR in the event of an exception or interrupt.

Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The

address of an instruction at which an interrupt or exception occurs is saved to SPC.

Global base register, GBR (32 bits, initial value undefined): GBR is referenced as the base

address in a GBR-referencing MOV instruction.

Vector base register, VBR (32 bits, privilege protection, initial value = H'0000 0000): VBR is

referenced as the branch destination base address in the event of an exception or interrupt. For

details, see section 5, Exceptions.

Saved general register 15, SGR (32 bits, privilege protection, initial value undefined): The

contents of R15 are saved to SGR in the event of an exception or interrupt.

Debug base register, DBR (32 bits, privilege protection, initial value undefined): When the

user break debug function is enabled (BRCR.UBDE = 1), DBR is referenced as the user break

handler branch destination address instead of VBR.

2.2.5 System Registers

Multiply-and-accumulate register high, MACH (32 bits, initial value undefined)

Multiply-and-accumulate register low, MACL (32 bits, initial value undefined)

MACH/MACL is used for the added value in a MAC instruction, and to store a MAC instruction

or MUL operation result.

Procedure register, PR (32 bits, initial value undefined): The return address is stored in PR in a

subroutine call using a BSR, BSRF, or JSR instruction, and PR is referenced by the subroutine

return instruction (RTS).

Program counter, PC (32 bits, initial value = H'A000 0000): PC indicates the instruction fetch

address.

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Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001)

31 22 21 20 19 18 17 12 11 7 6 2 1 0

— FR SZ PR DN Cause Enable Flag RM

Note: —: Reserved. These bits are always read as 0, and should only be written with 0.

• FR: Floating-point register bank

FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15; FPR0_BANK1–

FPR15_BANK1 are assigned to XF0–XF15.

FR = 1: FPR0_BANK0–FPR15_BANK0 are assigned to XF0–XF15; FPR0_BANK1–

FPR15_BANK1 are assigned to FR0–FR15.

• SZ: Transfer size mode

SZ = 0: The data size of the FMOV instruction is 32 bits.

SZ = 1: The data size of the FMOV instruction is a 32-bit register pair (64 bits).

• PR: Precision mode

PR = 0: Floating-point instructions are executed as single-precision operations.

PR = 1: Floating-point instructions are executed as double-precision operations (the result of

instructions for which double-precision is not supported is undefined).

Do not set SZ and PR to 1 simultaneously; this setting is reserved.

[SZ, PR = 11]: Reserved (FPU operation instruction is undefined.)

• DN: Denormalization mode

DN = 0: A denormalized number is treated as such.

DN = 1: A denormalized number is treated as zero.

• Cause: FPU exception cause field

• Enable: FPU exception enable field

• Flag: FPU exception flag field

FPU

Error (E)

Invalid

Operation (V)

Division

by Zero (Z)

Overflow

(O)

Underflow

(U)

Inexact

(I)

Cause FPU exception

cause field

Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12

Enable FPU exception

enable field

None Bit 11 Bit 10 Bit 9 Bit 8 Bit 7

Flag FPU exception

flag field

None Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

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When an FPU operation instruction is executed, the FPU exception cause field is cleared to

zero first. When the next FPU exception is occured, the corresponding bits in the FPU

exception cause field and FPU exception flag field are set to 1. The FPU exception flag field

holds the status of the exception generated after the field was last cleared.

• RM: Rounding mode

RM = 00: Round to Nearest

RM = 01: Round to Zero

RM = 10: Reserved

RM = 11: Reserved

• Bits 22 to 31: Reserved

Floating-point communication register, FPUL (32 bits, initial value undefined): Data transfer

between FPU registers and CPU registers is carried out via the FPUL register.

Programming Note: When SZ = 1 and big endian mode is selected, FMOV can be used for

double-precision floating-point load or store operations. In little endian mode, two 32-bit data size

moves must be executed, with SZ = 0, to load or store a double-precision floating-point number.

2.3 Memory-Mapped Registers

Appendix A, Address List shows the control registers mapped to memory. The control registers

are double-mapped to the following two memory areas. All registers have two addresses.

H'1C00 0000–H'1FFF FFFF

H'FC00 0000–H'FFFF FFFF

These two areas are used as follows.

• H'1C00 0000–H'1FFF FFFF

This area must be accessed using the address translation function of the MMU. Setting the

page number of this area to the corresponding filed of the TLB enables access to a memory-

mapped register. Accessing this area without using the address translation function of the

MMU is not guaranteed.

• H'FC00 0000–H'FFFF FFFF

Access to area H'FF00 0000–H'FFFF FFFF in user mode will cause an address error. Memory-

mapped registers can be referenced in user mode by means of access that involves address

translation.

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Note: Do not access undefined locations in either area The operation of an access to an

undefined location is undefined. Also, memory-mapped registers must be accessed using a

fixed data size. The operation of an access using an invalid data size is undefined.

2.4 Data Format in Registers

or a word (16 bits), it is sign-extended into a longword when loaded into a register.

31 0

Longword

2.5 Data Formats in Memory

Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in

8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is

sign-extended before being loaded into a register.

A word operand must be accessed starting from a word boundary (even address of a 2-byte unit:

address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte

unit: address 4n). An address error will result if this rule is not observed. A byte operand can be

accessed from any address.

Big endian or little endian byte order can be selected for the data format. The endian should be set

with the MD5 external pin in a power-on reset. Big endian is selected when the MD5 pin is low,

and little endian when high. The endian cannot be changed dynamically. Bit positions are

numbered left to right from most-significant to least-significant. Thus, in a 32-bit longword, the

leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant

bit.

The data format in memory is shown in figure 2.5.

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Address A

70707070

15 0 15 0

31 0

15 0

31 0

23 15 7 0

A + 1 A + 2 A + 3

Byte 0

Word 0

Longword

Word 1

Byte 1 Byte 2 Byte 3

A + 11

70707070

15 0

23 15 7 0

A + 10 A + 9 A + 8

Byte 3

Word 1

Longword

Word 0

Byte 2 Byte 1 Byte 0

Address A + 4

Address A + 8

Address A + 4

Address A

Big endian Little endian

Figure 2.5 Data Formats In Memory

Note: The SH-4 does not support endian conversion for the 64-bit data format. Therefore, if

double-precision floating-point format (64-bit) access is performed in little endian mode,

the upper and lower 32 bits will be reversed.

2.6 Processor States

The SH-4 has five processor states: the reset state, exception-handling state, bus-released state,

program execution state, and power-down state.

Reset State: In this state the CPU is reset. The reset state is entered when the RESET pin goes

low. The CPU enters the power-on reset state if the MRESET pin is high, and the manual reset

state if the MRESET pin is low. For more information on resets, see section 5, Exceptions.

In the power-on reset state, the internal state of the CPU and the on-chip peripheral module

registers are initialized. In the manual reset state, the internal state of the CPU and registers of on-

chip peripheral modules other than the bus state controller (BSC) are initialized. Since the bus

state controller (BSC) is not initialized in the manual reset state, refreshing operations continue.

Refer to the register configurations in the relevant sections for further details.

Exception-Handling State: This is a transient state during which the CPU's processor state flow

is altered by a reset, general exception, or interrupt exception handling source.

In the case of a reset, the CPU branches to address H'A000 0000 and starts executing the user-

coded exception handling program.

In the case of a general exception or interrupt, the program counter (PC) contents are saved in the

saved program counter (SPC), the status register (SR) contents are saved in the saved status

branches to the start address of the user-coded exception service routine found from the sum of the

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contents of the vector base address and the vector offset. See section 5, Exceptions, for more

information on resets, general exceptions, and interrupts.

Program Execution State: In this state the CPU executes program instructions in sequence.

Power-Down State: In the power-down state, CPU operation halts and power consumption is

reduced. The power-down state is entered by executing a SLEEP instruction. There are two modes

in the power-down state: sleep mode and standby mode. For details, see section 9, Power-Down

Modes.

Bus-Released State: In this state the CPU has released the bus to a device that requested it.

Transitions between the states are shown in figure 2.6.

RESET = 0,

MRESET = 1

RESET = 1,

MRESET = 0

RESET = 1,

MRESET = 1

Power-on reset state Manual reset state

Program execution state

Bus-released state

Exception-handling state

Interrupt Interrupt

End of exception

transition

processing

Bus request

clearance

Exception

interrupt

Bus request

clearance

Bus

request

Bus request

clearance

SLEEP instruction

with STBY bit

cleared

SLEEP instruction

with STBY bit set

From any state when

RESET = 0 and MRESET = 1 RESET = 0 and MRESET = 0

Reset state

Power-down state

Bus request

Standby modeSleep mode

Figure 2.6 Processor State Transitions

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2.7 Processor Modes

There are two processor modes: user mode and privileged mode. The processor mode is

determined by the processor mode bit (MD) in the status register (SR). User mode is selected

when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1. When the reset

state or exception state is entered, the MD bit is set to 1. There are certain registers and bits which

can only be accessed in privileged mode.

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Section 3 Memory Management Unit (MMU)

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Section 3 Memory Management Unit (MMU)

3.1 Overview

3.1.1 Features

The SH-4 can handle 29-bit external memory space from an 8-bit address space identifier and 32-

bit logical (virtual) address space. Address translation from virtual address to physical address is

performed using the memory management unit (MMU) built into the SH-4. The MMU performs

high-speed address translation by caching user-created address translation table information in an

address translation buffer (translation lookaside buffer: TLB). The SH-4 has four instruction TLB

(ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by

hardware. A paging system is used for address translation, with support for four page sizes (1, 4,

and 64 Kbytes, and 1 Mbyte). It is possible to set the virtual address space access right and

implement storage protection independently for privileged mode and user mode.

3.1.2 Role of the MMU

The MMU was conceived as a means of making efficient use of physical memory. As shown in

figure 3.1, when a process is smaller in size than the physical memory, the entire process can be

mapped onto physical memory, but if the process increases in size to the point where it does not fit

into physical memory, it becomes necessary to divide the process into smaller parts, and map the

parts requiring execution onto physical memory on an ad hoc basis ((1)). Having this mapping

onto physical memory executed consciously by the process itself imposes a heavy burden on the

process. The virtual memory system was devised as a means of handling all physical memory

mapping to reduce this burden ((2)). With a virtual memory system, the size of the available

virtual memory is much larger than the actual physical memory, and processes are mapped onto

this virtual memory. Thus processes only have to consider their operation in virtual memory, and

mapping from virtual memory to physical memory is handled by the MMU. The MMU is

normally managed by the OS, and physical memory switching is carried out so as to enable the

virtual memory required by a task to be mapped smoothly onto physical memory. Physical

memory switching is performed via secondary storage, etc.

The virtual memory system that came into being in this way works to best effect in a time sharing

system (TSS) that allows a number of processes to run simultaneously ((3)). Running a number of

processes in a TSS did not increase efficiency since each process had to take account of physical

memory mapping. Efficiency is improved and the load on each process reduced by the use of a

virtual memory system ((4)). In this system, virtual memory is allocated to each process. The task

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of the MMU is to map a number of virtual memory areas onto physical memory in an efficient

manner. It is also provided with memory protection functions to prevent a process from

inadvertently accessing another process's physical memory.

When address translation from virtual memory to physical memory is performed using the MMU,

it may happen that the translation information has not been recorded in the MMU, or the virtual

memory of a different process is accessed by mistake. In such cases, the MMU will generate an

exception, change the physical memory mapping, and record the new address translation

information.

Although the functions of the MMU could be implemented by software alone, having address

translation performed by software each time a process accessed physical memory would be very

inefficient. For this reason, a buffer for address translation (the translation lookaside buffer: TLB)

is provided in hardware, and frequently used address translation information is placed here. The

TLB can be described as a cache for address translation information. However, unlike a cache, if

address translation fails—that is, if an exception occurs—switching of the address translation

information is normally performed by software. Thus memory management can be performed in a

flexible manner by software.

There are two methods by which the MMU can perform mapping from virtual memory to physical

memory: the paging method, using fixed-length address translation, and the segment method,

using variable-length address translation. With the paging method, the unit of translation is a

fixed-size address space called a page (usually from 1 to 64 Kbytes in size).

In the following descriptions, the address space in virtual memory in the SH-4 is referred to as

virtual address space, and the address space in physical memory as physical address space.

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(2)

Process 1

Physical

memory

Process 1

Process 2

Process 3

Virtual

memory

Process 1

Process 2

Process 3

MMU

(4)(3)

(1)

Physical

memory

Physical

memory

Physical

memory

Physical

memory

Virtual

memory

Figure 3.1 Role of the MMU

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3.1.3 Register Configuration

The MMU registers are shown in table 3.1.

Table 3.1 MMU Registers

Name

Abbrevia-

tion

R/W

Initial

Value*1

Address*2

Area 7

Address*2

Access

Size

Page table entry high

PTEH R/W Undefined H'FF00 0000 H'1F00 0000 32

Page table entry low

PTEL R/W Undefined H'FF00 0004 H'1F00 0004 32

Page table entry

assistance register

PTEA R/W Undefined H'FF00 0034 H'1F00 0034 32

Translation table base

TTB R/W Undefined H'FF00 0008 H'1F00 0008 32

TLB exception address

TEA R/W Undefined H'FF00 000C H'1F00 000C 32

MMU control register MMUCR R/W H'0000 0000 H'FF00 0010 H'1F00 0010 32

Notes: 1. The initial value is the value after a power-on reset or manual reset.

2. This is the address when using the virtual/physical address space P4 area. When

making an access from physical address space area 7 using the TLB, the upper 3 bits

of the address are ignored.

3.1.4 Caution

Operation is not guaranteed if an area designated as a reserved area in this manual is accessed.

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3.2 Register Descriptions

There are six MMU-related registers.

31 10 9 87 0

VPN

PPN

— — ASID

1. PTEH

31 30 29 28 10 9 8 765 4 3 2 1 0

— — — — V SZ PR SZ C D SH

2. PTEL

31 4 32 0

TC SA

3. PTEA

31 0

TTB

4. TTB

Virtual address at which MMU exception or address error occurred

5. TEA

31 26 24 23 18 17 16 15 10 9 8 7 6 5 4 3 2 1 0

LRUI — — — — URC

SQMD

SV—————TI—AT

6. MMUCR

Note: — indicates a reserved bit: the write value must be 0, and a read will return 0.

URB

Figure 3.2 MMU-Related Registers

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1. Page table entry high register (PTEH): Longword access to PTEH can be performed from

H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number

(VPN) and address space identifier (ASID). When an MMU exception or address error exception

occurs, the VPN of the virtual address at which the exception occurred is set in the VPN field by

hardware. VPN varies according to the page size, but the VPN set by hardware when an exception

occurs consists of the upper 22 bits of the virtual address which caused the exception. VPN setting

can also be carried out by software. The number of the currently executing process is set in the

ASID field by software. ASID is not updated by hardware. VPN and ASID are recorded in the

UTLB by means of the LDLTB instruction.

A branch to the P0, P3, or U0 area which uses the updated ASID after the ASID field in PTEH is

rewritten should be made at least 6 instructions after the PTEH update instruction.

2. Page table entry low register (PTEL): Longword access to PTEL can be performed from

H'FF00 0004 in the P4 area and H'1F00 0004 in area 7. PTEL is used to hold the physical page

number and page management information to be recorded in the UTLB by means of the LDTLB

instruction. The contents of this register are not changed unless a software directive is issued.

3. Page table entry assistance register (PTEA): Longword access to PTEA can be performed

from H'FF00 0034 in the P4 area and H'1F00 0034 in area 7. PTEL is used to store assistance bits

for PCMCIA access to the UTLB by means of the LDTLB instruction. When performing access

from the CPU in the SH7750S and SH7750R with MMUCR.AT = 0, access is always performed

using the values of the SA and TC bits in this register. In the SH7750, it is not possible to access a

PCMCIA interface area with MMUCR.AT = 0. In this LSI, access to a PCMCIA interface area by

the DMAC is always performed using the DMAC's CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC,

and CHCRn.DTC values. The contents of this register are not changed unless a software directive

is issued.

4. Translation table base register (TTB): Longword access to TTB can be performed from

H'FF00 0008 in the P4 area and H'1F00 0008 in area 7. TTB is used, for example, to hold the base

address of the currently used page table. The contents of TTB are not changed unless a software

directive is issued. This register can be freely used by software.

5. TLB exception address register (TEA): Longword access to TEA can be performed from

H'FF00 000C in the P4 area and H'1F00 000C in area 7. After an MMU exception or address error

exception occurs, the virtual address at which the exception occurred is set in TEA by hardware.

The contents of this register can be changed by software.

6. MMU control register (MMUCR): MMUCR contains the following bits:

LRUI: Least recently used ITLB

URB: UTLB replace boundary

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URC: UTLB replace counter

SQMD: Store queue mode bit

SV: Single virtual mode bit

TI: TLB invalidate

AT: Address translation bit

Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00

0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR

rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an

instruction that performs data access to the P0, P3, U0, or store queue area should be located at

least four instructions after the MMUCR update instruction. Also, a branch instruction to the P0,

P3, or U0 area should be located at least eight instructions after the MMUCR update instruction.

MMUCR contents can be changed by software. The LRUI bits and URC bits may also be updated

by hardware.

• LRUI: Least recently used ITLB. The LRU (least recently used) method is used to decide the

ITLB entry to be replaced in the event of an ITLB miss. The entry to be purged from the ITLB

can be confirmed using the LRUI bits. LRUI is updated by means of the algorithm shown

below. A dash in this table means that updating is not performed.

LRUI

[5] [4] [3] [2] [1] [0]

When ITLB entry 0 is used 0 0 0 — — —

When ITLB entry 1 is used 1 — — 0 0 —

When ITLB entry 2 is used — 1 — 1 — 0

When ITLB entry 3 is used — — 1 — 1 1

Other than the above — — — — — —

When the LRUI bit settings are as shown below, the corresponding ITLB entry is updated by

an ITLB miss. An asterisk in this table means “don't care”.

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LRUI

[5] [4] [3] [2] [1] [0]

ITLB entry 0 is updated 1 1 1 * * *

ITLB entry 1 is updated 0 * * 1 1 *

ITLB entry 2 is updated * 0 * 0 * 1

ITLB entry 3 is updated * * 0 * 0 0

Other than the above Setting prohibited

Ensure that values for which “Setting prohibited” is indicated in the above table are not set at

the discretion of software. After a power-on or manual reset the LRUI bits are initialized to 0,

and therefore a prohibited setting is never made by a hardware update.

• URB: UTLB replace boundary. Bits that indicate the UTLB entry boundary at which

replacement is to be performed. Valid only when URB > 0.

• URC: UTLB replace counter. Random counter for indicating the UTLB entry for which

replacement is to be performed with an LDTLB instruction. URC is incremented each time the

UTLB is accessed. When URB > 0, URC is reset to 0 when the condition URC = URB occurs.

Also note that, if a value is written to URC by software which results in the condition URC >

URB, incrementing is first performed in excess of URB until URC = H'3F. URC is not

incremented by an LDTLB instruction.

• SQMD: Store queue mode bit. Specifies the right of access to the store queues.

0: User/privileged access possible

1: Privileged access possible (address error exception in case of user access)

• SV: Single virtual mode bit. Bit that switches between single virtual memory mode and

multiple virtual memory mode.

0: Multiple virtual memory mode

1: Single virtual memory mode

When this bit is changed, ensure that 1 is also written to the TI bit.

• TI: TLB invalidation bit. Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLB

bits. This bit always returns 0 when read.

• AT: Address translation enable bit. Specifies MMU enabling or disabling.

0: MMU disabled

1: MMU enabled

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MMU exceptions are not generated when the AT bit is 0. In the case of software that does not

use the MMU, therefore, the AT bit should be cleared to 0.

3.3 Address Space

3.3.1 Physical Address Space

The SH-4 supports a 32-bit physical address space, and can access a 4-Gbyte address space. When

the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical

address space. The physical address space is divided into a number of areas, as shown in figure

3.3. The physical address space is permanently mapped onto 29-bit external memory space; this

correspondence can be implemented by ignoring the upper 3 bits of the physical address space

addresses. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be accessed.

In user mode, a 2-Gbyte space in the U0 area can be accessed. Accessing the P1 to P4 areas

(except the store queue area) in user mode will cause an address error.

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External

memory space

Address error

Store queue area

User modePrivileged mode

P1 area

Cacheable

P0 area

Cacheable

P2 area

Non-cacheable

P3 area

Cacheable

P4 area

Non-cacheable

U0 area

Cacheable

H'0000 0000

H'8000 0000

H'E000 0000

H'E400 0000

H'FFFF FFFF

H'0000 0000

H'8000 0000

H'FFFF FFFF

H'A000 0000

H'C000 0000

H'E000 0000

Figure 3.3 Physical Address Space (MMUCR.AT = 0)

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In the SH7750, the CPU cannot access a PCMCIA interface area. When performing access from

the CPU to a PCMCIA interface area in the SH7750S or the SH7750R, access is always

performed using the values of the SA and TC bits set in the PTEA register.

The PCMCIA interface area is always accessed by the DMAC with the values of CHCRn.SSAn,

CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC in the DMAC. For details, see section 14, Direct

Memory Access Controller (DMAC).

P0, P1, P3, U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache. Whether or

not the cache is used is determined by the cache control register (CCR). When the cache is used,

with the exception of the P1 area, switching between the copy-back method and the write-through

method for write accesses is specified by the CCR.WT bit. For the P1 area, switching is specified

by the CCR.CB bit. Zeroizing the upper 3 bits of an address in these areas gives the corresponding

external memory space address. However, since area 7 in the external memory space is a reserved

area, a reserved area also appears in these areas.

P2 Area: The P2 area cannot be accessed using the cache. In the P2 area, zeroizing the upper 3

bits of an address gives the corresponding external memory space address. However, since area 7

in the external memory space is a reserved area, a reserved area also appears in this area.

P4 Area: The P4 area is mapped onto SH-4 on-chip I/O channels. This area cannot be accessed

using the cache. The P4 area is shown in detail in figure 3.4.

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H'E000 0000

H'E400 0000

H'F000 0000

H'F100 0000

H'F200 0000

H'F300 0000

H'F400 0000

H'F500 0000

H'F600 0000

H'F700 0000

H'F800 0000

H'FC00 0000

Store queue

Reserved area

Instruction cache address array

Instruction cache data array

Instruction TLB address array

Instruction TLB data arrays 1 and 2

Operand cache address array

Operand cache data array

Unified TLB address array

Unified TLB data arrays 1 and 2

Reserved area

Control register area

Figure 3.4 P4 Area

The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues

(SQs). When the MMU is disabled (MMUCR.AT = 0), the SQ access right is specified by the

MMUCR.SQMD bit. For details, see section 4.7, Store Queues.

The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache

address array. For details, see section 4.5.1, IC Address Array.

The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data

array. For details, see section 4.5.2, IC Data Array.

The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB

address array. For details, see section 3.7.1, ITLB Address Array.

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The area from H'F300 0000 to H'F3FF FFFF is used for direct access to instruction TLB data

arrays 1 and 2. For details, see sections 3.7.2, ITLB Data Array 1, and 3.7.3, ITLB Data Array 2.

The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address

array. For details, see section 4.5.3, OC Address Array.

The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data

array. For details, see section 4.5.4, OC Data Array.

The area from H'F600 0000 to H'F6FF FFFF is used for direct access to the unified TLB address

array. For details, see section 3.7.4, UTLB Address Array.

The area from H'F700 0000 to H'F7FF FFFF is used for direct access to unified TLB data arrays 1

and 2. For details, see sections 3.7.5, UTLB Data Array 1, and 3.7.6, UTLB Data Array 2.

The area from H'FF00 0000 to H'FFFF FFFF is the on-chip peripheral module control register

area. For details, see appendix A, Address List.

3.3.2 External Memory Space

The SH-4 supports a 29-bit external memory space. The external memory space is divided into

eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous

DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13, Bus State

Controller (BSC).

H'0000 0000

H'0400 0000

H'0800 0000

H'0C00 0000

H'1000 0000

H'1400 0000

H'1800 0000

H'1C00 0000

H'1FFF FFFF

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7 (reserved area)

Figure 3.5 External Memory Space

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3.3.3 Virtual Address Space

Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical memory space in

the SH-4 to be mapped onto any external memory space in 1-, 4-, or 64-Kbyte, or 1-Mbyte, page

units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be

increased to a maximum of 256. This is called the virtual memory space. Mapping from virtual

memory space to 29-bit external memory space is carried out using the TLB. Only when area 7 in

external memory space is accessed using virtual memory space, addresses H'1C00 0000 to H'1FFF

FFFF of area 7 are not designated as a reserved area, but are equivalent to the P4 area control

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External

memory space

256

U0 area

Cacheable

Address translation possible

Address error

Store queue area

P0 area

Cacheable

Address translation possible

User mode

Privileged mode

P1 area

Cacheable

Address translation not possible

P2 area

Non-cacheable

Address translation not possible

P3 area

Cacheable

Address translation possible

P4 area

Non-cacheable

Address translation not possible

Figure 3.6 Virtual Address Space (MMUCR.AT = 1)

In the state of cache enabling, when the areas of P0, P3, and U0 are mapped onto a PCMCIA

interface area by means of the TLB, it is necessary either to specify 1 for the WT bit or to specify

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0 for the C bit on that page. At that time, the regions are accessed by the values of SA and TC set

in page units of the TLB.

Here, access to the PCMCIA interface area by accessing an area of P1, P2, or P4 from the CPU is

disabled.

In addition, the PCMCIA interface area is always accessed by the DMAC with the values of

CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC in the DMAC. For details, see

section 14, Direct Memory Access Controller (DMAC).

P0, P3, U0 Areas: The P0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF), P3 area, and

U0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF) allow access using the cache and

address translation using the TLB. These areas can be mapped onto any external memory space in

1-, 4-, or 64-Kbyte, or 1-Mbyte, page units. When CCR is in the cache-enabled state and the TLB

enable bit (C bit) is 1, accesses can be performed using the cache. In write accesses to the cache,

switching between the copy-back method and the write-through method is indicated by the TLB

write-through bit (WT bit), and is specified in page units.

Only when the P0, P3, and U0 areas are mapped onto external memory space by means of the

TLB, addresses H'1C00 0000 to H'1FFF FFFF of area 7 in external memory space are allocated to

the control register area. This enables on-chip peripheral module control registers to be accessed

from the U0 area in user mode. In this case, the C bit for the corresponding page must be cleared

to 0.

P1, P2, P4 Areas: Address translation using the TLB cannot be performed for the P1, P2, or P4

area (except for the store queue area). Accesses to these areas are the same as for physical memory

space. The store queue area can be mapped onto any external memory space by the MMU.

However, operation in the case of an exception differs from that for normal P0, U0, and P3 spaces.

For details, see section 4.7, Store Queues.

3.3.4 On-Chip RAM Space

In the SH-4, half of the instruction cache can be used as on-chip RAM. This can be done by

changing the CCR settings.

When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0 area addresses H'7C00

0000 to H'7FFF FFFF are an on-chip RAM area. Data accesses (byte/word/longword/quadword)

can be used in this area. This area can only be used in RAM mode.

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3.3.5 Address Translation

When the MMU is used, the virtual address space is divided into units called pages, and

translation to physical addresses is carried out in these page units. The address translation table in

external memory contains the physical addresses corresponding to virtual addresses and additional

information such as memory protection codes. Fast address translation is achieved by caching the

contents of the address translation table located in external memory into the TLB. In the SH-4,

basically, the ITLB is used for instruction accesses and the UTLB for data accesses. In the event

of an access to an area other than the P4 area, the accessed virtual address is translated to a

physical address. If the virtual address belongs to the P1 or P2 area, the physical address is

uniquely determined without accessing the TLB. If the virtual address belongs to the P0, U0, or P3

area, the TLB is searched using the virtual address, and if the virtual address is recorded in the

TLB, a TLB hit is made and the corresponding physical address is read from the TLB. If the

accessed virtual address is not recorded in the TLB, a TLB miss exception is generated and

processing switches to the TLB miss exception routine. In the TLB miss exception routine, the

address translation table in external memory is searched, and the corresponding physical address

and page management information are recorded in the TLB. After the return from the exception

handling routine, the instruction which caused the TLB miss exception is re-executed.

3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode

There are two virtual memory systems, single virtual memory and multiple virtual memory, either

of which can be selected with the MMUCR.SV bit. In the single virtual memory system, a number

of processes run simultaneously, using virtual address space on an exclusive basis, and the

physical address corresponding to a particular virtual address is uniquely determined. In the

multiple virtual memory system, a number of processes run while sharing the virtual address

space, and a particular virtual address may be translated into different physical addresses

depending on the process. The only difference between the single virtual memory and multiple

virtual memory systems in terms of operation is in the TLB address comparison method (see

section 3.4.3, Address Translation Method).

3.3.7 Address Space Identifier (ASID)

In multiple virtual memory mode, the 8-bit address space identifier (ASID) is used to distinguish

between processes running simultaneously while sharing the virtual address space. Software can

set the ASID of the currently executing process in PTEH in the MMU. The TLB does not have to

be purged when processes are switched by means of ASID.

In single virtual memory mode, ASID is used to provide memory protection for processes running

simultaneously while using the virtual memory space on an exclusive basis.

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Note: In single virtual memory mode, entries with the same virtual page number (VPN) but

different ASIDs cannot be set in the TLB simultaneously.

3.4 TLB Functions

3.4.1 Unified TLB (UTLB) Configuration

The unified TLB (UTLB) is so called because of its use for the following two purposes:

1. To translate a virtual address to a physical address in a data access

2. As a table of address translation information to be recorded in the instruction TLB in the event

of an ITLB miss

Information in the address translation table located in external memory is cached into the UTLB.

The address translation table contains virtual page numbers and address space identifiers, and

corresponding physical page numbers and page management information. Figure 3.7 shows the

overall configuration of the UTLB. The UTLB consists of 64 fully-associative type entries. Figure

3.8 shows the relationship between the address format and page size.

PPN [28:10]

SZ [1:0]

PR [1:0]

ASID [7:0]

VPN [31:10]

Entry 0

Entry 1

Entry 2

PPN [28:10] SZ [1:0] SH C PR [1:0]

SA [2:0]

SA [2:0] TCASID [7:0] VPN [31:10] VEntry 63 D WT

Figure 3.7 UTLB Configuration

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• 1-Kbyte page

10 9 0

Virtual address

• 4-Kbyte page

12 11 0

Virtual address

• 64-Kbyte page

16 15 0

Virtual address

• 1-Mbyte page

20 19 0

Virtual address

VPN

Offset

VPN Offset

28 10 9 0

Physical address

28 12 11 0

Physical address

28 16 15 0

Physical address

28 20 19 0

Physical address

PPN Offset

Figure 3.8 Relationship between Page Size and Address Format

• VPN: Virtual page number

For 1-Kbyte page: upper 22 bits of virtual address

For 4-Kbyte page: upper 20 bits of virtual address

For 64-Kbyte page: upper 16 bits of virtual address

For 1-Mbyte page: upper 12 bits of virtual address

• ASID: Address space identifier

Indicates the process that can access a virtual page.

In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH

bit is 0, this identifier is compared with the ASID in PTEH when address comparison is

performed.

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• SH: Share status bit

When 0, pages are not shared by processes.

When 1, pages are shared by processes.

• SZ: Page size bits

Specify the page size.

00: 1-Kbyte page

01: 4-Kbyte page

10: 64-Kbyte page

11: 1-Mbyte page

• V: Validity bit

Indicates whether the entry is valid.

0: Invalid

1: Valid

Cleared to 0 by a power-on reset.

Not affected by a manual reset.

• PPN: Physical page number

Upper 22 bits of the physical address.

With a 1-Kbyte page, PPN bits [28:10] are valid.

With a 4-Kbyte page, PPN bits [28:12] are valid.

With a 64-Kbyte page, PPN bits [28:16] are valid.

With a 1-Mbyte page, PPN bits [28:20] are valid.

The synonym problem must be taken into account when setting the PPN (see section 3.5.5,

Avoiding Synonym Problems).

• PR: Protection key data

2-bit data expressing the page access right as a code.

00: Can be read only, in privileged mode

01: Can be read and written in privileged mode

10: Can be read only, in privileged or user mode

11: Can be read and written in privileged mode or user mode

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• C: Cacheability bit

Indicates whether a page is cacheable.

0: Not cacheable

1: Cacheable

When control register space is mapped, this bit must be cleared to 0.

When performing PCMCIA space mapping in the cache enabled state, either clear this bit to 0

or set the WT bit to 1.

• D: Dirty bit

Indicates whether a write has been performed to a page.

0: Write has not been performed

1: Write has been performed

• WT: Write-through bit

Specifies the cache write mode.

0: Copy-back mode

1: Write-through mode

When performing PCMCIA space mapping in the cache enabled state, either set this bit to 1 or

clear the C bit to 0.

• SA: Space attribute bits

Valid only when the page is mapped onto PCMCIA connected to area 5 or 6.

000: Undefined

001: Variable-size I/O space (base size according to IOIS16 signal)

010: 8-bit I/O space

011: 16-bit I/O space

100: 8-bit common memory space

101: 16-bit common memory space

110: 8-bit attribute memory space

111: 16-bit attribute memory space

• TC: Timing control bit

Used to select wait control register bits in the bus control unit for areas 5 and 6.

0: WCR2 (A5W2–A5W0) and PCR (A5PCW1–A5PCW0, A5TED2–A5TED0, A5TEH2–

A5TEH0) are used

1: WCR2 (A6W2–A6W0) and PCR (A6PCW1–A6PCW0, A6TED2–A6TED0, A6TEH2–

A6TEH0) are used

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3.4.2 Instruction TLB (ITLB) Configuration

The ITLB is used to translate a virtual address to a physical address in an instruction access.

Information in the address translation table located in the UTLB is cached into the ITLB. Figure

3.9 shows the overall configuration of the ITLB. The ITLB consists of 4 fully-associative type

entries. The address translation information is almost the same as that in the UTLB, but with the

following differences:

1. D and WT bits are not supported.

2. There is only one PR bit, corresponding to the upper of the PR bits in the UTLB.

PPN [28:10]

SZ [1:0]

ASID [7:0]

VPN [31:10]

Entry 0

Entry 1

Entry 2

Entry 3

SA [2:0]

Figure 3.9 ITLB Configuration

3.4.3 Address Translation Method

Figures 3.10 and 3.11 show flowcharts of memory accesses using the UTLB and ITLB.

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MMUCR.AT = 1

SH = 0

and (MMUCR.SV = 0 or

SR.MD = 0)

VPNs match

and ASIDs match and

V = 1

Only one

entry matches

SR.MD?

CCR.OCE?

CCR.CB? CCR.WT?

VPNs match

and V = 1

Cache access

in write-through mode

Memory access

Data TLB multiple

hit exception

Data TLB protection

violation exception

Data TLB miss

exception

Initial page write

exception

Data TLB protection

violation exception

Cache access

in copy-back mode

Data access to virtual address (VA)

On-chip I/O access

R/W?

VA is

in P4 area

VA is

in P2 area

VA is

in P1 area

VA is in P0, U0,

or P3 area

Yes

NoNo

Yes

1 (Privileged)

PR?

0 (User)

R/W? WW

RRRR

R/W?

(Non-cacheable)

WT?

C = 1

and CCR.OCE = 1

00 or

10 11 01 or 11 00 or 10

Figure 3.10 Flowchart of Memory Access Using UTLB

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MMUCR.AT = 1

SH = 0

and (MMUCR.SV = 0 or

SR.MD = 0)

VPNs match

and ASIDs match and

V = 1

Only one

entry matches

SR.MD?

CCR.ICE?

VPNs match

and V = 1

Memory access

Instruction TLB

multiple hit exception

Instruction TLB

miss exception

Instruction access to virtual address (VA)

VA is

in P4 area

VA is

in P2 area

VA is

in P1 area

VA is in P0, U0,

or P3 area

Yes

(Non-cacheable)

C = 1

and CCR.ICE = 1

PR?

Instruction TLB protection

violation exception

Match? Record in ITLB

Access prohibited

Yes

Hardware ITLB

miss handling

0 (User)

1 (Privileged)

Search UTLB

Cache access

Figure 3.11 Flowchart of Memory Access Using ITLB

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3.5 MMU Functions

3.5.1 MMU Hardware Management

The SH-4 supports the following MMU functions.

1. The MMU decodes the virtual address to be accessed by software, and performs address

translation by controlling the UTLB/ITLB in accordance with the MMUCR settings.

2. The MMU determines the cache access status on the basis of the page management

information read during address translation (C, WT, SA, and TC bits).

3. If address translation cannot be performed normally in a data access or instruction access, the

MMU notifies software by means of an MMU exception.

4. If address translation information is not recorded in the ITLB in an instruction access, the

MMU searches the UTLB, and if the necessary address translation information is recorded in

the UTLB, the MMU copies this information into the ITLB in accordance with

MMUCR.LRUI.

3.5.2 MMU Software Management

Software processing for the MMU consists of the following:

1. Setting of MMU-related registers. Some registers are also partially updated by hardware

automatically.

2. Recording, deletion, and reading of TLB entries. There are two methods of recording UTLB

entries: by using the LDTLB instruction, or by writing directly to the memory-mapped UTLB.

ITLB entries can only be recorded by writing directly to the memory-mapped ITLB. For

deleting or reading UTLB/ITLB entries, it is possible to access the memory-mapped

UTLB/ITLB.

3. MMU exception handling. When an MMU exception occurs, processing is performed based on

information set by hardware.

3.5.3 MMU Instruction (LDTLB)

A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB

instruction is issued, the SH-4 copies the contents of PTEH, PTEL, and PTEA to the UTLB entry

indicated by MMUCR.URC. ITLB entries are not updated by the LDTLB instruction, and

therefore address translation information purged from the UTLB entry may still remain in the

ITLB entry. As the LDTLB instruction changes address translation information, ensure that it is

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issued by a program in the P1 or P2 area. The operation of the LDTLB instruction is shown in

figure 3.12.

PPN [28:10]

SZ [1:0]

PR [1:0]

ASID [7:0]

VPN [31:10]

Entry 0

Entry 1

Entry 2

PPN [28:10] SZ [1:0] SH C PR [1:0]

SA [2:0]

SA [2:0] TCASID [7:0] VPN [31:10] VEntry 63 DWT

31 29 28 9 8 765 4 3 2 1 0

——VSZPRSZCDSH

PTEL

Write

UTLB

31 10 9 87 0

— ASID

PTEH

31 26 25 24 23 18 17 16 15 10 9 87 3 2 1 0

LRUI — URB — URC SV

SQMD

—TI—AT

MMUCR

VPN

PPN

31 432 0

—SA

PTEA

Entry specification

Figure 3.12 Operation of LDTLB Instruction

3.5.4 Hardware ITLB Miss Handling

In an instruction access, the SH-4 searches the ITLB. If it cannot find the necessary address

translation information (i.e. in the event of an ITLB miss), the UTLB is searched by hardware, and

if the necessary address translation information is present, it is recorded in the ITLB. This

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procedure is known as hardware ITLB miss handling. If the necessary address translation

information is not found in the UTLB search, an instruction TLB miss exception is generated and

processing passes to software.

3.5.5 Avoiding Synonym Problems

When 1- or 4-Kbyte pages are recorded in TLB entries, a synonym problem may arise. The

problem is that, when a number of virtual addresses are mapped onto a single physical address, the

same physical address data is recorded in a number of cache entries, and it becomes impossible to

guarantee data integrity. This problem does not occur with the instruction TLB or instruction

cache. In the SH-4, entry specification is performed using bits [13:5] of the virtual address in order

to achieve fast operand cache operation. However, bits [13:10] of the virtual address in the case of

a 1-Kbyte page, and bits [13:12] of the virtual address in the case of a 4-Kbyte page, are subject to

address translation. As a result, bits [13:10] of the physical address after translation may differ

from bits [13:10] of the virtual address.

Consequently, the following restrictions apply to the recording of address translation information

in UTLB entries.

1. When address translation information whereby a number of 1-Kbyte page UTLB entries are

translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:10]

values are the same.

2. When address translation information whereby a number of 4-Kbyte page UTLB entries are

translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:12]

values are the same.

3. Do not use 1-Kbyte page UTLB entry physical addresses with UTLB entries of a different

page size.

4. Do not use 4-Kbyte page UTLB entry physical addresses with UTLB entries of a different

page size.

The above restrictions apply only when performing accesses using the cache. When cache index

mode is used, VPN [25] is used for the entry address instead of VPN [13], and therefore the above

restrictions apply to VPN [25].

Note: When multiple items of address translation information use the same physical memory to

provide for future SuperH RISC engine family expansion, ensure that the VPN [20:10]

values are the same. Also, do not use the same physical address for address translation

information of different page sizes.

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3.6 MMU Exceptions

There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB

miss exception, instruction TLB protection violation exception, data TLB multiple hit exception,

data TLB miss exception, data TLB protection violation exception, and initial page write

exception. Refer to figures 3.10 and 3.11 for the conditions under which each of these exceptions

occurs.

3.6.1 Instruction TLB Multiple Hit Exception

An instruction TLB multiple hit exception occurs when more than one ITLB entry matches the

virtual address to which an instruction access has been made. If multiple hits occur when the

UTLB is searched by hardware in hardware ITLB miss handling, a data TLB multiple hit

exception will result.

When an instruction TLB multiple hit exception occurs a reset is executed, and cache coherency is

not guaranteed.

Hardware Processing: In the event of an instruction TLB multiple hit exception, hardware carries

out the following processing:

1. Sets the virtual address at which the exception occurred in TEA.

2. Sets exception code H'140 in EXPEVT.

3. Branches to the reset handling routine (H'A000 0000).

Software Processing (Reset Routine): The ITLB entries which caused the multiple hit exception

are checked in the reset handling routine. This exception is intended for use in program

debugging, and should not normally be generated.

3.6.2 Instruction TLB Miss Exception

An instruction TLB miss exception occurs when address translation information for the virtual

address to which an instruction access is made is not found in the UTLB entries by the hardware

ITLB miss handling procedure. The instruction TLB miss exception processing carried out by

hardware and software is shown below. This is the same as the processing for a data TLB miss

exception.

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Hardware Processing: In the event of an instruction TLB miss exception, hardware carries out

the following processing:

1. Sets the VPN of the virtual address at which the exception occurred in PTEH.

2. Sets the virtual address at which the exception occurred in TEA.

3. Sets exception code H'040 in EXPEVT.

4. Sets the PC value indicating the address of the instruction at which the exception occurred in

SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the

delayed branch instruction in SPC.

5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are

saved in SGR.

6. Sets the MD bit in SR to 1, and switches to privileged mode.

7. Sets the BL bit in SR to 1, and masks subsequent exception requests.

8. Sets the RB bit in SR to 1.

9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and

starts the instruction TLB miss exception handling routine.

Software Processing (Instruction TLB Miss Exception Handling Routine): Software is

responsible for searching the external memory page table and assigning the necessary page table

entry. Software should carry out the following processing in order to find and assign the necessary

page table entry.

1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table

entry recorded in the external memory address translation table. If necessary, the values of the

SA and TC bits should be written to PTEA.

2. When the entry to be replaced in entry replacement is specified by software, write that value to

URC in the MMUCR register. If URC is greater than URB at this time, the value should be

changed to an appropriate value after issuing an LDTLB instruction.

3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the TLB.

4. Finally, execute the exception handling return instruction (RTE), terminate the exception

handling routine, and return control to the normal flow. The RTE instruction should be issued

at least one instruction after the LDTLB instruction.

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3.6.3 Instruction TLB Protection Violation Exception

An instruction TLB protection violation exception occurs when, even though an ITLB entry

contains address translation information matching the virtual address to which an instruction

access is made, the actual access type is not permitted by the access right specified by the PR bit.

The instruction TLB protection violation exception processing carried out by hardware and

software is shown below.

Hardware Processing: In the event of an instruction TLB protection violation exception,

hardware carries out the following processing:

1. Sets the VPN of the virtual address at which the exception occurred in PTEH.

2. Sets the virtual address at which the exception occurred in TEA.

3. Sets exception code H'0A0 in EXPEVT.

4. Sets the PC value indicating the address of the instruction at which the exception occurred in

SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the

delayed branch instruction in SPC.

5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are

saved in SGR.

6. Sets the MD bit in SR to 1, and switches to privileged mode.

7. Sets the BL bit in SR to 1, and masks subsequent exception requests.

8. Sets the RB bit in SR to 1.

9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and

starts the instruction TLB protection violation exception handling routine.

Software Processing (Instruction TLB Protection Violation Exception Handling Routine):

Resolve the instruction TLB protection violation, execute the exception handling return instruction

(RTE), terminate the exception handling routine, and return control to the normal flow. The RTE

instruction should be issued at least one instruction after the LDTLB instruction.

3.6.4 Data TLB Multiple Hit Exception

A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual

address to which a data access has been made. A data TLB multiple hit exception is also generated

if multiple hits occur when the UTLB is searched in hardware ITLB miss handling.

When a data TLB multiple hit exception occurs a reset is executed, and cache coherency is not

guaranteed. The contents of PPN in the UTLB prior to the exception may also be corrupted.

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Hardware Processing: In the event of a data TLB multiple hit exception, hardware carries out the

following processing:

1. Sets the virtual address at which the exception occurred in TEA.

2. Sets exception code H'140 in EXPEVT.

3. Branches to the reset handling routine (H'A000 0000).

Software Processing (Reset Routine): The UTLB entries which caused the multiple hit exception

are checked in the reset handling routine. This exception is intended for use in program

debugging, and should not normally be generated.

3.6.5 Data TLB Miss Exception

A data TLB miss exception occurs when address translation information for the virtual address to

which a data access is made is not found in the UTLB entries. The data TLB miss exception

processing carried out by hardware and software is shown below.

Hardware Processing: In the event of a data TLB miss exception, hardware carries out the

following processing:

1. Sets the VPN of the virtual address at which the exception occurred in PTEH.

2. Sets the virtual address at which the exception occurred in TEA.

3. Sets exception code H'040 in the case of a read, or H'060 in the case of a write, in EXPEVT

(OCBP, OCBWB: read; OCBI, MOVCA.L: write).

4. Sets the PC value indicating the address of the instruction at which the exception occurred in

SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the

delayed branch instruction in SPC.

5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are

saved in SGR.

6. Sets the MD bit in SR to 1, and switches to privileged mode.

7. Sets the BL bit in SR to 1, and masks subsequent exception requests.

8. Sets the RB bit in SR to 1.

9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and

starts the data TLB miss exception handling routine.

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Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible

for searching the external memory page table and assigning the necessary page table entry.

Software should carry out the following processing in order to find and assign the necessary page

table entry.

1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table

entry recorded in the external memory address translation table. If necessary, the values of the

SA and TC bits should be written to PTEA.

2. When the entry to be replaced in entry replacement is specified by software, write that value to

URC in the MMUCR register. If URC is greater than URB at this time, the value should be

changed to an appropriate value after issuing an LDTLB instruction.

3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the

UTLB.

4. Finally, execute the exception handling return instruction (RTE), terminate the exception

handling routine, and return control to the normal flow. The RTE instruction should be issued

at least one instruction after the LDTLB instruction.

3.6.6 Data TLB Protection Violation Exception

A data TLB protection violation exception occurs when, even though a UTLB entry contains

address translation information matching the virtual address to which a data access is made, the

actual access type is not permitted by the access right specified by the PR bit. The data TLB

protection violation exception processing carried out by hardware and software is shown below.

Hardware Processing: In the event of a data TLB protection violation exception, hardware

carries out the following processing:

1. Sets the VPN of the virtual address at which the exception occurred in PTEH.

2. Sets the virtual address at which the exception occurred in TEA.

3. Sets exception code H'0A0 in the case of a read, or H'0C0 in the case of a write, in EXPEVT

(OCBP, OCBWB: read; OCBI, MOVCA.L: write).

4. Sets the PC value indicating the address of the instruction at which the exception occurred in

SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the

delayed branch instruction in SPC.

5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are

saved in SGR.

6. Sets the MD bit in SR to 1, and switches to privileged mode.

7. Sets the BL bit in SR to 1, and masks subsequent exception requests.

8. Sets the RB bit in SR to 1.

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9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and

starts the data TLB protection violation exception handling routine.

Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve

the data TLB protection violation, execute the exception handling return instruction (RTE),

terminate the exception handling routine, and return control to the normal flow. The RTE

instruction should be issued at least one instruction after the LDTLB instruction.

3.6.7 Initial Page Write Exception

An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains

address translation information matching the virtual address to which a data access (write) is

made, and the access is permitted. The initial page write exception processing carried out by

hardware and software is shown below.

Hardware Processing: In the event of an initial page write exception, hardware carries out the

following processing:

1. Sets the VPN of the virtual address at which the exception occurred in PTEH.

2. Sets the virtual address at which the exception occurred in TEA.

3. Sets exception code H'080 in EXPEVT.

4. Sets the PC value indicating the address of the instruction at which the exception occurred in

SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the

delayed branch instruction in SPC.

5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are

saved in SGR.

6. Sets the MD bit in SR to 1, and switches to privileged mode.

7. Sets the BL bit in SR to 1, and masks subsequent exception requests.

8. Sets the RB bit in SR to 1.

9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and

starts the initial page write exception handling routine.

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Software Processing (Initial Page Write Exception Handling Routine): The following

processing should be carried out as the responsibility of software:

1. Retrieve the necessary page table entry from external memory.

2. Write 1 to the D bit in the external memory page table entry.

3. Write to PTEL the values of the PPN, PR, SZ, C, D, WT, SH, and V bits in the page table

entry recorded in external memory. If necessary, the values of the SA and TC bits should be

written to PTEA.

4. When the entry to be replaced in entry replacement is specified by software, write that value to

URC in the MMUCR register. If URC is greater than URB at this time, the value should be

changed to an appropriate value after issuing an LDTLB instruction.

5. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the

UTLB.

6. Finally, execute the exception handling return instruction (RTE), terminate the exception

handling routine, and return control to the normal flow. The RTE instruction should be issued

at least one instruction after the LDTLB instruction.

3.7 Memory-Mapped TLB Configuration

To enable the ITLB and UTLB to be managed by software, their contents can be read and written

by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if

access is made from a program in another area. A branch to an area other than the P2 area should

be made at least 8 instructions after this MOV instruction. The ITLB and UTLB are allocated to

the P4 area in physical memory space. VPN, V, and ASID in the ITLB can be accessed as an

address array, PPN, V, SZ, PR, C, and SH as data array 1, and SA and TC as data array 2. VPN,

D, V, and ASID in the UTLB can be accessed as an address array, PPN, V, SZ, PR, C, D, WT, and

SH as data array 1, and SA and TC as data array 2. V and D can be accessed from both the address

array side and the data array side. Only longword access is possible. Instruction fetches cannot be

performed in these areas. For reserved bits, a write value of 0 should be specified; their read value

is undefined.

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3.7.1 ITLB Address Array

The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An

address array access requires a 32-bit address field specification (when reading or writing) and a

32-bit data field specification (when writing). Information for selecting the entry to be accessed is

specified in the address field, and VPN, V, and ASID to be written to the address array are

specified in the data field.

In the address field, bits [31:24] have the value H'F2 indicating the ITLB address array, and the

entry is selected by bits [9:8]. As longword access is used, 0 should be specified for address field

bits [1:0].

In the data field, VPN is indicated by bits [31:10], V by bit [8], and ASID by bits [7:0].

The following two kinds of operation can be used on the ITLB address array:

1. ITLB address array read

VPN, V, and ASID are read into the data field from the ITLB entry corresponding to the entry

set in the address field.

2. ITLB address array write

VPN, V, and ASID specified in the data field are written to the ITLB entry corresponding to

the entry set in the address field.

Address field

31 23 0

11110010 E

Data field

31 10 9 0

VPN

Legend:

VPN:

Virtual page number

Validity bit

Entry

987

ASID

ASID:

Address space identifier

Reserved bits (0 write value, undefined

read value)

Figure 3.13 Memory-Mapped ITLB Address Array

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3.7.2 ITLB Data Array 1

ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data

array access requires a 32-bit address field specification (when reading or writing) and a 32-bit

data field specification (when writing). Information for selecting the entry to be accessed is

specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are

specified in the data field.

In the address field, bits [31:23] have the value H'F30 indicating ITLB data array 1, and the entry

is selected by bits [9:8].

In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bit

[6], C by bit [3], and SH by bit [1].

The following two kinds of operation can be used on ITLB data array 1:

1. ITLB data array 1 read

PPN, V, SZ, PR, C, and SH are read into the data field from the ITLB entry corresponding to

the entry set in the address field.

2. ITLB data array 1 write

PPN, V, SZ, PR, C, and SH specified in the data field are written to the ITLB entry

corresponding to the entry set in the address field.

Address field

31 23 0

111100 011 E

Data field

Legend:

PPN:

SZ:

Physical page number

Validity bit

Entry

Page size bits

987

PR:

SH:

Protection key data

Cacheability bit

Share status bit

Reserved bits (0 write value, undefined read value)

31 210

1098730 29 28 4 365

SZ SHPR

CPPN

Figure 3.14 Memory-Mapped ITLB Data Array 1

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3.7.3 ITLB Data Array 2

ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data

array access requires a 32-bit address field specification (when reading or writing) and a 32-bit

data field specification (when writing). Information for selecting the entry to be accessed is

specified in the address field, and SA and TC to be written to data array 2 are specified in the data

field.

In the address field, bits [31:23] have the value H'F38 indicating ITLB data array 2, and the entry

is selected by bits [9:8].

In the data field, SA is indicated by bits [2:0], and TC by bit [3].

The following two kinds of operation can be used on ITLB data array 2:

1. ITLB data array 2 read

SA and TC are read into the data field from the ITLB entry corresponding to the entry set in

the address field.

2. ITLB data array 2 write

SA and TC specified in the data field are written to the ITLB entry corresponding to the entry

set in the address field.

Address field

31 23 0

11110011

Data field

Legend:

TC:

Timing control bit

Entry

SA:

Space attribute bits

Reserved bits (0 write value, undefined read value)

Figure 3.15 Memory-Mapped ITLB Data Array 2

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3.7.4 UTLB Address Array

The UTLB address array is allocated to addresses H'F600 0000 to H'F6FF FFFF in the P4 area. An

address array access requires a 32-bit address field specification (when reading or writing) and a

32-bit data field specification (when writing). Information for selecting the entry to be accessed is

specified in the address field, and VPN, D, V, and ASID to be written to the address array are

specified in the data field.

In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array, and the

entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether

or not address comparison is performed when writing to the UTLB address array.

In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASID by bits

[7:0].

The following three kinds of operation can be used on the UTLB address array:

1. UTLB address array read

VPN, D, V, and ASID are read into the data field from the UTLB entry corresponding to the

entry set in the address field. In a read, associative operation is not performed regardless of

whether the association bit specified in the address field is 1 or 0.

2. UTLB address array write (non-associative)

VPN, D, V, and ASID specified in the data field are written to the UTLB entry corresponding

to the entry set in the address field. The A bit in the address field should be cleared to 0.

3. UTLB address array write (associative)

When a write is performed with the A bit in the address field set to 1, comparison of all the

UTLB entries is carried out using the VPN specified in the data field and PTEH.ASID. The

usual address comparison rules are followed, but if a UTLB miss occurs, the result is no

operation, and an exception is not generated. If the comparison identifies a UTLB entry

corresponding to the VPN specified in the data field, D and V specified in the data field are

written to that entry. If there is more than one matching entry, a data TLB multiple hit

exception results. This associative operation is simultaneously carried out on the ITLB, and if a

matching entry is found in the ITLB, V is written to that entry. Even if the UTLB comparison

results in no operation, a write to the ITLB side only is performed as long as there is an ITLB

match. If there is a match in both the UTLB and ITLB, the UTLB information is also written to

the ITLB.

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Address field

Data field

Legend:

VPN:

Virtual page number

Validity bit

Entry

Dirty bit

ASID:

Address space identifier

Association bit

Reserved bits (0 write value, undefined read value)

31 0

98730 29 28

ASID

VPN

31 23 2 1 0

11110110 E

24 14 13

Figure 3.16 Memory-Mapped UTLB Address Array

3.7.5 UTLB Data Array 1

UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data

array access requires a 32-bit address field specification (when reading or writing) and a 32-bit

data field specification (when writing). Information for selecting the entry to be accessed is

specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data

array are specified in the data field.

In the address field, bits [31:23] have the value H'F70 indicating UTLB data array 1, and the entry

is selected by bits [13:8].

In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bits

[6:5], C by bit [3], D by bit [2], SH by bit [1], and WT by bit [0].

The following two kinds of operation can be used on UTLB data array 1:

1. UTLB data array 1 read

PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry

corresponding to the entry set in the address field.

2. UTLB data array 1 write

PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry

corresponding to the entry set in the address field.

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Address field

Data field

Legend:

PPN:

SZ:

Physical page number

Validity bit

Entry

Page size bits

Dirty bit

PR:

SH:

WT:

Protection key data

Cacheability bit

Share status bit

Write-through bit

Reserved bits

(0 write value, undefined read value)

31 210

10 9 8 730 29 28 4 365

PR CPPN

31 23 0

11110111

24 8 714 13

SZ SH WT

Figure 3.17 Memory-Mapped UTLB Data Array 1

3.7.6 UTLB Data Array 2

UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data

array access requires a 32-bit address field specification (when reading or writing) and a 32-bit

data field specification (when writing). Information for selecting the entry to be accessed is

specified in the address field, and SA and TC to be written to data array 2 are specified in the data

field.

In the address field, bits [31:23] have the value H'F78 indicating UTLB data array 2, and the entry

is selected by bits [13:8].

In the data field, TC is indicated by bit [3], and SA by bits [2:0].

The following two kinds of operation can be used on UTLB data array 2:

1. UTLB data array 2 read

SA and TC are read into the data field from the UTLB entry corresponding to the entry set in

the address field.

2. UTLB data array 2 write

SA and TC specified in the data field are written to the UTLB entry corresponding to the entry

set in the address field.

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Address field

31 23 0

11110111

Data field

24 8

3 2

Legend:

TC:

Timing control bit

Entry

SA:

Space attribute bits

Reserved bits (0 write value, undefined read value)

Figure 3.18 Memory-Mapped UTLB Data Array 2

3.8 Usage Notes

1. Address Space Identifier (ASID) in Single Virtual Memory Mode

Refer to the note in 3.3.7, Address Space Identifier (ASID).

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Section 4 Caches

4.1 Overview

4.1.1 Features

An SH7750 or SH7750S has an on-chip 8-Kbyte instruction cache (IC) for instructions and 16-

Kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 Kbytes) may

alternatively be used as on-chip RAM. The features of this cache are summarized in table 4.1

The SH7750R has an on-chip 16-Kbyte instruction cache (IC) for instructions and 32-Kbyte

operand cache (OC) for data. Half of the memory of the operand cache (16 Kbytes) may

alternatively be used as on-chip RAM. When the EMODE bit of the CCR register is 0, the

SH7750R's cache is set to operate in the SH7750/SH7750S-compatible mode and behaves as

shown in table 4.1. The features of the cache when the EMODE bit in the CCR register is 1 are

given in table 4.2. The EMODE bit is initialized to 0 after a power-on reset or manual reset.

For high-speed writing to external memories, this LSI supports 32 bytes × 2 of store queues (SQ).

Table 4.3 lists the features of these SQs.

Table 4.1 Cache Features (SH7750, SH7750S)

Item Instruction Cache Operand Cache

Capacity 8-Kbyte cache 16-Kbyte cache or 8-Kbyte cache +

8-Kbyte RAM

Type Direct mapping Direct mapping

Line size 32 bytes 32 bytes

Entries 256 512

Write method Copy-back/write-through selectable

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Table 4.2 Cache Features (SH7750R)

Item Instruction Cache Operand Cache

Capacity 16-Kbyte cache 32-Kbyte cache or 16-Kbyte cache +

16-Kbyte RAM

Type 2-way set-associative 2-way set-associative

Line size 32 bytes 32 bytes

Entries 256 entries/way 512 entries/way

Write method Copy-back/write-through selectable

Replacement method LRU (least-recently-used) algorithm LRU algorithm

Table 4.3 Features of Store Queues

Item Store Queues

Capacity 2 × 32 bytes

Addresses H'E000 0000 to H'E3FF FFFF

Write Store instruction (1-cycle write)

Write-back Prefetch instruction (PREF instruction)

Access right MMU off: according to MMUCR.SQMD

MMU on: according to individual page PR

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4.1.2 Register Configuration

Table 4.4 shows the cache control registers.

Table 4.4 Cache Control Registers

Name

Abbreviation

R/W

Initial

Value*1

Address*2

Area 7

Address*2

Access

Size

Cache control

CCR R/W H'0000 0000 H'FF00 001C H'1F00 001C 32

Queue address

control register 0

QACR0 R/W Undefined H'FF00 0038 H'1F00 0038 32

Queue address

control register 1

QACR1 R/W Undefined H'FF00 003C H'1F00 003C 32

Notes: 1. The initial value is the value after a power-on or manual reset.

2. This is the address when using the virtual/physical address space P4 area. The area 7

address is the address used when making an access from physical address space area

7 using the TLB.

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4.2 Register Descriptions

There are three cache and store queue related control registers, as shown in figure 4.1.

CCR

31 30 141615 12111098765432

ICI ICE ORAOIX OCI

AREA

WT OCE

IIXEMODE*

QACR0

31 54 210

AREA

QACR1

31 54 210

Notes: indicates reserved bits: 0 must be specified in a write; the read value is 0.

* SH7750R only

Figure 4.1 Cache and Store Queue Control Registers

(1) Cache Control Register (CCR): CCR contains the following bits:

EMODE: Double-sized cache mode (Only for SH7750R; reserved bit for SH7750 and SH7750S)

IIX: IC index enable

ICI: IC invalidation

ICE: IC enable

OIX: OC index enable

ORA: OC RAM enable

OCI: OC invalidation

CB: Copy-back enable

WT: Write-through enable

OCE: OC enable

Longword access to CCR can be performed from H'FF00 001C in the P4 area and H'1F00 001C in

area 7. The CCR bits are used for the cache settings described below. Consequently, CCR

modifications must only be made by a program in the non-cached P2 area. After CCR is updated,

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an instruction that performs data access to the P0, P1, P3, or U0 area should be located at least

four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or

U0 area should be located at least eight instructions after the CCR update instruction.

• EMODE: Double-sized cache mode bit

In the SH7750R, this bit indicates whether the double-sized cache mode is used or not.

This bit is reserved in the SH7750 and SH7750S. The EMODE bit must not be written to while

the cache is being used.

0: SH7750/SH7750S-compatible mode*1 (initial value)

1: Double-sized cache mode

• IIX: IC index enable bit

0: Effective address bits [12:5] used for IC entry selection

1: Effective address bits [25] and [11:5] used for IC entry selection

• ICI: IC invalidation bit

When 1 is written to this bit, the V bits of all IC entries are cleared to 0. This bit always returns

0 when read.

• ICE: IC enable bit

Indicates whether or not the IC is to be used. When address translation is performed, the IC

cannot be used unless the C bit in the page management information is also 1.

0: IC not used

1: IC used

• OIX: OC index enable bit*2

0: Effective address bits [13:5] used for OC entry selection

1: Effective address bits [25] and [12:5] used for OC entry selection

• ORA: OC RAM enable bit*3

When the OC is enabled (OCE = 1), the ORA bit specifies whether the half of the OC are to be

used as RAM. When the OC is not enabled (OCE = 0), the ORA bit should be cleared to 0.

0: Normal mode (the entire OC is used as a cache)

1: RAM mode (half of the OC is used as a cache and the other half is used as RAM)

• OCI: OC invalidation bit

When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always

returns 0 when read.

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• CB: Copy-back bit

Indicates the P1 area cache write mode.

0: Write-through mode

1: Copy-back mode

• WT: Write-through bit

Indicates the P0, U0, and P3 area cache write mode. When address translation is performed,

the value of the WT bit in the page management information has priority.

0: Copy-back mode

1: Write-through mode

• OCE: OC enable bit

Indicates whether or not the OC is to be used. When address translation is performed, the OC

cannot be used unless the C bit in the page management information is also 1.

0: OC not used

1: OC used

Notes: 1. No compatibility for RAM mode in OC index mode and address assignment in RAM

mode.

2. When the ORA bit is 1 in the SH7750R, the OIX bit should be cleared to 0.

3. When the OIX bit in the SH7750R is 1, the ORA bit should be cleared to 0.

(2) Queue Address Control Register 0 (QACR0): Longword access to QACR0 can be

performed from H'FF00 0038 in the P4 area and H'1F00 0038 in area 7. QACR0 specifies the area

onto which store queue 0 (SQ0) is mapped when the MMU is off.

(3) Queue Address Control Register 1 (QACR1): Longword access to QACR1 can be

performed from H'FF00 003C in the P4 area and H'1F00 003C in area 7. QACR1 specifies the

area onto which store queue 1 (SQ1) is mapped when the MMU is off.

4.3 Operand Cache (OC)

4.3.1 Configuration

The operand cache of the SH7750 or SH7750S is of the direct-mapping type and consists of 512

cache lines, each composed of a 19-bit tag, V bit, U bit, and 32-byte data. The SH7750R's operand

cache is 2-way set-associative. Each way consists of 512 cache lines.

Figure 4.2 shows the configuration of the operand cache for the SH7750 and SH7750S.

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Figure 4.3 shows the configuration of the operand cache for the SH7750R.

31 26 25 5 4 3 2 1

LW0

32 bits

LW1

32 bits

LW2

32 bits

LW3

32 bits

LW4

32 bits

LW5

32 bits

LW6

32 bits

LW7

32 bits

MMU

RAM area

determination

ORA

OIX [13] [12]

[11:5]

511 19 bits 1 bit 1 bit

TagUV

Address array Data array

Entry selection

Longword (LW) selection

Effective address

Write data

Read data

Hit signal

Compare

13 12 11 10 9 0

Figure 4.2 Configuration of Operand Cache (SH7750, SH7750S)

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31 26 25 5 4 2

LW0

32 bits

LW1

32 bits

LW2

32 bits

LW3

32 bits

LW4

32 bits

LW5

32 bits

LW6

32 bits

LW7

32 bits

1 bit

MMU

RAM area

judgment

OIX

ORA [13]

[12:5]

511 19 bits 1 bit 1 bit

Tag address U V

Address array

(way 0, way 1) Data array (way 0, way 1) LRU

Entry

selection

Longword (LW)

selection

Effective address

Write data

Read data

Hit signal

Compare

way 0

Compare

way 1

13 12 10 0

Figure 4.3 Configuration of Operand Cache (SH7750R)

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• Tag

Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached.

The tag is not initialized by a power-on or manual reset.

• V bit (validity bit)

Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is

valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.

• U bit (dirty bit)

The U bit is set to 1 if data is written to the cache line while the cache is being used in copy-

back mode. That is, the U bit indicates a mismatch between the data in the cache line and the

data in external memory. The U bit is never set to 1 while the cache is being used in write-

through mode, unless it is modified by accessing the memory-mapped cache (see section 4.5,

Memory-Mapped Cache Configuration (SH7750, SH7750S)). The U bit is initialized to 0 by a

power-on reset, but retains its value in a manual reset.

• Data field

The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized

by a power-on or manual reset.

• LRU (SH7750R only)

In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each

entry address. When an entry is registered, the LRU bit indicates which of the 2 ways it is to be

registered in. The LRU bit is a single bit of each entry, and its value is controlled by hardware.

The LRU (least-recently-used) algorithm is used for way selection, and selects the less recently

accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a manual reset.

The LRU bits cannot be read or written by software.

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4.3.2 Read Operation

When the OC is enabled (CCR.OCE = 1) and data is read by means of an effective address from a

cacheable area, the cache operates as follows:

1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5].

2. The tag is compared with bits [28:10] of the address resulting from effective address

translation by the MMU:

• If the tag matches and the V bit is 1 → (3a)

• If the tag matches and the V bit is 0 → (3b)

• If the tag does not match and the V bit is 0 → (3b)

• If the tag does not match, the V bit is 1, and the U bit is 0 → (3b)

• If the tag does not match, the V bit is 1, and the U bit is 1

→ (3c)

3a. Cache hit

The data indexed by effective address bits [4:0] is read from the data field of the cache line

indexed by effective address bits [13:5] in accordance with the access size

(quadword/longword/word/byte).

3b. Cache miss (no write-back)

Data is read into the cache line from the external memory space corresponding to the effective

address. Data reading is performed, using the wraparound method, in order from the longword

data corresponding to the effective address, and when the corresponding data arrives in the

cache, the read data is returned to the CPU. While the remaining one cache line of data is being

read, the CPU can execute the next processing. When reading of one line of data is completed,

the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V

bit.

3c. Cache miss (with write-back)

The tag and data field of the cache line indexed by effective address bits [13:5] are saved in the

write-back buffer. Then data is read into the cache line from the external memory space

corresponding to the effective address. Data reading is performed, using the wraparound

method, in order from the longword data corresponding to the effective address, and when the

corresponding data arrives in the cache, the read data is returned to the CPU. While the

remaining one cache line of data is being read, the CPU can execute the next processing. When

reading of one line of data is completed, the tag corresponding to the effective address is

recorded in the cache, 1 is written to the V bit, and 0 to the U bit. The data in the write-back

buffer is then written back to external memory.

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4.3.3 Write Operation

When the OC is enabled (CCR.OCE = 1) and data is written by means of an effective address to a

cacheable area, the cache operates as follows:

1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5].

2. The tag is compared with bits [28:10] of the address resulting from effective address

translation by the MMU:

Copy-back Write-through

• If the tag matches and the V bit is 1 → (3a) → (3b)

• If the tag matches and the V bit is 0 → (3c) → (3d)

• If the tag does not match and the V bit is 0 → (3c) → (3d)

• If the tag does not match, the V bit is 1, and the U bit is 0 → (3c) → (3d)

• If the tag does not match, the V bit is 1, and the U bit is 1

→ (3e) → (3d)

3a. Cache hit (copy-back)

A data write in accordance with the access size (quadword/longword/word/byte) is performed

for the data indexed by bits [4:0] of the effective address of the data field of the cache line

indexed by effective address bits [13:5]. Then 1 is set in the U bit.

3b. Cache hit (write-through)

A data write in accordance with the access size (quadword/longword/word/byte) is performed

for the data indexed by bits [4:0] of the effective address of the data field of the cache line

indexed by effective address bits [13:5]. A write is also performed to the corresponding

external memory using the specified access size.

3c. Cache miss (no copy-back/write-back)

A data write in accordance with the access size (quadword/longword/word/byte) is performed

for the data indexed by bits [4:0] of the effective address of the data field of the cache line

indexed by effective address bits [13:5]. Then, data is read into the cache line from the external

memory space corresponding to the effective address. Data reading is performed, using the

wraparound method, in order from the longword data corresponding to the effective address,

and one cache line of data is read excluding the written data. During this time, the CPU can

execute the next processing. When reading of one line of data is completed, the tag

corresponding to the effective address is recorded in the cache, and 1 is written to the V bit and

U bit.

3d. Cache miss (write-through)

A write of the specified access size is performed to the external memory corresponding to the

effective address. In this case, a write to cache is not performed.

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3e. Cache miss (with copy-back/write-back)

The tag and data field of the cache line indexed by effective address bits [13:5] are first saved

in the write-back buffer, and then a data write in accordance with the access size

(quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective

address of the data field of the cache line indexed by effective address bits [13:5]. Then, data is

read into the cache line from the external memory space corresponding to the effective

address. Data reading is performed, using the wraparound method, in order from the longword

data corresponding to the effective address, and one cache line of data is read excluding the

written data. During this time, the CPU can execute the next processing. When reading of one

line of data is completed, the tag corresponding to the effective address is recorded in the

cache, and 1 is written to the V bit and U bit. The data in the write-back buffer is then written

back to external memory.

4.3.4 Write-Back Buffer

In order to give priority to data reads to the cache and improve performance, this LSI has a write-

back buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache

entry into external memory as the result of a cache miss. The write-back buffer contains one cache

line of data and the physical address of the purge destination.

LW7Physical address bits [28:5] LW6LW5LW4LW3LW2LW1LW0

Figure 4.4 Configuration of Write-Back Buffer

4.3.5 Write-Through Buffer

This LSI has a 64-bit buffer for holding write data when writing data in write-through mode or

writing to a non-cacheable area. This allows the CPU to proceed to the next operation as soon as

the write to the write-through buffer is completed, without waiting for completion of the write to

external memory.

Physical address bits [28:0] LW1LW0

Figure 4.5 Configuration of Write-Through Buffer

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4.3.6 RAM Mode

Setting CCR.ORA to 1 enables half of the operand cache to be used as RAM. In the SH7750 or

SH7750S, the 8 Kbytes of operand cache entries 128 to 255 and 384 to 511 are used as RAM. In

the SH7750/SH7750S-compatible mode of the SH7750R, the 8-Kbyte area otherwise used for OC

entries 256 to 511 is designated as a RAM area. In the double-sized cache mode of the SH7750R,

a total of 16 Kbytes, comprising entries 256 to 511 in both of the ways of the operand cache, is

designated as a RAM area. Other entries can still be used as cache. RAM can be accessed using

addresses H'7C00 0000 to H'7FFF FFFF. Byte-, word-, longword-, and quadword-size data reads

and writes can be performed in the operand cache RAM area. Instruction fetches cannot be

performed in this area. With the SH7750R, the OC index mode is not available in RAM mode.

An example of RAM use in the SH7750 or SH7750S is shown below. Here, the 4 Kbytes

comprising OC entries 128 to 255 are designated as RAM area 1, and the 4 Kbytes comprising OC

entries 384 to 511 as RAM area 2.

• When OC index mode is off (CCR.OIX = 0)

H'7C00 0000 to H'7C00 0FFF (4 KB): Corresponds to RAM area 1

H'7C00 1000 to H'7C00 1FFF (4 KB): Corresponds to RAM area 1

H'7C00 2000 to H'7C00 2FFF (4 KB): Corresponds to RAM area 2

H'7C00 3000 to H'7C00 3FFF (4 KB): Corresponds to RAM area 2

H'7C00 4000 to H'7C00 4FFF (4 KB): Corresponds to RAM area 1

: : :

RAM areas 1 and 2 in the SH7750 or SH7750S then repeat every 8 Kbytes up to H'7FFF

FFFF.

Thus, to secure a continuous 8-Kbyte RAM area, the area from H'7C00 1000 to H'7C00 2FFF

can be used, for example.

• When OC index mode is on (CCR.OIX = 1)

H'7C00 0000 to H'7C00 0FFF (4 KB): Corresponds to RAM area 1

H'7C00 1000 to H'7C00 1FFF (4 KB): Corresponds to RAM area 1

H'7C00 2000 to H'7C00 2FFF (4 KB): Corresponds to RAM area 1

: : :

H'7DFF F000 to H'7DFF FFFF (4 KB): Corresponds to RAM area 1

H'7E00 0000 to H'7E00 0FFF (4 KB): Corresponds to RAM area 2

H'7E00 1000 to H'7E00 1FFF (4 KB): Corresponds to RAM area 2

: : :

H'7FFF F000 to H'7FFF FFFF (4 KB): Corresponds to RAM area 2

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As the distinction between RAM areas 1 and 2 is indicated by address bit [25], the area from

H'7DFF F000 to H'7E00 0FFF should be used to secure a continuous 8-Kbyte RAM area.

Examples of RAM usage with the SH7750R is shown below.

• In SH7750/SH7750S-compatible mode (CCR.EMODE = 0)

H'7C00 0000 to H'7C00 1FFF (8 KB): RAM area (entries 256 to 511)

H'7C00 2000 to H'7C00 3FFF (8 KB): RAM area (entries 256 to 511)

: : :

In the same pattern, shadows of the RAM area are created in 8-Kbyte blocks until H'7FFF

FFFF is reached.

• In double-sized cache mode (CCR.EMODE = 1)

In this mode, the 8 Kbytes comprising entries 256 to 511 of OC way 0 are designated as RAM

area 1 and the 8-Kbytes comprising entries 256 to 511 of OC way 1 are designated as RAM

area 2.

H'7C00 0000 to H'7C00 1FFF (8 KB): Corresponds to RAM area 1

H'7C00 2000 to H'7C00 3FFF (8 KB): Corresponds to RAM area 2

H'7C00 4000 to H'7C00 5FFF (8 KB): Corresponds to RAM area 1

H'7C00 6000 to H'7C00 7FFF (8 KB): Corresponds to RAM area 2

: : :

In the same pattern, shadows of the RAM area are created in 16-Kbyte blocks until H'7FFF

FFFF is reached.

4.3.7 OC Index Mode

Setting CCR.OIX to 1 enables OC indexing to be performed using bit [25] of the effective

address. This is called OC index mode. In normal mode, with CCR.OIX cleared to 0, OC indexing

is performed using bits [13:5] of the effective address. Using index mode allows the OC to be

handled as two areas by means of effective address bit [25], providing efficient use of the cache.

The SH7750R cannot be used in RAM mode when OC index mode is selected.

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4.3.8 Coherency between Cache and External Memory

Coherency between cache and external memory should be assured by software. In this LSI, the

following four new instructions are supported for cache operations. Details of these instructions

are given in the Programming Manual.

Invalidate instruction: OCBI @Rn Cache invalidation (no write-back)

Purge instruction: OCBP @Rn Cache invalidation (with write-back)

Write-back instruction: OCBWB @Rn Cache write-back

Allocate instruction: MOVCA.L R0,@Rn Cache allocation

4.3.9 Prefetch Operation

This LSI supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a

cache miss. If it is known that a cache miss will result from a read or write operation, it is possible

to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss

due to the read or write operation, and so improve software performance. If a prefetch instruction

is executed for data already held in the cache, or if the prefetch address results in a UTLB miss or

a protection violation, the result is no operation, and an exception is not generated. Details of the

prefetch instruction are given in the Programming Manual.

Prefetch instruction: PREF @Rn

4.3.10 Notes on Using Cache Enhanced Mode (SH7750R Only)

When cache enhanced mode (CCR.EMODE = 1) is specified and OC RAM mode (CCR.ORA =

1) is selected, in which half of the operand cache is used as internal RAM, internal RAM data may

be updated incorrectly.

Conditions Under which Problem Occurs: Incorrect data may be written to RAM when the

following four conditions are satisfied.

Condition 1: Cache enhanced mode (CCR.EMODE = 1) is specified.

Condition 2: The RAM mode (CCR.ORA = 1) in which half of the operand cache is used as

internal RAM is specified.

Condition 3: An exception or an interrupt occurs.

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Note: This includes a break triggered by a debugging tool swapping an instruction (a break

occurring when a TRAPA instruction or undefined instruction code H'FFFD is swapped

for an instruction).

Condition 4: A store instruction (MOV, FMOV, AND.B, OR, B, XOR.B, MOVCA.L, STC.L, or

STS.L) that accesses internal RAM (H'7C000000 to H'7FFFFFFF) exists within four

instructions after the instruction associated with the exception or interrupt described

in condition 3. This includes cases where the store instruction that accesses internal

RAM itself generates an exception.

Description: When the problem occurs, 8 bytes of incorrect data is written to the 8-byte boundary

that includes an address that differs by H'2000 from the address accessed by the store instruction

that accesses internal RAM mentioned in condition 4. For example, when a long word is stored at

address H'7C000204, the 8 bytes of data in the internal RAM mapped to addresses H'7C002200 to

H'7C002207 becomes corrupted.

Examples

Example 1 A store instruction accessing internal RAM occurs within four instructions after an

instruction generating a TLB miss exception.

MOV.L #H'0C400000, R0 R0 is an address causing a TLB miss.

MOV.L #H'7C000204, R1 R1 is an address mapped to internal RAM.

MOV.L @R0, R2 TLB miss exception occurs.

NOP 1st word

NOP 2nd word

NOP 3rd word

MOV.L R3, @R1 Store instruction accessing internal RAM

Example 2 A store instruction accessing internal RAM occurs within four instructions after an

instruction causing an interrupt to be accepted.

MOV.L #H'7C002000, R1 R1 is an address mapped to internal RAM.

MOV.L #H'12345678, R0 An interrupt is accepted after this instruction.

NOP 1st word

NOP 2nd word

NOP 3rd word

MOV.L R0, @R1 Store instruction accessing internal RAM

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Example 3 A debugging tool generates a break to swap an instruction.

Original Instruction String After Instruction Swap Break

MOV.L #H'C000000, R0 MOV.L #H'7C000000, R0 Contains address corresponding to R0.

ADD R0, R0 TRAPA #H'01 R0 address is not a problem in original

instruction string.

MOV.L R1, @R0 MOV.L R1, @R0 Internal RAM is accessed by a store

operation because ADD is not executed.

The store is cancelled, but 2LW starting

at H'7C002000 is corrupted.

Workarounds: When RAM mode is specified in cache enhanced mode, either of the following

workarounds can be used to avoid the problem.

Workaround 1:

Use only 8 Kbytes of the 16-Kbyte internal RAM area. In this case, RAM areas for which

address bits [12:0] are identical and only bit [13] differs must not be used. For example,

the 8-Kbyte RAM area from H'7C000000 to H'7C001FFF or from H'7C001000 to

H'7C002FFF may be used.

Note: When a break is used to swap instructions by a debugging tool, etc., a memory access

address may be changed when an instruction following the instruction generating the

break is swapped for another instruction, causing the unused 8-Kbyte RAM area to be

accessed. This will result in the problem described above. However, this phenomenon

only occurs during debugging when a break is used to swap instructions. Using a break

with no instruction swapping will not cause the problem.

Workaround 2:

Ensure that there are no instructions that generate an interrupt or exception within four

instructions after an instruction that accesses internal RAM. For example, the internal

RAM area can be used as a data table that is accessed only by load instructions, with

writes to the internal RAM area only being performed when the table is generated. It this

case, set SR.BL to 1 to disable interrupts while writing to the table. Also take measures to

ensure that no exceptions due to TLB misses, etc., occur while writing to the table.

Note: The problem still may occur when a break is used to swap instructions by a debugging

tool. This phenomenon only occurs during debugging when a break is used to swap

instructions. Using a break with no instruction swapping will not cause the problem.

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4.4 Instruction Cache (IC)

4.4.1 Configuration

The instruction cache of the SH7750 or SH7750S is of the direct-mapping type and consists of

256 cache lines, each composed of a 19-bit tag, V bit, and 32-byte data (16 instructions). The

SH7750R's instruction cache is 2-way set associative. Each way consists of 256 cache lines.

Figure 4.6 shows the configuration of the instruction cache for the SH7750 and SH7750S.

Figure 4.7 shows the configuration of the instruction cache for the SH7750R.

LW0

32 bits

LW1

32 bits

LW2

32 bits

LW3

32 bits

LW4

32 bits

LW5

32 bits

LW6

32 bits

LW7

32 bits

255 19 bits 1 bit

TagV

Address array

Longword (LW) selection

Data array

Read data

Hit signal

Compare

31 26 25 5 4 3 2 1

MMU

IIX [12]

[11:5]

Entry selection

Effective address

13 12 11 10 9 0

Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S)

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31 25 5 4 2

LW0

32 bits

LW1

32 bits

LW2

32 bits

LW3

32 bits

LW4

32 bits

LW5

32 bits

LW6

32 bits

LW7

32 bits

1 bit

MMU

IIX

[12]

[11:5]

255 19 bits 1 bit

Tag address V

Address array

(way 0, way1)

Longword (LW)

selection

LRU

Entry

selection

Data array (way 0, way 1)

Effective address

Read data

Hit signal

Compare

way 0

Compare

way 1

13 12 11 10 0

Figure 4.7 Configuration of Instruction Cache (SH7750R)

• Tag

Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is

not initialized by a power-on or manual reset.

• V bit (validity bit)

Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is

valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.

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• Data array

The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized

by a power-on or manual reset.

• LRU (SH7750R only)

In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each

entry address. When an entry is registered, the LRU bit indicates which of the 2 ways it is to be

registered in. The LRU bit is a single bit of each entry, and its usage is controlled by hardware.

The LRU (least-recently-used) algorithm is used for way selection, and selects the less recently

accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a manual reset.

The LRU bits cannot be read or written by software.

4.4.2 Read Operation

When the IC is enabled (CCR.ICE = 1) and instruction fetches are performed by means of an

effective address from a cacheable area, the instruction cache operates as follows:

1. The tag and V bit are read from the cache line indexed by effective address bits [12:5].

2. The tag is compared with bits [28:10] of the address resulting from effective address

translation by the MMU:

• If the tag matches and the V bit is 1 → (3a)

• If the tag matches and the V bit is 0 → (3b)

• If the tag does not match and the V bit is 0 → (3b)

• If the tag does not match and the V bit is 1 → (3b)

3a. Cache hit

The data indexed by effective address bits [4:2] is read as an instruction from the data field of

the cache line indexed by effective address bits [12:5].

3b. Cache miss

Data is read into the cache line from the external memory space corresponding to the effective

address. Data reading is performed, using the wraparound method, in order from the longword

data corresponding to the effective address, and when the corresponding data arrives in the

cache, the read data is returned to the CPU as an instruction. When reading of one line of data

is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is

written to the V bit.

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4.4.3 IC Index Mode

Setting CCR.IIX to 1 enables IC indexing to be performed using bit [25] of the effective address.

This is called IC index mode. In normal mode, with CCR.IIX cleared to 0, IC indexing is

performed using bits [12:5] of the effective address. Using index mode allows the IC to be handled

as two areas by means of effective address bit [25], providing efficient use of the cache.

4.5 Memory-Mapped Cache Configuration (SH7750, SH7750S)

To enable the IC and OC to be managed by software, their contents can be read and written by a

P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access

is made from a program in another area. In this case, a branch to the P0, U0, P1, or P3 area should

be made at least 8 instructions after this MOV instruction. The IC and OC are allocated to the P4

area in physical memory space. Only data accesses can be used on both the IC address array and

data array and the OC address array and data array, and accesses are always longword-size.

Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should

be specified; their read value is undefined.

4.5.1 IC Address Array

The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An

address array access requires a 32-bit address field specification (when reading or writing) and a

32-bit data field specification. The entry to be accessed is specified in the address field, and the

write tag and V bit are specified in the data field.

In the address field, bits [31:24] have the value H'F0 indicating the IC address array, and the entry

is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. The address array bit

[3] association bit (A bit) specifies whether or not association is performed when writing to the IC

address array. As only longword access is used, 0 should be specified for address field bits [1:0].

In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address

array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which

association is not performed. Data field bits [31:29] are used for the virtual address specification

only in the case of a write in which association is performed.

The following three kinds of operation can be used on the IC address array:

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1. IC address array read

The tag and V bit are read into the data field from the IC entry corresponding to the entry set in

the address field. In a read, associative operation is not performed regardless of whether the

association bit specified in the address field is 1 or 0.

2. IC address array write (non-associative)

The tag and V bit specified in the data field are written to the IC entry corresponding to the

entry set in the address field. The A bit in the address field should be cleared to 0.

3. IC address array write (associative)

When a write is performed with the A bit in the address field set to 1, the tag stored in the entry

specified in the address field is compared with the tag specified in the data field. If the MMU

is enabled at this time, comparison is performed after the virtual address specified by data field

bits [31:10] has been translated to a physical address using the ITLB. If the addresses match

and the V bit is 1, the V bit specified in the data field is written into the IC entry. In other

cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an

ITLB miss occurs during address translation, or the comparison shows a mismatch, an

interrupt is not generated, no operation is performed, and the write is not executed. If an

instruction TLB multiple hit exception occurs during address translation, processing switches

to the instruction TLB multiple hit exception handling routine.

Address field

31 23 12 543210

1 1 1 1 0 0 0 0 Entry A

Data field

31 10 9 1 0

Tag

Legend:

V: Validity bit

A: Association bit

: Reserved bits (0 write value, undefined read value)

24 13

Figure 4.8 Memory-Mapped IC Address Array

4.5.2 IC Data Array

The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data

array access requires a 32-bit address field specification (when reading or writing) and a 32-bit

data field specification. The entry to be accessed is specified in the address field, and the longword

data to be written is specified in the data field.

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In the address field, bits [31:24] have the value H'F1 indicating the IC data array, and the entry is

specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2]

are used for the longword data specification in the entry. As only longword access is used, 0

should be specified for address field bits [1:0].

The data field is used for the longword data specification.

The following two kinds of operation can be used on the IC data array:

1. IC data array read

Longword data is read into the data field from the data specified by the longword specification

bits in the address field in the IC entry corresponding to the entry set in the address field.

2. IC data array write

The longword data specified in the data field is written for the data specified by the longword

specification bits in the address field in the IC entry corresponding to the entry set in the

address field.

Address field

31 23 12 5 4 2 1 0

11110001

Entry

Data field

31 0

Longword data

Legend:

L: Longword specification bits

: Reserved bits (0 write value, undefined read value)

24 13

Figure 4.9 Memory-Mapped IC Data Array

4.5.3 OC Address Array

The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An

address array access requires a 32-bit address field specification (when reading or writing) and a

32-bit data field specification. The entry to be accessed is specified in the address field, and the

write tag, U bit, and V bit are specified in the data field.

In the address field, bits [31:24] have the value H'F4 indicating the OC address array, and the

entry is specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry

specification. The address array bit [3] association bit (A bit) specifies whether or not association

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is performed when writing to the OC address array. As only longword access is used, 0 should be

specified for address field bits [1:0].

In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0].

As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a

write in which association is not performed. Data field bits [31:29] are used for the virtual address

specification only in the case of a write in which association is performed.

The following three kinds of operation can be used on the OC address array:

1. OC address array read

The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the

entry set in the address field. In a read, associative operation is not performed regardless of

whether the association bit specified in the address field is 1 or 0.

2. OC address array write (non-associative)

The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to

the entry set in the address field. The A bit in the address field should be cleared to 0.

When a write is performed to a cache line for which the U bit and V bit are both 1, after write-

back of that cache line, the tag, U bit, and V bit specified in the data field are written.

3. OC address array write (associative)

When a write is performed with the A bit in the address field set to 1, the tag stored in the entry

specified in the address field is compared with the tag specified in the data field. If the MMU

is enabled at this time, comparison is performed after the virtual address specified by data field

bits [31:10] has been translated to a physical address using the UTLB. If the addresses match

and the V bit is 1, the U bit and V bit specified in the data field are written into the OC entry.

This operation is used to invalidate a specific OC entry. In other cases, no operation is

performed. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is

performed. If an UTLB miss occurs during address translation, or the comparison shows a

mismatch, an exception is not generated, no operation is performed, and the write is not

executed. If a data TLB multiple hit exception occurs during address translation, processing

switches to the data TLB multiple hit exception handling routine.

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Address field

31 23 543210

11110100

Entry

Data field

31 10 9 1 0

Tag

24 1314

Legend:

: Validity bit

U: Dirty bit

: Association bit

: Reserved bits (0 write value, undefined read value)

Figure 4.10 Memory-Mapped OC Address Array

4.5.4 OC Data Array

The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data

array access requires a 32-bit address field specification (when reading or writing) and a 32-bit

data field specification. The entry to be accessed is specified in the address field, and the longword

data to be written is specified in the data field.

In the address field, bits [31:24] have the value H'F5 indicating the OC data array, and the entry is

specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry specification.

Address field bits [4:2] are used for the longword data specification in the entry. As only longword

access is used, 0 should be specified for address field bits [1:0].

The data field is used for the longword data specification.

The following two kinds of operation can be used on the OC data array:

1. OC data array read

Longword data is read into the data field from the data specified by the longword specification

bits in the address field in the OC entry corresponding to the entry set in the address field.

2. OC data array write

The longword data specified in the data field is written for the data specified by the longword

specification bits in the address field in the OC entry corresponding the entry set in the address

field. This write does not set the U bit to 1 on the address array side.

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Address field

31 23 54 210

11110101

Entry

Data field

31 0

Longword data

24 1314

Legend:

: Longword specification bits

: Reserved bits (0 write value, undefined read value)

Figure 4.11 Memory-Mapped OC Data Array

4.6 Memory-Mapped Cache Configuration (SH7750R)

To enable the management of the IC and OC by software, a program running in the privileged

mode is allowed to access their contents.

The contents of IC can be read and written by using MOV instructions in a P2-area program

running in the privileged mode. Operation is not guaranteed for access from a program in some

other area. Any branching to other areas must take place at least 8 instructions after this MOV

instruction.

The contents of IC can be read and written by using MOV instructions in a P1- or P2-area program

running in the privileged mode. Operation is not guaranteed if access is attempted from a program

running in some other area. A branch to the P0, U0, or P3 area must be made at least 8 instructions

after this MOV instruction.

The IC and OC are allocated to the P4 area of the physical memory space. The address and data

arrays of both the IC and OC are only accessible by their data fields. Longword operations must be

used. Instruction fetches from these areas are not possible. For reserved bits, a write value of 0

should be specified; values read from such bits are undefined. Note that, in the SH7750/SH7750S-

compatible mode, the configuration of the SH7750R's memory-mapped cache is the same as that

of the SH7750 or SH7750S.

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4.6.1 IC Address Array

The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An

address array access requires a 32-bit address field specification (when reading or writing) and a

32-bit data field specification. The way and entry to be accessed is specified in the address field,

and the write tag and V bit are specified in the data field.

In the address field, bits [31:24] have the value H'F0 indicating the IC address array, the way is

specified by bit [13], and the entry by bits [12:5]. CCR.IIX has no effect on this entry

specification. The address array bit [3] association bit (A bit) specifies whether or not association

is performed when writing to the IC address array. As only longword access is used, 0 should be

specified for address field bits [1:0].

In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address

array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which

association is not performed. Data field bits [31:29] are used for the virtual address specification

only in the case of a write in which association is performed.

The following three kinds of operation can be used on the IC address array:

1. IC address array read

The tag and V bit are read into the data field from the IC entry corresponding to the way and

the entry set in the address field. In a read, associative operation is not performed regardless of

whether the association bit specified in the address field is 1 or 0.

2. IC address array write (non-associative)

The tag and V bit specified in the data field are written to the IC entry corresponding to the

way and the entry set in the address field. The A bit in the address field should be cleared to 0.

3. IC address array write (associative)

When a write is performed with the A bit in the address field set to 1, the tag for each of the

ways stored in the entry specified in the address field is compared with the tag specified in the

data field. The way number set by bit [13] is not used. If the MMU is enabled at this time,

comparison is performed after the virtual address specified by data field bits [31:10] has been

translated to a physical address using the ITLB. If the addresses match and the V bit for that

way is 1, the V bit specified in the data field is written into the IC entry. In other cases, no

operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB miss

occurs during address translation, or the comparison shows a mismatch, an interrupt is not

generated, no operation is performed, and the write is not executed. If an instruction TLB

multiple hit exception occurs during address translation, processing switches to the instruction

TLB multiple hit exception handling routine.

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Address field

31 23 12 543210

11110000 Entry

Way

Data field

31 10 9 1 0

Tag

Legend:

V: Validity bit

A: Association bit

: Reserved bits (0 write value, undefined read value

24 13

Figure 4.12 Memory-Mapped IC Address Array

4.6.2 IC Data Array

The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data

array access requires a 32-bit address field specification (when reading or writing) and a 32-bit

data field specification. The way and entry to be accessed is specified in the address field, and the

longword data to be written is specified in the data field.

In the address field, bits [31:24] have the value H'F1 indicating the IC data array, the way is

specified by bit [13], and the entry by bits [12:5]. CCR.IIX has no effect on this entry

specification. Address field bits [4:2] are used for the longword data specification in the entry. As

only longword access is used, 0 should be specified for address field bits [1:0].

The data field is used for the longword data specification.

The following two kinds of operation can be used on the IC data array:

1. IC data array read

Longword data is read into the data field from the data specified by the longword specification

bits in the address field in the IC entry corresponding to the way and entry set in the address

field.

2. IC data array write

The longword data specified in the data field is written for the data specified by the longword

specification bits in the address field in the IC entry corresponding to the way and entry set in

the address field.

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Address field

31 23 12 5 4 2 1 0

11110001

Entry

Data field

31 0

Longword data

Legend:

L: Longword specification bits

: Reserved bits (0 write value, undefined read value)

24 13

Way

Figure 4.13 Memory-Mapped IC Data Array

4.6.3 OC Address Array

The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An

address array access requires a 32-bit address field specification (when reading or writing) and a

32-bit data field specification. The way and entry to be accessed is specified in the address field,

and the write tag, U bit, and V bit are specified in the data field.

In the address field, bits [31:24] have the value H'F4 indicating the OC address array, the way is

specified by bit [14], and the entry by bits [13:5]. CCR.OIX has no effect on this entry

specification. In RAM mode (CCR.ORA = 1), the OC's address arrays are only accessible in the

memory-mapped cache area, and bit [13] is used to specify the way. For details about address

mapping, see section 4.6.5, Summary of the Memory-Mapping of the OC. The address array bit

[3] association bit (A bit) specifies whether or not association is performed when writing to the

OC address array. As only longword access is used, 0 should be specified for address field bits

[1:0].

In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0].

As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a

write in which association is not performed. Data field bits [31:29] are used for the virtual address

specification only in the case of a write in which association is performed.

The following three kinds of operation can be used on the OC address array:

1. OC address array read

The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the

way and the entry set in the address field. In a read, associative operation is not performed

regardless of whether the association bit specified in the address field is 1 or 0.

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2. OC address array write (non-associative)

The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to

the way and the entry set in the address field. The A bit in the address field should be cleared

to 0.

When a write is performed to a cache line for which the U bit and V bit are both 1, after write-

back of that cache line, the tag, U bit, and V bit specified in the data field are written.

3. OC address array write (associative)

When a write is performed with the A bit in the address field set to 1, the tag for each of the

ways stored in the entry specified in the address field is compared with the tag specified in the

data field. The way number set by bit [14] is not used. If the MMU is enabled at this time,

comparison is performed after the virtual address specified by data field bits [31:10] has been

translated to a physical address using the UTLB. If the addresses match and the V bit for that

way is 1, the U bit and V bit specified in the data field are written into the OC entry. This

operation is used to invalidate a specific OC entry. In other cases, no operation is performed. If

the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If

an UTLB miss occurs during address translation, or the comparison shows a mismatch, an

exception is not generated, no operation is performed, and the write is not executed. If a data

TLB multiple hit exception occurs during address translation, processing switches to the data

TLB multiple hit exception handling routine.

Address field

31 23 543210

11110100

Entry

Data field

31 10 9 1 0

Tag

24 131415

Legend:

: Validity bit

U: Dirty bit

: Association bit

: Reserved bits (0 write value, undefined read value)

Way

Figure 4.14 Memory-Mapped OC Address Array

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4.6.4 OC Data Array

The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data

array access requires a 32-bit address field specification (when reading or writing) and a 32-bit

data field specification. The way and entry to be accessed is specified in the address field, and the

longword data to be written is specified in the data field.

In the address field, bits [31:24] have the value H'F5 indicating the OC data array, the way is

specified by bit [14], and the entry by bits [13:5]. CCR.OIX has no effect on this entry

specification. In RAM mode (CCR.ORA = 1), the OC's data arrays are only accessible in the

memory-mapped cache area, and bit [13] is used to specify the way. For details about address

mapping, see section 4.6.5, Summary of the Memory-Mapping of the OC. Address field bits [4:2]

are used for the longword data specification in the entry. As only longword access is used, 0

should be specified for address field bits [1:0].

The data field is used for the longword data specification.

The following two kinds of operation can be used on the OC data array:

1. OC data array read

Longword data is read into the data field from the data specified by the longword specification

bits in the address field in the OC entry corresponding to the way and entry set in the address

field.

2. OC data array write

The longword data specified in the data field is written for the data specified by the longword

specification bits in the address field in the OC entry corresponding the way and entry set in

the address field. This write does not set the U bit to 1 on the address array side.

Address field

31 23 5 4 2 1 0

11110101

Entry

Data field

31 0

Longword data

24 131415

Legend:

: Longword specification bits

: Reserved bits (0 write value, undefined read value)

Way

Figure 4.15 Memory-Mapped OC Data Array

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4.6.5 Summary of the Memory-Mapping of the OC

The address ranges to which the OC is memory-mapped in the double-sized cache mode of the

SH7750R are summarized below, using examples of data-array access.

• In normal mode (CCR.ORA = 0)

H'F500 0000 to H'F500 3FFF (16 KB ): Way 0 (entries 0 to 511)

H'F500 4000 to H'F500 7FFF (16 KB ): Way 1 (entries 0 to 511)

: : :

In the same pattern, shadows of the cache area are created in 32-Kbyte blocks until H'F5FF

FFFF.

• In RAM mode (CCR. ORA = 1)

H'F500 0000 to H'F500 1FFF (8 KB ): Way 0 (entries 0 to 255)

H'F500 2000 to H'F500 3FFF (8 KB ): Way 1 (entries 0 to 255)

: : :

In the same pattern, shadows of the cache area are created in 16-Kbyte blocks until H'F5FF

FFFF.

4.7 Store Queues

This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external

memory.

In the SH7750S or SH7750R, if the SQs are not used the low power dissipation power-down

modes, in which SQ functions are stopped, can be used. The queue address control registers

(QACR0 and QACR1) cannot be accessed while SQ functions are stopped. See section 9, Power-

Down Modes, for the procedure for stopping SQ functions.

4.7.1 SQ Configuration

There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 4.16. These two store

queues can be set independently.

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SQ0 SQ0[0] SQ0[1] SQ0[2] SQ0[3] SQ0[4] SQ0[5] SQ0[6] SQ0[7]

SQ1 SQ1[0] SQ1[1] SQ1[2] SQ1[3] SQ1[4] SQ1[5] SQ1[6] SQ1[7]

4B 4B 4B 4B 4B 4B 4B 4B

Figure 4.16 Store Queue Configuration

4.7.2 SQ Writes

A write to the SQs can be performed using a store instruction (MOV) on P4 area H'E000 0000 to

H'E3FF FFFC. A longword or quadword access size can be used. The meaning of the address bits

is as follows:

[31:26]: 111000 Store queue specification

[25:6]: Don't care Used for external memory transfer/access right

[5]: 0/1 0: SQ0 specification 1: SQ1 specification

[4:2]: LW specification Specifies longword position in SQ0/SQ1

[1:0] 00 Fixed at 0

4.7.3 Transfer to External Memory

Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF).

Issuing a PREF instruction for P4 area H'E000 0000 to H'E3FF FFFC starts a burst transfer from

the SQs to external memory. The burst transfer length is fixed at 32 bytes, and the start address is

always at a 32-byte boundary. While the contents of one SQ are being transferred to external

memory, the other SQ can be written to without a penalty cycle, but writing to the SQ involved in

the transfer to external memory is deferred until the transfer is completed.

The SQ transfer destination external memory address bit [28:0] specification is as shown below,

according to whether the MMU is on or off.

• When MMU is on

The SQ area (H'E000 0000 to H'E3FF FFFF) is set in VPN of the UTLB, and the transfer

destination external memory address in PPN. The ASID, V, SZ, SH, PR, and D bits have the

same meaning as for normal address translation, but the C and WT bits have no meaning with

regard to this page. Since burst transfer is prohibited for PCMCIA areas, the SA and TC bits

also have no meaning.

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When a prefetch instruction is issued for the SQ area, address translation is performed and

external memory address bits [28:10] are generated in accordance with the SZ bit specification.

For external memory address bits [9:5], the address prior to address translation is generated in

the same way as when the MMU is off. External memory address bits [4:0] are fixed at 0.

Transfer from the SQs to external memory is performed to this address.

• When MMU is off

The SQ area (H'E000 0000 to H'E3FF FFFF) is specified as the address to issue a PREF

instruction. The meaning of address bits [31:0] is as follows:

[31:26]: 111000 Store queue specification

[25:6]: Address External memory address bits [25:6]

[5]: 0/1 0: SQ0 specification

1: SQ1 specification and external memory address bit [5]

[4:2]: Don't care No meaning in a prefetch

[1:0] 00 Fixed at 0

External memory address bits [28:26], which cannot be generated from the above address, are

generated from the QACR0/1 registers.

QACR0 [4:2]: External memory address bits [28:26] corresponding to SQ0

QACR1 [4:2]: External memory address bits [28:26] corresponding to SQ1

External memory address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte

boundary. In the SH7750, data transfer to a PCMCIA interface area cannot be performed using

an SQ. In the SH7750S or SH7750R, data transfer to a PCMCIA interface area is always

performed using the SA and TC bits in the PTEA register.

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4.7.4 SQ Protection

Determination of an exception in a write to an SQ or transfer to external memory (PREF

instruction) is performed as follows according to whether the MMU is on or off. In the SH7750 or

SH7750S, if an exception occurs in an SQ write, the SQ contents may be corrupted. In the

SH7750R, original SQ contents are guaranteed. If an exception occurs in transfer from an SQ to

external memory, the transfer to external memory will be aborted.

• When MMU is on

Operation is in accordance with the address translation information recorded in the UTLB, and

MMUCR.SQMD. Write type exception judgment is performed for writes to the SQs, and read

type for transfer from the SQs to external memory (PREF instruction), and a TLB miss

exception, protection violation exception, or initial page write exception is generated.

However, if SQ access is enabled, in privileged mode only, by MMUCR.SQMD, an address

error will be flagged in user mode even if address translation is successful.

• When MMU is off

Operation is in accordance with MMUCR.SQMD.

0: Privileged/user access possible

1: Privileged access possible

If the SQ area is accessed in user mode when MMUCR.SQMD is set to 1, an address error will

be flagged.

4.7.5 Reading the SQs (SH7750R Only)

In the SH7750R, a load instruction may be executed in the privileged mode to read the contents of

the SQs from the address range of H'FF001000 to H'FF00103C in the P4 area. Only longword

access is possible.

[31:6] : H'FF001000 : Store queue specification

[5] : 0/1 : 0: SQ0 specification, 1: SQ1 specification

[4:2] : LW specification : Specification of longword position in SQ0 or SQ1

[1:0] : 00 : Fixed at 0

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4.7.6 SQ Usage Notes

If an exception occurs within the three instructions preceding an instruction that writes to an SQ in

the SH7750 and SH7750S, a branch may be made to the exception handling routine after

execution of the SQ write that should be suppressed when an exception occurs.

This may be due to the bug described in (1) or (2) below.

(1) When SQ data is transferred to external memory within a normal program

If a PREF instruction for transfer from an SQ to external memory is included in the three

instructions preceding an SQ store instruction, the SQ is updated because the SQ write that

should be suppressed when a branch is made to the exception handling routine is executed, and

after returning from the exception handling routine the execution order of the PREF instruction

and SQ store instruction is reversed, so that erroneous data may be transferred to external

memory.

(2) When SQ data is transferred to external memory in an exception handling routine

If store queue contents are transferred to external memory within an exception handling

routine, erroneous data may be transferred to external memory.

Example 1: When an SQ store instruction is executed after a PREF instruction for transfer from that same SQ

to external memory

PREF instruction

; PREF instruction for transfer from SQ to external memory

; Address of this instruction is saved to SPC when exception occurs.

; Instruction 1, instruction 2, or instruction 3 may be executed on return from exception handling routine.

Instruction 1 ; May be executed if an SQ store instruction.

Instruction 2 ; May be executed if an SQ store instruction.

Instruction 3 ; May be executed if an SQ store instruction.

Instruction 4 ; Not executed even if an SQ store instruction.

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Example 2: When an instruction that generates an exception branches using a branch instruction

Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs.

Instruction 2 ; May be executed if instruction 1 is a delay slot instruction and an instruction to store data to SQ.

Instruction 3

Instruction 4

Instruction 5

Instruction 6

Instruction 7 (branch destination of instruction 1)

; May be executed if an SQ access instruction.

Instruction 8 ; May be executed if an SQ store instruction.

Example 3: When an instruction that generates an exception does not branch using a branch instruction

Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs.

Instruction 2 ; May be executed if an SQ store instruction.

Instruction 3 ; May be executed if an SQ store instruction.

Instruction 4 ; May be executed if an SQ store instruction.

Instruction 5

To recover from this problem it is necessary that conditions A and B be satisfied.

A: After the PREF instruction to transfer data from the store queue (SQ0, SQ1) to external

memory, a store instruction for the same store queue must be executed, and conditions (1) and

(2) below must be satisfied.

(1) Three NOP instructions*1 must be inserted between the above two instructions.

(2) There must not be a PREF instruction to transfer data from the store queue to external

memory in the delay slot of the branch instruction.

B: There must be no PREF instruction to transfer data from the store queue to external memory

executed in the exception handling routine.

If such an instruction is executed, and if there is a store to the store queue instruction among

the four instructions*2 at the address referred to by SPC, the data transferred to external

memory by the PREF instruction may indicate that execution of the store instruction has

completed.

Notes: 1. If there are other instructions between the above two instructions, the problem can be

avoided if the other instructions and NOP instructions together total three or more

instructions.

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2. If the instruction at the address referred to by SPC is a branch instruction the two

instructions at the branch destination may be affected.

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Section 5 Exceptions

5.1 Overview

5.1.1 Features

Exception handling is processing handled by a special routine, separate from normal program

processing, that is executed by the CPU in case of abnormal events. For example, if the executing

instruction ends abnormally, appropriate action must be taken in order to return to the original

program sequence, or report the abnormality before terminating the processing. The process of

generating an exception handling request in response to abnormal termination, and passing control

to a user-written exception handling routine, in order to support such functions, is given the

generic name of exception handling.

SH-4 exception handling is of three kinds: for resets, general exceptions, and interrupts.

5.1.2 Register Configuration

The registers used in exception handling are shown in table 5.1.

Table 5.1 Exception-Related Registers

Name

Abbrevia-

tion

R/W

Initial Value*1

Address*2

Area 7

Address*2

Access

Size

TRAPA exception

TRA R/W Undefined H'FF00 0020 H'1F00 0020 32

Exception event

EXPEVT R/W H'0000 0000/

H'0000 0020*1

H'FF00 0024 H'1F00 0024 32

Interrupt event

INTEVT R/W Undefined H'FF00 0028 H'1F00 0028 32

Notes: 1. H'0000 0000 is set in a power-on reset, and H'0000 0020 in a manual reset.

2. This is the address when using the virtual/physical address space P4 area. The area 7

address is the address used when making an access from physical address space area

7 using the TLB.

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5.2 Register Descriptions

There are three registers related to exception handling. Addresses are allocated to these registers,

and they can be accessed by specifying the P4 address or area 7 address.

1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12-

bit exception code. The exception code set in EXPEVT is that for a reset or general exception

event. The exception code is set automatically by hardware when an exception occurs.

EXPEVT can also be modified by software.

2. The interrupt event register (INTEVT) resides at P4 address H'FF00 0028, and contains a 12-

bit exception code. The exception code set in INTEVT is that for an interrupt request. The

exception code is set automatically by hardware when an exception occurs. INTEVT can also

be modified by software.

3. The TRAPA exception register (TRA) resides at P4 address H'FF00 0020, and contains 8-bit

immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when

a TRAPA instruction is executed. TRA can also be modified by software.

The bit configurations of EXPEVT, INTEVT, and TRA are shown in figure 5.1.

31 0

0 0 0 0

31 10 9 1 0

Legend:

0: Reserved bits. These bits are always read as 0, and should only be written with 0.

imm: 8-bit immediate data of the TRAPA instruction

12 11

EXPEVT and INTEVT

TRA

imm

Exception code

Figure 5.1 Register Bit Configurations

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5.3 Exception Handling Functions

5.3.1 Exception Handling Flow

In exception handling, the contents of the program counter (PC), status register (SR), and R15 are

saved in the saved program counter (SPC), saved status register (SSR), and saved general

register15(SGR), and the CPU starts execution of the appropriate exception handling routine

according to the vector address. An exception handling routine is a program written by the user to

handle a specific exception. The exception handling routine is terminated and control returned to

the original program by executing a return-from-exception instruction (RTE). This instruction

restores the PC and SR contents and returns control to the normal processing routine at the point at

which the exception occurred.

The SGR contents are not written back to R15 by an RTE instruction.

The basic processing flow is as follows. See section 2, Programming Model, for the meaning of

the individual SR bits.

1. The PC, SR, and R15 contents are saved in SPC, SSR, and SGR.

2. The block bit (BL) in SR is set to 1.

3. The mode bit (MD) in SR is set to 1.

4. The register bank bit (RB) in SR is set to 1.

5. In a reset, the FPU disable bit (FD) in SR is cleared to 0.

6. The exception code is written to bits 11–0 of the exception event register (EXPEVT) or

interrupt event register (INTEVT).

7. The CPU branches to the determined exception handling vector address, and the exception

handling routine begins.

5.3.2 Exception Handling Vector Addresses

The reset vector address is fixed at H'A000 0000. General exception and interrupt vector addresses

are determined by adding the offset for the specific event to the vector base address, which is set

by software in the vector base register (VBR). In the case of the TLB miss exception, for example,

the offset is H'0000 0400, so if H'9C08 0000 is set in VBR, the exception handling vector address

will be H'9C08 0400. If a further exception occurs at the exception handling vector address, a

duplicate exception will result, and recovery will be difficult; therefore, fixed physical addresses

(P1, P2) should be specified for vector addresses.

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5.4 Exception Types and Priorities

Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and

exception/interrupt codes.

Table 5.2 Exceptions

Exception

Category

Execution

Mode

Exception

Priority

Level

Priority

Order

Vector

Address

Offset

Exception

Code

DMTE0 H'640

DMTE1 H'660

DMTE2 H'680

DMTE3 H'6A0

DMTE4

H'780

DMTE5

H'7A0

DMTE6

H'7C0

DMTE7

H'7E0

DMAC

DMAE H'6C0

ERI H'700

RXI H'720

BRI H'740

Interrupt Completion

type

Peripheral

module

interrupt

(module/

source)

SCIF

TXI

4 *2 (VBR) H'600

H'760

Priority: Priority is first assigned by priority level, then by priority order within each level (the lowest

number represents the highest priority).

Exception transition destination: Control passes to H'A000 0000 in a reset, and to [VBR + offset] in

other cases.

Exception code: Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt.

IRL: Interrupt request level (pins IRL3–IRL0).

Module/source: See the sections on the relevant peripheral modules.

Notes: 1. When BRCR.UBDE = 1, PC = DBR. In other cases, PC = VBR + H'100.

2. The priority order of external interrupts and peripheral module interrupts can be set by

software.

3. SH7750R only.

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5.5 Exception Flow

5.5.1 Exception Flow

Figure 5.2 shows an outline flowchart of the basic operations in instruction execution and

exception handling. For the sake of clarity, the following description assumes that instructions are

executed sequentially, one by one. Figure 5.2 shows the relative priority order of the different

kinds of exceptions (reset/general exception/interrupt). Register settings in the event of an

exception are shown only for SSR, SPC, SGR, EXPEVT/INTEVT, SR, and PC, but other registers

may be set automatically by hardware, depending on the exception. For details, see section 5.6,

Description of Exceptions. Also, see section 5.6.4, Priority Order with Multiple Exceptions, for

exception handling during execution of a delayed branch instruction and a delay slot instruction,

and in the case of instructions in which two data accesses are performed.

Execute next instruction

Is highest-

priority exception

re-exception

type? Cancel instruction execution

result

Yes

SSR ← SR

SPC ← PC

SGR ← R15

EXPEVT/INTEVT ← exception code

SR.{MD,RB,BL} ← 111

PC ← (BRCR.UBDE=1 && User_Break?

DBR: (VBR + Offset))

EXPEVT ← exception code

SR. {MD, RB, BL, FD, IMASK} ← 11101111

PC ← H'A000 0000

Interrupt

requested?

General

exception requested?

Reset

requested?

Figure 5.2 Instruction Execution and Exception Handling

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5.5.2 Exception Source Acceptance

A priority ranking is provided for all exceptions for use in determining which of two or more

simultaneously generated exceptions should be accepted. Five of the general exceptions—the

general illegal instruction exception, slot illegal instruction exception, general FPU disable

exception, slot FPU disable exception, and unconditional trap exception—are detected in the

process of instruction decoding, and do not occur simultaneously in the instruction pipeline. These

exceptions therefore all have the same priority. General exceptions are detected in the order of

instruction execution. However, exception handling is performed in the order of instruction flow

(program order). Thus, an exception for an earlier instruction is accepted before that for a later

instruction. An example of the order of acceptance for general exceptions is shown in figure 5.3.

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IF ID

ID EX

EX MA

MA WB

TLB miss (data access)Pipeline flow:

Order of detection:

Instruction n

Instruction n+1

General illegal instruction exception (instruction n+1) and

TLB miss (instruction n+2) are detected simultaneously

Order of exception handling:

TLB miss (instruction n) Program order

Instruction n+2

General illegal instruction exception

IF ID EX MA WB

TLB miss (instruction access)

Legend:

IF: Instruction fetch

ID: Instruction decode

EX: Instruction execution

MA: Memory access

WB: Write-back

Instruction n+3

TLB miss (instruction n)

Re-execution of instruction n

General illegal instruction exception

(instruction n+1)

Re-execution of instruction n+1

TLB miss (instruction n+2)

Re-execution of instruction n+2

Execution of instruction n+3

Figure 5.3 Example of General Exception Acceptance Order

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5.5.3 Exception Requests and BL Bit

When the BL bit in SR is 0, general exception and interrupts are accepted.

When the BL bit in SR is 1 and a general exception other than a user break is generated, the CPU's

internal registers and the registers of the other modules are set to their states following a manual

reset, and the CPU branches to the same address as in a reset (H'A000 0000). For the operation in

the event of a user break, see section 20, User Break Controller (UBC).

If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL

bit has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held

pending or accepted according to the setting made by software.

Thus, normally, SPC and SSR are saved and then the BL bit in SR is cleared to 0, to enable

multiple exception state acceptance.

5.5.4 Return from Exception Handling

The RTE instruction is used to return from exception handling. When the RTE instruction is

executed, the SPC contents are restored to PC and the SSR contents to SR, and the CPU returns

from the exception handling routine by branching to the SPC address. If SPC and SSR were saved

to external memory, set the BL bit in SR to 1 before restoring the SPC and SSR contents and

issuing the RTE instruction.

5.6 Description of Exceptions

The various exception handling operations are described here, covering exception sources,

transition addresses, and processor operation when a transition is made.

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5.6.1 Resets

(1) Power-On Reset

• Sources:

⎯ SCK2 pin high level and RESET pin low level

⎯ When the watchdog timer overflows while the WT/IT bit is set to 1 and the RSTS bit is

cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits.

• Transition address: H'A000 0000

• Transition operations:

Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a

branch is made to PC = H'A000 0000.

In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,

RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK)

are set to B'1111.

CPU and on-chip peripheral module initialization is performed. For details, see the register

descriptions in the relevant sections. For some CPU functions, the TRST pin and RESET pin

must be driven low. It is therefore essential to execute a power-on reset and drive the TRST

pin low when powering on.

If the SCK2 pin is changed to the low level while the RESET pin is low, a manual reset may

occur after the power-on reset operation. Do not drive the SCK2 pin low during this interval

(see figure 22.3).

Power_on_reset()

{

EXPEVT = H'00000000;

VBR = H'00000000;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

SR.IMASK = B'1111;

SR.FD=0;

Initialize_CPU();

Initialize_Module(PowerOn);

PC = H'A0000000;

}

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(2) Manual Reset

• Sources:

⎯ SCK2 pin low level and RESET pin low level

⎯ When a general exception other than a user break occurs while the BL bit is set to 1 in SR

⎯ When the watchdog timer overflows while the WT/IT bit and RSTS bit are both set to 1 in

WTCSR. For details, see section 10, Clock Oscillation Circuits.

• Transition address: H'A000 0000

• Transition operations:

Exception code H'020 is set in EXPEVT, initialization of VBR and SR is performed, and a

branch is made to PC = H'A000 0000.

In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,

RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK)

are set to B'1111.

CPU and on-chip peripheral module initialization is performed. For details, see the register

descriptions in the relevant sections.

Manual_reset()

{

EXPEVT = H'00000020;

VBR = H'00000000;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

SR.IMASK = B'1111;

SR.FD = 0;

Initialize_CPU();

Initialize_Module(Manual);

PC = H'A0000000;

}

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Table 5.3 Types of Reset

Reset State Transition

Conditions

Internal States

Type SCK2 RESET CPU On-Chip Peripheral Modules

Power-on reset High Low Initialized

Manual reset Low Low Initialized

See Register Configuration in

each section

(3) H-UDI Reset

• Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion)

• Transition address: H'A000 0000

• Transition operations:

Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a

branch is made to PC = H'A000 0000.

In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,

RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK)

are set to B'1111.

CPU and on-chip peripheral module initialization is performed. For details, see the register

descriptions in the relevant sections.

H-UDI_reset()

{

EXPEVT = H'00000000;

VBR = H'00000000;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

SR.IMASK = B'1111;

SR.FD = 0;

Initialize_CPU();

Initialize_Module(PowerOn);

PC = H'A0000000;

}

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(4) Instruction TLB Multiple-Hit Exception

• Source: Multiple ITLB address matches

• Transition address: H'A000 0000

• Transition operations:

The virtual address (32 bits) at which this exception occurred is set in TEA, and the

corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates

the ASID when this exception occurred.

Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a

branch is made to PC = H'A000 0000.

In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,

RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK)

are set to B'1111.

CPU and on-chip peripheral module initialization is performed in the same way as in a manual

reset. For details, see the register descriptions in the relevant sections.

TLB_multi_hit()

{

TEA = EXCEPTION_ADDRESS;

PTEH.VPN = PAGE_NUMBER;

EXPEVT = H'00000140;

VBR = H'00000000;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

SR.IMASK = B'1111;

SR.FD = 0;

Initialize_CPU();

Initialize_Module(Manual);

PC = H'A0000000;

}

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(5) Operand TLB Multiple-Hit Exception

• Source: Multiple UTLB address matches

• Transition address: H'A000 0000

• Transition operations:

The virtual address (32 bits) at which this exception occurred is set in TEA, and the

corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates

the ASID when this exception occurred.

Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a

branch is made to PC = H'A000 0000.

In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,

RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK)

are set to B'1111.

CPU and on-chip peripheral module initialization is performed in the same way as in a manual

reset. For details, see the register descriptions in the relevant sections.

TLB_multi_hit()

{

TEA = EXCEPTION_ADDRESS;

PTEH.VPN = PAGE_NUMBER;

EXPEVT = H'00000140;

VBR = H'00000000;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

SR.IMASK = B'1111;

SR.FD = 0;

Initialize_CPU();

Initialize_Module(Manual);

PC = H'A0000000;

}

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5.6.2 General Exceptions

(1) Data TLB Miss Exception

• Source: Address mismatch in UTLB address comparison

• Transition address: VBR + H'0000 0400

• Transition operations:

The virtual address (32 bits) at which this exception occurred is set in TEA, and the

corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates

the ASID when this exception occurred.

The PC and SR contents for the instruction at which this exception occurred are saved in SPC

and SSR, and the contents of R15 are saved in SGR.

Exception code H'040 (for a read access) or H'060 (for a write access) is set in EXPEVT. The

BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400.

To speed up TLB miss processing, the offset is separate from that of other exceptions.

Data_TLB_miss_exception()

{

TEA = EXCEPTION_ADDRESS;

PTEH.VPN = PAGE_NUMBER;

SPC = PC;

SSR = SR;

SGR = R15;

EXPEVT = read_access ? H'00000040 : H'00000060;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000400;

}

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(2) Instruction TLB Miss Exception

• Source: Address mismatch in ITLB address comparison

• Transition address: VBR + H'0000 0400

• Transition operations:

The virtual address (32 bits) at which this exception occurred is set in TEA, and the

corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates

the ASID when this exception occurred.

The PC and SR contents for the instruction at which this exception occurred are saved in SPC

and SSR, and the contents of R15 are saved in SGR.

Exception code H'040 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a

branch is made to PC = VBR + H'0400.

To speed up TLB miss processing, the offset is separate from that of other exceptions.

ITLB_miss_exception()

{

TEA = EXCEPTION_ADDRESS;

PTEH.VPN = PAGE_NUMBER;

SPC = PC;

SSR = SR;

SGR = R15;

EXPEVT = H'00000040;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000400;

}

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(3) Initial Page Write Exception

• Source: TLB is hit in a store access, but dirty bit D = 0

• Transition address: VBR + H'0000 0100

• Transition operations:

The virtual address (32 bits) at which this exception occurred is set in TEA, and the

corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates

the ASID when this exception occurred.

The PC and SR contents for the instruction at which this exception occurred are saved in SPC

and SSR, and the contents of R15 are saved in SGR.

Exception code H'080 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a

branch is made to PC = VBR + H'0100.

Initial_write_exception()

{

TEA = EXCEPTION_ADDRESS;

PTEH.VPN = PAGE_NUMBER;

SPC = PC;

SSR = SR;

SGR = R15;

EXPEVT = H'00000080;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000100;

}

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(4) Data TLB Protection Violation Exception

• Source: The access does not accord with the UTLB protection information (PR bits) shown

below.

PR Privileged Mode User Mode

00 Only read access possible Access not possible

01 Read/write access possible Access not possible

10 Only read access possible Only read access possible

11 Read/write access possible Read/write access possible

• Transition address: VBR + H'0000 0100

• Transition operations:

The virtual address (32 bits) at which this exception occurred is set in TEA, and the

corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates

the ASID when this exception occurred.

The PC and SR contents for the instruction at which this exception occurred are saved in SPC

and SSR, and the contents of R15 are saved in SGR.

Exception code H'0A0 (for a read access) or H'0C0 (for a write access) is set in EXPEVT. The

BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.

Data_TLB_protection_violation_exception()

{

TEA = EXCEPTION_ADDRESS;

PTEH.VPN = PAGE_NUMBER;

SPC = PC;

SSR = SR;

SGR = R15;

EXPEVT = read_access ? H'000000A0 : H'000000C0;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000100;

}

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(5) Instruction TLB Protection Violation Exception

• Source: The access does not accord with the ITLB protection information (PR bits) shown

below.

PR Privileged Mode User Mode

0 Access possible Access not possible

1 Access possible Access possible

• Transition address: VBR + H'0000 0100

• Transition operations:

The virtual address (32 bits) at which this exception occurred is set in TEA, and the

corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates

the ASID when this exception occurred.

The PC and SR contents for the instruction at which this exception occurred are saved in SPC

and SSR, and the contents of R15 are saved in SGR.

Exception code H'0A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a

branch is made to PC = VBR + H'0100.

ITLB_protection_violation_exception()

{

TEA = EXCEPTION_ADDRESS;

PTEH.VPN = PAGE_NUMBER;

SPC = PC;

SSR = SR;

SGR = R15;

EXPEVT = H'000000A0;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000100;

}

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(6) Data Address Error

• Sources:

⎯ Word data access from other than a word boundary (2n +1)

⎯ Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3)

⎯ Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n

+ 4, 8n + 5, 8n + 6, or 8n + 7)

⎯ Access to area H'8000 0000–H'FFFF FFFF in user mode

• Transition address: VBR + H'0000 0100

• Transition operations:

The virtual address (32 bits) at which this exception occurred is set in TEA, and the

corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates

the ASID when this exception occurred.

The PC and SR contents for the instruction at which this exception occurred are saved in SPC

and SSR, and the contents of R15 are saved in SGR.

Exception code H'0E0 (for a read access) or H'100 (for a write access) is set in EXPEVT. The

BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For

details, see section 3, Memory Management Unit (MMU).

Data_address_error()

{

TEA = EXCEPTION_ADDRESS;

PTEN.VPN = PAGE_NUMBER;

SPC = PC;

SSR = SR;

SGR = R15;

EXPEVT = read_access? H'000000E0: H'00000100;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000100;

}

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(7) Instruction Address Error

• Sources:

⎯ Instruction fetch from other than a word boundary (2n +1)

⎯ Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode

• Transition address: VBR + H'0000 0100

• Transition operations:

The virtual address (32 bits) at which this exception occurred is set in TEA, and the

corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates

the ASID when this exception occurred.

The PC and SR contents for the instruction at which this exception occurred are saved in SPC

and SSR, and the contents of R15 are saved in SGR.

Exception code H'0E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a

branch is made to PC = VBR + H'0100. For details, see section 3, Memory Management Unit

(MMU).

Instruction_address_error()

{

TEA = EXCEPTION_ADDRESS;

PTEN.VPN = PAGE_NUMBER;

SPC = PC;

SSR = SR;

SGR = R15;

EXPEVT = H'000000E0;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000100;

}

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(8) Unconditional Trap

• Source: Execution of TRAPA instruction

• Transition address: VBR + H'0000 0100

• Transition operations:

As this is a processing-completion-type exception, the PC contents for the instruction

following the TRAPA instruction are saved in SPC. The values of SR and R15 when the

TRAPA instruction is executed are saved in SSR and SGR. The 8-bit immediate value in the

TRAPA instruction is multiplied by 4, and the result is set in TRA [9:0]. Exception code H'160

is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC =

VBR + H'0100.

TRAPA_exception()

{

SPC = PC + 2;

SSR = SR;

SGR = R15;

TRA = imm << 2;

EXPEVT = H'00000160;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000100;

}

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(9) General Illegal Instruction Exception

• Sources:

⎯ Decoding of an undefined instruction not in a delay slot

Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S

Undefined instruction: H'FFFD

⎯ Decoding in user mode of a privileged instruction not in a delay slot

Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC

instructions that access GBR

• Transition address: VBR + H'0000 0100

• Transition operations:

The PC and SR contents for the instruction at which this exception occurred are saved in SPC

and SSR, and the contents of R15 are saved in SGR.

Exception code H'180 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a

branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other

than H'FFFD is decoded.

General_illegal_instruction_exception()

{

SPC = PC;

SSR = SR;

SGR = R15;

EXPEVT = H'00000180;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000100;

}

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(10) Slot Illegal Instruction Exception

• Sources:

⎯ Decoding of an undefined instruction in a delay slot

Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S

Undefined instruction: H'FFFD

⎯ Decoding of an instruction that modifies PC in a delay slot

Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,

BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR

⎯ Decoding in user mode of a privileged instruction in a delay slot

Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC

instructions that access GBR

⎯ Decoding of a PC-relative MOV instruction or MOVA instruction in a delay slot

• Transition address: VBR + H'0000 0100

• Transition operations:

The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and

R15 contents when this exception occurred are saved in SSR and SGR.

Exception code H'1A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a

branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other

than H'FFFD is decoded.

Slot_illegal_instruction_exception()

{

SPC = PC - 2;

SSR = SR;

SGR = R15;

EXPEVT = H'000001A0;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000100;

}

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(11) General FPU Disable Exception

• Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1

• Transition address: VBR + H'0000 0100

• Transition operations:

The PC and SR contents for the instruction at which this exception occurred are saved in SPC

and SSR, and the contents of R15 are saved in SGR.

Exception code H'800 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a

branch is made to PC = VBR + H'0100.

Note: * FPU instructions are instructions in which the first 4 bits of the instruction code are H'F

(but excluding undefined instruction H'FFFD), and the LDS, STS, LDS.L, and STS.L

instructions corresponding to FPUL and FPSCR.

General_fpu_disable_exception()

{

SPC = PC;

SSR = SR;

SGR = R15;

EXPEVT = H'00000800;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000100;

}

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(12) Slot FPU Disable Exception

• Source: Decoding of an FPU instruction in a delay slot with SR.FD =1

• Transition address: VBR + H'0000 0100

• Transition operations:

The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and

R15 contents when this exception occurred are saved in SSR and SGR.

Exception code H'820 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a

branch is made to PC = VBR + H'0100.

Slot_fpu_disable_exception()

{

SPC = PC - 2;

SSR = SR;

SGR = R15;

EXPEVT = H'00000820;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000100;

}

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(13) User Breakpoint Trap

• Source: Fulfilling of a break condition set in the user break controller

• Transition address: VBR + H'0000 0100, or DBR

• Transition operations:

In the case of a post-execution break, the PC contents for the instruction following the

instruction at which the breakpoint is set are set in SPC. In the case of a pre-execution break,

the PC contents for the instruction at which the breakpoint is set are set in SPC.

The SR and R15 contents when the break occurred are saved in SSR and SGR. Exception code

H'1E0 is set in EXPEVT.

The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. It is

also possible to branch to PC = DBR.

For details of PC, etc., when a data break is set, see section 20, User Break Controller (UBC).

User_break_exception()

{

SPC = (pre_execution break? PC : PC + 2);

SSR = SR;

SGR = R15;

EXPEVT = H'000001E0;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = (BRCR.UBDE==1 ? DBR : VBR + H'00000100);

}

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(14) FPU Exception

• Source: Exception due to execution of a floating-point operation

• Transition address: VBR + H'0000 0100

• Transition operations:

The PC and SR contents for the instruction at which this exception occurred are saved in SPC

and SSR, and the contents of R15 are saved in SGR. Exception code H'120 is set in EXPEVT.

The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.

FPU_exception()

{

SPC = PC;

SSR = SR;

SGR = R15;

EXPEVT = H'00000120;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000100;

}

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5.6.3 Interrupts

(1) NMI

• Source: NMI pin edge detection

• Transition address: VBR + H'0000 0600

• Transition operations:

The contents of PC and SR immediately after the instruction at which this interrupt was

accepted are saved in SPC and SSR, and the contents of R15 are saved in SGR.

Exception code H'1C0 is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a

branch is made to PC = VBR + H'0600. When the BL bit in SR is 0, this interrupt is not

masked by the interrupt mask bits in SR, and is accepted at the highest priority level. When the

BL bit in SR is 1, a software setting can specify whether this interrupt is to be masked or

accepted. For details, see section 19, Interrupt Controller (INTC).

NMI()

{

SPC = PC;

SSR = SR;

SGR = R15;

INTEVT = H'000001C0;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000600;

}

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(2) IRL Interrupts

• Source: The interrupt mask bit setting in SR is smaller than the IRL (3–0) level, and the BL bit

in SR is 0 (accepted at instruction boundary).

• Transition address: VBR + H'0000 0600

• Transition operations:

The PC contents immediately after the instruction at which the interrupt is accepted are set in

SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR.

The code corresponding to the IRL (3–0) level is set in INTEVT. See table 19.5, Interrupt

Exception Handling Sources and Priority Order, for the corresponding codes. The BL, MD,

and RB bits are set to 1 in SR, and a branch is made to VBR + H'0600. The acceptance level is

not set in the interrupt mask bits in SR. When the BL bit in SR is 1, the interrupt is masked.

For details, see section 19, Interrupt Controller (INTC).

IRL()

{

SPC = PC;

SSR = SR;

SGR = R15;

INTEVT = H'00000200 ~ H'000003C0;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000600;

}

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(3) Peripheral Module Interrupts

• Source: The interrupt mask bit setting in SR is smaller than the peripheral module (H-UDI,

GPIO, DMAC, TMU, RTC, SCI, SCIF, WDT, or REF) interrupt level, and the BL bit in SR is

0 (accepted at instruction boundary).

• Transition address: VBR + H'0000 0600

• Transition operations:

The PC contents immediately after the instruction at which the interrupt is accepted are set in

SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR.

The code corresponding to the interrupt source is set in INTEVT. The BL, MD, and RB bits

are set to 1 in SR, and a branch is made to VBR + H'0600. The module interrupt levels should

be set as values between B'0000 and B'1111 in the interrupt priority registers (IPRA–IPRC) in

the interrupt controller. For details, see section 19, Interrupt Controller (INTC).

Module_interruption()

{

SPC = PC;

SSR = SR;

SGR = R15;

INTEVT = H'00000400 ~ H'00000B80;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'00000600;

}

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5.6.4 Priority Order with Multiple Exceptions

With some instructions, such as instructions that make two accesses to memory, and the

indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple

exceptions occur. Care is required in these cases, as the exception priority order differs from the

normal order.

1. Instructions that make two accesses to memory

With MAC instructions, memory-to-memory arithmetic/logic instructions, and TAS

instructions, two data transfers are performed by a single instruction, and an exception will be

detected for each of these data transfers. In these cases, therefore, the following order is used

to determine priority.

a. Data address error in first data transfer

b. TLB miss in first data transfer

c. TLB protection violation in first data transfer

d. Initial page write exception in first data transfer

e. Data address error in second data transfer

f. TLB miss in second data transfer

g. TLB protection violation in second data transfer

h. Initial page write exception in second data transfer

2. Indivisible delayed branch instruction and delay slot instruction

As a delayed branch instruction and its associated delay slot instruction are indivisible, they

are treated as a single instruction. Consequently, the priority order for exceptions that occur in

these instructions differs from the usual priority order. The priority order shown below is for

the case where the delay slot instruction has only one data transfer.

a. A check is performed for the interrupt type and reexecution type exceptions of priority

levels 1 and 2 in the delayed branch instruction.

b. A check is performed for the interrupt type and reexecution type exceptions of priority

levels 1 and 2 in the delay slot instruction.

c. A check is performed for the completion type exception of priority level 2 in the delayed

branch instruction.

d. A check is performed for the completion type exception of priority level 2 in the delay slot

instruction.

e. A check is performed for priority level 3 in the delayed branch instruction and priority

level 3 in the delay slot instruction. (There is no priority ranking between these two.)

f. A check is performed for priority level 4 in the delayed branch instruction and priority

level 4 in the delay slot instruction. (There is no priority ranking between these two.)

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If the delay slot instruction has a second data transfer, two checks are performed in step b, as in

1 above.

If the accepted exception (the highest-priority exception) is a delay slot instruction re-

execution type exception, the branch instruction PR register write operation (PC → PR

operation performed in BSR, BSRF, JSR) is inhibited.

5.7 Usage Notes

1. Return from exception handling

a. Check the BL bit in SR with software. If SPC and SSR have been saved to external

memory, set the BL bit in SR to 1 before restoring them.

b. Issue an RTE instruction. When RTE is executed, the SPC contents are set in PC, the SSR

contents are set in SR, and branch is made to the SPC address to return from the exception

handling routine.

2. If a general exception or interrupt occurs when SR.BL = 1

a. General exception

When a general exception other than a user break occurs, a manual reset is executed. The

value in EXPEVT at this time is H'0000 0020; the value of the SPC and SSR registers is

undefined.

b. Interrupt

If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after

the BL bit in SR has been cleared to 0 by software. If a nonmaskable interrupt (NMI)

occurs, it can be held pending or accepted according to the setting made by software. In the

sleep or standby state, however, an interrupt is accepted even if the BL bit in SR is set to 1.

3. SPC when an exception occurs

a. Re-execution type general exception

The PC value for the instruction in which the general exception occurred is set in SPC, and

the instruction is re-executed after returning from exception handling. If an exception

occurs in a delay slot instruction, however, the PC value for the delay slot instruction is

saved in SPC regardless of whether or not the preceding delayed branch instruction

condition is satisfied.

b. Completion type general exception or interrupt

The PC value for the instruction following that in which the general exception occurred is

set in SPC. If an exception occurs in a branch instruction with delay slot, however, the PC

value for the branch destination is saved in SPC.

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4. An exception must not be generated in an RTE instruction delay slot, as the operation will be

undefined in this case.

5.8 Restrictions

1. Restrictions on first instruction of exception handling routine

• Do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at address VBR + H'100, VBR

+ H'400, or VBR + H'600.

• When the UBDE bit in the BRCR register is set to 1 and the user break debug support

function* is used, do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at the address

indicated by the DBR register.

Note: * See section 20.4, User Break Debug Support Function.

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Section 6 Floating-Point Unit (FPU)

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Section 6 Floating-Point Unit (FPU)

6.1 Overview

The floating-point unit (FPU) has the following features:

• Conforms to IEEE754 standard

• 32 single-precision floating-point registers (can also be referenced as 16 double-precision

registers)

• Two rounding modes: Round to Nearest and Round to Zero

• Two denormalization modes: Flush to Zero and Treat Denormalized Number

• Six exception sources: FPU Error, Invalid Operation, Divide By Zero, Overflow, Underflow,

and Inexact

• Comprehensive instructions: Single-precision, double-precision, graphics support, system

control

When the FD bit in SR is set to 1, the FPU cannot be used, and an attempt to execute an FPU

instruction will cause an FPU disable exception.

6.2 Data Formats

6.2.1 Floating-Point Format

A floating-point number consists of the following three fields:

• Sign (s)

• Exponent (e)

• Fraction (f)

The FPU can handle single-precision and double-precision floating-point numbers, using the

formats shown in figures 6.1 and 6.2.

se f

30 23 22 0

Figure 6.1 Format of Single-Precision Floating-Point Number

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se f

62 52 51 0

Figure 6.2 Format of Double-Precision Floating-Point Number

The exponent is expressed in biased form, as follows:

e = E + bias

The range of unbiased exponent E is Emin – 1 to Emax + 1. The two values Emin – 1 and Emax + 1 are

distinguished as follows. Emin – 1 indicates zero (both positive and negative sign) and a

denormalized number, and Emax + 1 indicates positive or negative infinity or a non-number (NaN).

Table 6.1 shows bias, Emin, and Emax values.

Table 6.1 Floating-Point Number Formats and Parameters

Parameter Single-Precision Double-Precision

Total bit width 32 bits 64 bits

Sign bit 1 bit 1 bit

Exponent field 8 bits 11 bits

Fraction field 23 bits 52 bits

Precision 24 bits 53 bits

Bias +127 +1023

Emax +127 +1023

Emin –126 –1022

Floating-point number value v is determined as follows:

If E = Emax + 1 and f ≠ 0, v is a non-number (NaN) irrespective of sign s

If E = Emax + 1 and f = 0, v = (–1)s (infinity) [positive or negative infinity]

If Emin ≤ E ≤ Emax , v = (–1)s2E (1.f) [normalized number]

If E = Emin – 1 and f ≠ 0, v = (–1)s2Emin (0.f) [denormalized number]

If E = Emin – 1 and f = 0, v = (–1)s0 [positive or negative zero]

Table 6.2 shows the ranges of the various numbers in hexadecimal notation.

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Table 6.2 Floating-Point Ranges

Type Single-Precision Double-Precision

Signaling non-number H'7FFFFFFF to H'7FC00000 H'7FFFFFFF FFFFFFFF to

H'7FF80000 00000000

Quiet non-number H'7FBFFFFF to H'7F800001 H'7FF7FFFF FFFFFFFF to

H'7FF00000 00000001

Positive infinity H'7F800000 H'7FF00000 00000

Positive normalized

number

H'7F7FFFFF to H'00800000 H'7FEFFFFF FFFFFFFF to

H'00100000 00000000

Positive denormalized

number

H'007FFFFF to H'00000001 H'000FFFFF FFFFFFFF to

H'00000000 00000001

Positive zero H'00000000 H'00000000 00000000

Negative zero H'80000000 H'80000000 00000000

Negative denormalized

number

H'80000001 to H'807FFFFF H'80000000 00000001 to

H'800FFFFF FFFFFFFF

Negative normalized

number

H'80800000 to H'FF7FFFFF H'80100000 00000000 to

H'FFEFFFFF FFFFFFFF

Negative infinity H'FF800000 H'FFF00000 00000000

Quiet non-number H'FF800001 to H'FFBFFFFF H'FFF00000 00000001 to

H'FFF7FFFF FFFFFFFF

Signaling non-number H'FFC00000 to H'FFFFFFFF H'FFF80000 00000000 to

H'FFFFFFFF FFFFFFFF

6.2.2 Non-Numbers (NaN)

Figure 6.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case:

• Sign bit: Don't care

• Exponent field: All bits are 1

• Fraction field: At least one bit is 1

The NaN is a signaling NaN (sNaN) if the MSB of the fraction field is 1, and a quiet NaN (qNaN)

if the MSB is 0.

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x 11111111 Nxxxxxxxxxxxxxxxxxxxxxx

30 23 22 0

N = 1: sNaN

N = 0: qNaN

Figure 6.3 Single-Precision NaN Bit Pattern

An sNaN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point

value.

• When the EN.V bit in the FPSCR register is 0, the operation result (output) is a qNaN.

• When the EN.V bit in the FPSCR register is 1, an invalid operation exception will be

generated. In this case, the contents of the operation destination register are unchanged.

If a qNaN is input in an operation that generates a floating-point value, and an sNaN has not been

input in that operation, the output will always be a qNaN irrespective of the setting of the EN.V bit

in the FPSCR register. An exception will not be generated in this case.

The qNAN values generated by the FPU as operation results are as follows:

• Single-precision qNaN: H'7FBFFFFF

• Double-precision qNaN: H'7FF7FFFF FFFFFFFF

See the individual instruction descriptions for details of floating-point operations when a non-

number (NaN) is input.

6.2.3 Denormalized Numbers

For a denormalized number floating-point value, the exponent field is expressed as 0, and the

fraction field as a non-zero value.

When the DN bit in the FPU's status register FPSCR is 1, a denormalized number (source operand

or operation result) is always flushed to 0 in a floating-point operation that generates a value (an

operation other than copy, FNEG, or FABS).

When the DN bit in FPSCR is 0, a denormalized number (source operand or operation result) is

processed as it is. See the individual instruction descriptions for details of floating-point

operations when a denormalized number is input.

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6.3 Registers

6.3.1 Floating-Point Registers

Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floating-

point registers, referenced by specifying FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–

XF15, XD0/2/4/6/8/10/12/14, or XMTRX.

1. Floating-point registers, FPRi_BANKj (32 registers)

FPR0_BANK0–FPR15_BANK0

FPR0_BANK1–FPR15_BANK1

2. Single-precision floating-point registers, FRi (16 registers)

When FPSCR.FR = 0, FR0–FR15 indicate FPR0_BANK0–FPR15_BANK0;

when FPSCR.FR = 1, FR0–FR15 indicate FPR0_BANK1–FPR15_BANK1.

3. Double-precision floating-point registers, DRi (8 registers): A DR register comprises two FR

registers

DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7},

DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15}

4. Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises

four FR registers

FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7},

FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15}

5. Single-precision floating-point extended registers, XFi (16 registers)

When FPSCR.FR = 0, XF0–XF15 indicate FPR0_BANK1–FPR15_BANK1;

when FPSCR.FR = 1, XF0–XF15 indicate FPR0_BANK0–FPR15_BANK0.

6. Double-precision floating-point extended registers, XDi (8 registers): An XD register

comprises two XF registers

XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7},

XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15}

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7. Single-precision floating-point extended register matrix: XMTRX

XMTRX comprises all 16 XF registers

XMTRX = XF0 XF4 XF8 XF12

XF1 XF5 XF9 XF13

XF2 XF6 XF10 XF14

XF3 XF7 XF11 XF15

FPR0 _BANK0

FPR1_BANK0

FPR2_BANK0

FPR3_BANK0

FPR4_BANK0

FPR5_BANK0

FPR6_BANK0

FPR7_BANK0

FPR8_BANK0

FPR9_BANK0

FPR10_BANK0

FPR11_BANK0

FPR12_BANK0

FPR13_BANK0

FPR14_BANK0

FPR15_BANK0

XF0

XF1

XF2

XF3

XF4

XF5

XF6

XF7

XF8

XF9

XF10

XF11

XF12

XF13

XF14

XF15

FR0

FR1

FR2

FR3

FR4

FR5

FR6

FR7

FR8

FR9

FR10

FR11

FR12

FR13

FR14

FR15

DR0

DR2

DR4

DR6

DR8

DR10

DR12

DR14

FV0

FV4

FV8

FV12

XD0 XMTRX

XD2

XD4

XD6

XD8

XD10

XD12

XD14

FPR0_BANK1

FPR1_BANK1

FPR2_BANK1

FPR3_BANK1

FPR4_BANK1

FPR5_BANK1

FPR6_BANK1

FPR7_BANK1

FPR8_BANK1

FPR9_BANK1

FPR10_BANK1

FPR11_BANK1

FPR12_BANK1

FPR13_BANK1

FPR14_BANK1

FPR15_BANK1

XF0

XF1

XF2

XF3

XF4

XF5

XF6

XF7

XF8

XF9

XF10

XF11

XF12

XF13

XF14

XF15

FR0

FR1

FR2

FR3

FR4

FR5

FR6

FR7

FR8

FR9

FR10

FR11

FR12

FR13

FR14

FR15

DR0

DR2

DR4

DR6

DR8

DR10

DR12

DR14

FV0

FV4

FV8

FV12

XD0XMTRX

XD2

XD4

XD6

XD8

XD10

XD12

XD14

FPSCR.FR = 0 FPSCR.FR = 1

Figure 6.4 Floating-Point Registers

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6.3.2 Floating-Point Status/Control Register (FPSCR)

Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001)

31 22 21 20 19 18 17 12 11 7 6 2 1 0

— FR SZ PR DN Cause Enable Flag RM

Note: —: Reserved. These bits are always read as 0, and should only be written with 0.

• FR: Floating-point register bank

FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15; FPR0_BANK1–

FPR15_BANK1 are assigned to XF0–XF15.

FR = 1: FPR0_BANK0–FPR15_BANK0 are assigned to XF0–XF15; FPR0_BANK1–

FPR15_BANK1 are assigned to FR0–FR15.

• SZ: Transfer size mode

SZ = 0: The data size of the FMOV instruction is 32 bits.

SZ = 1: The data size of the FMOV instruction is a 32-bit register pair (64 bits).

• PR: Precision mode

PR = 0: Floating-point instructions are executed as single-precision operations.

PR = 1: Floating-point instructions are executed as double-precision operations (graphics

support instructions are undefined).

Do not set SZ and PR to 1 simultaneously; this setting is reserved.

[SZ, PR = 11]: Reserved (FPU operation instruction is undefined.)

• DN: Denormalization mode

DN = 0: A denormalized number is treated as such.

DN = 1: A denormalized number is treated as zero.

• Cause: FPU exception cause field

• Enable: FPU exception enable field

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• Flag: FPU exception flag field

FPU

Error (E)

Invalid

Operation (V)

Division

by Zero (Z)

Overflow

(O)

Underflow

(U)

Inexact

(I)

Cause FPU exception

cause field

Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12

Enable FPU exception

enable field

None Bit 11 Bit 10 Bit 9 Bit 8 Bit 7

Flag FPU exception

flag field

None Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

When an FPU operation instruction is executed, the FPU exception cause field is cleared to

zero first. When the next FPU exception is occured, the corresponding bits in the FPU

exception cause field and FPU exception flag field are set to 1. The FPU exception flag field

holds the status of the exception generated after the field was last cleared.

• RM: Rounding mode

RM = 00: Round to Nearest

RM = 01: Round to Zero

RM = 10: Reserved

RM = 11: Reserved

• Bits 22 to 31: Reserved

These bits are always read as 0, and should only be written with 0.

6.3.3 Floating-Point Communication Register (FPUL)

Information is transferred between the FPU and CPU via the FPUL register. The 32-bit FPUL

instructions. For example, to convert the integer stored in general register R1 to a single-precision

floating-point number, the processing flow is as follows:

R1 → (LDS instruction) → FPUL → (single-precision FLOAT instruction) → FR1

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6.4 Rounding

In a floating-point instruction, rounding is performed when generating the final operation result

from the intermediate result. Therefore, the result of combination instructions such as FMAC,

FTRV, and FIPR will differ from the result when using a basic instruction such as FADD, FSUB,

or FMUL. Rounding is performed once in FMAC, but twice in FADD, FSUB, and FMUL.

There are two rounding methods, the method to be used being determined by the RM field in

FPSCR.

• RM = 00: Round to Nearest

• RM = 01: Round to Zero

Round to Nearest: The value is rounded to the nearest expressible value. If there are two nearest

expressible values, the one with an LSB of 0 is selected.

If the unrounded value is 2Emax (2 – 2–P) or more, the result will be infinity with the same sign as the

unrounded value. The values of Emax and P, respectively, are 127 and 24 for single-precision, and

1023 and 53 for double-precision.

Round to Zero: The digits below the round bit of the unrounded value are discarded.

If the unrounded value is larger than the maximum expressible absolute value, the value will be

the maximum expressible absolute value.

6.5 Floating-Point Exceptions

FPU-related exceptions are as follows:

• General illegal instruction/slot illegal instruction exception

The exception occurs if an FPU instruction is executed when SR.FD = 1.

• FPU exceptions

The exception sources are as follows:

⎯ FPU error (E): When FPSCR.DN = 0 and a denormalized number is input

⎯ Invalid operation (V): In case of an invalid operation, such as NaN input

⎯ Division by zero (Z): Division with a zero divisor

⎯ Overflow (O): When the operation result overflows

⎯ Underflow (U): When the operation result underflows

⎯ Inexact exception (I): When overflow, underflow, or rounding occurs

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The FPSCR cause field contains bits corresponding to all of above sources E, V, Z, O, U, and

I, and the FPSCR flag and enable fields contain bits corresponding to sources V, Z, O, U, and

I, but not E. Thus, FPU errors cannot be disabled.

When an exception source occurs, the corresponding bit in the cause field is set to 1, and 1 is

added to the corresponding bit in the flag field. When an exception source does not occur, the

corresponding bit in the cause field is cleared to 0, but the corresponding bit in the flag field

remains unchanged.

• Enable/disable exception handling

The FPU supports enable exception handling and disable exception handling.

Enable exception handling is initiated in the following cases:

⎯ FPU error (E): FPSCR.DN = 0 and a denormalized number is input

⎯ Invalid operation (V): FPSCR.EN.V = 1 and (instruction = FTRV or invalid operation)

⎯ Division by zero (Z): FPSCR.EN.Z = 1 and division with a zero divisor

⎯ Overflow (O): FPSCR.EN.O = 1 and instruction with possibility of operation result

overflow

⎯ Underflow (U): FPSCR.EN.U = 1 and instruction with possibility of operation result

underflow

⎯ Inexact exception (I): FPSCR.EN.I = 1 and instruction with possibility of inexact operation

result

For information on these possibilities, see the individual instruction descriptions in chapter 9 of

the SH-4 Software Manual. The particulars differ demanding on the instruction. All exception

events that originate in the FPU are assigned as the same exception event. The meaning of an

exception is determined by software by reading system register FPSCR and interpreting the

information it contains. If no bits are set in the cause field of FPSCR when one or more of bits

O, U, I, and V (in case of FTRV only) are set in the enable field, this indicates that an actual

exception source is not generated. Also, the destination register is not changed by any enable

exception handling operation.

Except for the above, the FPU disables exception handling. In all processing, the bit

corresponding to source V, Z, O, U, or I is set to 1, and disable exception handling is provided

for each exception.

⎯ Invalid operation (V): qNAN is generated as the result.

⎯ Division by zero (Z): Infinity with the same sign as the unrounded value is generated.

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⎯ Overflow (O):

When rounding mode = RZ, the maximum normalized number, with the same sign as the

unrounded value, is generated.

When rounding mode = RN, infinity with the same sign as the unrounded value is

generated.

⎯ Underflow (U):

When FPSCR.DN = 0, a denormalized number with the same sign as the unrounded value,

or zero with the same sign as the unrounded value, is generated.

When FPSCR.DN = 1, zero with the same sign as the unrounded value, is generated.

⎯ Inexact exception (I): An inexact result is generated.

6.6 Graphics Support Functions

The FPU supports two kinds of graphics functions: new instructions for geometric operations, and

pair single-precision transfer instructions that enable high-speed data transfer.

6.6.1 Geometric Operation Instructions

Geometric operation instructions perform approximate-value computations. To enable high-speed

computation with a minimum of hardware, the FPU ignores comparatively small values in the

partial computation results of four multiplications. Consequently, the error shown below is

produced in the result of the computation:

Maximum error = MAX (individual multiplication result ×

–MIN (number of multiplier significant digits–1, number of multiplicand significant digits–1)) + MAX (result value × 2–23, 2–149)

The number of significant digits is 24 for a normalized number and 23 for a denormalized number

(number of leading zeros in the fractional part).

In future version of SuperH RISC engine family, the above error is guaranteed, but the same result

as SH7750 is not guaranteed.

FIPR FVm, FVn (m, n: 0, 4, 8, 12): This instruction is basically used for the following purposes:

• Inner product (m ≠ n):

This operation is generally used for surface/rear surface determination for polygon surfaces.

• Sum of square of elements (m = n):

This operation is generally used to find the length of a vector.

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Since approximate-value computations are performed to enable high-speed computation, the

inexact exception (I) bit in the cause field and flag field is always set to 1 when an FIPR

instruction is executed. Therefore, if the corresponding bit is set in the enable field, enable

exception handling will be executed.

FTRV XMTRX, FVn (n: 0, 4, 8, 12): This instruction is basically used for the following

purposes:

• Matrix (4 × 4) ⋅ vector (4):

This operation is generally used for viewpoint changes, angle changes, or movements called

vector transformations (4-dimensional). Since affine transformation processing for angle +

parallel movement basically requires a 4 × 4 matrix, the FPU supports 4-dimensional

operations.

• Matrix (4 × 4) × matrix (4 × 4):

This operation requires the execution of four FTRV instructions.

Since approximate-value computations are performed to enable high-speed computation, the

inexact exception (I) bit in the cause field and flag field is always set to 1 when an FTRV

instruction is executed. Therefore, if the corresponding bit is set in the enable field, enable

exception handling will be executed. For the same reason, it is not possible to check all data types

in the registers beforehand when executing an FTRV instruction. If the V bit is set in the enable

field, enable exception handling will be executed.

FRCHG: This instruction modifies banked registers. For example, when the FTRV instruction is

executed, matrix elements must be set in an array in the background bank. However, to create the

actual elements of a translation matrix, it is easier to use registers in the foreground bank. When

the LDC instruction is used on FPSCR, this instruction expends 4 to 5 cycles in order to maintain

the FPU state. With the FRCHG instruction, an FPSCR.FR bit modification can be performed in

one cycle.

6.6.2 Pair Single-Precision Data Transfer

In addition to the geometric operation instructions, the FPU also supports high-speed data transfer

instructions.

When FPSCR.SZ = 1, the FPU can perform data transfer by means of pair single-precision data

transfer instructions.

• FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14)

• FMOV DRm/XDm, @Rn (m: 0, 2, 4, 6, 8, 10, 12, 14; n: 0 to 15)

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These instructions enable two single-precision (2 × 32-bit) data items to be transferred; that is, the

transfer performance of these instructions is doubled.

• FSCHG

This instruction changes the value of the SZ bit in FPSCR, enabling fast switching between use

and non-use of pair single-precision data transfer.

Programming Note:

When FPSCR.SZ = 1 and big-endian mode is used, FMOV can be used for a double-precision

floating-point load or store. In little-endian mode, a double-precision floating-point load or store

requires execution of two 32-bit data size operations with FPSCR.SZ = 0.

6.7 Usage Notes

6.7.1 Rounding Mode and Underflow Flag

When using the Round to Nearest rounding mode, the underflow flag may not be set in cases

defined as underflow by the IEEE754 standard.

Under the IEEE754 standard, when the Round to Nearest rounding mode is used and infinite-

precision operation result x is (i) or (ii) (single-precision) or (iii) or (iv) (double-precision), there

are cases where “the result after rounding is a normalized number, but an underflow results.”

In such cases where “the result after rounding is a normalized number, but an underflow results,”

the FPU does not set the underflow flag to 1. In these cases the operation result, the value written

to FRn, is correct. Also, if an FPU exception occurs, the underflow flag is not set to 1 but the

inexact flag is set to 1 in such cases. Generation of FPU exceptions can be enabled by setting the

enable field to 1.

(i) H'007FFFFF < x < H'00800000

(ii) H'807FFFFF > x > H'80800000

(iii) H'000FFFFF FFFFFFFF < x < H'00100000 00000000

(iv) H'800FFFFF FFFFFFFF > x > H'80100000 00000000

Examples

• Single-precision

When FPSCR.RM = 00 (Round to Nearest) and FPSCR.PR = 0 (single-precision), and the

FMUL instruction (H'00FFF000 * H'3F000800) is executed.

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a. According to IEEE754 standard

Operation result: H'00800000

FPSCR: H'0004300C

b. FPU

Operation result: H'00800000

FPSCR: H'00041004

• Double-precision

When FPSCR.RM = 00 (Round to Nearest) and FPSCR.PR = 1 (double-precision), and the

FDIV instruction (H'001FFFFF FFFFFFFF / H'40000000 00000000) is executed.

a. According to IEEE754 standard

Operation result: H'00100000 00000000

FPSCR: H'000C300C

b. FPU

Operation result: H'00100000 00000000

FPSCR: H'000C1004

Workarounds

1. Use FPSCR.RM = 01, that is to say Round to Zero rather than Round to Nearest mode.

2. Use FPSCR.RM = 00, that is to say Round to Nearest mode, and set the enable field to 1 to

enable generation of inexact exceptions so that the exception handling routine can be used to

check whether or not an underflow has occurred.

6.7.2 Setting of Overflow Flag by FIPR or FTRV Instruction

When the maximum error produced by the FIPR or FTRV instruction exceeds the maximum value

expressible as a normalized number (H'7F7FFFFF), the overflow flag may be set, even through

the operation result is a positive or negative zero (H'00000000 or H'80000000).

Example: The operation result (FR7) after executing the instruction FIPR FV4, FV0 is

H'00000000 (positive zero), but the overflow flag may be set nevertheless.

FPSCR = H'00040001

FR0 = H'FF7EF631 , FR1 = H80000000 , FR2 = H'8087F451 , FR3 = H'7F7EF631

FR4 = H'7F7EF631 , FR5 = H'0087F451 , FR6 = H'7F7EF631 , FR7 = H'7F7EF631

Workaround: Avoid using the FIPR and FTRV instructions, and use the FADD, FMUL, and

FMAC instructions instead.

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6.7.3 Sign of Operation Result when Using FIPR or FTRV Instruction

When two or more data items used in an operation by the FIPR or FTRV instruction are infinity,

and all of the infinity items in the multiplication results have the same sign, the sign of the

operation result may be incorrect.

Workarounds

1. Do not use infinity. If conditions a. to c. below are satisfied, infinity is never used in

operations.

a. Use Round to Zero (FPSCR.RM = 01) as the rounding mode.

b. Do not divide by zero.

c. Do not transfer a value of positive or negative infinity to FR0 to FR15 or to XF0 to XF15.

2. Avoid using the FIPR and FTRV instructions, and use the FADD, FMUL, and FMAC

instructions instead.

6.7.4 Notes on Double-Precision FADD and FSUB Instructions

Description: If the input data for a double-precision FADD instruction or a double-precision

FSUB instruction satisfies all of the conditions listed below, the inexact bits (FPSCR.Flag.I and

FPSCR.Cause.I) may not be set even through the operation result is inexact.

Condition 1: The operation instruction is a double-precision FADD instruction or a double-

precision FSUB instruction.

Condition 2: The difference between the DRn and DRm exponents is between 43 and 50.

Condition 3: At least one of bits 31 to 24 of the mantissa portion of whichever of DRn and DRm

has the smaller absolute value is 1.

Condition 4: Bits 23 to 0 of the mantissa portion of whichever of DRn and DRm has the smaller

absolute value are all 0.

Condition 5: Bits 40 to 32 of the mantissa portion of whichever of DRn and DRm has the smaller

absolute value are all 0.

In addition, the result of an operation meeting the above conditions may have a rounding error.

Specifically, in a case where the closest expressible value less than the unrounded value should be

selected, the closest expressible value greater than the unrounded value is selected instead.

Conversely, in a case where the closest expressible value greater than the unrounded value should

be selected, the closest expressible value less than the unrounded value is selected instead.

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Example: If the double-precision FSUB instruction (FSUB DR0, DR2) is executed with input

data DR0 = H'C1F00000 80000000, DR2 = H'C4B250D2 0CC1FB74, and FPSCR = H'000C0001,

the correct operation result is DR2 = H'C4B250D2 0CC1F973, and FPSCR.Flag.I and

FPSCR.Cause.I should be set to 1. However, the result actually produced by the FPU is DR2 =

H'C4B250D2 0CC1F974, and FPSCR.Flag.I and FPSCR.Cause.I are not set to 1.

Effects: In addition to the problem described above, the numerical size of the result of the

operation may contain a minute operation error equivalent to 1/256 of the LSB of the mantissa of

the unrounded value. This is can be described as within the scope of the subsequent rounding

mechanism. Strictly speaking, it consists of the following.

a: The infinite-precision operation result

b: The closest expressible value less than a

c: The closest expressible value greater than a

d: The operation result when a is rounded correctly

e: The operation result when a is rounded by the FPU

• The rounding error when rounding is performed correctly in Round to Nearest mode is:

0 ≤ | d − a | ≤ (1/2) × (c − b)

And the rounding error when rounding is performed by the FPU is:

0 ≤ | e − a | < (129/256) × (c − b)

If c – b is considered the LSB of the mantissa, the range of rounding error is equivalent to

1/256 of the LSB of the mantissa of the correctly rounded value.

• The rounding error when rounding is performed correctly in Round to Zero mode is:

(−1) × (c − b) < | d |−| a | ≤ 0

And the rounding error when rounding is performed by the FPU is:

(−1) × (c − b) < | e |−| a | < (1/256) × (c − b)

If c – b is considered the LSB of the mantissa, the range of rounding error is equivalent to

1/256 of the LSB of the mantissa of the correctly rounded value.

6.7.5 Notes on FPU Double-Precision Operation Instructions (SH7750 Only)

The operation result may be incorrect when denormalized numbers are used as input with a

double-precision FDIV, FADD, FSUB, or FMUL instruction, even in the mode capable of

handling denormalized numbers.

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This problem affects applications in science and engineering where extreme precision is required.

It is limited to cases where double-precision floating-point instructions are used to handle

denormalized numbers. The problem does not affect cases where double-precision floating-point

instructions are used but denormalized numbers are treated as zero, or cases where only single-

precision floating-point instructions are used.

Examples: The problem manifests itself in either of two ways. In one type of case a. and b. the

result is incorrect when denormalized numbers are used as input. In the other c. the result is

incorrect when a denormalized number and qNaN are used as input.

a. When the input for a double-precision FDIV instruction includes a denormalized number, an

incorrect result of zero or infinity may be generated.

b. When the input for a double-precision FMUL instruction includes a denormalized number, an

incorrect result of infinity may be generated.

c. When the input for a double-precision FDIV, FADD, FSUB, or FMUL instruction consists of a

denormalized number and qNaN, the result may be incorrect.

Effects: The effect of the problem is greatest in cases where denormalized numbers are used as

input with a double-precision FDIV or FMUL instruction, and an incorrect value is written to a

such as denormalized number / denormalized number = 0 or denormalized number / 0 = 0.

Workarounds: Ordinarily, workaround 1. may be used. Workaround 2. is for calculations in

science or engineering applications where extreme precision and the use of denormalized numbers

are necessary.

1. When using double-precision floating-point instructions, set FPSCR.DN to 1 to select the

mode in which denormalized numbers are treated as 0.

This workaround does not result in any decrease in performance.

2. Avoid cases where using denormalized numbers as input produce incorrect results a. and b. by

means of software. Refer to “Modifying Software” below for details.

(i) Save the contents of the source and destination registers (DRn).

(ii) When a double-precision FDIV instruction generates a result of zero or infinity, call a user-

specified function for processing denormalized numbers.

Use a TRAP routine to avoid cases where an incorrect result is generated when using a

denormalized number and qNaN as input c.. Refer to “Modifying a TRAP Routine” below for

details.

(i) When the input for a double-precision FDIV, FADD, FSUB, or FMUL instruction consists

of a denormalized number and qNaN, use a TRAP routine to write the value of qNaN

(H'7FF7FFFF_FFFFFFFF) to the destination register.

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Details

Definitions: The data patterns that cause the problem are defined below. Item (A) to (D) in the

tables correspond to the following data patterns.

• Double-precision denormalized number (A)

H'00000000_XXXXXXXX or H'80000000_XXXXXXXX (X: 0 or 1)

However, H'XXXXXXXX != H'00000000

• Double-precision denormalized number (B)

H'000YYYYY_XXXXXXXX or H'800YYYYY_XXXXXXXX (X: 0 or 1)

However, H'YYYYY != H'00000

• Double-precision qNaN (C)

However, H'XXXXXXXX != H'00000000

• Double-precision qNaN (D) Note: As defined

H'7FFXXXXX_XXXXXXXX or H'FFFXXXXX_XXXXXXXX (X: 0 or 1)

However, H'XXXXX_XXXXXXXX != H'00000_00000000

Incorrect Operation Results: Table 6.3 lists instructions and data combinations that produce

incorrect operation results when FPSCR.DN = I'b0 (mode in which denormalized numbers are

treated as denormalized numbers).

Input items (A) to (C) are the data patterns defined in “Definitions” above, and problem types (1)

to (7) correspond to the incorrect operation results classified in tables 6.4 to 6.6.

The incorrect operation results for problem types (1), (2), (3), and (7) are zero or infinity.

In problem types (4), (5), and (6), an FPU error exception trap is generated and no value is output

for qNaN.

Case (a) corresponds to problem types (1), (2), and (3); case (b) corresponds to (7); and case (c)

corresponds to (4), (5), and (6).

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Table 6.3 Incorrect Operation Result

Input

Problem Type Instruction DRm DRn SH-4

Expected

Value

(1) FDIV +0/–0 (A) DENORM +0/–0 DZ

(A) DENORM +0/–0 (2) FDIV

(A) DENORM (A) DENORM

+0/–0 FPU Error

(3) FDIV (A) DENORM +INF/–INF +INF/–INF FPU Error

(4) FDIV

(B) DENORM (C) qNaN

FPU Error qNaN*

DENORM (C) qNaN

FPU Error qNaN*

(B) DENORM (C) qNaN

FPU Error qNaN*

(A) DENORM +INF/–INF (7) FMUL

+INF/–INF (A) DENORM

+INF/–INF FPU Error

Note: * qNaN: H'7FF7FFFF_FFFFFFFF

The above operations complete normally when FPSCR.DN = 1.

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Special cases involving double-precision FDIV, FADD, FSUB, and FMUL instructions are

summarized below.

: Shaded portion indicates normal operation.

: Unshaded portion indicates incorrect operation result, and FPU output values are listed

Table 6.4 FDIV DRm, DRn (DRn/DRm → DRn)

DRn

DRm NORM

DIV

Invalid

−0

+INF

INF

+INF

INF

Invalid

−INF

INF

+INF

(A)

Positive

DENORM

+0 (1)

−0 (1)

(A)

Negative

DENORM

Error

−0 (1)

+0 (1)

Error

(B)

DENORM

(C)

qNaN

(D)

qNaN sNaN

Invalid

NORM

−0

+INF

−INF

(A) Positive

DENORM

(A) Negative

DENORM

(B) DENORM

(D) qNaN

sNaN

−0 (2)

+0 (2)

−0 (2)

Error (4)

+0 (2)

−0 (2)

(3)

+INF

(3)

−INF

(3)

−INF

(3)

+INF

Error (4)

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Table 6.5 FADD DRm, DRn (DRn + DRm → DRn)

FSUB DRm, DRn (DRn − DRm → DRn)

DRn

DRm NORM

ADD

−INF

−0

+INF

Invalid

−INF

Invalid

−INF

(A)

Positive

DENORM

(A)

Negative

DENORM

Error

(B)

DENORM

(C)

qNaN

(D)

qNaN sNaN

Invalid

NORM

−0

+INF

−INF

(A) Positive

DENORM

(A) Negative

DENORM

(B) DENORM

(D) qNaN

sNaN

Error (5)

Table 6.6 FMUL DRm, DRn (DRn*DRm → DRn)

DRn

DRm NORM

MUL

INF

−0

Invalid

−0

+INF

INF

Invalid

+INF

−INF

+INF

(A)

Positive

DENORM

+INF (7)

−INF (7)

(A)

Negative

DENORM

Error

−INF (7)

+INF (7)

(B)

DENORM

(C)

qNaN

(D)

qNaN sNaN

Invalid

NORM

−0

+INF

−INF

(A) Positive

DENORM

(A) Negative

DENORM

(B) DENORM

(D) qNaN

sNaN

Error (6)

+INF

(7)

−INF

(7)

−INF

(7)

+INF

(7)

Error (6)

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Modifying Software

Problem types (1), (2), and (3): Deal with problem types (1), (2), and (3) in table 6.3 using

software based on the flowchart below.

Adjust the source operands by multiplying them by 21536, then calculate them as normalized

numbers.

In the case of problem type (1), if the Divide by Zero exception is enabled, the divide by zero

exception trap is generated and the destination register does not change. If the Divide by Zero

exception is disabled, the contents of the destination register become infinity with the sign based

on the input operands.

Is operation result

±INF or ±0?

Yes

START

END

Save source DRn

FDIV DRm, DRn

Problem type (1), (2),

or (3)?

Yes

Restore source DRn

DRm × 2

1536

, DRn × 2

1536

FDIV DRm, DRn

Problem type (7): In the case of problem type (7) in table 6.3, no FPU error occurs. The operation

result is correct and there is no need for a software workaround.

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Modifying a TRAP Routine: For problem types (4), (5), and (6) in table 6.3, add code to the

TRAP routine to check the instruction and input data as indicated in table 6.7 and to write the

contents of qNaN to the destination register.

In this case the value of qNaN must always be H'7FF7FFFF_FFFFFFFF.

Table 6.7 TRAP Routine Processing

Input Check

Problem Type Instruction Check DRm DRn

Operation Result

FDIV qNaN DENORM qNaN

(4)

FDIV DENORM qNaN qNaN

FADD/FSUB qNaN DENORM qNaN (5)

FADD/FSUB DENORM qNaN qNaN

FMUL qNaN DENORM qNaN (6)

FMUL DENORM qNaN qNaN

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Section 7 Instruction Set

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Section 7 Instruction Set

7.1 Execution Environment

PC: At the start of instruction execution, PC indicates the address of the instruction itself.

Data sizes and data types: The SH-4's instruction set is implemented with 16-bit fixed-length

instructions. The SH-4 can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-

bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved to

and from memory using longword or quadword size. Double-precision floating-point data (64 bits)

can be moved to and from memory using longword size. When a double-precision floating-point

operation is specified (FPSCR.PR = 1), the result of an operation using quadword access will be

undefined. When the SH-4 moves byte-size or word-size data from memory to a register, the data

is sign-extended.

Load-Store Architecture: The SH-4 features a load-store architecture in which operations are

basically executed using registers. Except for bit-manipulation operations such as logical AND

that are executed directly in memory, operands in an operation that requires memory access are

loaded into registers and the operation is executed between the registers.

Delayed Branches: Except for the two branch instructions BF and BT, the SH-4's branch

instructions and RTE are delayed branches. In a delayed branch, the instruction following the

branch is executed before the branch destination instruction. This execution slot following a

delayed branch is called a delay slot. For example, the BRA execution sequence is as follows:

Static Sequence Dynamic Sequence

BRA TARGET BRA TARGET

ADD R1, R0

next_2

ADD R1, R0

target_instr

ADD in delay slot is executed before

branching to TARGET

Delay Slot: An illegal instruction exception may occur when a specific instruction is executed in a

delay slot. See section 5, Exceptions. The instruction following BF/S or BT/S for which the

branch is not taken is also a delay slot instruction.

T Bit: The T bit in the status register (SR) is used to show the result of a compare operation, and

is referenced by a conditional branch instruction. An example of the use of a conditional branch

instruction is shown below.

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ADD #1, R0 ; T bit is not changed by ADD operation

CMP/EQ R1, R0 ; If R0 = R1, T bit is set to 1

BT TARGET ; Branches to TARGET if T bit = 1 (R0 = R1)

In an RTE delay slot, status register (SR) bits are referenced as follows. In instruction access, the

MD bit is used before modification, and in data access, the MD bit is accessed after modification.

The other bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot

instruction execution. The STC and STC.L SR instructions access all SR bits after modification.

Constant Values: An 8-bit constant value can be specified by the instruction code and an

immediate value. 16-bit and 32-bit constant values can be defined as literal constant values in

memory, and can be referenced by a PC-relative load instruction.

MOV.W @(disp, PC), Rn

MOV.L @(disp, PC), Rn

There are no PC-relative load instructions for floating-point operations. However, it is possible to

set 0.0 or 1.0 by using the FLDI0 or FLDI1 instruction on a single-precision floating-point

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7.2 Addressing Modes

Addressing modes and effective address calculation methods are shown in table 7.1. When a

location in virtual memory space is accessed (MMUCR.AT = 1), the effective address is translated

into a physical memory address. If multiple virtual memory space systems are selected

(MMUCR.SV = 0), the least significant bit of PTEH is also referenced as the access ASID. See

section 3, Memory Management Unit (MMU).

Table 7.1 Addressing Modes and Effective Addresses

Addressing

Mode

Instruction

Format

Effective Address Calculation Method

Calculation

Formula

direct

Rn Effective address is register Rn.

(Operand is register Rn contents.)

—

indirect

@Rn Effective address is register Rn contents.

Rn Rn

Rn → EA

(EA: effective

address)

indirect

with post-

increment

@Rn+ Effective address is register Rn contents.

A constant is added to Rn after instruction

execution: 1 for a byte operand, 2 for a word

operand, 4 for a longword operand, 8 for a

quadword operand.

Rn Rn

1/2/4/8

Rn + 1/2/4/8

Rn → EA

After instruction

execution

Byte:

Rn + 1 → Rn

Word:

Rn + 2 → Rn

Longword:

Rn + 4 → Rn

Quadword:

Rn + 8 → Rn

indirect

with pre-

decrement

@–Rn Effective address is register Rn contents,

decremented by a constant beforehand:

1 for a byte operand, 2 for a word operand,

4 for a longword operand, 8 for a quadword

operand.

1/2/4/8

Rn – 1/2/4/8

–

Rn – 1/2/4/8

Byte:

Rn – 1 → Rn

Word:

Rn – 2 → Rn

Longword:

Rn – 4 → Rn

Quadword:

Rn – 8 → Rn

Rn → EA

(Instruction

executed

with Rn after

calculation)

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Addressing

Mode

Instruction

Format

Effective Address Calculation Method

Calculation

Formula

indirect with

displacement

@(disp:4, Rn) Effective address is register Rn contents with

4-bit displacement disp added. After disp is

zero-extended, it is multiplied by 1 (byte), 2 (word),

or 4 (longword), according to the operand size.

Rn + disp × 1/2/4

1/2/4

disp

(zero-extended)

Byte: Rn +

disp → EA

Word: Rn +

disp × 2 → EA

Longword:

Rn + disp × 4

→ EA

Indexed

indirect

@(R0, Rn) Effective address is sum of register Rn and R0

contents.

Rn + R0

Rn + R0 → EA

GBR indirect

with

displacement

@(disp:8,

GBR)

Effective address is register GBR contents with

8-bit displacement disp added. After disp is

zero-extended, it is multiplied by 1 (byte), 2 (word),

or 4 (longword), according to the operand size.

GBR

1/2/4

GBR

+ disp × 1/2/4

disp

(zero-extended)

Byte: GBR +

disp → EA

Word: GBR +

disp × 2 → EA

Longword:

GBR + disp ×

4 → EA

Indexed

GBR indirect

@(R0, GBR) Effective address is sum of register GBR and R0

contents.

GBR

GBR + R0

GBR + R0 →

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Addressing

Mode

Instruction

Format

Effective Address Calculation Method

Calculation

Formula

PC-relative

with

displacement

@(disp:8, PC) Effective address is PC+4 with 8-bit displacement

disp added. After disp is zero-extended, it is

multiplied by 2 (word), or 4 (longword), according

to the operand size. With a longword operand,

the lower 2 bits of PC are masked.

H'FFFFFFFC

PC + 4 + disp

× 2

or PC &

H'FFFFFFFC

+ 4 + disp × 4

2/4

disp

(zero-extended)

* With longword operand

Word: PC + 4

+ disp × 2 →

Longword:

PC &

H'FFFFFFFC

+ 4 + disp × 4

→ EA

PC-relative disp:8 Effective address is PC+4 with 8-bit displacement

disp added after being sign-extended and

multiplied by 2.

disp

(sign-extended)

PC + 4 + disp × 2

PC + 4 + disp

× 2 → Branch-

Target

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Addressing

Mode

Instruction

Format

Effective Address Calculation Method

Calculation

Formula

PC-relative disp:12 Effective address is PC+4 with 12-bit displacement

disp added after being sign-extended and

multiplied by 2.

disp

(sign-extended)

PC + 4 + disp × 2

PC + 4 + disp

× 2 → Branch-

Target

Rn Effective address is sum of PC+4 and Rn.

+PC + 4 + Rn

PC + 4 + Rn

→ Branch-

Target

Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or

XOR instruction is zero-extended.

—

#imm:8 8-bit immediate data imm of MOV, ADD, or

CMP/EQ instruction is sign-extended.

—

#imm:8 8-bit immediate data imm of TRAPA instruction is

zero-extended and multiplied by 4.

—

Note: For the addressing modes below that use a displacement (disp), the assembler descriptions

in this manual show the value before scaling (×1, ×2, or ×4) is performed according to the

operand size. This is done to clarify the operation of the chip. Refer to the relevant

assembler notation rules for the actual assembler descriptions.

@ (disp:4, Rn) ; Register indirect with displacement

@ (disp:8, GBR) ; GBR indirect with displacement

@ (disp:8, PC) ; PC-relative with displacement

disp:8, disp:12 ; PC-relative

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7.3 Instruction Set

Table 7.2 shows the notation used in the following SH instruction list.

Table 7.2 Notation Used in Instruction List

Item Format Description

Instruction

mnemonic

OP.Sz SRC, DEST OP: Operation code

Sz: Size

SRC: Source

DEST: Source and/or destination operand

Summary of

operation

→, ←: Transfer direction

(xx): Memory operand

M/Q/T: SR flag bits

&: Logical AND of individual bits

|: Logical OR of individual bits

∧: Logical exclusive-OR of individual bits

~: Logical NOT of individual bits

<<n, >>n: n-bit shift

Instruction code MSB ↔ LSB mmmm: Register number (Rm, FRm)

nnnn: Register number (Rn, FRn)

0000: R0, FR0

0001: R1, FR1

1111: R15, FR15

mmm: Register number (DRm, XDm, Rm_BANK)

nnn: Register number (DRm, XDm, Rn_BANK)

000: DR0, XD0, R0_BANK

001: DR2, XD2, R1_BANK

111: DR14, XD14, R7_BANK

mm: Register number (FVm)

nn: Register number (FVn)

00: FV0

01: FV4

10: FV8

11: FV12

iiii: Immediate data

dddd: Displacement

Privileged mode “Privileged” means the instruction can only be executed

in privileged mode.

T bit Value of T bit after

instruction execution

—: No change

Note: Scaling (×1, ×2, ×4, or ×8) is executed according to the size of the instruction operand(s).

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Table 7.3 Fixed-Point Transfer Instructions

Instruction Operation Instruction Code Privileged T Bit

MOV #imm,Rn imm → sign extension → Rn 1110nnnniiiiiiii — —

MOV.W @(disp,PC),Rn (disp × 2 + PC + 4) → sign

extension → Rn

1001nnnndddddddd — —

MOV.L @(disp,PC),Rn (disp × 4 + PC & H'FFFFFFFC

+ 4) → Rn

1101nnnndddddddd — —

MOV Rm,Rn Rm → Rn 0110nnnnmmmm0011 — —

MOV.B Rm,@Rn Rm → (Rn) 0010nnnnmmmm0000 — —

MOV.W Rm,@Rn Rm → (Rn) 0010nnnnmmmm0001 — —

MOV.L Rm,@Rn Rm → (Rn) 0010nnnnmmmm0010 — —

MOV.B @Rm,Rn (Rm) → sign extension → Rn 0110nnnnmmmm0000 — —

MOV.W @Rm,Rn (Rm) → sign extension → Rn 0110nnnnmmmm0001 — —

MOV.L @Rm,Rn (Rm) → Rn 0110nnnnmmmm0010 — —

MOV.B Rm,@-Rn Rn-1 → Rn, Rm → (Rn) 0010nnnnmmmm0100 — —

MOV.W Rm,@-Rn Rn-2 → Rn, Rm → (Rn) 0010nnnnmmmm0101 — —

MOV.L Rm,@-Rn Rn-4 → Rn, Rm → (Rn) 0010nnnnmmmm0110 — —

MOV.B @Rm+,Rn (Rm)→ sign extension → Rn,

Rm + 1 → Rm

0110nnnnmmmm0100 — —

MOV.W @Rm+,Rn (Rm) → sign extension → Rn,

Rm + 2 → Rm

0110nnnnmmmm0101 — —

MOV.L @Rm+,Rn (Rm) → Rn, Rm + 4 → Rm 0110nnnnmmmm0110 — —

MOV.B R0,@(disp,Rn) R0 → (disp + Rn) 10000000nnnndddd — —

MOV.W R0,@(disp,Rn) R0 → (disp × 2 + Rn) 10000001nnnndddd — —

MOV.L Rm,@(disp,Rn) Rm → (disp × 4 + Rn) 0001nnnnmmmmdddd — —

MOV.B @(disp,Rm),R0 (disp + Rm) → sign extension

→ R0

10000100mmmmdddd — —

MOV.W @(disp,Rm),R0 (disp × 2 + Rm) → sign

extension → R0

10000101mmmmdddd — —

MOV.L @(disp,Rm),Rn (disp × 4 + Rm) → Rn 0101nnnnmmmmdddd — —

MOV.B Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0100 — —

MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0101 — —

MOV.L Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0110 — —

MOV.B @(R0,Rm),Rn (R0 + Rm) → sign extension

→ Rn

0000nnnnmmmm1100 — —

MOV.W @(R0,Rm),Rn (R0 + Rm) → sign extension

→ Rn

0000nnnnmmmm1101 — —

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Instruction Operation Instruction Code Privileged T Bit

MOV.L @(R0,Rm),Rn (R0 + Rm) → Rn 0000nnnnmmmm1110 — —

MOV.B R0,@(disp,GBR) R0 → (disp + GBR) 11000000dddddddd — —

MOV.W R0,@(disp,GBR) R0 → (disp × 2 + GBR) 11000001dddddddd — —

MOV.L R0,@(disp,GBR) R0 → (disp × 4 + GBR) 11000010dddddddd — —

MOV.B @(disp,GBR),R0 (disp + GBR) →

sign extension → R0

11000100dddddddd — —

MOV.W @(disp,GBR),R0 (disp × 2 + GBR) →

sign extension → R0

11000101dddddddd — —

MOV.L @(disp,GBR),R0 (disp × 4 + GBR) → R0 11000110dddddddd — —

MOVA @(disp,PC),R0 disp × 4 + PC & H'FFFFFFFC

+ 4 → R0

11000111dddddddd — —

MOVT Rn T → Rn 0000nnnn00101001 — —

SWAP.B Rm,Rn Rm → swap lower 2 bytes

→ Rn

0110nnnnmmmm1000 — —

SWAP.W Rm,Rn Rm → swap upper/lower

words → Rn

0110nnnnmmmm1001 — —

XTRCT Rm,Rn Rm:Rn middle 32 bits → Rn 0010nnnnmmmm1101 — —

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Table 7.4 Arithmetic Operation Instructions

Instruction Operation Instruction Code Privileged T Bit

ADD Rm,Rn Rn + Rm → Rn 0011nnnnmmmm1100 — —

ADD #imm,Rn Rn + imm → Rn 0111nnnniiiiiiii — —

ADDC Rm,Rn Rn + Rm + T → Rn, carry → T 0011nnnnmmmm1110 — Carry

ADDV Rm,Rn Rn + Rm → Rn, overflow → T 0011nnnnmmmm1111 — Overflow

CMP/EQ #imm,R0 When R0 = imm, 1 → T

Otherwise, 0 → T

10001000iiiiiiii — Comparison

result

CMP/EQ Rm,Rn When Rn = Rm, 1 → T

Otherwise, 0 → T

0011nnnnmmmm0000 — Comparison

result

CMP/HS Rm,Rn When Rn ≥ Rm (unsigned),

1 → T

Otherwise, 0 → T

0011nnnnmmmm0010 — Comparison

result

CMP/GE Rm,Rn When Rn ≥ Rm (signed), 1 → T

Otherwise, 0 → T

0011nnnnmmmm0011 — Comparison

result

CMP/HI Rm,Rn When Rn > Rm (unsigned),

1 → T

Otherwise, 0 → T

0011nnnnmmmm0110 — Comparison

result

CMP/GT Rm,Rn When Rn > Rm (signed), 1 → T

Otherwise, 0 → T

0011nnnnmmmm0111 — Comparison

result

CMP/PZ Rn When Rn ≥ 0, 1 → T

Otherwise, 0 → T

0100nnnn00010001 — Comparison

result

CMP/PL Rn When Rn > 0, 1 → T

Otherwise, 0 → T

0100nnnn00010101 — Comparison

result

CMP/STR Rm,Rn When any bytes are equal,

1 → T

Otherwise, 0 → T

0010nnnnmmmm1100 — Comparison

result

DIV1 Rm,Rn 1-step division (Rn ÷ Rm) 0011nnnnmmmm0100 — Calculation

result

DIV0S Rm,Rn MSB of Rn → Q,

MSB of Rm → M, M^Q → T

0010nnnnmmmm0111 — Calculation

result

DIV0U 0 → M/Q/T 0000000000011001 — 0

DMULS.L Rm,Rn Signed, Rn × Rm → MAC,

32 × 32 → 64 bits

0011nnnnmmmm1101 — —

DMULU.L Rm,Rn Unsigned, Rn × Rm → MAC,

32 × 32 → 64 bits

0011nnnnmmmm0101 — —

DT Rn Rn – 1 → Rn; when Rn = 0,

1 → T

When Rn ≠ 0, 0 → T

0100nnnn00010000 — Comparison

result

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Instruction Operation Instruction Code Privileged T Bit

EXTS.B Rm,Rn Rm sign-extended from

byte → Rn

0110nnnnmmmm1110 — —

EXTS.W Rm,Rn Rm sign-extended from

word → Rn

0110nnnnmmmm1111 — —

EXTU.B Rm,Rn Rm zero-extended from

byte → Rn

0110nnnnmmmm1100 — —

EXTU.W Rm,Rn Rm zero-extended from

word → Rn

0110nnnnmmmm1101 — —

MAC.L @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC →

MAC

Rn + 4 → Rn, Rm + 4 → Rm

32 × 32 + 64 → 64 bits

0000nnnnmmmm1111 — —

MAC.W @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC →

MAC

Rn + 2 → Rn, Rm + 2 → Rm

16 × 16 + 64 → 64 bits

0100nnnnmmmm1111 — —

MUL.L Rm,Rn Rn × Rm → MACL

32 × 32 → 32 bits

0000nnnnmmmm0111 — —

MULS.W Rm,Rn Signed, Rn × Rm → MACL

16 × 16 → 32 bits

0010nnnnmmmm1111 — —

MULU.W Rm,Rn Unsigned, Rn × Rm → MACL

16 × 16 → 32 bits

0010nnnnmmmm1110 — —

NEG Rm,Rn 0 – Rm → Rn 0110nnnnmmmm1011 — —

NEGC Rm,Rn 0 – Rm – T → Rn, borrow → T 0110nnnnmmmm1010 — Borrow

SUB Rm,Rn Rn – Rm → Rn 0011nnnnmmmm1000 — —

SUBC Rm,Rn Rn – Rm – T → Rn, borrow → T 0011nnnnmmmm1010 — Borrow

SUBV Rm,Rn Rn – Rm → Rn, underflow → T 0011nnnnmmmm1011 — Underflow

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Table 7.5 Logic Operation Instructions

Instruction Operation Instruction Code Privileged T Bit

AND Rm,Rn Rn & Rm → Rn 0010nnnnmmmm1001 — —

AND #imm,R0 R0 & imm → R0 11001001iiiiiiii — —

AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 +

GBR)

11001101iiiiiiii — —

NOT Rm,Rn ~Rm → Rn 0110nnnnmmmm0111 — —

OR Rm,Rn Rn | Rm → Rn 0010nnnnmmmm1011 — —

OR #imm,R0 R0 | imm → R0 11001011iiiiiiii — —

OR.B #imm,@(R0,GBR) (R0 + GBR) | imm → (R0 + GBR)11001111iiiiiiii —

TAS.B @Rn When (Rn) = 0, 1 → T

Otherwise, 0 → T

In both cases, 1 → MSB of (Rn)

0100nnnn00011011 — Test result

TST Rm,Rn Rn & Rm; when result = 0,

1 → T

Otherwise, 0 → T

0010nnnnmmmm1000 — Test result

TST #imm,R0 R0 & imm; when result = 0,

1 → T

Otherwise, 0 → T

11001000iiiiiiii — Test result

TST.B #imm,@(R0,GBR)

(R0 + GBR) & imm; when result

= 0, 1 → T

Otherwise, 0 → T

11001100iiiiiiii — Test result

XOR Rm,Rn Rn ∧ Rm → Rn 0010nnnnmmmm1010 — —

XOR #imm,R0 R0 ∧ imm → R0 11001010iiiiiiii — —

XOR.B #imm,@(R0,GBR) (R0 + GBR) ∧ imm → (R0 +

GBR)

11001110iiiiiiii — —

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Table 7.6 Shift Instructions

Instruction Operation Instruction Code Privileged T Bit

ROTL Rn T ← Rn ← MSB 0100nnnn00000100 — MSB

ROTR Rn LSB → Rn → T 0100nnnn00000101 — LSB

ROTCL Rn T ← Rn ← T 0100nnnn00100100 — MSB

ROTCR Rn T → Rn → T 0100nnnn00100101 — LSB

SHAD Rm,Rn When Rn ≥ 0, Rn << Rm → Rn

When Rn < 0, Rn >> Rm →

[MSB → Rn]

0100nnnnmmmm1100 — —

SHAL Rn T ← Rn ← 0 0100nnnn00100000 — MSB

SHAR Rn MSB → Rn → T 0100nnnn00100001 — LSB

SHLD Rm,Rn When Rn ≥ 0, Rn << Rm → Rn

When Rn < 0, Rn >> Rm →

[0 → Rn]

0100nnnnmmmm1101 — —

SHLL Rn T ← Rn ← 0 0100nnnn00000000 — MSB

SHLR Rn 0 → Rn → T 0100nnnn00000001 — LSB

SHLL2 Rn Rn << 2 → Rn 0100nnnn00001000 — —

SHLR2 Rn Rn >> 2 → Rn 0100nnnn00001001 — —

SHLL8 Rn Rn << 8 → Rn 0100nnnn00011000 — —

SHLR8 Rn Rn >> 8 → Rn 0100nnnn00011001 — —

SHLL16 Rn Rn << 16 → Rn 0100nnnn00101000 — —

SHLR16 Rn Rn >> 16 → Rn 0100nnnn00101001 — —

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Table 7.7 Branch Instructions

Instruction Operation Instruction Code Privileged T Bit

BF label When T = 0, disp × 2 + PC +

4 → PC

When T = 1, nop

10001011dddddddd — —

BF/S label Delayed branch; when T = 0,

disp × 2 + PC + 4 → PC

When T = 1, nop

10001111dddddddd — —

BT label When T = 1, disp × 2 + PC +

4 → PC

When T = 0, nop

10001001dddddddd — —

BT/S label Delayed branch; when T = 1,

disp × 2 + PC + 4 → PC

When T = 0, nop

10001101dddddddd — —

BRA label Delayed branch, disp × 2 +

PC + 4 → PC

1010dddddddddddd — —

BRAF Rn Delayed branch, Rn + PC +

4 → PC

0000nnnn00100011 — —

BSR label Delayed branch, PC + 4 → PR,

disp × 2 + PC + 4 → PC

1011dddddddddddd — —

BSRF Rn Delayed branch, PC + 4 → PR,

Rn + PC + 4 → PC

0000nnnn00000011 — —

JMP @Rn Delayed branch, Rn → PC 0100nnnn00101011 — —

JSR @Rn Delayed branch, PC + 4 → PR,

Rn → PC

0100nnnn00001011 — —

RTS Delayed branch, PR → PC 0000000000001011 — —

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Table 7.8 System Control Instructions

Instruction Operation Instruction Code Privileged T Bit

CLRMAC 0 → MACH, MACL 0000000000101000 — —

CLRS 0 → S 0000000001001000 — —

CLRT 0 → T 0000000000001000 — 0

LDC Rm,SR Rm → SR 0100mmmm00001110 Privileged LSB

LDC Rm,GBR Rm → GBR 0100mmmm00011110 — —

LDC Rm,VBR Rm → VBR 0100mmmm00101110 Privileged —

LDC Rm,SSR Rm → SSR 0100mmmm00111110 Privileged —

LDC Rm,SPC Rm → SPC 0100mmmm01001110 Privileged —

LDC Rm,DBR Rm → DBR 0100mmmm11111010 Privileged —

LDC Rm,Rn_BANK Rm → Rn_BANK (n = 0 to 7) 0100mmmm1nnn1110 Privileged —

LDC.L @Rm+,SR (Rm) → SR, Rm + 4 → Rm 0100mmmm00000111 Privileged LSB

LDC.L @Rm+,GBR (Rm) → GBR, Rm + 4 → Rm 0100mmmm00010111 — —

LDC.L @Rm+,VBR (Rm) → VBR, Rm + 4 → Rm 0100mmmm00100111 Privileged —

LDC.L @Rm+,SSR (Rm) → SSR, Rm + 4 → Rm 0100mmmm00110111 Privileged —

LDC.L @Rm+,SPC (Rm) → SPC, Rm + 4 → Rm 0100mmmm01000111 Privileged —

LDC.L @Rm+,DBR (Rm) → DBR, Rm + 4 → Rm 0100mmmm11110110 Privileged —

LDC.L @Rm+,Rn_BANK (Rm) → Rn_BANK,

Rm + 4 → Rm

0100mmmm1nnn0111 Privileged —

LDS Rm,MACH Rm → MACH 0100mmmm00001010 — —

LDS Rm,MACL Rm → MACL 0100mmmm00011010 — —

LDS Rm,PR Rm → PR 0100mmmm00101010 — —

LDS.L @Rm+,MACH (Rm) → MACH, Rm + 4 → Rm 0100mmmm00000110 — —

LDS.L @Rm+,MACL (Rm) → MACL, Rm + 4 → Rm 0100mmmm00010110 — —

LDS.L @Rm+,PR (Rm) → PR, Rm + 4 → Rm 0100mmmm00100110 — —

LDTLB PTEH/PTEL → TLB 0000000000111000 Privileged —

MOVCA.L R0,@Rn R0 → (Rn) (without fetching

cache block)

0000nnnn11000011 — —

NOP No operation 0000000000001001 — —

OCBI @Rn Invalidates operand cache block 0000nnnn10010011 — —

OCBP @Rn Writes back and invalidates

operand cache block

0000nnnn10100011 — —

OCBWB @Rn Writes back operand cache block0000nnnn10110011 — —

PREF @Rn (Rn) → operand cache 0000nnnn10000011 — —

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Instruction Operation Instruction Code Privileged T Bit

RTE Delayed branch, SSR/SPC →

SR/PC

0000000000101011 Privileged —

SETS 1 → S 0000000001011000 — —

SETT 1 → T 0000000000011000 — 1

SLEEP Sleep or standby 0000000000011011 Privileged —

STC SR,Rn SR → Rn 0000nnnn00000010 Privileged —

STC GBR,Rn GBR → Rn 0000nnnn00010010 — —

STC VBR,Rn VBR → Rn 0000nnnn00100010 Privileged —

STC SSR,Rn SSR → Rn 0000nnnn00110010 Privileged —

STC SPC,Rn SPC → Rn 0000nnnn01000010 Privileged —

STC SGR,Rn SGR → Rn 0000nnnn00111010 Privileged —

STC DBR,Rn DBR → Rn 0000nnnn11111010 Privileged —

STC Rm_BANK,Rn Rm_BANK → Rn (m = 0 to 7) 0000nnnn1mmm0010 Privileged —

STC.L SR,@-Rn Rn – 4 → Rn, SR → (Rn) 0100nnnn00000011 Privileged —

STC.L GBR,@-Rn Rn – 4 → Rn, GBR → (Rn) 0100nnnn00010011 — —

STC.L VBR,@-Rn Rn – 4 → Rn, VBR → (Rn) 0100nnnn00100011 Privileged —

STC.L SSR,@-Rn Rn – 4 → Rn, SSR → (Rn) 0100nnnn00110011 Privileged —

STC.L SPC,@-Rn Rn – 4 → Rn, SPC → (Rn) 0100nnnn01000011 Privileged —

STC.L SGR,@-Rn Rn – 4 → Rn, SGR → (Rn) 0100nnnn00110010 Privileged —

STC.L DBR,@-Rn Rn – 4 → Rn, DBR → (Rn) 0100nnnn11110010 Privileged —

STC.L Rm_BANK,@-Rn Rn – 4 → Rn,

Rm_BANK → (Rn) (m = 0 to 7)

0100nnnn1mmm0011 Privileged —

STS MACH,Rn MACH → Rn 0000nnnn00001010 — —

STS MACL,Rn MACL → Rn 0000nnnn00011010 — —

STS PR,Rn PR → Rn 0000nnnn00101010 — —

STS.L MACH,@-Rn Rn – 4 → Rn, MACH → (Rn) 0100nnnn00000010 — —

STS.L MACL,@-Rn Rn – 4 → Rn, MACL → (Rn) 0100nnnn00010010 — —

STS.L PR,@-Rn Rn – 4 → Rn, PR → (Rn) 0100nnnn00100010 — —

TRAPA #imm PC + 2 → SPC, SR → SSR,

#imm << 2 → TRA,

H'160 → EXPEVT,

VBR + H'0100 → PC

11000011iiiiiiii — —

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Table 7.9 Floating-Point Single-Precision Instructions

Instruction Operation Instruction Code Privileged T Bit

FLDI0 FRn H'00000000 → FRn 1111nnnn10001101 — —

FLDI1 FRn H'3F800000 → FRn 1111nnnn10011101 — —

FMOV FRm,FRn FRm → FRn 1111nnnnmmmm1100 — —

FMOV.S @Rm,FRn (Rm) → FRn 1111nnnnmmmm1000 — —

FMOV.S @(R0,Rm),FRn (R0 + Rm) → FRn 1111nnnnmmmm0110 — —

FMOV.S @Rm+,FRn (Rm) → FRn, Rm + 4 → Rm 1111nnnnmmmm1001 — —

FMOV.S FRm,@Rn FRm → (Rn) 1111nnnnmmmm1010 — —

FMOV.S FRm,@-Rn Rn-4 → Rn, FRm → (Rn) 1111nnnnmmmm1011 — —

FMOV.S FRm,@(R0,Rn) FRm → (R0 + Rn) 1111nnnnmmmm0111 — —

FMOV DRm,DRn DRm → DRn 1111nnn0mmm01100 — —

FMOV @Rm,DRn (Rm) → DRn 1111nnn0mmmm1000 — —

FMOV @(R0,Rm),DRn (R0 + Rm) → DRn 1111nnn0mmmm0110 — —

FMOV @Rm+,DRn (Rm) → DRn, Rm + 8 → Rm 1111nnn0mmmm1001 — —

FMOV DRm,@Rn DRm → (Rn) 1111nnnnmmm01010 — —

FMOV DRm,@-Rn Rn-8 → Rn, DRm → (Rn) 1111nnnnmmm01011 — —

FMOV DRm,@(R0,Rn) DRm → (R0 + Rn) 1111nnnnmmm00111 — —

FLDS FRm,FPUL FRm → FPUL 1111mmmm00011101 — —

FSTS FPUL,FRn FPUL → FRn 1111nnnn00001101 — —

FABS FRn FRn & H'7FFF FFFF → FRn 1111nnnn01011101 — —

FADD FRm,FRn FRn + FRm → FRn 1111nnnnmmmm0000 — —

FCMP/EQ FRm,FRn When FRn = FRm, 1 → T

Otherwise, 0 → T

1111nnnnmmmm0100 — Comparison

result

FCMP/GT FRm,FRn When FRn > FRm, 1 → T

Otherwise, 0 → T

1111nnnnmmmm0101 — Comparison

result

FDIV FRm,FRn FRn/FRm → FRn 1111nnnnmmmm0011 — —

FLOAT FPUL,FRn (float) FPUL → FRn 1111nnnn00101101 — —

FMAC FR0,FRm,FRn FR0 * FRm + FRn → FRn 1111nnnnmmmm1110 — —

FMUL FRm,FRn FRn * FRm → FRn 1111nnnnmmmm0010 — —

FNEG FRn FRn ∧ H'80000000 → FRn 1111nnnn01001101 — —

FSQRT FRn

FRn → FRn

1111nnnn01101101 — —

FSUB FRm,FRn FRn – FRm → FRn 1111nnnnmmmm0001 — —

FTRC FRm,FPUL (long) FRm → FPUL 1111mmmm00111101 — —

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Table 7.10 Floating-Point Double-Precision Instructions

Instruction Operation Instruction Code Privileged T Bit

FABS DRn DRn & H'7FFF FFFF FFFF FFFF

→ DRn

1111nnn001011101 — —

FADD DRm,DRn DRn + DRm → DRn 1111nnn0mmm00000 — —

FCMP/EQ DRm,DRn When DRn = DRm, 1 → T

Otherwise, 0 → T

1111nnn0mmm00100 — Comparison

result

FCMP/GT DRm,DRn When DRn > DRm, 1 → T

Otherwise, 0 → T

1111nnn0mmm00101 — Comparison

result

FDIV DRm,DRn DRn /DRm → DRn 1111nnn0mmm00011 — —

FCNVDS DRm,FPUL double_to_ float[DRm] → FPUL 1111mmm010111101 — —

FCNVSD FPUL,DRn float_to_ double [FPUL] → DRn 1111nnn010101101 — —

FLOAT FPUL,DRn (float)FPUL → DRn 1111nnn000101101 — —

FMUL DRm,DRn DRn * DRm → DRn 1111nnn0mmm00010 — —

FNEG DRn DRn ^ H'8000 0000 0000 0000

→ DRn

1111nnn001001101 — —

FSQRT DRn

DRn → DRn

1111nnn001101101 — —

FSUB DRm,DRn DRn – DRm → DRn 1111nnn0mmm00001 — —

FTRC DRm,FPUL (long) DRm → FPUL 1111mmm000111101 — —

Table 7.11 Floating-Point Control Instructions

Instruction Operation Instruction Code Privileged T Bit

LDS Rm,FPSCR Rm → FPSCR 0100mmmm01101010 — —

LDS Rm,FPUL Rm → FPUL 0100mmmm01011010 — —

LDS.L @Rm+,FPSCR (Rm) → FPSCR, Rm+4 → Rm 0100mmmm01100110 — —

LDS.L @Rm+,FPUL (Rm) → FPUL, Rm+4 → Rm 0100mmmm01010110 — —

STS FPSCR,Rn FPSCR → Rn 0000nnnn01101010 — —

STS FPUL,Rn FPUL → Rn 0000nnnn01011010 — —

STS.L FPSCR,@-Rn Rn – 4 → Rn, FPSCR → (Rn) 0100nnnn01100010 — —

STS.L FPUL,@-Rn Rn – 4 → Rn, FPUL → (Rn) 0100nnnn01010010 — —

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Table 7.12 Floating-Point Graphics Acceleration Instructions

Instruction Operation Instruction Code Privileged T Bit

FMOV DRm,XDn DRm → XDn 1111nnn1mmm01100 — —

FMOV XDm,DRn XDm → DRn 1111nnn0mmm11100 — —

FMOV XDm,XDn XDm → XDn 1111nnn1mmm11100 — —

FMOV @Rm,XDn (Rm) → XDn 1111nnn1mmmm1000 — —

FMOV @Rm+,XDn (Rm) → XDn, Rm + 8 → Rm 1111nnn1mmmm1001 — —

FMOV @(R0,Rm),XDn (R0 + Rm) → XDn 1111nnn1mmmm0110 — —

FMOV XDm,@Rn XDm → (Rn) 1111nnnnmmm11010 — —

FMOV XDm,@-Rn Rn – 8 → Rn, XDm → (Rn) 1111nnnnmmm11011 — —

FMOV XDm,@(R0,Rn) XDm → (R0+Rn) 1111nnnnmmm10111 — —

FIPR FVm,FVn inner_product [FVm, FVn] →

FR[n+3]

1111nnmm11101101 — —

FTRV XMTRX,FVn transform_vector [XMTRX, FVn]

→ FVn

1111nn0111111101 — —

FRCHG ~FPSCR.FR → FPSCR.FR 1111101111111101 — —

FSCHG ~FPSCR.SZ → FPSCR.SZ 1111001111111101 — —

7.4 Usage Notes

7.4.1 Notes on TRAPA Instruction, SLEEP Instruction, and Undefined Instruction

(H'FFFD)

• Incorrect data may be written to the cache when a TRAPA instruction or undefined instruction

code H'FFFD is executed.

• The ITLB hit judgment may be incorrect when a TRAPA instruction or undefined instruction

code H'FFFD is executed, causing a multi-hit exception to occur after re-registration.

• Incorrect data may be written to an FPU-related register or to the MACH or MACL register

when a TRAPA instruction, SLEEP instruction, or undefined instruction code H'FFFD is

executed.

Conditions Under which Problem Occurs

1. Incorrect data may be written to the instruction cache when the following three conditions

occur at the same time.

a. The instruction cache is enabled (CCR.ICE = 1).

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b. A TRAPA instruction or undefined instruction code H'FFFD in a cache-enabled area is

executed.

c. The four words of data following the TRAPA instruction or undefined instruction code

H'FFFD mentioned in b. contain code that can be interpreted as an instruction to access

(read or write) an address (H'F0000000 to H'F7FFFFFF) mapped to the internal cache or

internal TLB.

2. Incorrect data may be written to the operand cache when the following three conditions occur

at the same time.

a. The operand cache is enabled (CCR.OCE = 1).

b. Undefined instruction code H'FFFD is executed.

c. The four words of data following the undefined instruction code H'FFFD mentioned in b.

contain code that can be interpreted as an OCBI, OCBP, OCBWB, or TAS.B instruction

accessing an address (H'E0000000 to H'E3FFFFFF) mapped to the internal store queue.

3. The ITLB hit judgment may be incorrect when the following three conditions occur at the

same time. If an ITLB hit is erroneously judged to be a miss, ITLB re-registration is

performed. This can cause an ITLB multi-hit exception to occur.

a. The MMU enabled (MMUCR.AT = 1).

b. A TRAPA instruction or undefined instruction code H'FFFD in a TLB conversion area

(area U0, P0, or P3) is executed.

c. The four words of data following the TRAPA instruction or undefined instruction code

H'FFFD mentioned in b. contain code that can be interpreted as an instruction to access

(read or write) an address (H'F0000000 to H'F7FFFFFF) mapped to the internal cache or

internal TLB.

4. Incorrect data may be written to an FPU-related register (FR0 to FR15, XF0 to XF15, FPSCR,

or FPUL) or to the MACH or MACL register when the following two conditions occur at the

same time.

a. A TRAPA instruction, SLEEP instruction, or undefined instruction code H'FFFD is

executed

b. The eight words of data following the TRAPA instruction, SLEEP instruction, or undefined

instruction code H'FFFD mentioned in a. contain H'Fxxx (an instruction with H'F as the

first four bits), excluding H'FFFD, and the code can be interpreted, in combination with

FPSCR.PR at that point, as an undefined instruction.

Example: Instruction H'FxxE (x: any hexadecimal digit) is defined here as undefined when

FPSCR.PR is set to 1.

Note: The number of instructions following the instructions mentioned above that may be

affected by the problem is as follows: in the case of 1. to 3., the number of instructions

that can be executed in 2xIck, and in the case of 4., the number of instructions that can be

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executed in 4xIck. The maximum number of instructions that can be executed in 2xIck or

4xIck is four or eight, respectively. Therefore, the affected codes are those occurring in

“the four words (or eight words) of data following the instruction.”

Workarounds: To prevent the problem, use either of workarounds a. or b. below.

a. Include a NOP instruction in the eight words of data following each TRAPA instruction,

SLEEP instruction, or undefined instruction code H'FFFD.

b. Include an OR R0,R0 instruction in the five words of data following each TRAPA instruction,

SLEEP instruction, or undefined instruction code H'FFFD. This workaround also applies to

cases where “the eight words of data following the … instruction … contain H'Fxxx,” as

mentioned in condition 4. b., because two OR instructions are never executed simultaneously,

so a minimum of 5xIck is required for execution.

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Section 8 Pipelining

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Section 8 Pipelining

This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor.

Instruction execution is pipelined, and two instructions can be executed in parallel. The execution

cycles depend on the implementation of a processor. Definitions in this section may not be

applicable to SH-4 Series products other than this LSI.

8.1 Pipelines

Figure 8.1 shows the basic pipelines. Normally, a pipeline consists of five or six stages: instruction

fetch (I), decode and register read (D), execution (EX/SX/F0/F1/F2/F3), data access (NA/MA),

and write-back (S/FS). An instruction is executed as a combination of basic pipelines. Figure 8.2

shows the instruction execution patterns.

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1. General Pipeline

• Instruction fetch • Instruction

decode

• Issue

• Register read

• Destination address calculation

for PC-relative branch

• Non-memory

data access

• Write-back

IDEX

• Operation

NA S

2. General Load/Store Pipeline

• Instruction fetch • Instruction

decode

• Issue

• Register read

• Memory

data access

• Write-back

IDEX

• Address

calculation

MA S

3. Special Pipeline

• Instruction fetch • Instruction

decode

• Issue

• Register read

• Non-memory

data access

• Write-back

IDSX

• Operation

NA S

4. Special Load/Store Pipeline

• Instruction fetch • Instruction

decode

• Issue

• Register read

• Memory

data access

• Write-back

IDSX

• Address

calculation

MA S

5. Floating-Point Pipeline

• Instruction fetch • Instruction

decode

• Issue

• Register read

• Computation 2 • Computation 3

• Write-back

IDF1

• Computation 1

F2 FS

6. Floating-Point Extended Pipeline

• Instruction fetch • Instruction

decode

• Issue

• Register read

• Computation 1 • Computation 3

• Write-back

IDF0

• Computation 0

F1 F2 FS

• Computation 2

Computation: Takes several cycles

7. FDIV/FSQRT Pipeline

Figure 8.1 Basic Pipelines

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1. 1-step operation: 1 issue cycle

EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*,

DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#,

ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT,

LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS,

single-/double-precision FABS/FNEG

IDEX NA S

2. Load/store: 1 issue cycle

MOV.[BWL]. FMOV*@, LDS.L to FPUL, LDTLB, PREF, STS.L from FPUL/FPSCR

IDEX MA S

3. GBR-based load/store: 1 issue cycle

MOV.[BWL]@(d,GBR)

IDSX MA S

4. JMP, RTS, BRAF: 2 issue cycles

IDEX NA S

DEX NA S

5. TST.B: 3 issue cycles

IDSX MA S

DSX NA S

6. AND.B, OR.B, XOR.B: 4 issue cycles

IDSX MA S

DSX NA S

DSX MA S

7. TAS.B: 5 issue cycles

IDEX MA S

DEX MA S

DEX NA S

DEX MA S

8. RTE: 5 issue cycles

IDEX NA S

DEX NA S

9. SLEEP: 4 issue cycles

IDEX NA S

DEX NA S

Figure 8.2 Instruction Execution Patterns

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10. OCBI: 1 issue cycle

IDEX MA S

11. OCBP, OCBWB: 1 issue cycle

IDEX MA S

12. MOVCA.L: 1 issue cycle

IDEX MA S

13. TRAPA: 7 issue cycles

IDEX NA S

DEX NA S

14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle

IDEX NA S

15. LDC to GBR: 3 issue cycles

IDEX NA S

16. LDC to SR: 4 issue cycles

IDEX NA S

IDEX MA S

17. LDC.L to DBR/Rp_BANK/SSR/SPC/VBR: 1 issue cycle

18. LDC.L to GBR: 3 issue cycles

IDEX MA S

Figure 8.2 Instruction Execution Patterns (cont)

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19. LDC.L to SR: 4 issue cycles

IDEX MA S

20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles

IDSX NA S

DSX NA S

21. STC.L from SGR: 3 issue cycles

IDSX NA S

DSX NA S

22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles

IDSX NA S

DSX MA S

23. STC.L from SGR: 3 issue cycles

IDSX NA S

DSX NA S

DSX MA S

24. LDS to PR, JSR, BSRF: 2 issue cycles

IDEX NA S

DSX

25. LDS.L to PR: 2 issue cycles

IDEX MA S

DSX

26. STS from PR: 2 issue cycles

IDSX NA S

DSX NA S

27. STS.L from PR: 2 issue cycles

IDSX NA S

DSX MA S

28. CLRMAC, LDS to MACH/L: 1 issue cycle

IDEX NA S

F1 F2 FS

29. LDS.L to MACH/L: 1 issue cycle

IDEX MA S

F1 F2 FS

30. STS from MACH/L: 1 issue cycle

IDEX NA S

Figure 8.2 Instruction Execution Patterns (cont)

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31. STS.L from MACH/L: 1 issue cycle

IDEX MA S

32. LDS to FPSCR: 1 issue cycle

IDEX NA S

33. LDS.L to FPSCR: 1 issue cycle

IDEX MA S

34. Fixed-point multiplication: 2 issue cycles

DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W

IDEX NA S

(CPU)

DEX NA S

(FPU)

f1 F2 FS

35. MAC.W, MAC.L: 2 issue cycles

IDEX MA S

(CPU)

DEX MA S

(FPU)

f1 F2 FS

36. Single-precision floating-point computation: 1 issue cycle

FCMP/EQ,FCMP/GT, FADD,FLOAT,FMAC,FMUL,FSUB,FTRC,FRCHG,FSCHG

IDF1 F2 FS

37. Single-precision FDIV/SQRT: 1 issue cycle

IDF1 F2 FS

F1 F2 FS

38. Double-precision floating-point computation 1: 1 issue cycle

FCNVDS, FCNVSD, FLOAT, FTRC

IDF1 F2 FS

dF1 F2 FS

39. Double-precision floating-point computation 2: 1 issue cycle

FADD, FMUL, FSUB

IDF1 F2 FS

dF1 F2 FS

F1 F2 FS

Figure 8.2 Instruction Execution Patterns (cont)

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IDF1 F2 FS

DF1 F2 FS

40. Double-precision FCMP: 2 issue cycles

FCMP/EQ,FCMP/GT

IDF1 F2 FS

F1 F2 FS

41. Double-precision FDIV/SQRT: 1 issue cycle

FDIV, FSQRT

F1 F2

F1 F2 FS

42. FIPR: 1 issue cycle

I D F0 F1 F2 FS

43. FTRV: 1 issue cycle

F1 F2 FS

DF0

F1 F2 FS

dF0

F1 F2 FS

dF0

F1 F2 FS

dF0

Notes: ??

: Locks D-stage

: Register read only

: Locks, but no operation is executed.

: Can overlap another f1, but not another F1.

: Cannot overlap a stage of the same kind, except when two instructions are

executed in parallel.

Figure 8.2 Instruction Execution Patterns (cont)

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8.2 Parallel-Executability

Instructions are categorized into six groups according to the internal function blocks used, as

shown in table 8.1. Table 8.2 shows the parallel-executability of pairs of instructions in terms of

groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel.

Table 8.1 Instruction Groups

1. MT Group

CLRT CMP/HI Rm,Rn MOV Rm,Rn

CMP/EQ #imm,R0 CMP/HS Rm,Rn NOP

CMP/EQ Rm,Rn CMP/PL Rn SETT

CMP/GE Rm,Rn CMP/PZ Rn TST #imm,R0

CMP/GT Rm,Rn CMP/STR Rm,Rn TST Rm,Rn

2. EX Group

ADD #imm,Rn MOVT Rn SHLL2 Rn

ADD Rm,Rn NEG Rm,Rn SHLL8 Rn

ADDC Rm,Rn NEGC Rm,Rn SHLR Rn

ADDV Rm,Rn NOT Rm,Rn SHLR16 Rn

AND #imm,R0 OR #imm,R0 SHLR2 Rn

AND Rm,Rn OR Rm,Rn SHLR8 Rn

DIV0S Rm,Rn ROTCL Rn SUB Rm,Rn

DIV0U ROTCR Rn SUBC Rm,Rn

DIV1 Rm,Rn ROTL Rn SUBV Rm,Rn

DT Rn ROTR Rn SWAP.B Rm,Rn

EXTS.B Rm,Rn SHAD Rm,Rn SWAP.W Rm,Rn

EXTS.W Rm,Rn SHAL Rn XOR #imm,R0

EXTU.B Rm,Rn SHAR Rn XOR Rm,Rn

EXTU.W Rm,Rn SHLD Rm,Rn XTRCT Rm,Rn

MOV #imm,Rn SHLL Rn

MOVA @(disp,PC),R0 SHLL16 Rn

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3. BR Group

BF disp BRA disp BT disp

BF/S disp BSR disp BT/S disp

4. LS Group

FABS DRn FMOV.S @Rm+,FRn MOV.L R0,@(disp,GBR)

FABS FRn FMOV.S FRm,@(R0,Rn) MOV.L Rm,@(disp,Rn)

FLDI0 FRn FMOV.S FRm,@-Rn MOV.L Rm,@(R0,Rn)

FLDI1 FRn FMOV.S FRm,@Rn MOV.L Rm,@-Rn

FLDS FRm,FPUL FNEG DRn MOV.L Rm,@Rn

FMOV @(R0,Rm),DRn FNEG FRn MOV.W @(disp,GBR),R0

FMOV @(R0,Rm),XDn FSTS FPUL,FRn MOV.W @(disp,PC),Rn

FMOV @Rm,DRn LDS Rm,FPUL MOV.W @(disp,Rm),R0

FMOV @Rm,XDn MOV.B @(disp,GBR),R0 MOV.W @(R0,Rm),Rn

FMOV @Rm+,DRn MOV.B @(disp,Rm),R0 MOV.W @Rm,Rn

FMOV @Rm+,XDn MOV.B @(R0,Rm),Rn MOV.W @Rm+,Rn

FMOV DRm,@(R0,Rn) MOV.B @Rm,Rn MOV.W R0,@(disp,GBR)

FMOV DRm,@-Rn MOV.B @Rm+,Rn MOV.W R0,@(disp,Rn)

FMOV DRm,@Rn MOV.B R0,@(disp,GBR) MOV.W Rm,@(R0,Rn)

FMOV DRm,DRn MOV.B R0,@(disp,Rn) MOV.W Rm,@-Rn

FMOV DRm,XDn MOV.B Rm,@(R0,Rn) MOV.W Rm,@Rn

FMOV FRm,FRn MOV.B Rm,@-Rn MOVCA.L R0,@Rn

FMOV XDm,@(R0,Rn) MOV.B Rm,@Rn OCBI @Rn

FMOV XDm,@-Rn MOV.L @(disp,GBR),R0 OCBP @Rn

FMOV XDm,@Rn MOV.L @(disp,PC),Rn OCBWB @Rn

FMOV XDm,DRn MOV.L @(disp,Rm),Rn PREF @Rn

FMOV XDm,XDn MOV.L @(R0,Rm),Rn STS FPUL,Rn

FMOV.S @(R0,Rm),FRn MOV.L @Rm,Rn

FMOV.S @Rm,FRn MOV.L @Rm+,Rn

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5. FE Group

FADD DRm,DRn FIPR FVm,FVn FSQRT DRn

FADD FRm,FRn FLOAT FPUL,DRn FSQRT FRn

FCMP/EQ FRm,FRn FLOAT FPUL,FRn FSUB DRm,DRn

FCMP/GT FRm,FRn FMAC FR0,FRm,FRn FSUB FRm,FRn

FCNVDS DRm,FPUL FMUL DRm,DRn FTRC DRm,FPUL

FCNVSD FPUL,DRn FMUL FRm,FRn FTRC FRm,FPUL

FDIV DRm,DRn FRCHG FTRV XMTRX,FVn

FDIV FRm,FRn FSCHG

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6. CO Group

AND.B #imm,@(R0,GBR) LDS Rm,FPSCR STC SR,Rn

BRAF Rm LDS Rm,MACH STC SSR,Rn

BSRF Rm LDS Rm,MACL STC VBR,Rn

CLRMAC LDS Rm,PR STC.L DBR,@-Rn

CLRS LDS.L @Rm+,FPSCR STC.L GBR,@-Rn

DMULS.L Rm,Rn LDS.L @Rm+,FPUL STC.L Rp_BANK,@-Rn

DMULU.L Rm,Rn LDS.L @Rm+,MACH STC.L SGR,@-Rn

FCMP/EQ DRm,DRn LDS.L @Rm+,MACL STC.L SPC,@-Rn

FCMP/GT DRm,DRn LDS.L @Rm+,PR STC.L SR,@-Rn

JMP @Rn LDTLB STC.L SSR,@-Rn

JSR @Rn MAC.L @Rm+,@Rn+ STC.L VBR,@-Rn

LDC Rm,DBR MAC.W @Rm+,@Rn+ STS FPSCR,Rn

LDC Rm,GBR MUL.L Rm,Rn STS MACH,Rn

LDC Rm,Rp_BANK MULS.W Rm,Rn STS MACL,Rn

LDC Rm,SPC MULU.W Rm,Rn STS PR,Rn

LDC Rm,SR OR.B #imm,@(R0,GBR) STS.L FPSCR,@-Rn

LDC Rm,SSR RTE STS.L FPUL,@-Rn

LDC Rm,VBR RTS STS.L MACH,@-Rn

LDC.L @Rm+,DBR SETS STS.L MACL,@-Rn

LDC.L @Rm+,GBR SLEEP STS.L PR,@-Rn

LDC.L @Rm+,Rp_BANK STC DBR,Rn TAS.B @Rn

LDC.L @Rm+,SPC STC GBR,Rn TRAPA #imm

LDC.L @Rm+,SR STC Rp_BANK,Rn TST.B #imm,@(R0,GBR)

LDC.L @Rm+,SSR STC SGR,Rn XOR.B #imm,@(R0,GBR)

LDC.L @Rm+,VBR STC SPC,Rn

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Table 8.2 Parallel-Executability

2nd Instruction

MT EX BR LS FE CO

MT O O O O O X

EX O X O O O X

BR O O X O O X

LS O O O X O X

FE O O O O X X

1st

Instruction

CO X X X X X X

Legend:

O: Can be executed in parallel

X: Cannot be executed in parallel

8.3 Execution Cycles and Pipeline Stalling

There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware

unit operates on one of these clocks, as follows:

• I-clock: CPU, FPU, MMU, caches

• B-clock: External bus controller

• P-clock: Peripheral units

The frequency ratios of the three clocks are determined with the frequency control register

(FRQCR). In this section, machine cycles are based on the I-clock unless otherwise specified. For

details of FRQCR, see section 10, Clock Oscillation Circuits.

Instruction execution cycles are summarized in table 8.3. Penalty cycles due to a pipeline stall or

freeze are not considered in this table.

• Issue rate: Interval between the issue of an instruction and that of the next instruction

• Latency: Interval between the issue of an instruction and the generation of its result

(completion)

• Instruction execution pattern (see figure 8.2)

• Locked pipeline stages (see table 8.3)

• Interval between the issue of an instruction and the start of locking (see table 8.3)

• Lock time: Period of locking in machine cycle units (see table 8.3)

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The instruction execution sequence is expressed as a combination of the execution patterns shown

in figure 8.2. One instruction is separated from the next by the number of machine cycles for its

issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the

same stages of another instruction; the only exception is when two instructions are executed in

parallel under parallel-executability conditions. Refer to (a) through (d) in figure 8.3 for some

simple examples.

Latency is the interval between issue and completion of an instruction, and is also the interval

between the execution of two instructions with an interdependent relationship. When there is

interdependency between two instructions fetched simultaneously, the latter of the two is stalled

for the following number of cycles:

• (Latency) cycles when there is flow dependency (read-after-write)

• (Latency - 1) or (latency - 2) cycles when there is output dependency (write-after-write)

⎯ Single/double-precision FDN, FSQRT is the preceding instruction (latency – 1) cycles

⎯ The other FE group is the preceding instruction (latency – 2) cycles

• 5 or 2 cycles when there is anti-flow dependency (write-after-read), as in the following cases:

⎯ FTRV is the preceding instruction (5 cycle)

⎯ A double-precision FADD, FSUB, or FMUL is the preceding instruction (2 cycles)

In the case of flow dependency, latency may be exceptionally increased or decreased, depending

on the combination of sequential instructions (figure 8.3 (e)).

• When a floating-point (FP) computation is followed by an FP register store, the latency of the

FP computation may be decreased by 1 cycle.

• If there is a load of the shift amount immediately before an SHAD/SHLD instruction, the

latency of the load is increased by 1 cycle.

• If an instruction with a latency of less than 2 cycles, including write-back to an FP register, is

followed by a double-precision FP instruction, FIPR, or FTRV, the latency of the first

instruction is increased to 2 cycles.

The number of cycles in a pipeline stall due to flow dependency will vary depending on the

combination of interdependent instructions or the fetch timing (see figure 8.3. (e)).

Output dependency occurs when the destination operands are the same in a preceding FE group

instruction and a following LS group instruction.

For the stall cycles of an instruction with output dependency, the longest latency to the last write-

back among all the destination operands must be applied instead of “latency” (see figure 8.3 (f)).

A stall due to output dependency with respect to FPSCR, which reflects the result of an FP

Section 8 Pipelining

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REJ09B0366-0700

operation, never occurs. For example, when FADD follows FDIV with no dependency between FP

registers, FADD is not stalled even if both instructions update the cause field of FPSCR.

Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL,

FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS. See figure 8.3

(g).

If an executing instruction locks any resource—i.e. a function block that performs a basic

operation—a following instruction that happens to attempt to use the locked resource must be

stalled (figure 8.3 (h)). This kind of stall can be compensated by inserting one or more instructions

independent of the locked resource to separate the interfering instructions. For example, when a

load instruction and an ADD instruction that references the loaded value are consecutive, the 2-

cycle stall of the ADD is eliminated by inserting three instructions without dependency. Software

performance can be improved by such instruction scheduling.

Other penalties arise in the event of exceptions or external data accesses, as follows.

• Instruction TLB miss

• Instruction access to external memory (instruction cache miss, etc.)

• Data access to external memory (operand cache miss, etc.)

• Data access to a memory-mapped control register.

During the penalty cycles of an instruction TLB miss or external instruction access, no instruction

is issued, but execution of instructions that have already been issued continues. The penalty for a

data access is a pipeline freeze: that is, the execution of uncompleted instructions is interrupted

until the arrival of the requested data. The number of penalty cycles for instruction and data

accesses is largely dependent on the user's memory subsystems.

Section 8 Pipelining

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(a) Serial execution: non-parallel-executable instructions

ADD R2,R1

MOV.L @R4,R5

MOV R1,R2

SHAD R0,R1

ADD R2,R3

IDEX NA S

...

1 stall cycle

(b) Parallel execution: parallel-executable and no dependency

IDEX NA S

IDEX MA S

AND.B#1,@(R0,GBR) IDSX MA S

DSX MA S

DSX NA S

(d) Branch

1 issue cycle

4 issue cycles

...

IDEX NA S

2-cycle latency for I-stage of branch destination

1 stall cycle

IDEX NA S

BT/S L_far

ADD R0,R1

SUB R2,R3

BT/S L_far

ADD R0,R1

L_far

IDEX NA S

———

...

No stall

BT L_skip

ADD #1,R0

L_skip:

...

iDEAS

4 stall cycles

EX-group SHAD and EX-group ADD

cannot be executed in parallel. Therefore,

SHAD is issued first, and the following

ADD is recombined with the next

instruction.

EX-group ADD and LS-group MOV.L can

be executed in parallel. Overlapping of

stages in the 2nd instruction is possible.

AND.B and MOV are fetched

simultaneously, but MOV is stalled due to

resource locking. After the lock is released,

MOV is refetched together with the next

instruction.

No stall occurs if the branch is not taken.

If the branch is taken, the I-stage of the

branch destination is stalled for the period

of latency. This stall can be covered with a

delay slot instruction which is not parallel-

executable with the branch instruction.

Even if the BT/BF branch is taken, the I-

stage of the branch destination is not

stalled if the displacement is zero.

Figure 8.3 Examples of Pipelined Execution

Section 8 Pipelining

Rev.7.00 Oct. 10, 2008 Page 246 of 1074

REJ09B0366-0700

(e) Flow dependency

IDEX NA S

MOV R0,R1

ADD R2,R1

MOV.L @R1,R1

IDEX NA S

IDEX MA S

I...

...

Zero-cycle latency

1-cycle latency

1 stall cycle

MOV.L @R1,R1

ADD R0,R1

IDEX MA S

EX NA S

2-cycle latency

1 stall cycle

MOV.L @R1,R1

SHAD R1,R2

FADD FR1,FR2

STS FPUL,R1

STS FPSCR,R2

IDEX NA S

4-cycle latency for FPSCR

2 stall cycles

IDF1 F2 FS

IDEX MA S

2-cycle latency

2 stall cycles

EX NA Sd

1-cycle increase

IDF1 F2 FS

dF1 F2 FS

F1 F2 FS

dF1 F2 FS

EX NA S

FADD DR0,DR2

7-cycle latency for lower FR

8-cycle latency for upper FR

FMOV FR3,FR5

FMOV FR2,FR4

FLOAT FPUL,DR0

FMOV.S FR0,@-R15

FR3 write

FR2 write

IDF1 F2 FS

dF1 F2 FS

IDEX MA S

3-cycle latency for upper/lower FR

FR1 write

FR0 write

FLDI1 FR3

FIPR FV0,FV4

FMOV @R1,XD14

FTRV XMTRX,FV0

IDEX NA S

IDdF0 F1 F2 FS

Zero-cycle latency

3-cycle increase

3 stall cycles

IDEX MA S

IDdF0 F1 F2 FS

dF0 F1 FS

dF0 F2F1 FS

dF1F0 F2 FS

2-cycle latency

1-cycle increase

3 stall cycles

The following instruction, ADD, is not

stalled when executed after an instruction

with zero-cycle latency, even if there is

dependency.

ADD and MOV.L are not executed in

parallel, since MOV.L references the result

of ADD as its destination address.

Because MOV.L and ADD are not fetched

simultaneously in this example, ADD is

stalled for only 1 cycle even though the

latency of MOV.L is 2 cycles.

Due to the flow dependency between the

load and the SHAD/SHLD shift amount,

the latency of the load is increased to 3

cycles.

Figure 8.3 Examples of Pipelined Execution (cont)

Section 8 Pipelining

Rev.7.00 Oct. 10, 2008 Page 247 of 1074

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IDEX NA S

DF1 F2 FS

(e) Flow dependency (cont)

LDS R0,FPUL

FLOAT FPUL,FR0

LDS R1,FPUL

FLOAT FPUL,R1

Effectively 1-cycle latency for consecutive LDS/FLOAT instructions

IDEX NA S

DF1 F2 FS

IDEX NA S

Effectively 1-cycle latency for consecutive

FTRC/STS instructions

FTRC FR0,FPUL

STS FPUL,R0

FTRC FR1,FPUL

STS FPUL,R1

(f) Output dependency

DF1 F2 FS

F1 F2 FS

11-cycle latency

10 stall cycles = latency (11) - 1 The registers are written-back

in program order.

DF1 F2

dF1 F2 FS

F1 F2 FS

EX NA S

7-cycle latency for lower FR

8-cycle latency for upper FR

6 stall cycles = longest latency (8) - 2

FR2 write

FR3 write

DF1 F2

dF1 F2 FS

dF1

F0 F2 FS

(g) Anti-flow dependency

EX MA S

5 stall cycles

DF1 F2 FS

dF1 F2 FS

EX NA S

2 stall cycles

dF1 F2 FS

F1 F2 FS

FSQRT FR4

FMOV FR0,FR4

FADD DR0,DR2

FMOV FR0,FR3

FTRV XMTRX,FV0

FMOV @R1,XD0

FADD DR0,DR2

FMOV FR4,FR1

Figure 8.3 Examples of Pipelined Execution (cont)

Section 8 Pipelining

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(h) Resource conflict

F1 stage locked for 1 cycle

Latency

1 cycle/issue

1 stall cycle (F1 stage resource conflict)

FDIV FR6,FR7

FMAC FR0,FR8,FR9

FMAC FR0,FR10,FR11

FMAC FR0,FR12,FR13

FIPR FV8,FV0

FADD FR15,FR4

IDF1F0 F2 FS

IDF1 F2 FS

1 stall cycle

LDS.L @R15+,PR IDEX MA FS

DSX

SX NA S

3 stall cycles

STC GBR,R2

FADD DR0,DR2 IDF1 F2 FS

dF1 F2 FS

F1 F2 FS

EX MA S

f1 F2 FS

5 stall cycles

MAC.W @R1+,@R2+

IDEX MA S

f1 F2 FS

DEX MA S

f1 F2 FS

F1 F2 FS

dF1 F2 FS

F1 ...

3 stall cycles

1 stall

cycle

2 stall cycles

MAC.W @R1+,@R2+

FADD DR4,DR6

f1 stage can overlap preceding f1,

but F1 cannot overlap f1.

DEX MA

IDF1 F2 FS

F1 F2 FS

F1 F2

IDFS

IDF1 F2 FS

#1 #2 #3 .................................................. #10 #11#8 #9 #12

...

Figure 8.3 Examples of Pipelined Execution (cont)

Section 8 Pipelining

Rev.7.00 Oct. 10, 2008 Page 249 of 1074

REJ09B0366-0700

Table 8.3 Execution Cycles

Lock

Functional

Category No. Instruction

Instruc-

tion

Group

Issue

Rate Latency

Execu-

tion

Pattern Stage Start Cycles

1 EXTS.B Rm,Rn EX 1 1 #1 — — —

2 EXTS.W Rm,Rn EX 1 1 #1 — — —

3 EXTU.B Rm,Rn EX 1 1 #1 — — —

4 EXTU.W Rm,Rn EX 1 1 #1 — — —

5 MOV Rm,Rn MT 1 0 #1 — — —

6 MOV #imm,Rn EX 1 1 #1 — — —

7 MOVA @(disp,PC),R0 EX 1 1 #1 — — —

8 MOV.W @(disp,PC),Rn LS 1 2 #2 — — —

9 MOV.L @(disp,PC),Rn LS 1 2 #2 — — —

10 MOV.B @Rm,Rn LS 1 2 #2 — — —

11 MOV.W @Rm,Rn LS 1 2 #2 — — —

12 MOV.L @Rm,Rn LS 1 2 #2 — — —

13 MOV.B @Rm+,Rn LS 1 1/2 #2 — — —

14 MOV.W @Rm+,Rn LS 1 1/2 #2 — — —

15 MOV.L @Rm+,Rn LS 1 1/2 #2 — — —

16 MOV.B @(disp,Rm),R0 LS 1 2 #2 — — —

17 MOV.W @(disp,Rm),R0 LS 1 2 #2 — — —

18 MOV.L @(disp,Rm),Rn LS 1 2 #2 — — —

19 MOV.B @(R0,Rm),Rn LS 1 2 #2 — — —

20 MOV.W @(R0,Rm),Rn LS 1 2 #2 — — —

21 MOV.L @(R0,Rm),Rn LS 1 2 #2 — — —

22 MOV.B @(disp,GBR),R0 LS 1 2 #3 — — —

23 MOV.W @(disp,GBR),R0 LS 1 2 #3 — — —

24 MOV.L @(disp,GBR),R0 LS 1 2 #3 — — —

25 MOV.B Rm,@Rn LS 1 1 #2 — — —

26 MOV.W Rm,@Rn LS 1 1 #2 — — —

27 MOV.L Rm,@Rn LS 1 1 #2 — — —

28 MOV.B Rm,@-Rn LS 1 1/1 #2 — — —

29 MOV.W Rm,@-Rn LS 1 1/1 #2 — — —

30 MOV.L Rm,@-Rn LS 1 1/1 #2 — — —

Data transfer

instructions

31 MOV.B R0,@(disp,Rn) LS 1 1 #2 — — —

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Lock

Functional

Category No. Instruction

Instruc-

tion

Group

Issue

Rate Latency

Execu-

tion

Pattern Stage Start Cycles

32 MOV.W R0,@(disp,Rn) LS 1 1 #2 — — —

33 MOV.L Rm,@(disp,Rn) LS 1 1 #2 — — —

34 MOV.B Rm,@(R0,Rn) LS 1 1 #2 — — —

35 MOV.W Rm,@(R0,Rn) LS 1 1 #2 — — —

36 MOV.L Rm,@(R0,Rn) LS 1 1 #2 — — —

37 MOV.B R0,@(disp,GBR) LS 1 1 #3 — — —

38 MOV.W R0,@(disp,GBR) LS 1 1 #3 — — —

39 MOV.L R0,@(disp,GBR) LS 1 1 #3 — — —

40 MOVCA.L R0,@Rn LS 1 3–7 #12 MA 4 3–7

41 MOVT Rn EX 1 1 #1 — — —

42 OCBI @Rn LS 1 1–2 #10 MA 4 1–2

43 OCBP @Rn LS 1 1–5 #11 MA 4 1–5

44 OCBWB @Rn LS 1 1–5 #11 MA 4 1–5

45 PREF @Rn LS 1 1 #2 — — —

46 SWAP.B Rm,Rn EX 1 1 #1 — — —

47 SWAP.W Rm,Rn EX 1 1 #1 — — —

Data transfer

instructions

48 XTRCT Rm,Rn EX 1 1 #1 — — —

49 ADD Rm,Rn EX 1 1 #1 — — —

50 ADD #imm,Rn EX 1 1 #1 — — —

51 ADDC Rm,Rn EX 1 1 #1 — — —

52 ADDV Rm,Rn EX 1 1 #1 — — —

53 CMP/EQ #imm,R0 MT 1 1 #1 — — —

54 CMP/EQ Rm,Rn MT 1 1 #1 — — —

55 CMP/GE Rm,Rn MT 1 1 #1 — — —

56 CMP/GT Rm,Rn MT 1 1 #1 — — —

57 CMP/HI Rm,Rn MT 1 1 #1 — — —

58 CMP/HS Rm,Rn MT 1 1 #1 — — —

59 CMP/PL Rn MT 1 1 #1 — — —

60 CMP/PZ Rn MT 1 1 #1 — — —

61 CMP/STR Rm,Rn MT 1 1 #1 — — —

Fixed-point

arithmetic

instructions

62 DIV0S Rm,Rn EX 1 1 #1 — — —

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Lock

Functional

Category No. Instruction

Instruc-

tion

Group

Issue

Rate Latency

Execu-

tion

Pattern Stage Start Cycles

63 DIV0U EX 1 1 #1 — — —

64 DIV1 Rm,Rn EX 1 1 #1 — — —

65 DMULS.L Rm,Rn CO 2 4/4 #34 F1 4 2

66 DMULU.L Rm,Rn CO 2 4/4 #34 F1 4 2

67 DT Rn EX 1 1 #1 — — —

68 MAC.L @Rm+,@Rn+ CO 2 2/2/4/4 #35 F1 4 2

69 MAC.W @Rm+,@Rn+ CO 2 2/2/4/4 #35 F1 4 2

70 MUL.L Rm,Rn CO 2 4/4 #34 F1 4 2

71 MULS.W Rm,Rn CO 2 4/4 #34 F1 4 2

72 MULU.W Rm,Rn CO 2 4/4 #34 F1 4 2

73 NEG Rm,Rn EX 1 1 #1 — — —

74 NEGC Rm,Rn EX 1 1 #1 — — —

75 SUB Rm,Rn EX 1 1 #1 — — —

76 SUBC Rm,Rn EX 1 1 #1 — — —

Fixed-point

arithmetic

instructions

77 SUBV Rm,Rn EX 1 1 #1 — — —

78 AND Rm,Rn EX 1 1 #1 — — —

79 AND #imm,R0 EX 1 1 #1 — — —

80 AND.B #imm,@(R0,GBR) CO 4 4 #6 — — —

81 NOT Rm,Rn EX 1 1 #1 — — —

82 OR Rm,Rn EX 1 1 #1 — — —

83 OR #imm,R0 EX 1 1 #1 — — —

84 OR.B #imm,@(R0,GBR) CO 4 4 #6 — — —

85 TAS.B @Rn CO 5 5 #7 — — —

86 TST Rm,Rn MT 1 1 #1 — — —

87 TST #imm,R0 MT 1 1 #1 — — —

88 TST.B #imm,@(R0,GBR) CO 3 3 #5 — — —

89 XOR Rm,Rn EX 1 1 #1 — — —

90 XOR #imm,R0 EX 1 1 #1 — — —

Logical

instructions

91 XOR.B #imm,@(R0,GBR) CO 4 4 #6 — — —

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Lock

Functional

Category No. Instruction

Instruc-

tion

Group

Issue

Rate Latency

Execu-

tion

Pattern Stage Start Cycles

92 ROTL Rn EX 1 1 #1 — — —

93 ROTR Rn EX 1 1 #1 — — —

94 ROTCL Rn EX 1 1 #1 — — —

95 ROTCR Rn EX 1 1 #1 — — —

96 SHAD Rm,Rn EX 1 1 #1 — — —

97 SHAL Rn EX 1 1 #1 — — —

98 SHAR Rn EX 1 1 #1 — — —

99 SHLD Rm,Rn EX 1 1 #1 — — —

100 SHLL Rn EX 1 1 #1 — — —

101 SHLL2 Rn EX 1 1 #1 — — —

102 SHLL8 Rn EX 1 1 #1 — — —

103 SHLL16 Rn EX 1 1 #1 — — —

104 SHLR Rn EX 1 1 #1 — — —

105 SHLR2 Rn EX 1 1 #1 — — —

106 SHLR8 Rn EX 1 1 #1 — — —

Shift

instructions

107 SHLR16 Rn EX 1 1 #1 — — —

108 BF disp BR 1 2 (or 1) #1 — — —

109 BF/S disp BR 1 2 (or 1) #1 — — —

110 BT disp BR 1 2 (or 1) #1 — — —

111 BT/S disp BR 1 2 (or 1) #1 — — —

112 BRA disp BR 1 2 #1 — — —

113 BRAF Rn CO 2 3 #4 — — —

114 BSR disp BR 1 2 #14 SX 3 2

115 BSRF Rn CO 2 3 #24 SX 3 2

116 JMP @Rn CO 2 3 #4 — — —

117 JSR @Rn CO 2 3 #24 SX 3 2

Branch

instructions

118 RTS CO 2 3 #4 — — —

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Lock

Functional

Category No. Instruction

Instruc-

tion

Group

Issue

Rate Latency

Execu-

tion

Pattern Stage Start Cycles

119 NOP MT 1 0 #1 — — —

120 CLRMAC CO 1 3 #28 F1 3 2

121 CLRS CO 1 1 #1 — — —

122 CLRT MT 1 1 #1 — — —

123 SETS CO 1 1 #1 — — —

124 SETT MT 1 1 #1 — — —

125 TRAPA #imm CO 7 7 #13 — — —

126 RTE CO 5 5 #8 — — —

127 SLEEP CO 4 4 #9 — — —

128 LDTLB CO 1 1 #2 — — —

129 LDC Rm,DBR CO 1 3 #14 SX 3 2

130 LDC Rm,GBR CO 3 3 #15 SX 3 2

131 LDC Rm,Rp_BANK CO 1 3 #14 SX 3 2

132 LDC Rm,SR CO 4 4 #16 SX 3 2

133 LDC Rm,SSR CO 1 3 #14 SX 3 2

134 LDC Rm,SPC CO 1 3 #14 SX 3 2

135 LDC Rm,VBR CO 1 3 #14 SX 3 2

136 LDC.L @Rm+,DBR CO 1 1/3 #17 SX 3 2

137 LDC.L @Rm+,GBR CO 3 3/3 #18 SX 3 2

138 LDC.L @Rm+,Rp_BANK CO 1 1/3 #17 SX 3 2

139 LDC.L @Rm+,SR CO 4 4/4 #19 SX 3 2

140 LDC.L @Rm+,SSR CO 1 1/3 #17 SX 3 2

141 LDC.L @Rm+,SPC CO 1 1/3 #17 SX 3 2

142 LDC.L @Rm+,VBR CO 1 1/3 #17 SX 3 2

143 LDS Rm,MACH CO 1 3 #28 F1 3 2

144 LDS Rm,MACL CO 1 3 #28 F1 3 2

145 LDS Rm,PR CO 2 3 #24 SX 3 2

146 LDS.L @Rm+,MACH CO 1 1/3 #29 F1 3 2

147 LDS.L @Rm+,MACL CO 1 1/3 #29 F1 3 2

148 LDS.L @Rm+,PR CO 2 2/3 #25 SX 3 2

149 STC DBR,Rn CO 2 2 #20 — — —

System

control

instructions

150 STC SGR,Rn CO 3 3 #21 — — —

Section 8 Pipelining

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Lock

Functional

Category No. Instruction

Instruc-

tion

Group

Issue

Rate Latency

Execu-

tion

Pattern Stage Start Cycles

151 STC GBR,Rn CO 2 2 #20 — — —

152 STC Rp_BANK,Rn CO 2 2 #20 — — —

153 STC SR,Rn CO 2 2 #20 — — —

154 STC SSR,Rn CO 2 2 #20 — — —

155 STC SPC,Rn CO 2 2 #20 — — —

156 STC VBR,Rn CO 2 2 #20 — — —

157 STC.L DBR,@-Rn CO 2 2/2 #22 — — —

158 STC.L SGR,@-Rn CO 3 3/3 #23 — — —

159 STC.L GBR,@-Rn CO 2 2/2 #22 — — —

160 STC.L Rp_BANK,@-Rn CO 2 2/2 #22 — — —

161 STC.L SR,@-Rn CO 2 2/2 #22 — — —

162 STC.L SSR,@-Rn CO 2 2/2 #22 — — —

163 STC.L SPC,@-Rn CO 2 2/2 #22 — — —

164 STC.L VBR,@-Rn CO 2 2/2 #22 — — —

165 STS MACH,Rn CO 1 3 #30 — — —

166 STS MACL,Rn CO 1 3 #30 — — —

167 STS PR,Rn CO 2 2 #26 — — —

168 STS.L MACH,@-Rn CO 1 1/1 #31 — — —

169 STS.L MACL,@-Rn CO 1 1/1 #31 — — —

System

control

instructions

170 STS.L PR,@-Rn CO 2 2/2 #27 — — —

171 FLDI0 FRn LS 1 0 #1 — — —

172 FLDI1 FRn LS 1 0 #1 — — —

173 FMOV FRm,FRn LS 1 0 #1 — — —

174 FMOV.S @Rm,FRn LS 1 2 #2 — — —

175 FMOV.S @Rm+,FRn LS 1 1/2 #2 — — —

176 FMOV.S @(R0,Rm),FRn LS 1 2 #2 — — —

177 FMOV.S FRm,@Rn LS 1 1 #2 — — —

178 FMOV.S FRm,@-Rn LS 1 1/1 #2 — — —

179 FMOV.S FRm,@(R0,Rn) LS 1 1 #2 — — —

180 FLDS FRm,FPUL LS 1 0 #1 — — —

Single-

precision

floating-point

instructions

181 FSTS FPUL,FRn LS 1 0 #1 — — —

Section 8 Pipelining

Rev.7.00 Oct. 10, 2008 Page 255 of 1074

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Lock

Functional

Category No. Instruction

Instruc-

tion

Group

Issue

Rate Latency

Execu-

tion

Pattern Stage Start Cycles

182 FABS FRn LS 1 0 #1 — — —

183 FADD FRm,FRn FE 1 3/4 #36 — — —

184 FCMP/EQ FRm,FRn FE 1 2/4 #36 — — —

185 FCMP/GT FRm,FRn FE 1 2/4 #36 — — —

186 FDIV FRm,FRn FE 1 12/13 #37 F3 2 10

F1 11 1

187 FLOAT FPUL,FRn FE 1 3/4 #36 — — —

188 FMAC FR0,FRm,FRn FE 1 3/4 #36 — — —

189 FMUL FRm,FRn FE 1 3/4 #36 — — —

190 FNEG FRn LS 1 0 #1 — — —

191 FSQRT FRn FE 1 11/12 #37 F3 2 9

F1 10 1

192 FSUB FRm,FRn FE 1 3/4 #36 — — —

193 FTRC FRm,FPUL FE 1 3/4 #36 — — —

194 FMOV DRm,DRn LS 1 0 #1 — — —

195 FMOV @Rm,DRn LS 1 2 #2 — — —

196 FMOV @Rm+,DRn LS 1 1/2 #2 — — —

197 FMOV @(R0,Rm),DRn LS 1 2 #2 — — —

198 FMOV DRm,@Rn LS 1 1 #2 — — —

199 FMOV DRm,@-Rn LS 1 1/1 #2 — — —

Single-

precision

floating-point

instructions

200 FMOV DRm,@(R0,Rn) LS 1 1 #2 — — —

201 FABS DRn LS 1 0 #1 — — —

202 FADD DRm,DRn FE 1 (7, 8)/9 #39 F1 2 6

203 FCMP/EQ DRm,DRn CO 2 3/5 #40 F1 2 2

204 FCMP/GT DRm,DRn CO 2 3/5 #40 F1 2 2

205 FCNVDS DRm,FPUL FE 1 4/5 #38 F1 2 2

206 FCNVSD FPUL,DRn FE 1 (3, 4)/5 #38 F1 2 2

F3 2 23

F1 22 3

207 FDIV DRm,DRn FE 1 (24, 25)/

#41

F1 2 2

208 FLOAT FPUL,DRn FE 1 (3, 4)/5 #38 F1 2 2

Double-

precision

floating-point

instructions

209 FMUL DRm,DRn FE 1 (7, 8)/9 #39 F1 2 6

Section 8 Pipelining

Rev.7.00 Oct. 10, 2008 Page 256 of 1074

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Lock

Functional

Category No. Instruction

Instruc-

tion

Group

Issue

Rate Latency

Execu-

tion

Pattern Stage Start Cycles

210 FNEG DRn LS 1 0 #1 — — —

F3 2 22

F1 21 3

211 FSQRT DRn FE 1 (23, 24)/

#41

F1 2 2

212 FSUB DRm,DRn FE 1 (7, 8)/9 #39 F1 2 6

Double-

precision

floating-point

instructions

213 FTRC DRm,FPUL FE 1 4/5 #38 F1 2 2

214 LDS Rm,FPUL LS 1 1 #1 — — —

215 LDS Rm,FPSCR CO 1 4 #32 F1 3 3

216 LDS.L @Rm+,FPUL CO 1 1/2 #2 — — —

217 LDS.L @Rm+,FPSCR CO 1 1/4 #33 F1 3 3

218 STS FPUL,Rn LS 1 3 #1 — — —

219 STS FPSCR,Rn CO 1 3 #1 — — —

220 STS.L FPUL,@-Rn CO 1 1/1 #2 — — —

FPU system

control

instructions

221 STS.L FPSCR,@-Rn CO 1 1/1 #2 — — —

222 FMOV DRm,XDn LS 1 0 #1 — — —

223 FMOV XDm,DRn LS 1 0 #1 — — —

224 FMOV XDm,XDn LS 1 0 #1 — — —

225 FMOV @Rm,XDn LS 1 2 #2 — — —

226 FMOV @Rm+,XDn LS 1 1/2 #2 — — —

227 FMOV @(R0,Rm),XDn LS 1 2 #2 — — —

228 FMOV XDm,@Rn LS 1 1 #2 — — —

229 FMOV XDm,@-Rm LS 1 1/1 #2 — — —

230 FMOV XDm,@(R0,Rn) LS 1 1 #2 — — —

231 FIPR FVm,FVn FE 1 4/5 #42 F1 3 1

232 FRCHG FE 1 1/4 #36 — — —

233 FSCHG FE 1 1/4 #36 — — —

F0 2 4

Graphics

acceleration

instructions

234 FTRV XMTRX,FVn FE 1 (5, 5, 6,

7)/8

#43

F1 3 4

Notes: 1. See table 8.1 for the instruction groups.

2. Latency “L1/L2...”: Latency corresponding to a write to each register, including

MACH/MACL/FPSCR.

Example: MOV.B @Rm+, Rn “1/2”: The latency for Rm is 1 cycle, and the latency for

Rn is 2 cycles.

3. Branch latency: Interval until the branch destination instruction is fetched

Section 8 Pipelining

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4. Conditional branch latency “2 (or 1)”: The latency is 2 for a nonzero displacement, and

1 for a zero displacement.

5. Double-precision floating-point instruction latency “(L1, L2)/L3”: L1 is the latency for FR

[n+1], L2 that for FR [n], and L3 that for FPSCR.

6. FTRV latency “(L1, L2, L3, L4)/L5”: L1 is the latency for FR [n], L2 that for FR [n+1], L3

that for FR [n+2], L4 that for FR [n+3], and L5 that for FPSCR.

7. Latency “L1/L2/L3/L4” of MAC.L and MAC.W instructions: L1 is the latency for Rm, L2

that for Rn, L3 that for MACH, and L4 that for MACL.

8. Latency “L1/L2” of MUL.L, MULS.W, MULU.W, DMULS.L, and DMULU.L instructions:

L1 is the latency for MACH, and L2 that for MACL.

9. Execution pattern: The instruction execution pattern number (see figure 8.2)

10. Lock/stage: Stage locked by the instruction

11. Lock/start: Locking start cycle; 1 is the first D-stage of the instruction.

12. Lock/cycles: Number of cycles locked

Exceptions:

1. When a floating-point computation instruction is followed by an FMOV store, an STS

FPUL, Rn instruction, or an STS.L FPUL, @-Rn instruction, the latency of the floating-

point computation is decreased by 1 cycle.

2. When the preceding instruction loads the shift amount of the following SHAD/SHLD, the

latency of the load is increased by 1 cycle.

3. When an LS group instruction with a latency of less than 3 cycles is followed by a

double-precision floating-point instruction, FIPR, or FTRV, the latency of the first

instruction is increased to 3 cycles.

Example: In the case of FMOV FR4,FR0 and FIPR FV0,FV4, FIPR is stalled for 2

cycles.

4. When MAC/MUL/DMUL is followed by an STS.L MAC, @-Rn instruction, the latency of

MAC/MUL/DMUL is 5 cycles.

5. In the case of consecutive executions of MAC/MUL/DMUL, the latency is decreased to

2 cycles.

6. When an LDS to MAC is followed by an STS.L MAC, @-Rn instruction, the latency of

the LDS to MAC is 4 cycles.

7. When an LDS to MAC is followed by MAC/MUL/DMUL, the latency of the LDS to MAC

is 1 cycle.

8. When an FSCHG or FRCHG instruction is followed by an LS group instruction that

reads or writes to a floating-point register, the aforementioned LS group instruction[s]

cannot be executed in parallel.

9. When a single-precision FTRC instruction is followed by an “STS FPUL, Rn” instruction,

the latency of the single-precision FTRC instruction is 1 cycle.

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8.4 Usage Notes

The following are additional notes on pipeline operation and the method of calculating the number

of clock cycles.

The number of states (I clock cycles) required for stages where an external bus access, etc., occurs

may include an increased number of cycles, in addition to the number of memory access cycles set

by the bus state controller (BSC), etc.

For example, the occurrence of the following may result in idle cycles as observed from the

external bus.

1. Transfer of data from the logical address bus to the physical address bus

2. Transfer of data between buses using different operation clocks

The stages where external memory access occurs include some instruction fetch (I) and some

memory access (MA) stages.

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Section 9 Power-Down Modes

9.1 Overview

In the power-down modes, some of the on-chip peripheral modules and the CPU functions are

halted, enabling power consumption to be reduced.

9.1.1 Types of Power-Down Modes

The following power-down modes and functions are provided:

• Sleep mode

• Deep sleep mode

• Standby mode

• Hardware standby mode*

• Module standby function (TMU, RTC, SCI/SCIF, DMAC, SQ*, and UBC*)

Note: * SH7750S, SH7750R only

Table 9.1 shows the conditions for entering these modes from the program execution state, the

status of the CPU and peripheral modules in each mode, and the method of exiting each mode.

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Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes

Status

Power-

Down

Mode

Entering

Conditions

CPG

CPU

On-Chip

Memory

On-chip

Peripheral

Modules

Pins

External

Memory

Exiting

Method

Sleep SLEEP

instruction

executed

while STBY

bit is 0 in

STBCR

Operating Halted

(registers

held)

Held Operating Held Refreshing

• Interrupt

• Reset

Deep

sleep

SLEEP

instruction

executed

while STBY

bit is 0 in

STBCR,

and DSLP

bit is 1 in

STBCR2

Operating Halted

(registers

held)

Held Operating

(DMA

halted)

Held Self-

refreshing

• Interrupt

• Reset

Standby SLEEP

instruction

executed

while STBY

bit is 1 in

STBCR

Halted Halted

(registers

held)

Held Halted* Held Self-

refreshing

• Interrupt

• Reset

Hardware

standby

(SH7750S,

SH7750R)

Setting CA

pin low

Halted Halted Undefined Halted* High

impedance

Undefined • Power-on

reset

Module

standby

Setting

MSTP bit

to 1 in

STBCR/

STBCR2

Operating Operating Held Specified

modules

halted*

Held Refreshing

• Clearing

MSTP bit

to 0

• Reset

Note: * The RTC operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock

(RTC)).

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9.1.2 Register Configuration

Table 9.2 shows the registers used for power-down mode control.

Table 9.2 Power-Down Mode Registers

Name Abbreviation R/W Initial Value P4 Address

Area 7

Address

Access

Size

Standby control

STBCR R/W H'00 H'FFC00004 H'1FC00004 8

Standby control

STBCR2 R/W H'00 H'FFC00010 H'1FC00010 8

Clock stop

CLKSTP00 R/W H'00000000 H'FE0A0000 H'1E0A0000 32

Clock release

CLKSTPCLR00 W H'00000000 H'FE0A0008 H'1E0A0008 32

Note: * SH7750R only

9.1.3 Pin Configuration

Table 9.3 shows the pins used for power-down mode control.

Table 9.3 Power-Down Mode Pins

Pin Name Abbreviation I/O Function

Processor status 1

Processor status 0

STATUS1

STATUS0

Output Indicate the processor's operating status.

(STATUS1, STATUS0)

HH: Reset

HL: Sleep mode

LH: Standby mode

LL: Normal operation

Hardware standby

request

(SH7750S and

SH7750R only)

CA Input Transits to hardware standby mode by a

low-level input to the pin.

Legend:

H: High level

L: Low level

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9.2 Register Descriptions

9.2.1 Standby Control Register (STBCR)

The standby control register (STBCR) is an 8-bit readable/writable register that specifies the

power-down mode status. It is initialized to H'00 by a power-on reset via the RESET pin or due to

watchdog timer overflow.

Bit: 7 6 5 4 3 2 1 0

STBY PHZ PPU MSTP4 MSTP3 MSTP2 MSTP1 MSTP0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7—Standby (STBY): Specifies a transition to standby mode.

Bit 7: STBY Description

0 Transition to sleep mode on execution of SLEEP instruction (Initial value)

1 Transition to standby mode on execution of SLEEP instruction

Bit 6—Peripheral Module Pin High Impedance Control (PHZ): Controls the state of

peripheral module related pins in standby mode. When the PHZ bit is set to 1, peripheral module

related pins go to the high-impedance state in standby mode.

For the relevant pins, see section 9.2.2, Peripheral Module Pin High Impedance Control.

Bit 6: PHZ Description

0 Peripheral module related pins are in normal state (Initial value)

1 Peripheral module related pins go to high-impedance state

Bit 5—Peripheral Module Pin Pull-Up Control (PPU): Controls the state of peripheral module

related pins. When the PPU bit is cleared to 0, the pull-up resistor is turned on for peripheral

module related pins in the input or high-impedance state.

For the relevant pins, see section 9.2.3, Peripheral Module Pin Pull-Up Control.

Bit 5: PPU Description

0 Peripheral module related pin pull-up resistors are on (Initial value)

1 Peripheral module related pin pull-up resistors are off

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Bit 4—Module Stop 4 (MSTP4): Specifies stopping of the clock supply to the DMAC among the

on-chip peripheral modules. The clock supply to the DMAC is stopped when the MSTP4 bit is set

to 1. When DMA transfer is used, stop the transfer before setting the MSTP4 bit to 1. When DMA

transfer is performed after clearing the MSTP4 bit to 0, DMAC settings must be made again.

Bit 4: MSTP4 Description

0 DMAC operates (Initial value)

1 DMAC clock supply is stopped

Bit 3—Module Stop 3 (MSTP3): Specifies stopping of the clock supply to serial communication

interface channel 2 (SCIF) among the on-chip peripheral modules. The clock supply to the SCIF is

stopped when the MSTP3 bit is set to 1.

Bit 3: MSTP3 Description

0 SCIF operates (Initial value)

1 SCIF clock supply is stopped

Bit 2—Module Stop 2 (MSTP2): Specifies stopping of the clock supply to the timer unit (TMU)

among the on-chip peripheral modules. The clock supply to the TMU is stopped when the MSTP2

bit is set to 1.

Bit 2: MSTP2 Description

0 TMU operates (Initial value)

1 TMU clock supply is stopped

Bit 1—Module Stop 1 (MSTP1): Specifies stopping of the clock supply to the realtime clock

(RTC) among the on-chip peripheral modules. The clock supply to the RTC is stopped when the

MSTP1 bit is set to 1. When the clock supply is stopped, RTC registers cannot be accessed but the

counters continue to operate.

Bit 1: MSTP1 Description

0 RTC operates (Initial value)

1 RTC clock supply is stopped

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Bit 0—Module Stop 0 (MSTP0): Specifies stopping of the clock supply to serial communication

interface channel 1 (SCI) among the on-chip peripheral modules. The clock supply to the SCI is

stopped when the MSTP0 bit is set to 1.

Bit 0: MSTP0 Description

0 SCI operates (Initial value)

1 SCI clock supply is stopped

9.2.2 Peripheral Module Pin High Impedance Control

When bit 6 in the standby control register (STBCR) is set to 1, peripheral module related pins go

to the high-impedance state in standby mode.

• Relevant Pins

SCI related pins MD0/SCK MD1/TXD2

MD7/TXD MD8/RTS2

CTS2

DMA related pins DACK0 DRAK0

DACK1 DRAK1

• Other Information

The setting in this register is invalid when the above pins are used as port output pins.

For details of pin states, see Appendix E, Pin Functions.

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9.2.3 Peripheral Module Pin Pull-Up Control

When bit 5 in the standby control register (STBCR) is cleared to 0, peripheral module related pins

are pulled up when in the input or high-impedance state.

• Relevant Pins

SCI related pins MD0/SCK MD1/TXD2 MD2/RXD2

MD7/TXD MD8/RTS2 SCK2/MRESET

RXD CTS2

DMA related pins DREQ0 DACK0 DRAK0

DREQ1 DACK1 DRAK1

TMU related pin TCLK

• Other Information

The setting in this register is invalid in the hardware standby mode.

For details of pin states, see Appendix E, Pin Functions.

9.2.4 Standby Control Register 2 (STBCR2)

Standby control register 2 (STBCR2) is an 8-bit readable/writable register that specifies the sleep

mode and deep sleep mode transition conditions. It is initialized to H'00 by a power-on reset via

the RESET pin or due to watchdog timer overflow.

Bit: 7 6 5 4 3 2 1 0

DSLP STHZ — — — — MSTP6* MSTP5*

Initial value: 0 0 0 0 0 0 0 0

R/W:

R/W R/W R R R R R/W R/W

Note: * Reserved bit in the SH7750.

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Bit 7—Deep Sleep (DSLP): Specifies a transition to deep sleep mode

Bit 7: DSLP Description

0 Transition to sleep mode or standby mode on execution of SLEEP

instruction, according to setting of STBY bit in STBCR register (Initial value)

1 Transition to deep sleep mode on execution of SLEEP instruction*

Note: * When the STBY bit in the STBCR register is 0

Bit 6—STATUS Pin High-Impedance Control (STHZ): This bit selects whether the STATUS0

and STATUS1 pins are set to high-impedance when in hardware standby mode.

Bit 6: STHZ Description

0 Sets STATUS0, 1 pins to high-impedance when in hardware standby mode

(Initial value)

1 Drives STATUS0, 1 pins to LH when in hardware standby mode

Bits 5 to 2—Reserved: Only 0 should only be written to these bits; operation cannot be

guaranteed if 1 is written. These bits are always read as 0.

Bits 1 and 0 (SH7750)—Reserved: Only 0 should only be written to these bits; operation cannot

be guaranteed if 1 is written. These bits are always read as 0.

Bit 1 (SH7750S and SH7750R)—Module Stop 6 (MSTP6): Specifies that the clock supply to

the store queue (SQ) in the cache controller (CCN) is stopped. Setting the MSTP6 bit to 1 stops

the clock supply to the SQ, and the SQ functions are therefore unavailable.

Bit 1: MSTP6 Description

0 SQ operating (Initial value)

1 Clock supply to SQ stopped

Bit 0 (SH7750S and SH7750R)—Module Stop 5 (MSTP5): Specifies stopping of the clock

supply to the user break controller (UBC) among the on-chip peripheral modules. See section

20.6, User Break Controller Stop Function, for how to set the clock supply.

Bit 0: MSTP5 Description

0 UBC operating (Initial value)

1 Clock supply to UBC stopped

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9.2.5 Clock-Stop Register 00 (CLKSTP00) (SH7750R Only)

Clock-stop register 00 (CLKSTP00) controls the operation clock for peripheral modules. To

resume supply of the clock signal, write a 1 to the corresponding bit in the CLKSTPCLR00

CLKSTP00 register is a 32-bit register that can be read from or written to. It is initialized to

H'0000 0000 by a power-on reset, but not by a manual reset or when the device enters standby

mode.

Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

— — — — — — — — — — — — — — — —

Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W: R R R R R R R R R R R R R R R R

Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

— — — — — — — — — — — — — —

CSTP1 CSTP0

Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W: R R R R R R R R R R R R R R R/W R/W

Bits 31 to 2—Reserved: Any data written to these bits should always be 0. These bits are always

read as 0.

Bit 1—Clock stop 1 (CSTP1): This bit specifies stopping of the peripheral clock supply to

channels 3 and 4 of the timer unit (TMU).

Bit 1: CSTP1 Description

0 Peripheral clock is supplied to TMU channels 3 and 4 (Initial value)

1 Peripheral clock supply to TMU channels 3 and 4 is stopped

Bit 0⎯Clock Stop 0 (CSTP0): Specifies stopping of the peripheral clock supply to the interrupt

controller (INTC). If this bit is set, INTC does not detect interrupts on the TMU's channels 3 and

Bit 0: CSTP0 Description

0 INTC detects interrupts on channels 3 and 4 of the TMU (Initial value)

1 INTC does not detect interrupts on channels 3 and 4 of the TMU

Section 9 Power-Down Modes

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9.2.6 Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only)

The clock-stop clear register 00 (CLKSTPCLR00) is a 32-bit write-only register that clears the

corresponding bits of the CLKSTP00 register.

Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W: W W W W W W W W W W W W W W W W

Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W: W W W W W W W W W W W W W W W W

Bits 31 to 0⎯Clock-Stop Clear: Specify whether or not to clear the corresponding bit of the

clock-stop setting. See section 9.2.5, Clock-Stop Register 00 (CLKSTP00) (SH7750R only), for

the correspondence between the bits and the clocks that are stopped.

Bits 31 to 0 Description

0 Does not change the clock-stop setting for the corresponding clock

1 Clears the clock-stop setting for the corresponding clock

9.3 Sleep Mode

9.3.1 Transition to Sleep Mode

If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0, the chip switches

from the program execution state to sleep mode. After execution of the SLEEP instruction, the

CPU halts but its register contents are retained. The on-chip peripheral modules continue to

operate, and the clock continues to be output from the CKIO pin.

In sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at the

STATUS0 pin.

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9.3.2 Exit from Sleep Mode

Sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a

reset. In sleep mode, interrupts are accepted even if the BL bit in the SR register is 1. If necessary,

SPC and SSR should be saved to the stack before executing the SLEEP instruction.

Exit by Interrupt: When an NMI, IRL, or on-chip peripheral module interrupt is generated, sleep

mode is exited and interrupt exception handling is executed. The code corresponding to the

interrupt source is set in the INTEVT register.

Exit by Reset: Sleep mode is exited by means of a power-on or manual reset via the RESET pin,

or a power-on or manual reset executed when the watchdog timer overflows.

9.4 Deep Sleep Mode

9.4.1 Transition to Deep Sleep Mode

If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0 and the DSLP bit

in STBCR2 is set to 1, the chip switches from the program execution state to deep sleep mode.

After execution of the SLEEP instruction, the CPU halts but its register contents are retained.

Except for the DMAC*, on-chip peripheral modules continue to operate. The clock continues to be

output to the CKIO pin, but all bus access (including auto refresh) stops. When using memory that

requires refreshing, set the self-refresh function prior to making the transition to deep sleep mode.

In deep sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at

the STATUS0 pin.

Note: * Terminate DMA transfers prior to making the transition to deep sleep mode. If you

make a transition to deep sleep mode while DMA transfers are in progress, the results

of those transfers cannot be guaranteed.

9.4.2 Exit from Deep Sleep Mode

As with sleep mode, deep sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip

peripheral module) or a reset.

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9.5 Standby Mode

9.5.1 Transition to Standby Mode

If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches

from the program execution state to standby mode. In standby mode, the on-chip peripheral

modules halt as well as the CPU. Clock output from the CKIO pin is also stopped.

The CPU and cache register contents are retained. Some on-chip peripheral module registers are

initialized. The state of the peripheral module registers in standby mode is shown in table 9.4.

Table 9.4 State of Registers in Standby Mode

Module

Initialized Registers

Registers That Retain

Their Contents

Interrupt controller — All registers

User break controller — All registers

Bus state controller — All registers

On-chip oscillation circuits — All registers

Timer unit TSTR register* All registers except TSTR

Realtime clock — All registers

Direct memory access controller — All registers

Serial communication interface See Appendix A, Address List See Appendix A, Address List

Notes: DMA transfer should be terminated before making a transition to standby mode. Transfer

results are not guaranteed if standby mode is entered during transfer.

* Not initialized when the realtime clock (RTC) is in use (see section 12, Timer Unit

(TMU)).

The procedure for a transition to standby mode is shown below.

1. Clear the TME bit in the WDT timer control register (WTCSR) to 0, and stop the WDT.

Set the initial value for the up-count in the WDT timer counter (WTCNT), and set the clock to

be used for the up-count in bits CKS2–CKS0 in the WTCSR register.

2. Set the STBY bit in the STBCR register to 1, then execute a SLEEP instruction.

3. When standby mode is entered and the chip's internal clock stops, a low-level signal is output

at the STATUS1 pin, and a high-level signal at the STATUS0 pin.

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9.5.2 Exit from Standby Mode

Standby mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a

reset via the RESET pin.

Exit by Interrupt: A hot start can be performed by means of the on-chip WDT. When an NMI,

IRL*1, RTC, or GPIO*2 interrupt is detected, the WDT starts counting. After the count overflows,

clocks are supplied to the entire chip, standby mode is exited, and the STATUS1 and STATUS0

pins both go low. Interrupt exception handling is then executed, and the code corresponding to the

interrupt source is set in the INTEVT register. In standby mode, interrupts are accepted even if the

BL bit in the SR register is 1, and so, if necessary, SPC and SSR should be saved to the stack

before executing the SLEEP instruction.

The phase of the CKIO pin clock output may be unstable immediately after an interrupt is

detected, until standby mode is exited.

Notes: 1. Only when the RTC clock (32.768 kHz) is operating (see section 19.2.2, IRL

Interrupts), standby mode can be exited by means of IRL3–IRL0 (when the IRL3–

IRL0 level is higher than the SR register IMASK mask level).

2. GPIO can be used to cancel standby mode when the RTC clock (32.768 kHz) is

operating (when the GPIO level is higher than the SR register IMASK mask level).

Exit by Reset: Standby mode is exited by means of a reset (power-on or manual) via the RESET

pin. The RESET pin should be held low until clock oscillation stabilizes. The internal clock

continues to be output at the CKIO pin.

9.5.3 Clock Pause Function

In standby mode, it is possible to stop or change the frequency of the clock input from the EXTAL

pin. This function is used as follows.

1. Enter standby mode following the transition procedure described above.

2. When standby mode is entered and the chip's internal clock stops, a low-level signal is output

at the STATUS1 pin, and a high-level signal at the STATUS0 pin.

3. The input clock is stopped, or its frequency changed, after the STATUS1 pin goes low and the

STATUS0 pin high.

4. When the frequency is changed, input an NMI or IRL interrupt after the change. When the

clock is stopped, input an NMI or IRL interrupt after applying the clock.

5. After the time set in the WDT, clock supply begins inside the chip, the STATUS1 and

STATUS0 pins both go low, and operation is resumed from interrupt exception handling.

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9.6 Module Standby Function

9.6.1 Transition to Module Standby Function

Setting the MSTP6–MSTP0, CSTP1, and CSTP0 bits in the standby control register to 1 enables

the clock supply to the corresponding on-chip peripheral modules to be halted. Use of this

function allows power consumption in sleep mode to be further reduced.

In the module standby state, the on-chip peripheral module external pins retain their states prior to

halting of the modules, and most registers retain their states prior to halting of the modules.

Section 9 Power-Down Modes

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Bit Description

CSTP1*6 0 Peripheral clock is supplied to TMU channels 3 and 4

1 Peripheral clock supplied to TMU channels 3 and 4 is stopped

CSTP0*6 0 INTC detects interrupts on TMU channels 3 and 4

1 INTC does not detect interrupts on TMU channels 3 and 4

MSTP6*4 0 SQ operates

1 Clock supplied to SQ is stopped

MSTP5*4 0 UBC operates

1 Clock supplied to UBC is stopped*5

MSTP4 0 DMAC operates

1 Clock supplied to DMAC is stopped*3

MSTP3 0 SCIF operates

1 Clock supplied to SCIF is stopped

MSTP2 0 TMU operates

1 Clock supplied to TMU is stopped, and register is initialized*1

MSTP1 0 RTC operates

1 Clock supplied to RTC is stopped*2

MSTP0 0 SCI operates

1 Clock supplied to SCI is stopped

Notes: 1. The register initialized is the same as in standby mode, but initialization is not

performed if the RTC clock is not in use (see section 12, Timer Unit (TMU)).

2. The counter operates when the START bit in RCR2 is 1 (see section 11, Realtime

Clock (RTC)).

3. Terminate DMA transfers prior to making the transition to module standby mode. If you

make a transition to module standby mode while DMA transfers are in progress, the

results of those transfers cannot be guaranteed.

4. SH7750S, SH7750R only

5. For details, see section 20.6, User Break Controller Stop Function.

6. SH7750R only

9.6.2 Exit from Module Standby Function

The module standby function is exited by clearing the MSTP6–MSTP0, CSTP1, and CSTP0 bits

to 0, or by a power-on reset via the RESET pin or a power-on reset caused by watchdog timer

overflow.

Section 9 Power-Down Modes

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9.7 Hardware Standby Mode (SH7750S, SH7750R Only)

9.7.1 Transition to Hardware Standby Mode

Setting the CA pin level low effects a transition to hardware standby mode. In this mode, all

modules other than the RTC stop, as in the standby mode selected using the SLEEP command.

Hardware standby mode differs from standby mode as follows:

1. Interrupts and manual resets are not available;

2. All output pins other than the STATUS pin are in the high-impedance state and the pull-up

resistance is off.

3. On the SH7750S, the RTC continues to operate even when no power is supplied to power pins

other than the RTC power supply pin.

The status of the STATUS pin is determined by the STHZ bit of STBCR2. See appendix E, Pin

Functions, for details of output pin states.

Operation when a low-level is input to the CA pin when in the standby mode depends on the CPG

status, as follows:

1. In standby mode

The clock remains stopped and a transition is made to the hardware standby state.

2. When WDT is operating when standby mode is exited by interrupt

Standby mode is momentarily exited, the CPU restarts, and then a transition is made to

hardware standby mode.

Note that the level of the CA pin must be kept low while in hardware standby mode.

9.7.2 Exit from Hardware Standby Mode

Hardware standby mode can only be exited by effecting a power-on reset.

Setting the CA pin level high after the RESET pin level has been set low and the SCK2 pin high

starts the clock to oscillate. The RESET pin level should be kept low until the clock has stabilized,

then set high so that the CPU starts the power-on reset exiting procedure.

Note that hardware standby mode cannot be exited using interrupts or a manual reset.

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9.7.3 Usage Notes

1. The CA pin level must be kept high when the RTC power supply is started (figure 9.15).

2. On the SH7750R, power must be supplied to the other power supply pins (VDD, VDDQ, VDD−CPG,

VDD−PLL1, and VDD−PLL2), in addition to the RTC power supply pin, in hardware standby mode.

9.8 STATUS Pin Change Timing

The STATUS1 and STATUS0 pin change timing is shown below.

The meaning of the STATUS pin settings is as follows:

Reset: HH (STATUS1 high, STATUS0 high)

Sleep: HL (STATUS1 high, STATUS0 low)

Standby: LH (STATUS1 low, STATUS0 high)

Normal: LL (STATUS1 low, STATUS0 low)

The meaning of the clock units is as follows:

Bcyc: Bus clock cycle

Pcyc: Peripheral clock cycle

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9.8.1 In Reset

Power-On Reset

CKIO

RESET

STATUS

SCK2

Normal Reset Normal

0–5 Bcyc

0–30 Bcyc

PLL stabilization

time

Figure 9.1 STATUS Output in Power-On Reset

Manual Reset

CKIO

RESET*

STATUS Normal Reset Normal

SCK2

0–30 Bcyc

≥ 0 Bcyc

Note: * In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting

until the end of the currently executing bus cycle.

Must be asserted for

tRESW or longer

Figure 9.2 STATUS Output in Manual Reset

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9.8.2 In Exit from Standby Mode

Standby → Interrupt

CKIO

STATUS Normal Standby Normal

WDT count

Oscillation stops Interrupt request WDT overflow

Figure 9.3 STATUS Output in Standby → Interrupt Sequence

Standby → Power-On Reset

Reset

CKIO

ESET

STATUS Normal Reset Normal

0–10 Bcyc

Standby

Oscillation stops

SCK2

0–30 Bcyc

Notes: 1. When standby mode is exited by means of a power-on reset, a WDT count is not

performed. Hold RESET low for the PLL oscillation stabilization time.

2. Undefined

Figure 9.4 STATUS Output in Standby → Power-On Reset Sequence

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Standby → Manual Reset

Reset

CKIO

ESET

STATUS Normal Reset Normal

0–10 Bcyc

Standby

Oscillation stops

SCK2

0–30 Bcyc

Notes: 1. When standby mode is exited by means of a manual reset, a WDT count is not

performed. Hold RESET low for the PLL oscillation stabilization time.

2. Undefined

Figure 9.5 STATUS Output in Standby → Manual Reset Sequence

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9.8.3 In Exit from Sleep Mode

Sleep → Interrupt

CKIO

STATUS Normal Sleep Normal

Interrupt request

Figure 9.6 STATUS Output in Sleep → Interrupt Sequence

Sleep → Power-On Reset

Reset

CKIO

STATUS Normal Reset

Sleep Normal

0–10 Bcyc 0–30 Bcyc

ESET*1

SCK2

Notes: 1. When sleep mode is exited by means of a power-on reset, hold RESET low for the

oscillation stabilization time.

2. Undefined

Figure 9.7 STATUS Output in Sleep → Power-On Reset Sequence

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Sleep → Manual Reset

Reset

RESET*

STATUS Normal Reset

Sleep Normal

CKIO

0–30 Bcyc 0–30 Bcyc

Note: * Hold RESET low until STATUS = reset.

SCK2

Figure 9.8 STATUS Output in Sleep → Manual Reset Sequence

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9.8.4 In Exit from Deep Sleep Mode

Deep Sleep → Interrupt

CKIO

STATUS Normal Sleep Normal

Interrupt request

Figure 9.9 STATUS Output in Deep Sleep → Interrupt Sequence

Deep Sleep → Power-On Reset

Reset

CKIO

STATUS Normal Sleep Reset Normal

0–10 Bcyc 0–30 Bcyc

RESET

SCK2

Notes: 1. When deep sleep mode is exited by means of a power-on reset, hold RESET low for the

oscillation stabilization time.

2. Undefined

Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence

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Deep Sleep → Manual Reset

Reset

RESET

STATUS Normal Sleep Reset Normal

CKIO

0–30 Bcyc 0–30 Bcyc

Note: * Hold RESET low until STATUS = reset.

SCK2

Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence

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9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only)

Figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode.

The CA pin level must be kept low while in hardware standby mode.

After setting the RESET pin level low, the clock starts when the CA pin level is switched to high.

CKIO

SCK2 (High)

STATUS Reset

0–10 Bcyc0–10 Bcyc

RESET

Waiting for end of bus cycle

Notes: 1. Same at sleep and reset.

2. Undefined

3. High impedance when STBCR2. STHZ = 0

Normal

Standby

Figure 9.12 Hardware Standby Mode Timing

(When CA = Low in Normal Operation)

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CKIO

(High)

STATUS Standby

0–10 Bcyc

Normal

RESET

(High)

SCK2

WDT count

WDT overflowInterrupt request

Note: * High impedance when STBCR2. STHZ = 0

Standby*

Figure 9.13 Hardware Standby Mode Timing

(When CA = Low in WDT Operation)

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DDQ

SCK2

Min 0s

Max 50 μs

ESET

Note: * V

DDQ

, V

DD-CPG

, V

DD-PLL1

, V

DD-PLL2

min

Figure 9.14 Timing When Power Other than VDD-RTC Is Off

DD-RTC

SCK2

RESET

, V

DDQ*

Min 0s

Note: * V

, V

DD-PLL1/2

, V

DDQ

, V

DD-CPG

Power-on oscillation

setting time

Figure 9.15 Timing When VDD-RTC Power Is Off → On

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9.9 Usage Notes

9.9.1 Note on Current Consumption

After a power-on reset, the current consumption may exceed the maximum value for sleep mode

or standby mode during the period until one or more of the arithmetic operation or floating-point

operation instructions listed below is executed.

1. Arithmetic operation instructions

MAC.W, MAC.L

2. Floating-point operation instructions

⎯ When FPSCR.PR = 0

FADD, FSUB, FMUL, FMAC, FLOAT, FTRC, FDIV, FSQRT, FIPR, FTRV

⎯ When FPSCR.PR = 1

FADD, FSUB, FMUL, FLOAT, FTRC, FDIV, FSQRT, FCNVSD, FCNVDS

Workaround: After a power-on reset, execute one or more of the above instructions before

transitioning to sleep mode or standby mode.

Example: To reduce the effect on FPSCR, arrange the following two instructions starting at

H'A0000000.

Address Instruction String

H'A0000000 FLDI1 FR0

H'A0000002 FADD FR0, FR0 ; FLDI1 FR0 loads 1 into FR0,

: : ; so the cause and flag bits of FPSCR are not set to 1.

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Section 10 Clock Oscillation Circuits

10.1 Overview

The on-chip oscillation circuits comprise a clock pulse generator (CPG) and a watchdog timer

(WDT).

The CPG generates the clocks supplied inside the processor and performs power-down mode

control.

The WDT is a single-channel timer used to count the clock stabilization time when exiting standby

mode or the frequency is changed. It can be used as a normal watchdog timer or an interval timer.

10.1.1 Features

The CPG has the following features:

• Three clocks

The CPG can generate the CPU clock (Ick) used by the CPU, FPU, caches, and TLB, the

peripheral module clock (Pck) used by the peripheral modules, and the bus clock (Bck) used

by the external bus interface.

• Six clock modes

Any of six clock operating modes can be selected, with different combinations of CPU clock,

bus clock, and peripheral module clock division ratios after a power-on reset.

• Frequency change function

PLL (phase-locked loop) circuits and a frequency divider in the CPG enable the CPU clock,

bus clock, and peripheral module clock frequencies to be changed independently. Frequency

changes are performed by software in accordance with the settings in the frequency control

• PLL on/off control

Power consumption can be reduced by stopping the PLL circuits during low-frequency

operation.

• Power-down mode control

It is possible to stop the clock in sleep mode and standby mode, and to stop specific modules

with the module standby function.

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The WDT has the following features

• Can be used to secure clock stabilization time

Used when exiting standby mode or a temporary standby state when the clock frequency is

changed.

• Can be switched between watchdog timer mode and interval timer mode

• Internal reset generation in watchdog timer mode

An internal reset is executed on counter overflow.

Power-on reset or manual reset can be selected.

• Interrupt generation in interval timer mode

An interval timer interrupt is generated on counter overflow.

• Selection of eight counter input clocks

Any of eight clocks can be selected, scaled from the ×1 clock of frequency divider 2 shown in

figure 10.1.

The CPG is described in sections 10.2 to 10.6, and the WDT in sections 10.7 to 10.9.

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10.2 Overview of CPG

10.2.1 Block Diagram of CPG

Figure 10.1 (1) shows a block diagram of the CPG in the SH7750 and SH7750S, and figure 10.1

(2) a block diagram of the CPG in the SH7750R.

Legend:

FRQCR: Frequency control register

STBCR: Standby control register

STBCR2: Standby control register 2

Oscillator circuit

PLL circuit 1

Frequency

divider 2

Crystal

oscillation

circuit

Frequency

divider 1

PLL circuit 2

CPU clock (Ick)

cycle Icyc

Peripheral module

clock (Pck) cycle

Pcyc

Bus clock (Bck)

cycle Bcyc

CPG control unit

Clock frequency

control circuit

Standby control

circuit

Bus interface

Internal bus

XTAL

EXTAL

MD8

CKIO

MD2

MD1

MD0

FRQCR STBCR2

×1

×1/2

×1/3

×1/4

×1/6

×1/8

×6

×1/2

×1

STBCR

Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S)

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Legend:

FRQCR:

STBCR:

STBCR2:

Frequency control register

Standby control register

Standby control register 2

Oscillator circuit

PLL circuit 1

Frequency

divider 2

Crystal

oscillation

circuit

CPU clock (Ick)

cycle Icyc

Peripheral module

clock (Pck) cycle

Pcyc

Bus clock (Bck)

cycle Bcyc

CPG control unit

Clock frequency

control circuit

Standby control

circuit

Bus interface

Internal bus

XTAL

EXTAL

MD8

CKIO

MD2

MD1

MD0

FRQCR

STBCR2

×1

×1/2

×1/3

×1/4

×1/6

×1/8

×6

×12

PLL circuit 2

×1

STBCR

Figure 10.1 (2) Block Diagram of CPG (SH7750R)

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The function of each of the CPG blocks is described below.

PLL Circuit 1: PLL circuit 1 has a function for multiplying the clock frequency from the EXTAL

pin or crystal oscillation circuit by 6 with the SH7750 and SH7750S, and by 6 or 12 with the

SH7750R. Starting and stopping is controlled by a frequency control register setting. Control is

performed so that the internal clock rising edge phase matches the input clock rising edge phase.

PLL Circuit 2: PLL circuit 2 coordinates the phases of the bus clock and the CKIO pin output

clock. Starting and stopping is controlled by a frequency control register setting.

Crystal Oscillation Circuit: This is the oscillator circuit used when a crystal resonator is

connected to the XTAL and EXTAL pins. Use of the crystal oscillation circuit can be selected

with the MD8 pin.

Frequency Divider 1 (SH7750 and SH7750S only): Frequency divider 1 has a function for

adjusting the clock waveform duty to 50% by halving the input clock frequency when clock input

from the EXTAL pin is supplied internally without using PLL circuit 1.

Frequency Divider 2: Frequency divider 2 generates the CPU clock (Ick), bus clock (Bck), and

peripheral module clock (Pck). The division ratio is set in the frequency control register.

Clock Frequency Control Circuit: The clock frequency control circuit controls the clock

frequency by means of the MD pins and frequency control register.

Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillation

circuits and other modules when the clock is switched and in sleep and standby modes.

Frequency Control Register (FRQCR): The frequency control register contains control bits for

clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU clock, bus clock,

and peripheral module clock frequency division ratios.

Standby Control Register (STBCR): The standby control register contains power save mode

control bits. For further information on the standby control register, see section 9, Power-Down

Modes.

Standby Control Register 2 (STBCR2): Standby control register 2 contains a power save mode

control bit. For further information on standby control register 2, see section 9, Power-Down

Modes.

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10.2.2 CPG Pin Configuration

Table 10.1 shows the CPG pins and their functions.

Table 10.1 CPG Pins

Pin Name Abbreviation I/O Function

Mode control pins MD0 Input Set clock operating mode

MD1

MD2

XTAL Output Connects crystal resonator

EXTAL Input Connects crystal resonator, or used as

external clock input pin

Crystal I/O pins

(clock input pins)

MD8 Input Selects use/non-use of crystal resonator

When MD8 = 0, external clock is input from

EXTAL

When MD8 = 1, crystal resonator is

connected directly to EXTAL and XTAL

Clock output pin CKIO Output Used as external clock output pin

Level can also be fixed

CKIO enable pin CKE Output 0 when CKIO output clock is unstable and in

case of synchronous DRAM self-refreshing*

Note: * Set to 1 in a power-on reset.

For details of synchronous DRAM self-refreshing, see section 13.3.5, Synchronous

DRAM Interface.

10.2.3 CPG Register Configuration

Table 10.2 shows the CPG register configuration.

Table 10.2 CPG Register

Name

Abbreviation

R/W

Initial Value

P4 Address

Area 7

Address

Access

Size

Frequency control

FRQCR R/W Undefined* H'FFC00000 H'1FC00000 16

Note: * Depends on the clock operating mode set by pins MD2–MD0.

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10.3 Clock Operating Modes

Tables 10.3 (1) and 10.3 (2) show the clock operating modes corresponding to various

combinations of mode control pin (MD2–MD0) settings (initial settings such as the frequency

division ratio).

Table 10.4 shows FRQCR settings and internal clock frequencies.

Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S)

External

Pin Combination

Frequency

(vs. Input Clock)

Clock

Operating

Mode MD2 MD1 MD0

1/2

Frequency

Divider PLL1 PLL2

CPU

Clock

Bus

Clock

Peripheral

Module

Clock

FRQCR

Initial Value

0 0 Off On On 6 3/2 3/2 H'0E1A

1 Off On On 6 1 1 H'0E23

2 0 On On On 3 1 1/2 H'0E13

1 Off On On 6 2 1 H'0E13

4 0 On On On 3 3/2 3/4 H'0E0A

1 0

1 Off On On 6 3 3/2 H'0E0A

Notes: 1. Turning on/off of the ½ frequency divider is solely determined by the clock operating

mode.

2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input

frequency (fEX) and CKIO clock output (fOP) in section 22.3.1, Clock and Control Signal

Timing.

Table 10.3 (2) Clock Operating Modes (SH7750R)

External

Pin Combination

Frequency

(vs. Input Clock)

Clock

Operating

Mode MD2 MD1 MD0 PLL1 PLL2

CPU

Clock

Bus

Clock

Peripheral

Module Clock

FRQCR

Initial Value

0 0 On (×12) On 12 3 3 H'0E1A

1 On (×12) On 12 3/2 3/2 H'0E2C

2 0 On (×6) On 6 2 1 H'0E13

1 On (×12) On 12 4 2 H'0E13

4 0 On (×6) On 6 3 3/2 H'0E0A

1 On (×12) On 12 6 3 H'0E0A

1 0 Off (×6) Off 1 1/2 1/2 H'0808

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Notes: 1. The multiplication factor of PLL 1 is solely determined by the clock operating mode.

2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input

frequency (fEX) and CKIO clock output (fOP) in section 22.3.1, Clock and Control Signal

Timing.

Table 10.4 FRQCR Settings and Internal Clock Frequencies

Frequency Division Ratio of Frequency Divider 2

FRQCR

(Lower 9 Bits) CPU Clock Bus Clock Peripheral Module Clock

H'008 1/2

H'00A 1/4

H'00C

1/2

1/8

H'011 1/3

H'013

1/3

1/6

H'01A 1/4

H'01C

1/4

1/8

H'023 1/6 1/6

H'02C

1/8 1/8

H'05A 1/4

H'05C

1/4

1/8

H'063 1/6 1/6

H'06C

1/2

1/8 1/8

H'0A3 1/3 1/6 1/6

H'0EC 1/4 1/8 1/8

Note: For the lower 9 bits of FRQCR, do not set values other than those shown in the table.

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10.4 CPG Register Description

10.4.1 Frequency Control Register (FRQCR)

The frequency control register (FRQCR) is a 16-bit readable/writable register that specifies

use/non-use of clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU

clock, bus clock, and peripheral module clock frequency division ratios. Only word access can be

used on FRQCR.

FRQCR is initialized only by a power-on reset via the RESET pin. The initial value of each bit is

determined by the clock operating mode.

Bit: 15 14 13 12 11 10 9 8

— — — — CKOEN PLL1EN PLL2EN IFC2

Initial value: 0 0 0 0 1 1 1 —

R/W: R/W R/W R/W R R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

IFC1 IFC0 BFC2 BFC1 BFC0 PFC2 PFC1 PFC0

Initial value: — — — — — — — —

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 to 12—Reserved: These bits are always read as 0, and should only be written with 0.

Bit 11—Clock Output Enable (CKOEN): Specifies whether a clock is output from the CKIO

pin or the CKIO pin is placed in the high-impedance state. When the CKIO pin goes to the high-

impedance state, operation continues at the operating frequency before this state was entered.

When the CKIO pin becomes high-impedance, it is pulled up.

Bit 11: CKOEN Description

0 CKIO pin goes to high-impedance state (pulled up*)

1 Clock is output from CKIO pin (Initial value)

Note: * It is not pulled up in hardware standby mode.

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Bit 10—PLL Circuit 1 Enable (PLL1EN): Specifies whether PLL circuit 1 is on or off.

Bit 10: PLL1EN Description

0 PLL circuit 1 is not used

1 PLL circuit 1 is used (Initial value)

Bit 9—PLL Circuit 2 Enable (PLL2EN): Specifies whether PLL circuit 2 is on or off.

Bit 9: PLL2EN Description

0 PLL circuit 2 is not used

1 PLL circuit 2 is used (Initial value)

Bits 8 to 6—CPU Clock Frequency Division Ratio (IFC): These bits specify the CPU clock

frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1

output frequency.

Bit 8: IFC2 Bit 7: IFC1 Bit 6: IFC0 Description

0 0 0 ×1

1 ×1/2

1 0 ×1/3

1 ×1/4

1 0 0 ×1/6

1 ×1/8

Other than the above Setting prohibited (Do not set)

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Bits 5 to 3—Bus Clock Frequency Division Ratio (BFC): These bits specify the bus clock

frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1

output frequency.

Bit 5: BFC2 Bit 4: BFC1 Bit 3: BFC0 Description

0 0 0 ×1

1 ×1/2

1 0 ×1/3

1 ×1/4

1 0 0 ×1/6

1 ×1/8

Other than the above Setting prohibited (Do not set)

Bits 2 to 0—Peripheral Module Clock Frequency Division Ratio (PFC): These bits specify the

peripheral module clock frequency division ratio with respect to the input clock, 1/2 frequency

divider, or PLL circuit 1 output frequency.

Bit 2: PFC2 Bit 1: PFC1 Bit 0: PFC0 Description

0 0 0 ×1/2

1 ×1/3

1 0 ×1/4

1 ×1/6

1 0 0 ×1/8

Other than the above Setting prohibited (Do not set)

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10.5 Changing the Frequency

There are two methods of changing the internal clock frequency: by changing stopping and

starting of PLL circuit 1, and by changing the frequency division ratio of each clock. In both cases,

control is performed by software by means of the frequency control register. These methods are

described below.

10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off)

When PLL circuit 1 is changed from the stopped to started state, a PLL stabilization time is

required. The oscillation stabilization time count is performed by the on-chip WDT.

1. Set a value in WDT to provide the specified oscillation stabilization time, and stop the WDT.

The following settings are necessary:

WTCSR register TME bit = 0: WDT stopped

WTCSR register CKS2–CKS0 bits: WDT count clock division ratio

WTCNT counter: Initial counter value

2. Set the PLL1EN bit to 1.

3. Internal processor operation stops temporarily, and the WDT starts counting up. The internal

clock stops and an unstable clock is output to the CKIO pin.

4. After the WDT count overflows, clock supply begins within the chip and the processor

resumes operation. The WDT stops after overflowing.

10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)

When PLL circuit 2 is on, a PLL circuit 1 and PLL circuit 2 oscillation stabilization time is

required.

1. Make WDT settings as in section 10.5.1.

2. Set the PLL1EN bit to 1.

3. Internal processor operation stops temporarily, PLL circuit 1 oscillates, and the WDT starts

counting up. The internal clock stops and an unstable clock is output to the CKIO pin.

4. After the WDT count overflows, PLL circuit 2 starts oscillating. The WDT resumes its up-

count from the value set in step 1 above. During this time, also, the internal clock is stopped

and an unstable clock is output to the CKIO pin.

5. After the WDT count overflows, clock supply begins within the chip and the processor

resumes operation. The WDT stops after overflowing.

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10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On)

If PLL circuit 2 is on when the bus clock frequency division ratio is changed, a PLL circuit 2

oscillation stabilization time is required.

1. Make WDT settings as in section 10.5.1.

2. Set the BFC2–BFC0 bits to the desired value.

3. Internal processor operation stops temporarily, and the WDT starts counting up. The internal

clock stops and an unstable clock is output to the CKIO pin.

4. After the WDT count overflows, clock supply begins within the chip and the processor

resumes operation. The WDT stops after overflowing.

10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off)

If PLL circuit 2 is off when the bus clock frequency division ratio is changed, a WDT count is not

performed.

1. Set the BFC2–BFC0 bits to the desired value.

2. The set clock is switched to immediately.

10.5.5 Changing CPU or Peripheral Module Clock Division Ratio

When the CPU or peripheral module clock frequency division ratio is changed, a WDT count is

not performed.

1. Set the IFC2–IFC0 or PFC2–PFC0 bits to the desired value.

2. The set clock is switched to immediately.

10.6 Output Clock Control

The CKIO pin can be switched between clock output and a fixed level setting by means of the

CKOEN bit in the FRQCR register. When the CKIO pin goes to the high-impedance state, it is

pulled up.

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10.7 Overview of Watchdog Timer

10.7.1 Block Diagram

Figure 10.2 shows a block diagram of the WDT.

Standby

release

Internal reset

request

Interrupt

request

Standby

control

Reset

control

Interrupt

control

WTCSR WTCNT

Bus interface

Clock selection

Overflow

Frequency divider

Clock selector

Clock

WDT

Legend:

WTCSR: Watchdog timer control/status register

WTCNT: Watchdog timer counter

Standby

mode

Frequency

divider 2 ×1

clock

Figure 10.2 Block Diagram of WDT

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10.7.2 Register Configuration

The WDT has the two registers summarized in table 10.5. These registers control clock selection

and timer mode switching.

Table 10.5 WDT Registers

Name

Abbreviation

R/W

Initial

Value

P4 Address

Area 7

Address

Access Size

Watchdog timer

counter

WTCNT R/W* H'00 H'FFC00008 H'1FC00008 R: 8, W: 16*

Watchdog timer

control/status

WTCSR R/W* H'00 H'FFC0000C H'1FC0000C R: 8, W: 16*

Note: * Use word-size access when writing. Perform the write with the upper byte set to H'5A or

H'A5, respectively. Byte- and longword-size writes cannot be used.

Use byte access when reading.

10.8 WDT Register Descriptions

10.8.1 Watchdog Timer Counter (WTCNT)

The watchdog timer counter (WTCNT) is an 8-bit readable/writable counter that counts up on the

selected clock. When WTCNT overflows, a reset is generated in watchdog timer mode, or an

interrupt in interval timer mode. WTCNT is initialized to H'00 only by a power-on reset via the

RESET pin.

To write to the WTCNT counter, use a word-size access with the upper byte set to H'5A. To read

WTCNT, use a byte-size access.

Bit: 7 6 5 4 3 2 1 0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

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10.8.2 Watchdog Timer Control/Status Register (WTCSR)

The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register

containing bits for selecting the count clock and timer mode, and overflow flags.

WTCSR is initialized to H'00 only by a power-on reset via the RESET pin. It retains its value in

an internal reset due to WDT overflow. When used to count the clock stabilization time when

exiting standby mode, WTCSR retains its value after the counter overflows.

To write to the WTCSR register, use a word-size access with the upper byte set to H'A5. To read

WTCSR, use a byte-size access.

Bit: 7 6 5 4 3 2 1 0

TME WT/IT RSTS WOVF IOVF CKS2 CKS1 CKS0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7—Timer Enable (TME): Specifies starting and stopping of timer operation. Clear this bit to

0 when using the WDT in standby mode or to change a clock frequency.

Bit 7: TME Description

0 Up-count stopped, WTCNT value retained (Initial value)

1 Up-count started

Bit 6—Timer Mode Select (WT/IT): Specifies whether the WDT is used as a watchdog timer or

interval timer.

Bit 6: WT/IT Description

0 Interval timer mode (Initial value)

1 Watchdog timer mode

Note: The up-count may not be performed correctly if WT/IT is modified while the WDT is running.

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Bit 5—Reset Select (RSTS): Specifies the kind of reset to be performed when WTCNT overflows

in watchdog timer mode. This setting is ignored in interval timer mode.

Bit 5: RSTS Description

0 Power-on reset (Initial value)

1 Manual reset

Bit 4—Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed in

watchdog timer mode. This flag is not set in interval timer mode.

Bit 4: WOVF Description

0 No overflow (Initial value)

1 WTCNT has overflowed in watchdog timer mode

Bit 3—Interval Timer Overflow Flag (IOVF): Indicates that WTCNT has overflowed in

interval timer mode. This flag is not set in watchdog timer mode.

Bit 3: IOVF Description

0 No overflow (Initial value)

1 WTCNT has overflowed in interval timer mode

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Bits 2 to 0—Clock Select 2 to 0 (CKS2–CKS0): These bits select the clock used for the WTCNT

count from eight clocks obtained by dividing the frequency divider 2 input clock*. The overflow

periods shown in the following table are for use of a 33 MHz input clock, with frequency divider 1

off, and PLL circuit 1 on (×6).

Note: * When PLL1 is switched on or off, the clock following the switch is used.

Description

Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Division Ratio Overflow Period

0 0 0 1/32 (Initial value) 41 μs

1 1/64 82 μs

1 0 1/128 164 μs

1 1/256 328 μs

1 0 0 1/512 656 μs

1 1/1024 1.31 ms

1 0 1/2048 2.62 ms

1 1/4096 5.25 ms

Note: The up-count may not be performed correctly if bits CKS2–CKS0 are modified while the

WDT is running. Always stop the WDT before modifying these bits.

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10.8.3 Notes on Register Access

The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR)

differ from other registers in being more difficult to write to. The procedure for writing to these

registers is given below.

Writing to WTCNT and WTCSR: These registers must be written to with a word transfer

instruction. They cannot be written to with a byte or longword transfer instruction. When writing

to WTCNT, perform the transfer with the upper byte set to H'5A and the lower byte containing the

write data. When writing to WTCSR, perform the transfer with the upper byte set to H'A5 and the

lower byte containing the write data. This transfer procedure writes the lower byte data to

WTCNT or WTCSR. The write formats are shown in figure 10.3.

15 8 7 0

H'5A Write data

Address: H'FFC00008

(H'1FC00008)

15 8 7 0

H'A5 Write data

Address: H'FFC0000C

(H'1FC0000C)

WTCSR write

WTCNT write

Figure 10.3 Writing to WTCNT and WTCSR

10.9 Using the WDT

10.9.1 Standby Clearing Procedure

The WDT is used when clearing standby mode by means of an NMI or other interrupt. The

procedure is shown below. (As the WDT does not operate when standby mode is cleared with a

reset, the RESET pin should be held low until the clock stabilizes.)

1. Be sure to clear the TME bit in the WTCSR register to 0 before making a transition to standby

mode. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused

when the count overflows.

2. Select the count clock to be used with bits CKS2–CKS0 in the WTCSR register, and set the

initial value in the WTCNT counter. Make these settings so that the time until the count

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overflows is at least as long as the clock oscillation stabilization time. For details of the clock

oscillation stabilization time, see section 22.3.1, Clock and Control Signal Timing.

3. Make a transition to standby mode, and stop the clock, by executing a SLEEP instruction.

4. The WDT starts counting on detection of an NMI signal transition edge or an interrupt.

5. When the WDT count overflows, the CPG starts clock supply and the processor resumes

operation. The WOVF flag in the WTCSR register is not set at this time.

6. The counter stops at a value of H'00–H'01. The value at which the counter stops depends on

the clock ratio.

10.9.2 Frequency Changing Procedure

The WDT is used in a frequency change using the PLL. It is not used when the frequency is

changed simply by making a frequency divider switch.

1. Be sure to clear the TME bit in the WTCSR register to 0 before making a frequency change. If

the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the

count overflows.

2. Select the count clock to be used with bits CKS2–CKS0 in the WTCSR register, and set the

initial value in the WTCNT counter. Make these settings so that the time until the count

overflows is at least as long as the clock oscillation stabilization time. For details of the clock

oscillation stabilization time, see section 22.3.1, Clock and Control Signal Timing.

3. When the frequency control register (FRQCR) is modified, the clock stops, and the standby

state is entered temporarily. The WDT starts counting.

4. When the WDT count overflows, the CPG starts clock supply and the processor resumes

operation. The WOVF flag in the WTCSR register is not set at this time.

5. The counter stops at a value of H'00–H'01. The value at which the counter stops depends on

the clock ratio.

6. When re-setting WTCNT immediately after modifying the frequency control register

(FRQCR), first read the counter and confirm that its value is as described in step 5 above.

10.9.3 Using Watchdog Timer Mode

1. Set the WT/IT bit in the WTCSR register to 1, select the type of reset with the RSTS bit, and

the count clock with bits CKS2–CKS0, and set the initial value in the WTCNT counter.

2. When the TME bit in the WTCSR register is set to 1, the count starts in watchdog timer mode.

3. During operation in watchdog timer mode, write H'00 to the counter periodically so that it does

not overflow.

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4. When the counter overflows, the WDT sets the WOVF flag in the WTCSR register to 1, and

generates a reset of the type specified by the RSTS bit. The counter then continues counting.

10.9.4 Using Interval Timer Mode

When the WDT is operating in interval timer mode, an interval timer interrupt is generated each

time the counter overflows. This enables interrupts to be generated at fixed intervals.

1. Clear the WT/IT bit in the WTCSR register to 0, select the count clock with bits CKS2–CKS0,

and set the initial value in the WTCNT counter.

2. When the TME bit in the WTCSR register is set to 1, the count starts in interval timer mode.

3. When the counter overflows, the WDT sets the IOVF flag in the WTCSR register to 1, and

sends an interval timer interrupt request to INTC. The counter continues counting.

10.10 Notes on Board Design

When Using a Crystal Resonator: Place the crystal resonator and capacitors close to the EXTAL

and XTAL pins. To prevent induction from interfering with correct oscillation, ensure that no

other signal lines cross the signal lines for these pins.

EXTAL XTAL

SH7750

SH7750S

SH7750R

CL1 CL2

Avoid crossing signal lines Recommended values

CL1 = CL2 = 0–33 pF

R = 0Ω

Note: The values for CL1, CL2, and the damping resistance should be determined after

consultation with the crystal resonator manufacturer.

Figure 10.4 Points for Attention when Using Crystal Resonator

When Inputting External Clock from EXTAL Pin: Make no connection to the XTAL pin.

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When Using a PLL Oscillator Circuit: Separate VDD-CPG and VSS-CPG from the other VDD

and VSS lines at the board power supply source, and insert resistors RCB and RB and bypass

capacitors CPB and CB close to the pins as noise filters.

VDD-PLL1

CPB1

CPB2

RCB1

Recommended values

RCB1 = RCB2 = 10 Ω

CPB1 = CPB2 = 10 μF

RB = 10 Ω

CB = 10 μF

RCB2

3.3 V

VSS-PLL1

VDD-PLL2

SH7750

SH7750S

SH7750R VSS-PLL2

VDD-CPG

VSS-CPG

Figure 10.5 Points for Attention when Using PLL Oscillator Circuit

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10.11 Usage Notes

10.11.1 Invalid Manual Reset Triggered by Watchdog Timer (SH7750 and SH7750S)

Under certain conditions the watchdog timer (WDT) may trigger an invalid manual reset.

Conditions Under which Problem Occurs: The internal WDT triggers an invalid manual reset

when all of the following four conditions are satisfied.

1. After the WDT overflows, regardless of the values of the WT/IT and RSTS bits in WTCSR.

2. Before the counter (WTCNT) is incremented by the clock specified by the WTCSR.CKS bit.

3. The value of at least one of the TME, WT/IT, and RSTS bits in WTCSR is 0.

4. A value of 1 is written to the TME, WT/IT, and RSTS bits in WTCSR.

Workaround: A workaround for this problem is to use software to increment WTCNT before

writing 1 to the TME, WT/IT, and RSTS bits in WTCSR. Specific lines of code for this purpose

are listed below.

Example: Add the following lines of code before the instructions for writing 1 to the TME,

WT/IT, and RSTS bits in WTCSR.

MOV.L #WTCNT,R7

MOV.W #H'5A00,R8

MOV.W R8,@R7

MOV.L #WTCSR,R9

MOV.W #H'A580,R10

MOV.W R10,@R9

LOOP_WDT:

MOV.B @R7,R0

CMP/EQ #H'00, R0

BT LOOP_WDT

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Section 11 Realtime Clock (RTC)

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Section 11 Realtime Clock (RTC)

11.1 Overview

This LSI includes an on-chip realtime clock (RTC) and a 32.768 kHz crystal oscillation circuit for

use by the RTC.

11.1.1 Features

The RTC has the following features.

• Clock and calendar functions (BCD display)

Counts seconds, minutes, hours, day-of-week, days, months, and years.

• 1 to 64 Hz timer (binary display)

The 64 Hz counter register indicates a state of 64 Hz to 1 Hz within the RTC frequency divider

• Start/stop function

• 30-second adjustment function

• Alarm interrupts

Comparison with second, minute, hour, day-of-week, day, month, or year (year is available

only with the SH7750R) can be selected as the alarm interrupt condition

• Periodic interrupts

An interrupt period of 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1

second, or 2 seconds can be selected

• Carry interrupt

Carry interrupt function indicating a second counter carry, or a 64 Hz counter carry when the

64 Hz counter is read

• Automatic leap year adjustment

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11.1.2 Block Diagram

Figure 11.1 shows a block diagram of the RTC.

R64CNT

RTCCLK

16.384 kHz

32.768 kHz

128 Hz

ATI PRI

CUI

RCR1

RCR2

RCR3*

RYRCNTRMONCNTRWKCNTRDAYCNTRHRCNTRMINCNTRSECCNT

RSECAR RMINAR RHRAR RDAYAR RWKAR RMONAR

Prescaler

RTC crystal

oscillation

circuit

RTC operation

control unit

RESET, STBY, etc

Counter unit

Interrupt

control unit

To registers

Bus interface

RYRAR*

Internal peripheral module bus

Note: * SH7750R only

Figure 11.1 Block Diagram of RTC

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11.1.3 Pin Configuration

Table 11.1 shows the RTC pins.

Table 11.1 RTC Pins

Pin Name Abbreviation I/O Function

RTC oscillation circuit crystal pin EXTAL2 Input Connects crystal to RTC oscillation circuit

RTC oscillation circuit crystal pin XTAL2 Output Connects crystal to RTC oscillation circuit

Clock input/clock output TCLK I/O External clock input pin/input capture

control input pin/RTC output pin (shared

with TMU)

Dedicated RTC power supply VDD-RTC — RTC oscillation circuit power supply pin*

Dedicated RTC GND pin VSS-RTC — RTC oscillation circuit GND pin*

Note: * Power must be supplied to the RTC power supply pins even when the RTC is not used.

11.1.4 Register Configuration

Table 11.2 summarizes the RTC registers.

Table 11.2 RTC Registers

Initialization

Name

Abbrevia-

tion

R/W

Power-

Reset

Manual

Reset

Standby

Mode

Initial

Value

P4 Address

Area 7

Address

Access

Size

64 Hz

counter

R64CNT R Counts Counts Counts Undefined H'FFC80000 H'1FC80000 8

Second

counter

RSECCNT R/W Counts Counts Counts Undefined H'FFC80004 H'1FC80004 8

Minute

counter

RMINCNT R/W Counts Counts Counts Undefined H'FFC80008 H'1FC80008 8

Hour

counter

RHRCNT R/W Counts Counts Counts Undefined H'FFC8000C H'1FC8000C 8

Day-of-

week

counter

RWKCNT R/W

Counts Counts Counts Undefined H'FFC80010 H'1FC80010 8

Day

counter

RDAYCNT R/W Counts Counts Counts Undefined H'FFC80014 H'1FC80014 8

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Initialization

Name

Abbrevia-

tion

R/W

Power-On

Reset

Manual

Reset

Standby

Mode

Initial

Value

P4 Address

Area 7

Address

Access

Size

Month

counter

RMONCNT R/W Counts Counts Counts Undefined H'FFC80018 H'1FC80018 8

Year

counter

RYRCNT R/W Counts Counts Counts Undefined H'FFC8001C H'1FC8001C 16

Second

alarm

RSECAR R/W Initialized*1Held Held Undefined*1H'FFC80020 H'1FC80020 8

Minute

alarm

RMINAR R/W Initialized*1Held Held Undefined*1H'FFC80024 H'1FC80024 8

Hour

alarm

RHRAR R/W Initialized*1Held Held Undefined*1H'FFC80028 H'1FC80028 8

Day-of-

week

alarm

RWKAR R/W Initialized*1Held Held Undefined*1H'FFC8002C H'1FC8002C 8

Day

alarm

RDAYAR R/W Initialized*1Held Held Undefined*1H'FFC80030 H'1FC80030 8

Month

alarm

RMONAR R/W Initialized*1Held Held Undefined*1H'FFC80034 H'1FC80034 8

RTC

control

RCR1 R/W Initialized Initialized Held H'00*3 H'FFC80038 H'1FC80038 8

RTC

control

RCR2 R/W Initialized Initialized*2 Held H'09*4 H'FFC8003C H'1FC8003C 8

RTC

control

3*5

RCR3 R/W Initialized Held Held H'00 H'FFC80050 H'1FC80050 8

Year

alarm

RYRAR R/W Held Held Held Undefined H'FFC80054 H'1FC80054 16

Notes: 1. The ENB bit in each register is initialized.

2. Bits other than the RTCEN bit and START bit are initialized.

3. The value of the CF bit and AF bit is undefined.

4. The value of the PEF bit is undefined.

5. SH7750R only

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11.2 Register Descriptions

11.2.1 64 Hz Counter (R64CNT)

R64CNT is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC

frequency divider.

If this register is read when a carry is generated from the 128 kHz frequency division stage, bit 7

(CF) in RTC control register 1 (RCR1) is set to 1, indicating the simultaneous occurrence of the

carry and the 64 Hz counter read. In this case, the read value is not valid, and so R64CNT must be

read again after first writing 0 to the CF bit in RCR1 to clear it.

When the RESET bit or ADJ bit in RTC control register 2 (RCR2) is set to 1, the RTC frequency

divider is initialized and R64CNT is initialized to H'00.

R64CNT is not initialized by a power-on or manual reset, or in standby mode.

Bit 7 is always read as 0 and cannot be modified.

Bit: 7 6 5 4 3 2 1 0

— 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz

Initial value: 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined

R/W: R R R R R R R R

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11.2.2 Second Counter (RSECCNT)

RSECCNT is an 8-bit readable/writable register used as a counter for setting and counting the

BCD-coded second value in the RTC. It counts on the carry (transition of the R64CNT.1Hz bit

from 0 to 1) generated once per second by the 64 Hz counter.

The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set.

Write processing should be performed after stopping the count with the START bit in RCR2, or

by using the carry flag.

RSECCNT is not initialized by a power-on or manual reset, or in standby mode.

Bit 7 is always read as 0. A write to this bit is invalid, but the write value should always be 0.

Bit: 7 6 5 4 3 2 1 0

— 10-second units 1-second units

Initial value: 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined

R/W: R R/W R/W R/W R/W R/W R/W R/W

11.2.3 Minute Counter (RMINCNT)

RMINCNT is an 8-bit readable/writable register used as a counter for setting and counting the

BCD-coded minute value in the RTC. It counts on the carry generated once per minute by the

second counter.

The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set.

Write processing should be performed after stopping the count with the START bit in RCR2, or

by using the carry flag.

RMINCNT is not initialized by a power-on or manual reset, or in standby mode.

Bit 7 is always read as 0. A write to this bit is invalid, but the write value should always be 0.

Bit: 7 6 5 4 3 2 1 0

— 10-minute units 1-minute units

Initial value: 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined

R/W: R R/W R/W R/W R/W R/W R/W R/W

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11.2.4 Hour Counter (RHRCNT)

RHRCNT is an 8-bit readable/writable register used as a counter for setting and counting the

BCD-coded hour value in the RTC. It counts on the carry generated once per hour by the minute

counter.

The setting range is decimal 00 to 23. The RTC will not operate normally if any other value is set.

Write processing should be performed after stopping the count with the START bit in RCR2, or

by using the carry flag.

RHRCNT is not initialized by a power-on or manual reset, or in standby mode.

Bits 7 and 6 are always read as 0. A write to these bits is invalid, but the write value should always

be 0.

Bit: 7 6 5 4 3 2 1 0

— — 10-hour units 1-hour units

Initial value: 0 0 Undefined Undefined Undefined Undefined Undefined Undefined

R/W: R R R/W R/W R/W R/W R/W R/W

11.2.5 Day-of-Week Counter (RWKCNT)

RWKCNT is an 8-bit readable/writable register used as a counter for setting and counting the

BCD-coded day-of-week value in the RTC. It counts on the carry generated once per day by the

hour counter.

The setting range is decimal 0 to 6. The RTC will not operate normally if any other value is set.

Write processing should be performed after stopping the count with the START bit in RCR2, or

by using the carry flag.

RWKCNT is not initialized by a power-on or manual reset, or in standby mode.

Bits 7 to 3 are always read as 0. A write to these bits is invalid, but the write value should always

be 0.

Bit: 7 6 5 4 3 2 1 0

— — — — — Day of week code

Initial value: 0 0 0 0 0 Undefined Undefined Undefined

R/W: R R R R R R/W R/W R/W

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Day-of-week code 0 1 2 3 4 5 6

Day of week Sun Mon Tue Wed Thu Fri Sat

11.2.6 Day Counter (RDAYCNT)

RDAYCNT is an 8-bit readable/writable register used as a counter for setting and counting the

BCD-coded day value in the RTC. It counts on the carry generated once per day by the hour

counter.

The setting range is decimal 01 to 31. The RTC will not operate normally if any other value is set.

Write processing should be performed after stopping the count with the START bit in RCR2, or

by using the carry flag.

RDAYCNT is not initialized by a power-on or manual reset, or in standby mode.

The setting range for RDAYCNT depends on the month and whether the year is a leap year, so

care is required when making the setting. Taking the year counter (RYRCNT) value as the year,

leap year calculation is performed according to whether or not the value is divisible by 400, 100,

and 4.

Bits 7 and 6 are always read as 0. A write to these bits is invalid, but the write value should always

be 0.

Bit: 7 6 5 4 3 2 1 0

— — 10-day units 1-day units

Initial value: 0 0 Undefined Undefined Undefined Undefined Undefined Undefined

R/W: R R R/W R/W R/W R/W R/W R/W

11.2.7 Month Counter (RMONCNT)

RMONCNT is an 8-bit readable/writable register used as a counter for setting and counting the

BCD-coded month value in the RTC. It counts on the carry generated once per month by the day

counter.

The setting range is decimal 01 to 12. The RTC will not operate normally if any other value is set.

Write processing should be performed after stopping the count with the START bit in RCR2, or

by using the carry flag.

RMONCNT is not initialized by a power-on or manual reset, or in standby mode.

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Bits 7 to 5 are always read as 0. A write to these bits is invalid, but the write value should always

be 0.

Bit: 7 6 5 4 3 2 1 0

— — —

0-month

unit

1-month units

Initial value: 0 0 0 Undefined Undefined Undefined Undefined Undefined

R/W: R R R R/W R/W R/W R/W R/W

11.2.8 Year Counter (RYRCNT)

RYRCNT is a 16-bit readable/writable register used as a counter for setting and counting the

BCD-coded year value in the RTC. It counts on the carry generated once per year by the month

counter.

The setting range is decimal 0000 to 9999. The RTC will not operate normally if any other value

is set. Write processing should be performed after stopping the count with the START bit in

RCR2, or by using the carry flag.

RYRCNT is not initialized by a power-on or manual reset, or in standby mode.

Bit: 15 14 13 12 11 10 9 8

1000-year units 100-year units

Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

10-year units 1-year units

Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Section 11 Realtime Clock (RTC)

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11.2.9 Second Alarm Register (RSECAR)

RSECAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded

second value counter, RSECCNT. When the ENB bit is set to 1, the RSECAR value is compared

with the RSECCNT value. Comparison between the counter and the alarm register is performed

for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in

which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.

The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other

value is set.

The ENB bit in RSECAR is initialized to 0 by a power-on reset. The other fields in RSECAR are

not initialized by a power-on or manual reset, or in standby mode.

Bit: 7 6 5 4 3 2 1 0

ENB 10-second units 1-second units

Initial value: 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

11.2.10 Minute Alarm Register (RMINAR)

RMINAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded

minute value counter, RMINCNT. When the ENB bit is set to 1, the RMINAR value is compared

with the RMINCNT value. Comparison between the counter and the alarm register is performed

for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in

which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.

The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other

value is set.

The ENB bit in RMINAR is initialized by a power-on reset. The other fields in RMINAR are not

initialized by a power-on or manual reset, or in standby mode.

Bit: 7 6 5 4 3 2 1 0

ENB 10-minute units 1-minute units

Initial value: 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Section 11 Realtime Clock (RTC)

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11.2.11 Hour Alarm Register (RHRAR)

RHRAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded

hour value counter, RHRCNT. When the ENB bit is set to 1, the RHRAR value is compared with

the RHRCNT value. Comparison between the counter and the alarm register is performed for

those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in

which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.

The setting range is decimal 00 to 23 + ENB bit. The RTC will not operate normally if any other

value is set.

The ENB bit in RHRAR is initialized by a power-on reset. The other fields in RHRAR are not

initialized by a power-on or manual reset, or in standby mode.

Bit 6 is always read as 0. A write to this bit is invalid, but the write value should always be 0.

Bit: 7 6 5 4 3 2 1 0

ENB — 10-hour units 1-hour units

Initial value: 0 0 Undefined Undefined Undefined Undefined Undefined Undefined

R/W: R/W R R/W R/W R/W R/W R/W R/W

11.2.12 Day-of-Week Alarm Register (RWKAR)

RWKAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded

day-of-week value counter, RWKCNT. When the ENB bit is set to 1, the RWKAR value is

compared with the RWKCNT value. Comparison between the counter and the alarm register is

performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and

RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective

values all match.

The setting range is decimal 0 to 6 + ENB bit. The RTC will not operate normally if any other

value is set.

The ENB bit in RWKAR is initialized by a power-on reset. The other fields in RWKAR are not

initialized by a power-on or manual reset, or in standby mode.

Bits 6 to 3 are always read as 0. A write to these bits is invalid, but the write value should always

be 0.

Section 11 Realtime Clock (RTC)

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Bit: 7 6 5 4 3 2 1 0

ENB — — — — Day of week code

Initial value: 0 0 0 0 0 Undefined Undefined Undefined

R/W: R/W R R R R R/W R/W R/W

Day-of-week code 0 1 2 3 4 5 6

Day of week Sun Mon Tue Wed Thu Fri Sat

11.2.13 Day Alarm Register (RDAYAR)

RDAYAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-

coded day value counter, RDAYCNT. When the ENB bit is set to 1, the RDAYAR value is

compared with the RDAYCNT value. Comparison between the counter and the alarm register is

performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and

RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective

values all match.

The setting range is decimal 01 to 31 + ENB bit. The RTC will not operate normally if any other

value is set. The setting range for RDAYAR depends on the month and whether the year is a leap

year, so care is required when making the setting.

The ENB bit in RDAYAR is initialized by a power-on reset. The other fields in RDAYAR are not

initialized by a power-on or manual reset, or in standby mode.

Bit 6 is always read as 0. A write to this bit is invalid, but the write value should always be 0.

Bit: 7 6 5 4 3 2 1 0

ENB — 10-day units 1-day units

Initial value: 0 0 Undefined Undefined Undefined Undefined Undefined Undefined

R/W: R/W R R/W R/W R/W R/W R/W R/W

Section 11 Realtime Clock (RTC)

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11.2.14 Month Alarm Register (RMONAR)

RMONAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-

coded month value counter, RMONCNT. When the ENB bit is set to 1, the RMONAR value is

compared with the RMONCNT value. Comparison between the counter and the alarm register is

performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and

RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective

values all match.

The setting range is decimal 01 to 12 + ENB bit. The RTC will not operate normally if any other

value is set.

The ENB bit in RMONAR is initialized by a power-on reset. The other fields in RMONAR are

not initialized by a power-on or manual reset, or in standby mode.

Bits 6 and 5 are always read as 0. A write to these bits is invalid, but the write value should always

be 0.

Bit: 7 6 5 4 3 2 1 0

ENB — —

0-month

unit

1-month units

Initial value: 0 0 0 Undefined Undefined Undefined Undefined Undefined

R/W: R/W R R R/W R/W R/W R/W R/W

11.2.15 RTC Control Register 1 (RCR1)

RCR1 is an 8-bit readable/writable register containing a carry flag and alarm flag, plus flags to

enable or disable interrupts for these flags.

The CIE and AIE bits are initialized to 0 by a power-on or manual reset; the value of bits other

than CIE and AIE is undefined. In standby mode RCR1 is not initialized, and retains its current

value.

Bit: 7 6 5 4 3 2 1 0

CF — — CIE AIE — — AF

Initial value: Undefined Undefined Undefined 0 0 Undefined Undefined Undefined

R/W: R/W R R R/W R/W R R R/W

Section 11 Realtime Clock (RTC)

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Bit 7—Carry Flag (CF): This flag is set to 1 on generation of a second counter carry, or a 64 Hz

counter carry when the 64 Hz counter is read. The count register value read at this time is not

guaranteed, and so the count register must be read again.

Bit 7: CF Description

0 No second counter carry, or 64 Hz counter carry when 64 Hz counter is read

[Clearing condition]

When 0 is written to CF

1 Second counter carry, or 64 Hz counter carry when 64 Hz counter is read

[Setting conditions]

• Generation of a second counter carry, or a 64 Hz counter carry when the

64 Hz counter is read

• When 1 is written to CF

Bit 4—Carry Interrupt Enable Flag (CIE): Enables or disables interrupt generation when the

carry flag (CF) is set to 1.

Bit 4: CIE Description

0 Carry interrupt is not generated when CF flag is set to 1 (Initial value)

1 Carry interrupt is generated when CF flag is set to 1

Bit 3—Alarm Interrupt Enable Flag (AIE): Enables or disables interrupt generation when the

alarm flag (AF) is set to 1.

Bit 3: AIE Description

0 Alarm interrupt is not generated when AF flag is set to 1 (Initial value)

1 Alarm interrupt is generated when AF flag is set to 1

Section 11 Realtime Clock (RTC)

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Bit 0—Alarm Flag (AF): Set to 1 when the alarm time set in those registers among RSECAR,

RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1

matches the respective counter values.

Bit 0: AF Description

0 Alarm registers and counter values do not match (Initial value)

[Clearing condition]

When 0 is written to AF

1 Alarm registers and counter values match*

[Setting condition]

When alarm registers in which the ENB bit is set to 1 and counter values

match*

Note: * Writing 1 does not change the value.

Bits 6, 5, 2, and 1—Reserved. The initial value of these bits is undefined. A write to these bits is

invalid, but the write value should always be 0.

11.2.16 RTC Control Register 2 (RCR2)

RCR2 is an 8-bit readable/writable register used for periodic interrupt control, 30-second

adjustment, and frequency divider RESET and RTC count control.

RCR2 is basically initialized to H'09 by a power-on reset, except that the value of the PEF bit is

undefined. In a manual reset, bits other than RTCEN and START are initialized, while the value

of the PEF bit is undefined. In standby mode RCR2 is not initialized, and retains its current value.

Bit: 7 6 5 4 3 2 1 0

PEF PES2 PES1 PES0 RTCEN ADJ RESET START

Initial value: Undefined 0 0 0 1 0 0 1

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Section 11 Realtime Clock (RTC)

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Bit 7—Periodic Interrupt Flag (PEF): Indicates interrupt generation at the interval specified by

bits PES2–PES0. When this flag is set to 1, a periodic interrupt is generated.

Bit 7: PEF Description

0 Interrupt is not generated at interval specified by bits PES2–PES0

[Clearing condition]

When 0 is written to PEF

1 Interrupt is generated at interval specified by bits PES2–PES0

[Setting conditions]

• Generation of interrupt at interval specified by bits PES2–PES0

• When 1 is written to PEF

Bits 6 to 4—Periodic Interrupt Enable (PES2–PES0): These bits specify the period for periodic

interrupts.

Bit 6: PES2 Bit 5: PES1 Bit 4: PES0 Description

0 0 0 No periodic interrupt generation (Initial value)

1 Periodic interrupt generated at 1/256-second intervals

1 0 Periodic interrupt generated at 1/64-second intervals

1 Periodic interrupt generated at 1/16-second intervals

1 0 0 Periodic interrupt generated at 1/4-second intervals

1 Periodic interrupt generated at 1/2-second intervals

1 0 Periodic interrupt generated at 1-second intervals

1 Periodic interrupt generated at 2-second intervals

Bit 3— Oscillation Circuit Enable (RTCEN): Controls the operation of the RTC crystal

oscillation circuit.

Bit 3: RTCEN Description

0 RTC crystal oscillation circuit halted

1 RTC crystal oscillation circuit operating (Initial value)

Section 11 Realtime Clock (RTC)

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Bit 2—30-Second Adjustment (ADJ): Used for 30-second adjustment. When 1 is written to this

bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is

rounded up to 1 minute. The frequency divider circuits (RTC prescaler and R64CNT) are also

reset at this time. This bit always returns 0 if read.

Bit 2: ADJ Description

0 Normal clock operation (Initial value)

1 30-second adjustment performed

Bit 1—Reset (RESET): The frequency divider circuits are initialized by writing 1 to this bit.

When 1 is written to the RESET bit, the frequency divider circuits (RTC prescaler and R64CNT)

are reset and the RESET bit is automatically cleared to 0 (i.e. does not need to be written with 0).

Bit 1: RESET Description

0 Normal clock operation (Initial value)

1 Frequency divider circuits are reset

Bit 0—Start Bit (START): Stops and restarts counter (clock) operation.

Bit 0: START Description

0 Second, minute, hour, day, day-of-week, month, and year counters are

stopped*

1 Second, minute, hour, day, day-of-week, month, and year counters operate

normally* (Initial value)

Note: * The 64 Hz counter continues to operate unless stopped by means of the RTCEN bit.

11.2.17 RTC Control Register 3 (RCR3) and Year-Alarm Register (RYRAR)

(SH7750R Only)

RCR3 and RYRAR are readable/writable registers. RYRAR is the alarm register for the RTC's

BCD-coded year-value counter RYRCNT. When the YENB bit of RCR3 is set to 1, the RYRCNT

value is compared with the RYRAR value. Comparison between the counter and the alarm register

only takes place with the alarm registers in which the ENB and YENB bits are set to 1. The alarm

flag of RCR1 is only set to 1 when the respective values all match.

The setting range of RYRAR is decimal 0000 to 9999, and normal operation is not obtained if a

value beyond this range is set here.

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RCR3 is initialized by a power-on reset, but RYRAR will not be initialized by a power-on or

manual reset, or by the device entering standby mode.

Bits 6 to 0 of RCR3 are always read as 0. Writing to these bits is invalid. If a value is written to

these bits, it should always be 0.

RCR3

Bit: 7 6 5 4 3 2 1 0

YENB — — — — — — —

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R R R R R R R

RYRAR

Bit: 15 14 13 12 11 10 9 8

1000 years 100 years

Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

10 years 1 year

Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Section 11 Realtime Clock (RTC)

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11.3 Operation

Examples of the use of the RTC are shown below.

11.3.1 Time Setting Procedures

Figure 11.2 shows examples of the time setting procedures.

Stop clock

Reset frequency divider

Set second/minute/hour/day/

day-of-week/month/year

Start clock operation

Set RCR2.RESET to 1

Clear RCR2.START to 0

In any order

Set RCR2.START to 1

(a) Setting time after stopping clock

Clear carry flag

Write to counter register

Carry flag = 1?

Ye s

Clear RCR1.CF to 0

(Write 1 to RCR1.AF so that alarm flag

is not cleared)

Set RYRCNT first and RSECCNT last

Read RCR1 register and check CF bit

(b) Setting time while clock is running

Figure 11.2 Examples of Time Setting Procedures

The procedure for setting the time after stopping the clock is shown in (a). The programming for

this method is simple, and it is useful for setting all the counters, from second to year.

Section 11 Realtime Clock (RTC)

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The procedure for setting the time while the clock is running is shown in (b). This method is

useful for modifying only certain counter values (for example, only the second data or hour data).

If a carry occurs during the write operation, the write data is automatically updated and there will

be an error in the set data. The carry flag should therefore be used to check the write status. If the

carry flag (RCR1.CF) is set to 1, the write must be repeated.

The interrupt function can also be used to determine the carry flag status.

Figure 11.3 shows examples of the time reading procedures.

Section 11 Realtime Clock (RTC)

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Disable carry interrupts

Clear carry flag

Read counter register

Carry flag = 1?

Clear RCR1.CIE to 0

Clear RCR1.CF to 0

(Write 1 to RCR1.AF so that alarm flag

is not cleared)

Read RCR1 register and check CF bit

(a) Reading time without using interrupts

Ye s

Clear carry flag

Enable carry interrupts

Clear carry flag

Read counter register

Interrupt generated?

Ye s

Disable carry interrupts

(b) Reading time using interrupts

Set RCR1.CIE to 1

Clear RCR1.CF to 0

(Write 1 to RCR1.AF so that alarm flag

is not cleared)

Clear RCR1.CIE to 0

Figure 11.3 Examples of Time Reading Procedures

If a carry occurs while the time is being read, the correct time will not be obtained and the read

must be repeated. The procedure for reading the time without using interrupts is shown in (a), and

the procedure using carry interrupts in (b). The method without using interrupts is normally used

to keep the program simple.

Section 11 Realtime Clock (RTC)

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11.3.3 Alarm Function

The use of the alarm function is illustrated in figure 11.4.

Clock running

Disable alarm interrupts

Set alarm time

Clear alarm flag

Enable alarm interrupts

Monitor alarm time

(Wait for interrupt or check

alarm flag)

Clear RCR1.AIE to prevent erroneous interrupts

Be sure to reset the flag as it may have been

set during alarm time setting

Set RCR1.AIE to 1

Figure 11.4 Example of Use of Alarm Function

An alarm can be generated by the second, minute, hour, day-of-week, day, month, or year (year is

available only with the SH7750R) value, or a combination of these. Write 1 to the ENB bit in the

alarm registers involved in the alarm setting, and set the alarm time in the lower bits. Write 0 to

the ENB bit in registers not involved in the alarm setting.

When the counter and the alarm time match, RCR1.AF is set to 1. Alarm detection can be

confirmed by reading this bit, but normally an interrupt is used. If 1 has been written to

RCR1.AIE, an alarm interrupt is generated in the event of alarm, enabling the alarm to be

detected.

The alarm flag remains set while the counter and alarm time match. If the alarm flag is cleared by

writing 0 during this period, it will therefore be set again immediately afterward. This needs to be

taken into consideration when writing the program.

Section 11 Realtime Clock (RTC)

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11.4 Interrupts

There are three kinds of RTC interrupt: alarm interrupts, periodic interrupts, and carry interrupts.

An alarm interrupt request (ATI) is generated when the alarm flag (AF) in RCR1 is set to 1 while

the alarm interrupt enable bit (AIE) is also set to 1.

A periodic interrupt request (PRI) is generated when the periodic interrupt enable bits (PES2–

PES0) in RCR2 are set to a value other than 000 and the periodic interrupt flag (PEF) is set to 1.

A carry interrupt request (CUI) is generated when the carry flag (CF) in RCR1 is set to 1 while the

carry interrupt enable bit (CIE) is also set to 1.

11.5 Usage Notes

11.5.1 Register Initialization

After powering on and making the RCR1 register settings, reset the frequency divider (by setting

RCR2.RESET to 1) and make initial settings for all the other registers.

11.5.2 Carry Flag and Interrupt Flag in Standby Mode

When the carry flag or interrupt flag is set to 1 at the same time this LSI transits to normal mode

from standby mode by a reset or interrupt, the flag may not be set to 1. After exiting standby

mode, check the counters to judge the flag states if necessary.

11.5.3 Crystal Oscillator Circuit

Crystal oscillator circuit constants (recommended values) are shown in table 11.3, and the RTC

crystal oscillator circuit in figure 11.5.

Table 11.3 Crystal Oscillator Circuit Constants (Recommended Values)

fosc C

in C

out

32.768 kHz 10–22 pF 10–22 pF

Section 11 Realtime Clock (RTC)

Rev.7.00 Oct. 10, 2008 Page 334 of 1074

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SH7750

SH7750S

SH7750R

EXTAL2 XTAL2

XTAL

out

Noise filter

RTC

3.3 V

VDD-RTC VSS-RTC

Notes: 1. Select either the C

or C

out

side for the frequency adjustment variable capacitor according to

requirements such as the adjustment range, degree of stability, etc.

2. Built-in resistance value R

(typ. value) = 10 MΩ, R

(typ. value) = 400 kΩ

3. C

and C

out

values include floating capacitance due to the wiring. Take care when using a solid-

earth board.

4. The crystal oscillation stabilization time depends on the mounted circuit constants, floating

capacitance, etc., and should be decided after consultation with the crystal resonator

manufacturer.

5. Place the crystal resonator and load capacitors C

and C

out

as close as possible to the chip.

(Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and

XTAL2 pins.)

6. Ensure that the crystal resonator connection pin (EXTAL2 and XTAL2) wiring is routed as far away

as possible from other power lines (except GND) and signal lines.

7. Insert a noise filter in the RTC power supply.

Figure 11.5 Example of Crystal Oscillator Circuit Connection

11.5.4 RTC Register Settings (SH7750 only)

Description: When setting values are written to an RTC register, values may change in writable

RTC counter registers other than that to which the settings are written.

The RTC registers are R64CNT, RSECCNT, RMINCNT, RHRCNT, RWKCNT, RDAYCNT,

RMONCNT, RYRCNT, RSECAR, RMINAR, RHRAR, RDAYAR, RWKAR, RMONAR, RCR1,

and RCR2. Of these, RSECCNT, RMINCNT, RHRCNT, RWKCNT, RDAYCNT, RMONCNT,

and RYRCNT are writeable registers.

Workarounds: To avoid the problem, use one of methods 1. to 3. below to write settings to the

RTC registers.

Section 11 Realtime Clock (RTC)

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1. Disable the DMAC channels used to access peripheral registers before writing to an RTC

status register is set to 1. Then use the next instruction to read from the same register.

2. Use the following method to write to an RTC register.

Read all writeable counter registers (1)

Write to the register whose value is to

be changed

Read all writeable counter registers (2)

Compare the values of (1) and (2)

Are the compared values valid?

Write operation complete

Ye s

Section 11 Realtime Clock (RTC)

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3. Use the following method to write to an RTC register.

Read all writeable counter registers (1)

Write 0 to RCR2.RTCEN

Read all writeable counter registers (2)

Compare the values of (1) and (2)

Write to the register whose value is to

be changed

Ye s

Write 1 to RCR2.RTCEN

Write operation complete

Write the valid value

Are the compared values valid?

Note: The operation of the RTC counter is stopped when RCR2.RTCEN is

cleared to 0. Therefore, using the above method will cause the RTC counter

value to fall behind the actual time by the amount of time that

RCR2.RTCEN was cleared to 0, and the cycle duration for cycle interrupt

generation will be lengthened as well.

Section 12 Timer Unit (TMU)

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Section 12 Timer Unit (TMU)

12.1 Overview

This LSI of microprocessors includes an on-chip 32-bit timer unit (TMU). The TMU of the

SH7750 or SH7750S has three 32-bit timer channels (channels 0 to 2), and the TMU of the

SH7750R has five channels (channels 0 to 4).

12.1.1 Features

The TMU has the following features.

• Auto-reload type 32-bit down-counter provided for each channel

• Input capture function provided in channel 2

• Selection of rising edge or falling edge as external clock input edge when external clock is

selected or input capture function is used

• 32-bit timer constant register for auto-reload use, readable/writable at any time, and 32-bit

down-counter provided for each channel

• For channels 0 to 2, selection of seven counter input clocks for each channel

External clock (TCLK), on-chip RTC output clock, five internal clocks (Pck/4, Pck/16, Pck/64,

Pck/256, Pck/1024) (Pck is the peripheral module clock)

• For channels 3 and 4, selection is made among five internal clocks (SH7750R only).

• Channels 0 to 2 can also operate in module standby mode when the on-chip RTC output clock

is selected as the counter input clock; that is, timer operation continues even when the clock

has been stopped for the TMU.

Timer count operations using an external or internal clock are only possible when a clock is

supplied to the timer unit.

• Two interrupt sources

One underflow source (each channel) and one input capture source (channel 2)

• DMAC data transfer request capability

On channel 2, a data transfer request is sent to the DMAC when an input capture interrupt is

generated.

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12.1.2 Block Diagram

Figure 12.1 shows a block diagram of the TMU.

RESET, STBY,

etc.

TUNE0,TUNE1 Pck/4,16, 64

TUNI2 ICPI2 TCLK RTCCLK TUNI3, 4

TMU

control unit Prescaler

To each

channel

To channels

0 to 2

TCLK

control unit

TOCR

TSTR

TSTR2

Interrupt

contrun unitCounter unit

Interrupt

contrun unitCounter unit

Interrupt

contrun unitCounter unit

Ch 0, 1 Ch 2 Ch 3, 4

Bus interface

Internal peripheral module bus

TCR TCOR TCNT TCR TCOR TCNTTCR2 TCOR2 TCNT2 TCPR2

Notes: 1. Signals with 1/4, 1/16, and 1/64 the Pck frequency, supplied to the on-chip peripheral functions.

2. SH7750R only

Figure 12.1 Block Diagram of TMU

12.1.3 Pin Configuration

Table 12.1 shows the TMU pins.

Table 12.1 TMU Pins

Pin Name Abbreviation I/O Function

Clock input/clock output TCLK I/O External clock input pin/input capture

control input pin/RTC output pin

(shared with RTC)

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 339 of 1074

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12.1.4 Register Configuration

Table 12.2 summarizes the TMU registers.

Table 12.2 TMU Registers

Initialization

Chan-

nel

Name

Abbre-

viation

R/W

Power-

Reset

Manual

Reset

Stand-

Mode

Initial Value

P4 Address

Area 7

Address

Access

Size

Com-

mon

Timer

output

control

TOCR R/W Ini-

tialized

Ini-

tialized

Held H'00 H'FFD80000 H'1FD80000 8

Timer

start

TSTR R/W Ini-

tialized

Ini-

tialized

Ini-

tialized*1

H'00 H'FFD80004 H'1FD80004 8

Timer

start

TSTR2*3R/W Ini-

tialized

Held Held H'00 H'FE100004 H'1E100004 8

0 Timer

constant

TCOR0 R/W Ini-

tialized

Ini-

tialized

Held H'FFFFFFFF H'FFD80008 H'1FD80008 32

Timer

counter 0

TCNT0 R/W Ini-

tialized

Ini-

tialized

Held*2 H'FFFFFFFF H'FFD8000C H'1FD8000C 32

Timer

control

TCR0 R/W Ini-

tialized

Ini-

tialized

Held H'0000 H'FFD80010 H'1FD80010 16

1 Timer

constant

TCOR1 R/W Ini-

tialized

Ini-

tialized

Held H'FFFFFFFF H'FFD80014 H'1FD80014 32

Timer

counter 1

TCNT1 R/W Ini-

tialized

Ini-

tialized

Held*2 H'FFFFFFFF H'FFD80018 H'1FD80018 32

Timer

control

TCR1 R/W Ini-

tialized

Ini-

tialized

Held H'0000 H'FFD8001C H'1FD8001C 16

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 340 of 1074

REJ09B0366-0700

Initialization

Chan-

nel

Name

Abbre-

viation

R/W

Power-

Reset

Manual

Reset

Stand-

Mode

Initial Value

P4 Address

Area 7

Address

Access

Size

2 Timer

constant

TCOR2 R/W Ini-

tialized

Ini-

tialized

Held H'FFFFFFFF H'FFD80020 H'1FD80020 32

Timer

counter 2

TCNT2 R/W Ini-

tialized

Ini-

tialized

Held*2 H'FFFFFFFF H'FFD80024 H'1FD80024 32

Timer

control

TCR2 R/W Ini-

tialized

Ini-

tialized

Held H'0000 H'FFD80028 H'1FD80028 16

Input

capture

TCPR2 R Held Held Held Undefined H'FFD8002C H'1FD8002C 32

3*3 Timer

constant

TCOR3 R/W Ini-

tialized

Held Held

H'FFFFFFFF H'FE100008 H'1E100008 32

Timer

counter 3

TCNT3 R/W

Ini-

tialized

Held Held

H'FFFFFFFF H'FE10000C H'1E10000C 32

Timer

control

TCR3 R/W

Ini-

tialized

Held Held

H'0000 H'FE100010 H'1E100010 16

4*3 Timer

constant

TCOR4 R/W Ini-

tialized

Held Held

H'FFFFFFFF H'FE100014 H'1E100014 32

Timer

counter 4

TCNT4 R/W

Ini-

tialized

Held Held

H'FFFFFFFF H'FE100018 H'1E100018 32

Timer

control

TCR4 R/W

Ini-

tialized

Held Held

H'0000 H'FE10001C H'1E10001C 16

Notes: 1. Not initialized in module standby mode when the input clock is the on-chip RTC output

clock.

2. Counts in module standby mode when the input clock is the on-chip RTC output clock.

3. H7750R only

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 341 of 1074

REJ09B0366-0700

12.2 Register Descriptions

12.2.1 Timer Output Control Register (TOCR)

TOCR is an 8-bit readable/writable register that specifies whether external pin TCLK is used as

the external clock or input capture control input pin, or as the on-chip RTC output clock output

pin.

TOCR is initialized to H'00 by a power-on or manual reset, but is not initialized in standby mode.

Bit: 7 6 5 4 3 2 1 0

— — — — — — — TCOE

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R R R/W

Bits 7 to 1—Reserved: These bits are always read as 0. A write to these bits is invalid, but the

write value should always be 0.

Bit 0—Timer Clock Pin Control (TCOE): Specifies whether timer clock pin TCLK is used as

the external clock or input capture control input pin, or as the on-chip RTC output clock output

pin.

Bit 0: TCOE Description

0 Timer clock pin (TCLK) is used as external clock input or input capture

control input pin (Initial value)

1 Timer clock pin (TCLK) is used as on-chip RTC output clock output pin*

Note: * Low level output in standby mode.

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 342 of 1074

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12.2.2 Timer Start Register (TSTR)

TSTR is an 8-bit readable/writable register that specifies whether the channel 0–2 timer counters

(TCNT) are operated or stopped.

TSTR is initialized to H'00 by a power-on or manual reset, or standby mode. In module standby

mode, TSTR is not initialized when the input clock selected by each channel is the on-chip RTC

output clock (RTCCLK), and is initialized only when the input clock is the external clock (TCLK)

or internal clock (Pck).

Bit: 7 6 5 4 3 2 1 0

— — — — — STR2 STR1 STR0

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R/W R/W R/W

Bits 7 to 3—Reserved: These bits are always read as 0. A write to these bits is invalid, but the

write value should always be 0.

Bit 2—Counter Start 2 (STR2): Specifies whether timer counter 2 (TCNT2) is operated or

stopped.

Bit 2: STR2 Description

0 TCNT2 count operation is stopped (Initial value)

1 TCNT2 performs count operation

Bit 1—Counter Start 1 (STR1): Specifies whether timer counter 1 (TCNT1) is operated or

stopped.

Bit 1: STR1 Description

0 TCNT1 count operation is stopped (Initial value)

1 TCNT1 performs count operation

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 343 of 1074

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Bit 0—Counter Start 0 (STR0): Specifies whether timer counter 0 (TCNT0) is operated or

stopped.

Bit 0: STR0 Description

0 TCNT0 count operation is stopped (Initial value)

1 TCNT0 performs count operation

12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only)

TSTR2 is an 8-bit readable/writable register that specifies whether the channels 3−4 timer

counters (TSTR2) run or are stopped.

TSTR2 is initialized to H'00 by a power-on reset and retains its value in standby mode. If standby

mode is entered when the STR3 or STR4 bit is set to 1, counting is halted at the same time as the

peripheral module clock is stopped. Counting is restarted on resumption of the clock-signal

supply.

Bit: 7 6 5 4 3 2 1 0

— — — — — — STR4 STR3

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R R/W R/W

Bits 7 to 2—Reserved: These bits are always read as 0. Writing to these bits is invalid. If a value

is written to these bits, it should always be 0.

Bit 1—Counter Start 4 (STR4): Specifies whether timer counter 4 (TCNT4) runs or is stopped.

Bit 1: STR4 Description

0 Counting by TCNT4 is stopped (Initial value)

1 Counting by TCNT4 proceeds

Bit 0—Counter Start 3 (STR3): Specifies whether timer counter 3 (TCNT3) runs or is stopped.

Bit 0: STR3 Description

0 Counting by TCNT3 is stopped (Initial value)

1 Counting by TCNT3 proceeds

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 344 of 1074

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12.2.4 Timer Constant Registers (TCOR)

The TCOR registers are 32-bit readable/writable registers. There are TCOR registers, one for each

channel.

When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT,

which continues counting down from the set value.

The TCOR registers for channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual

reset, but are not initialized and retain their contents in standby mode. The TCOR registers for

channels 3 and 4 of the SH7750R are initialized to H'FFFFFFFF by a power-on reset, but are not

initialized and retain their contents on a manual reset and in standby mode.

Bit: 31 30 29 2 1 0

· · · · · · · · · · · · ·

Initial value: 1 1 1 1 1 1

R/W: R/W R/W R/W R/W R/W R/W

12.2.5 Timer Counters (TCNT)

The TCNT registers are 32-bit readable/writable registers. There are TCNT registers, one for each

channel.

Each TCNT counts down on the input clock selected by TPSC2–TPSC0 in the timer control

When a TCNT counter underflows while counting down, the underflow flag (UNF) is set in the

corresponding timer control register (TCR). At the same time, the timer constant register (TCOR)

value is set in TCNT, and the count-down operation continues from the set value.

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 345 of 1074

REJ09B0366-0700

The TCNT registers for channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual

reset, but are not initialized and retain their contents in standby mode. The TCNT registers for

channels 3 and 4 of the SH7750R are initialized to H'FFFFFFFF by a power-on reset, but are not

initialized and retain their contents on a manual reset and in standby mode.

Bit: 31 30 29 2 1 0

· · · · · · · · · · · · ·

Initial value: 1 1 1 1 1 1

R/W: R/W R/W R/W R/W R/W R/W

When the input clock is the on-chip RTC output clock (RTCCLK) in channels 0 to 2, TCNT

counts even in module standby mode (that is, when the clock for the TMU is stopped). When the

input clock is the external clock (TCLK) or internal clock (Pck), TCNT contents are retained in

standby mode.

12.2.6 Timer Control Registers (TCR)

The TCR registers are 16-bit readable/writable registers. There are five TCR registers, one for

each channel.

Each TCR selects the count clock, specifies the edge when an external clock is selected in

channels 0 to 2, and controls interrupt generation when the flag indicating timer counter (TCNT)

underflow is set to 1. TCR2 is also used for channel 2 input capture control, and control of

interrupt generation in the event of input capture.

The TCR registers for channels 0 to 2 are initialized to H'0000 by a power-on or manual reset, but

are not initialized and retain their contents in standby mode. The TCR registers for channels 3 and

4 of the SH7750R are initialized to H'0000 by a power-on reset, but are not initialized and retain

their contents on a manual reset and in standby mode.

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 346 of 1074

REJ09B0366-0700

1. Channel 0 and 1 TCR bit configuration

Bit: 15 14 13 12 11 10 9 8

— — — — — — — UNF

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R R R/W

Bit: 7 6 5 4 3 2 1 0

— — UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R/W R/W R/W R/W R/W R/W

2. Channel 2 TCR bit configuration

Bit: 15 14 13 12 11 10 9 8

— — — — — — ICPF UNF

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R R/W R/W

Bit: 7 6 5 4 3 2 1 0

ICPE1 ICPE0 UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 347 of 1074

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3. TCR bit configuration for channels 3 and 4 (SH7750R only)

Bit: 15 14 13 12 11 10 9 8

— — — — — — — UNF

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R R R/W

Bit: 7 6 5 4 3 2 1 0

— — UNIE — — TPSC2 TPSC1 TPSC0

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R/W R R R/W R/W R/W

Bits 15 to 9, 7, and 6 (Channels 0 and 1); Bits 15 to 10 (Channel 2)—Reserved: These bits are

always read as 0. A write to these bits is invalid, but the write value should always be 0.

Bit 9—Input Capture Interrupt Flag (ICPF) (Channel 2 Only): Status flag, provided in

channel 2 only, that indicates the occurrence of input capture.

Bit 9: ICPF Description

0 Input capture has not occurred (Initial value)

[Clearing condition]

When 0 is written to ICPF

1 Input capture has occurred

[Setting condition]

When input capture occurs*

Note: * Writing 1 does not change the value.

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 348 of 1074

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Bit 8—Underflow Flag (UNF): Status flag that indicates the occurrence of underflow.

Bit 8: UNF Description

0 TCNT has not underflowed (Initial value)

[Clearing condition]

When 0 is written to UNF

1 TCNT has underflowed

[Setting condition]

When TCNT underflows*

Note: * Writing 1 does not change the value.

Bits 7 and 6—Input Capture Control (ICPE1, ICPE0) (Channel 2 Only): These bits, provided

in channel 2 only, specify whether the input capture function is used, and control enabling or

disabling of interrupt generation when the function is used.

When the input capture function is used, a data transfer request is sent to the DMAC in the event

of input capture.

When using the input capture function, the TCLK pin must be designated as an input pin with the

TCOE bit in the TOCR register. The CKEG bits specify whether the rising edge or falling edge of

the TCLK signal is used to set the TCNT2 value in the input capture register (TCPR2).

The TCNT2 value is set in TCPR2 only when the TCR2.ICPF bit is 0. When the TCR2.ICPF bit is

1, TCPR2 is not set in the event of input capture. When input capture occurs, a DMAC transfer

request is generated regardless of the value of the TCR2.ICPF bit. However, a new DMAC

transfer request is not generated until processing of the previous request is finished.

Bit 7: ICPE1 Bit 6: ICPE0 Description

0 0 Input capture function is not used (Initial value)

1 Reserved (Do not set)

1 0 Input capture function is used, but interrupt due to input capture

(TICPI2) is not enabled

Data transfer request is sent to DMAC in the event of input

capture

1 Input capture function is used, and interrupt due to input

capture (TICPI2) is enabled

Data transfer request is sent to DMAC in the event of input

capture

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 349 of 1074

REJ09B0366-0700

Bit 5—Underflow Interrupt Control (UNIE): Controls enabling or disabling of interrupt

generation when the UNF status flag is set to 1, indicating TCNT underflow.

Bit 5: UNIE Description

0 Interrupt due to underflow (TUNI) is not enabled (Initial value)

1 Interrupt due to underflow (TUNI) is enabled

Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the external clock input

edge when an external clock is selected or the input capture function is used in channels 0 to 2.

Bit 4: CKEG1 Bit 3: CKEG0 Description

0 0 Count/input capture register set on rising edge (Initial value)

1 Count/input capture register set on falling edge

1 X Count/input capture register set on both rising and falling edges

Note: X: 0 or 1 (don't care)

Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2–TPSC0): These bits select the TCNT count clock.

With channels 0 to 2, when the on-chip RTC output clock is selected as the count clock for a

channel, that channel can operate even in module standby mode. When another clock is selected,

the channel does not operate in standby mode.

Bit 2: TPSC2 Bit 1: TPSC1 Bit 0: TPSC0 Description

0 0 0 Counts on Pck/4 (Initial value)

1 Counts on Pck/16

1 0 Counts on Pck/64

1 Counts on Pck/256

1 0 0 Counts on Pck/1024

1 Reserved (Do not set)

1 0 Counts on on-chip RTC output clock

(Do not set this pattern for channel 3 or 4)

1 Counts on external clock

(Do not set this pattern for channel 3 or 4)

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 350 of 1074

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12.2.7 Input Capture Register 2 (TCPR2)

TCPR2 is a 32-bit read-only register for use with the input capture function, provided only in

channel 2.

The input capture function is controlled by means of the input capture control bits (ICPE) and

clock edge bits (CKEG) in TCR2. When input capture occurs, the TCNT2 value is copied into

TCPR2. The value is set in TCPR2 only when the ICPF bit in TCR2 is 0.

TCPR2 is not initialized by a power-on or manual reset, or in standby mode.

Bit: 31 30 29 2 1 0

· · · · · · · · · · · · ·

Initial value: Undefined

R/W: R R R R R R

12.3 Operation

Each channel has a 32-bit timer counter (TCNT) that performs count-down operations, and a 32-

bit timer constant register (TCOR). The channels have an auto-reload function that allows cyclic

count operations, and can also perform external event counting. Channel 2 also has an input

capture function.

12.3.1 Counter Operation

When one of bits STR0–STR4 is set to 1 in the timer start register (TSTR, TSTR2), the timer

counter (TCNT) for the corresponding channel starts counting. When TCNT underflows, the UNF

flag is set in the corresponding timer control register (TCR). If the UNIE bit in TCR is set to 1 at

this time, an interrupt request is sent to the CPU. At the same time, the value is copied from

TCOR into TCNT, and the count-down continues (auto-reload function).

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 351 of 1074

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Example of Count Operation Setting Procedure: Figure 12.2 shows an example of the count

operation setting procedure.

1. Select the count clock, for channel 0, 1, or 2, with bits TPSC2–TPSC0 in the timer control

TCOE bit in TOCR, and select the external clock edge with bits CKEG1 and CKEG0 in TCR.

2. Specify whether an interrupt is to be generated on TCNT underflow with the UNIE bit in TCR.

3. When the input capture function is used, set the ICPE bits in TCR, including specification of

whether the interrupt function is to be used.

4. Set a value in the timer constant register (TCOR).

5. Set the initial value in the timer counter (TCNT).

6. Set the STR bit to 1 in the timer start register (TSTR, TSTR2) to start the count.

Operation selection

Select count clock

Underflow interrupt

generation setting

When input capture

function is used

Input capture interrupt

generation setting

Timer constant

Set initial timer

counter value

Start count

Note: When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt

enabled state is set without clearing the flag, another interrupt will be generated.

Figure 12.2 Example of Count Operation Setting Procedure

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 352 of 1074

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Auto-Reload Count Operation: Figure 12.3 shows the TCNT auto-reload operation.

TCOR

H'00000000

STR0–STR2

UNF

TCNT value TCOR value set in TCNT

on underflow

Time

Figure 12.3 TCNT Auto-Reload Operation

TCNT Count Timing:

• Operating on internal clock

Any of five count clocks (Pck/4, Pck/16, Pck/64, Pck/256, or Pck/1024) scaled from the

peripheral module clock can be selected as the count clock by means of the TPSC2–TPSC0

bits in TCR.

Figure 12.4 shows the timing in this case.

Pck

Internal clock

TCNT N + 1 N N – 1

Figure 12.4 Count Timing when Operating on Internal Clock

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 353 of 1074

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• Operating on external clock

For channels 0 to 2, external clock pin (TCLK) input can be selected as the timer clock by

means of the TPSC2–TPSC0 bits in TCR. The rising edge, falling edge, or both edges can be

selected as the detected edge of the external clock with the CKEG1 and CKEG0 bits in TCR.

Figure 12.5 shows the timing for both-edge detection.

N + 1 N – 1N

Pck

External clock

input pin

TCNT

Figure 12.5 Count Timing when Operating on External Clock

• Operating on on-chip RTC output clock

The on-chip RTC output clock can be selected as the timer clock in channels 0 to 2 by means

of the TPSC2–TPSC0 bits in TCR. Figure 12.6 shows the timing in this case.

N + 1 N N – 1

RTC output clock

TCNT

Figure 12.6 Count Timing when Operating on On-Chip RTC Output Clock

12.3.2 Input Capture Function

Channel 2 has an input capture function.

The procedure for using the input capture function is as follows:

1. Use the TCOE bit in the timer output control register (TOCR) to set the TCLK pin to input

mode.

2. Use bits TPSC2–TPSC0 in the timer control register (TCR) to set an internal clock or the on-

chip RTC output clock as the timer operating clock.

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 354 of 1074

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3. Use bits IPCE1 and IPCE0 in TCR to specify use of the input capture function, and whether

interrupts are to generated when this function is used.

4. Use bits CKEG1 and CKEG0 in TCR to specify whether the rising or falling edge of the

TCLK signal is to be used to set the timer counter (TCNT) value in the input capture register

(TCPR2).

This function cannot be used in standby mode.

When input capture occurs, the TCNT2 value is set in TCPR2 only when the ICPF bit in TCR2 is

0. Also, a new DMAC transfer request is not generated until processing of the previous request is

finished.

Figure 12.7 shows the operation timing when the input capture function is used (with TCLK rising

edge detection).

TCOR

H'00000000

TCLK

TCPR2

TICPI2

TCNT value

TCOR value set in TCNT

on underflow

TCNT value set

Time

Figure 12.7 Operation Timing when Using Input Capture Function

Section 12 Timer Unit (TMU)

Rev.7.00 Oct. 10, 2008 Page 355 of 1074

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12.4 Interrupts

There are four TMU interrupt sources, comprising underflow interrupts and the input capture

interrupt (when the input capture function is used). Underflow interrupts are generated on each of

the channels, and input capture interrupts on channel 2 only.

An underflow interrupt request is generated (for each channel) when the UNF bit in TCR is 1 and

the interrupt enable bit for the corresponding channel is 1.

When the input capture function is used and an input capture request is generated, an interrupt is

requested if the input capture input flag (ICPF) in TCR2 is 1 and the input capture control bits

(ICPE1, ICPE0) in TCR2 are 11.

The TMU interrupt sources are summarized in table 12.3.

Table 12.3 TMU Interrupt Sources

Channel Interrupt Source Description Priority

0 TUNI0 Underflow interrupt 0 High

1 TUNI1 Underflow interrupt 1

2 TUNI2 Underflow interrupt 2

TICPI2 Input capture interrupt 2

3* TUNI3 Underflow interrupt 3

4* TUNI4 Underflow interrupt 4 Low

Note: * SH7750R only

12.5 Usage Notes

12.5.1 Register Writes

When performing a register write, timer count operation must be stopped by clearing the start bit

(STR0–STR4) for the relevant channel in the timer start register (TSTR, TSTR2).

Note that the timer start register (TSTR, TSTR2) can be written to, and the underflow flag (UNF)

and input capture flag (ICPF) of the timer control registers (TRCR0 to TCR4) can be cleared while

the count is in progress. When the flags (UNF, ICPF) are cleared while the count is in progress,

make sure not to change the values of bits other than those being cleared.

Section 12 Timer Unit (TMU)

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12.5.2 Underflow Flag Writes (SH7750 only)

If 1 is written to the UNF bit in TCR when the UNF bit is already set to 1, the UNF bit may be

cleared to 0.

The following workarounds can be used to avoid this problem.

1. Stopping channel counter operation

Use steps (i) to (iii) below to write 1 to UNF.

(i) Stop counter operation for the channel used to write to UNF.

(ii) Disable the DMAC channels used to access peripheral modules.

(iii) While SR.BL is set to 1, write (the same value as that written to TCR and using the same

access size (word)) to address H'FFD80080, then write 1 to UNF with the next instruction.

2. Not stopping channel counter operation

Make sure to write 0 to UNF. If it is necessary to monitor for underflows, use software to read

TCNT before and after writing to UNF and determine if an underflow has occurred.

12.5.3 TCNT Register Reads

When performing a TCNT register read, processing for synchronization with the timer count

operation is performed. If a timer count operation and register read processing are performed

simultaneously, the TCNT counter value prior to the count-down operation is read by means of the

synchronization processing.

12.5.4 Resetting the RTC Frequency Divider

When the on-chip RTC output clock is selected as the count clock, the RTC frequency divider

should be reset.

12.5.5 External Clock Frequency

Ensure that the external clock frequency for any channel does not exceed Pck/8.

Section 13 Bus State Controller (BSC)

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Section 13 Bus State Controller (BSC)

13.1 Overview

The functions of the bus state controller (BSC) include division of the external memory space, and

output of control signals in accordance with various types of memory and bus interface

specifications. The BSC functions allow DRAM, synchronous DRAM, SRAM, ROM, etc., to be

connected to this LSI, and also support the PCMCIA interface protocol, enabling system design to

be simplified and data transfers to be carried out at high speed by a compact system.

13.1.1 Features

The BSC has the following features:

• External memory space is managed as 7 independent areas

⎯ Maximum 64 Mbytes for each of areas 0 to 6

⎯ Bus width of each area can be set in a register (except area 0, which uses an external pin

setting)

⎯ Wait state insertion by RDY pin

⎯ Wait state insertion can be controlled by program

⎯ Specification of types of memory connectable to each area

⎯ Output the control signals of memory to each area

⎯ Automatic wait cycle insertion to prevent data bus collisions in case of consecutive

memory accesses to different areas, or a read access followed by a write access to the same

area

⎯ Write strobe setup time and hold time periods can be inserted in a write cycle to enable

connection to low-speed memory

• SRAM interface

⎯ Wait state insertion can be controlled by program

⎯ Wait state insertion by RDY pin

Connectable areas: 0 to 6

Settable bus widths: 64, 32, 16, 8

• DRAM interface

⎯ Row address/column address multiplexing according to DRAM capacity

⎯ Burst operation (fast page mode, EDO mode)

⎯ CAS-before-RAS refresh and self-refresh

Section 13 Bus State Controller (BSC)

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⎯ 8-CAS byte control for power-down operation

⎯ DRAM control signal timing can be controlled by register settings

⎯ Consecutive accesses to the same row address

Connectable areas: 2, 3

Settable bus widths: 64, 32, 16

• Synchronous DRAM interface

⎯ Row address/column address multiplexing according to synchronous DRAM capacity

⎯ Burst operation

⎯ Auto-refresh and self-refresh

⎯ Synchronous DRAM control signal timing can be controlled by register settings

⎯ Consecutive accesses to the same row address

Connectable areas: 2, 3

Settable bus widths: 64, 32

• Burst ROM interface

⎯ Wait state insertion can be controlled by program

⎯ Burst operation, executing the number of transfers set in a register

Connectable areas: 0, 5, 6

Settable bus widths: 64*, 32, 16, 8

• MPX interface

⎯ Address/data multiplexing

Connectable areas: 0 to 6

Settable bus widths: 64, 32

• Byte control SRAM interface

⎯ SRAM interface with byte control

Connectable areas: 1, 4

Settable bus widths: 64, 32, 16

• PCMCIA interface

⎯ Wait state insertion can be controlled by program

⎯ Bus sizing function for I/O bus width

• Fine refreshing control

⎯ Supports refresh operation immediately after self-refresh operation in low-power DRAM

by means of refresh counter overflow interrupt function

• Refresh counter can be used as interval timer

⎯ Interrupt request generated by compare-match

⎯ Interrupt request generated by refresh counter overflow

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 359 of 1074

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Note: * SH7750R only

13.1.2 Block Diagram

Figure 13.1 shows a block diagram of the BSC.

CS6–CS0

CE2A–CE2B

RD/FRAME

RD/WR

WE7–WE0

RAS

CAS7–CAS0, CASS

CKE

ICIORD, ICIOWR

REG

IOIS16

Internal bus

Bus

interface

WCR1

WCR2

WCR3

BCR1

BCR2

BCR3*

BCR4*

PCR

RFCR

RTCNT

RTCOR

RTCSR

Comparator

Refresh

control unit

Memory

control unit

Area

control unit

Wait

control unit

Interrupt

controller

BSC

Peripheral bus

Legend:

WCR: Wait control register

BCR: Bus control register

MCR: Memory control register

PCR: PCMCIA control register

Note: * SH7750R only

MCR

RDY

Module bus

RFCR: Refresh count register

RTCNT: Refresh timer count register

RTCOR: Refresh time constant register

RTCSR: Refresh timer control/status register

Figure 13.1 Block Diagram of BSC

Section 13 Bus State Controller (BSC)

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13.1.3 Pin Configuration

Table 13.1 shows the BSC pin configuration.

Table 13.1 BSC Pins

Name Signals I/O Description

Address bus A25−A0 O Address output

Data bus D63−D52,

D31−D0

I/O Data input/output

When port functions are used and DDT mode is

selected, input the DTR format. Otherwise, when

port functions are used, D63−D52 cannot be used

and should be left open.

Data bus/port D51−D32/

PORT19−

PORT0

I/O When port functions are not used: data input/output

When port functions are used: input/output port

(input or output set for each bit by register)

Bus cycle start BS O Signal that indicates the start of a bus cycle

When setting synchronous DRAM interface:

asserted once for a burst transfer

For other burst transfers: asserted each data cycle

Chip select 6−0 CS6−CS0 O Chip select signals that indicate the area being

accessed

CS5 and CS6 are also used as PCMCIA CE1A and

CE1B

Read/write RD/WR O Data bus input/output direction designation signal

Also used as the DRAM/synchronous

DRAM/PCMCIA interface write designation signal

Row address

strobe

RAS O RAS signal when setting DRAM/synchronous DRAM

interface

Read/column

address strobe/

cycle frame

RD/CASS/

FRAME

O Strobe signal that indicates a read cycle

When setting synchronous DRAM interface: CAS

signal

When setting MPX interface: FRAME signal

Section 13 Bus State Controller (BSC)

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Name Signals I/O Description

Data enable 0 WE0/CAS0/

DQM0

O When setting synchronous DRAM interface:

selection signal for D7–D0

When setting DRAM interface: CAS signal for

D7–D0

When setting MPX interface: high-level output

In other cases: write strobe signal for D7–D0

Data enable 1 WE1/CAS1/

DQM1

O When setting synchronous DRAM interface:

selection signal for D15–D8

When setting DRAM interface: CAS signal for

D15–D8

When setting PCMCIA interface: write strobe signal

When setting MPX interface: high-level output

In other cases: write strobe signal for D15–D8

Data enable 2 WE2/CAS2/

DQM2/ICIORD

O When setting synchronous DRAM interface:

selection signal for D23–D16

When setting DRAM interface: CAS signal for

D23–D16

When setting PCMCIA interface: ICIORD signal

When setting MPX interface: high-level output

In other cases: write strobe signal for D23–D16

Data enable 3 WE3/CAS3/

DQM3/ICIOWR

O When setting synchronous DRAM interface:

selection signal for D31–D24

When setting DRAM interface: CAS signal for

D31–D24

When setting PCMCIA interface: ICIOWR signal

When setting MPX interface: high-level output

In other cases: write strobe signal for D31–D24

Data enable 4 WE4/CAS4/

DQM4

O When setting synchronous DRAM interface:

selection signal for D39–D32

When setting DRAM interface: CAS signal for

D39–D32

When setting MPX interface: high-level output

In other cases: write strobe signal for D39–D32

Section 13 Bus State Controller (BSC)

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Name Signals I/O Description

Data enable 5 WE5/CAS5/

DQM5

O When setting synchronous DRAM interface:

selection signal for D47–D40

When setting DRAM interface: CAS signal for

D47–D40

When setting MPX interface: high-level output

In other cases: write strobe signal for D47–D40

Data enable 6 WE6/CAS6/

DQM6

O When setting synchronous DRAM interface:

selection signal for D55–D48

When setting DRAM interface: CAS signal for

D55–D48

When setting MPX interface: high-level output

In other cases: write strobe signal for D55–D48

Data enable 7 WE7/CAS7/

DQM7/REG

O When setting synchronous DRAM interface:

selection signal for D63–D56

When setting DRAM interface: CAS signal for

D63–D56

When setting PCMCIA interface: REG signal

When setting MPX interface: high-level output

In other cases: write strobe signal for D63–D56

Ready RDY I Wait state request signal

Area 0 MPX

interface

specification/

16-bit I/O

MD6/IOIS16 I In power-on reset: Designates area 0 bus as MPX

interface (1: SRAM, 0: MPX)

When setting PCMCIA interface: 16-bit I/O

designation signal. Valid only in little-endian mode.

Clock enable CKE O Synchronous DRAM clock enable control signal

Bus release

request

BREQ/

BSACK

I Bus release request signal/bus acknowledge signal

Bus use

permission

BACK/

BSREQ

O Bus use permission signal/bus request

Area 0 bus

width/PCMCIA

card select

MD3/CE2A*1

MD4/CE2B*2

I/O In power-on reset*4: external space area 0 bus width

specification signal

When setting PCMCIA interface: CE2A, CE2B

Endian switchover/

row address strobe

MD5/RAS2*3 I/O Endian specification in a power-on reset.*4

RAS2 when DRAM is connected to area 2

Section 13 Bus State Controller (BSC)

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Name Signals I/O Description

Master/slave

switchover

MD7/TXD I/O Indicates master/slave status in a power-on reset.*4

Serial interface TXD

DMAC0

acknowledge

signal

DACK0 O DMAC channel 0 data acknowledge

DMAC1

acknowledge

signal

DACK1 O DMAC channel 1 data acknowledge

Read/column

address strobe/

cycle frame 2

RD2 O Same signal as RD/CASS/FRAME

This signal is used when the RD/CASS/FRAME

signal load is heavy.

Read/write 2 RD/WR2 O Same signal as RD/WR

This signal is used when the RD/WR signal load is

heavy.

Notes: 1. MD3/CE2A input/output switching is performed by BCR1.A56PCM. Output is selected

when BCR1.A56PCM = 1.

2. MD4/CE2B input/output switching is performed by BCR1.A56PCM. Output is selected

when BCR1.A56PCM = 1.

3. MD5/RAS2 input/output switching is performed by BCR1.DRAMTP. Output is selected

when BCR1.DRAMTP (2–0) = 101.

4. In a power-on reset by means of the RESET pin.

Section 13 Bus State Controller (BSC)

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13.1.4 Register Configuration

The BSC has the 11 registers shown in table 13.2. In addition, the synchronous DRAM mode

functions of these registers include control of interfaces to various types of memory, wait states,

and refreshing.

Table 13.2 BSC Registers

Name

Abbrevia-

tion

R/W Initial

Value

Address

Area 7

Address

Access

Size

Bus control register 1 BCR1 R/W H'0000 0000 H'FF80 0000 H'1F80 0000 32

Bus control register 2 BCR2 R/W H'3FFC H'FF80 0004 H'1F80 0004 16

Bus control register 3*2 BCR3 R/W H'0000 H'FF80 0050 H'1F80 0050 16

Bus control register 4*2 BCR4 R/W H'0000 0000 H'FE0A 00F0 H'1E0A 00F0 32

Wait state control

WCR1 R/W H'7777 7777 H'FF80 0008 H'1F80 0008 32

Wait state control

WCR2 R/W H'FFFE EFFF H'FF80 000C H'1F80 000C 32

Wait state control

WCR3 R/W H'0777 7777 H'FF80 0010 H'1F80 0010 32

Memory control register MCR R/W H'0000 0000 H'FF80 0014 H'1F80 0014 32

PCMCIA control register PCR R/W H'0000 H'FF80 0018 H'1F80 0018 16

Refresh timer

control/status register

RTCSR R/W H'0000 H'FF80 001C H'1F80 001C 16

Refresh timer counter RTCNT R/W H'0000 H'FF80 0020 H'1F80 0020 16

Refresh time constant

counter

RTCOR R/W H'0000 H'FF80 0024 H'1F80 0024 16

Refresh count register RFCR R/W H'0000 H'FF80 0028 H'1F80 0028 16

For

area 2

SDMR2 W — H'FF90 xxxx*1H'1F90 xxxx 8 Synchronous

DRAM mode

registers For

area 3

SDMR3 H'FF94 xxxx*1H'1F94 xxxx

Notes: 1. For details, see section 13.2.10, Synchronous DRAM Mode Register (SDMR).

2. Settable only for SH7750R.

Section 13 Bus State Controller (BSC)

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13.1.5 Overview of Areas

Space Divisions: The architecture of this LSI provides a 32-bit virtual address space. The virtual

address is divided into five areas according to the upper address value. External memory space

comprises a 29-bit address space, divided into eight areas.

The virtual address can be allocated to any external address by means of the memory management

unit (MMU). Details are given in section 3, Memory Management Unit (MMU). This section

describes the areas into which the external address is divided.

With this LSI, various kinds of memory or PC cards can be connected to the seven areas of

external address as shown in table 13.3, and chip select signals (CS0–CS6, CE2A, CE2B) are

output for each of these areas. CS0 is asserted when accessing area 0, and CS6 when accessing

area 6. When DRAM or synchronous DRAM is connected to area 2 or 3, signals such as RAS,

CAS, RD/WR, and DQM are also asserted. When the PCMCIA interface is selected for area 5 or

6, CE2A, CE2B is asserted in addition to CS5, CS6 for the byte to be accessed.

H'0000 0000

H'8000 0000

H'A000 0000

H'C000 0000

H'E000 0000

H'FFFF FFFF

H'E400 0000

H'0000 0000

H'0400 0000

H'0800 0000

H'0C00 0000

H'1000 0000

H'1400 0000

H'1800 0000

H'1FFF FFFF

H'1C00 0000

Area 0 (CS0)

Area 1 (CS1)

Area 2 (CS2)

Area 3 (CS3)

Area 4 (CS4)

Area 5 (CS5)

Area 6 (CS6)

Area 7 (reserved area)

P0 and

U0 areas

P1 area

P2 area

P3 area

Physical address

space

(MMU off)

Virtual address

space

(MMU on)

External memory

space

Store queue area

P4 area

P0 and

U0 areas

256

P1 area

P2 area

P3 area

Store queue area

P4 area

Notes: 1. When the MMU is off (MMUCR.AT = 0), the top 3 bits of the 32-bit address are ignored, and

memory is mapped onto a fixed 29-bit external address.

2. When the MMU is on (MMUCR.AT = 1), the P0, U0, P3, and store queue areas can be

mapped onto any external address using the TLB.

For details, see section 3, Memory Management Unit (MMU).

Figure 13.2 Correspondence between Virtual Address Space and External Memory Space

Section 13 Bus State Controller (BSC)

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Table 13.3 External Memory Space Map

Area

External

Addresses

Size

Connectable

Memory

Settable Bus

Widths

Access Size

SRAM 8, 16, 32, 64*1

Burst ROM 8, 16, 32*1, 64*7

0 H'00000000–

H'03FFFFFF

64 Mbytes

MPX 32, 64*1

8, 16, 32,

64*6 bits,

32 bytes

SRAM 8, 16, 32, 64*2

MPX 32, 64*2

1 H'04000000–

H'07FFFFFF

64 Mbytes

Byte control SRAM 16, 32, 64*2

8, 16, 32,

64*6 bits,

32 bytes

SRAM 8, 16, 32, 64*2

Synchronous DRAM 32, 64*2 *3

DRAM 16, 32*2 *3

2 H'08000000–

H'0BFFFFFF

64 Mbytes

MPX 32, 64*2

8, 16, 32,

64*6 bits,

32 bytes

SRAM 8, 16, 32, 64*2

Synchronous DRAM 32, 64*2 *3

DRAM 16, 32, 64*2 *3

3 H'0C000000–

H'0FFFFFFF

64 Mbytes

MPX 32, 64*2

8, 16, 32,

64*6 bits,

32 bytes

SRAM 8, 16, 32, 64*2

MPX 32, 64*2

4 H'10000000–

H'13FFFFFF

64 Mbytes

Byte control RAM 16, 32, 64*2

8, 16, 32,

64*6 bits,

32 bytes

SRAM 8, 16, 32, 64*2

MPX 32, 64*2

Burst ROM 8, 16, 32*2, 64*7

5 H'14000000–

H'17FFFFFF

64 Mbytes

PCMCIA 8, 16*2 *4

8, 16, 32,

64*6 bits,

32 bytes

SRAM 8, 16, 32, 64*2

MPX 32, 64*2

Burst ROM 8,16, 32*2, 64*7

6 H'18000000–

H'1BFFFFFF

64 Mbytes

PCMCIA 8,16*2 *4

8, 16, 32,

64*6 bits,

32 bytes

7*5 H'1C000000–

H'1FFFFFFF

64 Mbytes — —

Notes: 1. Memory bus width specified by external pins

2. Memory bus width specified by register

3. With synchronous DRAM interface, bus width is 32 or 64 bits only.

With DRAM interface, bus width is 16 or 32 bits only for area 2, and 16, 32, or 64 bits

only for area 3. Bus width of area 2 is as same as that of area 3 which is specified by

MCR.

4. With PCMCIA interface, bus width is 8 or 16 bits only.

5. Do not access a reserved area, as operation cannot be guaranteed in this case.

Section 13 Bus State Controller (BSC)

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6. 64-bit access applies only to transfer by the DMAC. (CHCRn. TS = 000)

In a transfer to an external memory by FMOV (FPSCR.SZ = 1), two transfer operations,

each with an access size of 32 bits, are conducted.

7. Settable only for SH7750R.

Area 0: H'00000000

Area 1: H'04000000

Area 2: H'08000000

Area 3: H'0C000000

Area 4: H'10000000

Area 5: H'14000000

Area 6: H'18000000

SRAM/burst ROM/MPX

SRAM/MPX/byte control SRAM

SRAM/synchronous DRAM/DRAM/

MPX

SRAM/synchronous DRAM/DRAM/

MPX

SRAM/MPX/byte control SRAM

SRAM/burst ROM/PCMCIA/MPX

The PCMCIA interface is

for memory and I/O card use

Figure 13.3 External Memory Space Allocation

Memory Bus Width: In this LSI, the memory bus width can be set independently for each space.

For area 0, a bus size of 8, 16, 32, or 64 bits can be selected in a power-on reset by the RESET pin,

using external pins. The relationship between the external pins (MD4 and MD3) and the bus width

in a power-on reset is shown below.

MD4 MD3 Bus Width

0 0 64 bits

1 8 bits

1 0 16 bits

1 32 bits

When SRAM interface or ROM is used in areas 1 to 6, a bus width of 8, 16, 32, or 64 bits can be

selected with bus control register 2 (BCR2). When burst ROM is used, a bus width of 8, 16, 32, or

64* bits can be selected. When byte control SRAM interface is used, a bus width of 16, 32, or 64

bits can be selected. When the MPX interface is used, a bus width of 32 or 64 bits can be selected.

When the DRAM interface is used, a bus width of 16, 32, or 64 bits can be selected with the

Section 13 Bus State Controller (BSC)

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memory control register (MCR). When the DRAM interface is used for area 2 or 3, a bus width of

16 or 32 bits should be set. For the synchronous DRAM interface, set a bus width of 32 or 64 bits

in the MCR register.

When using the PCMCIA interface, set a bus width of 8 or 16 bits.

For details, see section 13.3.7, PCMCIA Interface.

When using port functions, set a bus width of 8, 16, or 32 bits for all areas.

For details, see section 13.2.2, Bus Control Register 2 (BCR2), and section 13.2.8, Memory

Control Register (MCR).

The area 7 address range, H'1C000000 to H'1FFFFFFFF, is a reserved space and must not be used.

Note: * SH7750R only

13.1.6 PCMCIA Support

This LSI supports PCMCIA compliant interface specifications for external memory space areas 5

and 6.

The interfaces supported are the IC memory card interface and I/O card interface stipulated in

JEIDA specifications version 4.2 (PCMCIA2.1).

External memory space areas 5 and 6 support both the IC memory card interface and the I/O card

interface.

The PCMCIA interface is supported only in little-endian mode.

Table 13.4 PCMCIA Interface Features

Item Features

Access Random access

Data bus 8/16 bits

Memory type Mask ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM

Common memory capacity Max. 64 Mbytes

Attribute memory capacity Max. 64 Mbytes

Others Dynamic bus sizing for I/O bus width, access to PCMCIA interface

from address translation areas

Section 13 Bus State Controller (BSC)

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Table 13.5 PCMCIA Support Interfaces

IC Memory Card Interface I/O Card Interface

Signal

Name

I/O

Function

Signal

Name

I/O

Function

Corresponding

LSI Pin

1 GND Ground GND Ground —

2 D3 I/O Data D3 I/O Data D3

3 D4 I/O Data D4 I/O Data D4

4 D5 I/O Data D5 I/O Data D5

5 D6 I/O Data D6 I/O Data D6

6 D7 I/O Data D7 I/O Data D7

7 CE1 I Card enable CE1 I Card enable CS5 or CS6

8 A10 I Address A10 I Address A10

9 OE I Output enable OE I Output enable RD

10 A11 I Address A11 I Address A11

11 A9 I Address A9 I Address A9

12 A8 I Address A8 I Address A8

13 A13 I Address A13 I Address A13

14 A14 I Address A14 I Address A14

15 WE/PGM I Write enable WE/PGM I Write enable WE1

16 RDY/BSY O Ready/busy IREQ O Interrupt request Sensed on port

17 VCC Operating power

supply

VCC Operating power

supply

—

18 VPP1 Programming

power supply

VPP1 Programming/

peripheral power

supply

—

19 A16 I Address A16 I Address A16

20 A15 I Address A15 I Address A15

21 A12 I Address A12 I Address A12

22 A7 I Address A7 I Address A7

23 A6 I Address A6 I Address A6

24 A5 I Address A5 I Address A5

25 A4 I Address A4 I Address A4

26 A3 I Address A3 I Address A3

27 A2 I Address A2 I Address A2

Section 13 Bus State Controller (BSC)

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IC Memory Card Interface I/O Card Interface

Signal

Name

I/O

Function

Signal

Name

I/O

Function

Corresponding

LSI Pin

28 A1 I Address A1 I Address A1

29 A0 I Address A0 I Address A0

30 D0 I/O Data D0 I/O Data D0

31 D1 I/O Data D1 I/O Data D1

32 D2 I/O Data D2 I/O Data D2

33 WP* O Write protect IOIS16 O 16-bit I/O port IOIS16

34 GND Ground GND Ground —

35 GND Ground GND Ground —

36 CD1 O Card detection CD1 O Card detection Sensed on port

37 D11 I/O Data D11 I/O Data D11

38 D12 I/O Data D12 I/O Data D12

39 D13 I/O Data D13 I/O Data D13

40 D14 I/O Data D14 I/O Data D14

41 D15 I/O Data D15 I/O Data D15

42 CE2 I Card enable CE2 I Card enable CE2A or CE2B

43 RFSH I Refresh request RFSH I Refresh request Output from port

44 RFU Reserved IORD I I/O read ICIORD

45 RFU Reserved IOWR I I/O write ICIOWR

46 A17 I Address A17 I Address A17

47 A18 I Address A18 I Address A18

48 A19 I Address A19 I Address A19

49 A20 I Address A20 I Address A20

50 A21 I Address A21 I Address A21

51 VCC Power supply VCC Power supply —

52 VPP2 Programming

power supply

VPP2 Programming/

peripheral power

supply

—

53 A22 I Address A22 I Address A22

54 A23 I Address A23 I Address A23

55 A24 I Address A24 I Address A24

Section 13 Bus State Controller (BSC)

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IC Memory Card Interface I/O Card Interface

Signal

Name

I/O

Function

Signal

Name

I/O

Function

Corresponding

LSI Pin

56 A25 I Address A25 I Address A25

57 RFU Reserved RFU Reserved —

58 RESET I Reset RESET I Reset Output from port

59 WAIT O Wait request WAIT O Wait request RDY*2

60 RFU Reserved INPACK O Input acknowledge —

61 REG I Attribute memory

space select

REG I Attribute memory

space select

WE7

62 BVD2 O Battery voltage

detection

SPKR O Digital speech

signal

Sensed on port

63 BVD1 O Battery voltage

detection

STSCHG O Card status

change

Sensed on port

64 D8 I/O Data D8 I/O Data D8

65 D9 I/O Data D9 I/O Data D9

66 D10 I/O Data D10 I/O Data D10

67 CD2 O Card detection CD2 O Card detection Sensed on port

68 GND Ground GND Ground —

Note: 1. WP is not supported.

2. Input an external wait request with correct polarity.

Section 13 Bus State Controller (BSC)

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13.2 Register Descriptions

13.2.1 Bus Control Register 1 (BCR1)

Bus control register 1 (BCR1) is a 32-bit readable/writable register that specifies the function, bus

cycle status, etc., of each area.

BCR1 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or

in standby mode. External memory space other than area 0 should not be accessed until register

initialization is completed.

Bit: 31 30 29 28 27 26 25 24

ENDIAN MASTER A0MPX — — DPUP*2IPUP OPUP

Initial value: 0/1*1 0/1*1 0/1*1 0 0 0 0 0

R/W: R R R R R R/W R/W R/W

Bit: 23 22 21 20 19 18 17 16

— — A1MBC A4MBC

BREQEN PSHR MEMMPX DMABST*2

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R/W R/W R/W R/W R/W R

Bit: 15 14 13 12 11 10 9 8

HIZMEM HIZCNT A0BST2 A0BST1 A0BST0 A5BST2 A5BST1 A5BST0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

A6BST2 A6BST1 A6BST0 DRAMTP2 DRAMTP1 DRAMTP0 — A56PCM

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R R/W

Notes: 1. These bits sample external pin values in a power-on reset by means of the RESET pin.

2. SH7750R only.

Section 13 Bus State Controller (BSC)

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Bit 31—Endian Flag (ENDIAN): Samples the value of the endian specification external pin

(MD5) in a power-on reset by the RESET pin. The endian mode of all spaces is determined by this

bit. ENDIAN is a read-only bit.

Bit 31: ENDIAN Description

0 In a power-on reset, the endian setting external pin (MD5) is low,

designating big-endian mode

1 In a power-on reset, the endian setting external pin (MD5) is high,

designating little-endian mode

Bit 30—Master/Slave Flag (MASTER): Samples the value of the master/slave specification

external pin (MD7) in a power-on reset by the RESET pin. The master/slave status of all spaces is

determined by this bit. MASTER is a read-only bit.

Bit 30: MASTER Description

0 In a power-on reset, the master/slave setting external pin (MD7) is high,

designating master mode

1 In a power-on reset, the master/slave setting external pin (MD7) is low,

designating slave mode

Bit 29—Area 0 Memory Type (A0MPX): Samples the value of the area 0 memory type

specification external pin (MD6) in a power-on reset by the RESET pin. The memory type of area

0 is determined by this bit. A0MPX is a read-only bit.

Bit 29: A0MPX Description

0 In a power-on reset, the external pin specifying the area 0 memory type

(MD6) is high, designating the area 0 as SRAM interface

1 In a power-on reset, the external pin specifying the area 0 memory type

(MD6) is low, designating the area 0 as MPX interface

Bits 28, 27, 26*, 23, 22, 16*, and 1—Reserved: These bits are always read as 0, and should only

be written with 0.

Note: * SH7750, SH7750S only.

Section 13 Bus State Controller (BSC)

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Bit 26—Data pin Pullup Resistor Control (DPUP) (SH7750R only): Controls the pullup

resistance of the data pins (D63 to D0). It is initialized at a power-on reset. The pins are not pulled

up when access is performed or when the bus is released, even if the ON setting is selected.

Bit 26: DPUP Description

0 Sets pullup resistance of data pins (D63 to D0) ON (Initial value)

1 Sets pullup resistance of data pins (D63 to D0) OFF

Bit 25—Control Input Pin Pull-Up Resistor Control (IPUP): Specifies the pull-up resistor

status for control input pins (NMI, IRL0–IRL3, BREQ, MD6/IOIS16, RDY). IPUP is initialized

by a power-on reset.

Bit 25: IPUP Description

0 Pull-up resistor is on for control input pins (NMI, IRL0–IRL3, BREQ,

MD6/IOIS16, RDY) (Initial value)

1 Pull-up resistor is off for control input pins (NMI, IRL0–IRL3, BREQ,

MD6/IOIS16, RDY)

Bit 24—Control Output Pin Pull-Up Resistor Control (OPUP): Specifies the pull-up resistor

status for control output pins (A[25:0], BS, CSn, RD, WEn, RD/WR, RAS, RAS2, CE2A, CE2B,

RD2, RD/WR2) when high-impedance. OPUP is initialized by a power-on reset.

Bit 24: OPUP Description

0 Pull-up resistor is on for control output pins (A[25:0], BS, CSn, RD, WEn,

RD/WR, RAS, RAS2, CE2A, CE2B, RD2, RD/WR2) (Initial value)

1 Pull-up resistor is off for control output pins (A[25:0], BS, CSn, RD, WEn,

RD/WR, RAS, RAS2, CE2A, CE2B, RD2, RD/WR2)

Bit 21—Area 1 SRAM Byte Control Mode (A1MBC): MPX interface has priority when an

MPX interface is set. This bit is initialized by a power-on reset.

Bit 21: A1MBC Description

0 Area 1 SRAM is set to normal mode (Initial value)

1 Area 1 SRAM is set to byte control mode

Section 13 Bus State Controller (BSC)

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Bit 20—Area 4 SRAM Byte Control Mode (A4MBC): MPX interface has priority when an

MPX interface is set. This bit is initialized by a power-on reset.

Bit 20: A4MBC Description

0 Area 4 SRAM is set to normal mode (Initial value)

1 Area 4 SRAM is set to byte control mode

Bit 19—BREQ Enable (BREQEN): Indicates whether external requests can be accepted.

BREQEN is initialized to the external request acceptance disabled state by a power-on reset. It is

ignored in the case of a slave mode startup.

Bit 19: BREQEN Description

0 External requests are not accepted (Initial value)

1 External requests are accepted

Bit 18—Partial-Sharing Bit (PSHR): Sets partial-sharing mode. PSHR is valid only in the case

of a master mode startup.

Bit 18: PSHR Description

0 Master mode (Initial value)

1 Partial-sharing mode

Bit 17—Area 1 to 6 MPX Interface Specification (MEMMPX): Sets the MPX interface when

areas 1 to 6 are set as SRAM interface (or burst ROM interface). MEMMPX is initialized by a

power-on reset.

Bit 17: MEMMPX Description

0 SRAM interface (or burst ROM interface) is selected when areas 1 to 6 are

set as SRAM interface (or burst ROM interface) (Initial value)

1 MPX interface is selected when areas 1 to 6 are set as SRAM interface (or

burst ROM interface)

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Bit 16—DMAC Burst Mode Transfer Priority Setting (DMABST) (SH7750R Only):

Specifies the priority of burst mode transfers by the DMAC. When OFF, the priority is as follows:

bus privilege released, refresh, DMAC, CPU. When ON, the bus privileges are released and

refresh operations are not performed until the end of the DMAC's burst transfer. This bit is

initialized at a power-on reset.

Bit 16: DMABST Description

0 DMAC burst mode transfer priority specification OFF (Initial value)

1 DMAC burst mode transfer priority specification ON

Bit 15—High Impedance Control (HIZMEM): Specifies the state of address and other signals

(A[25:0], BS, CSn, RD/WR, CE2A, CE2B) in software standby mode.

Bit 15: HIZMEM Description

0 The A[25:0], BS, CSn, RD/WR, CE2A, and CE2B signals go to high-

impedance (High-Z) in standby mode and when the bus is released

(Initial value)

1 The A[25:0], BS, CSn, RD/WR, CE2A, and CE2B signals are driven in

standby mode. When the bus is released, they go to high-impedance.

Bit 14—High Impedance Control (HIZCNT): Specifies the state of the RAS and CAS signals in

software standby mode and when the bus is released.

Bit 14: HIZCNT Description

0 The RAS, RAS2, WEn/CASn/DQMn, RD/CASS/FRAME, and RD2 signals

go to high-impedance (High-Z) in standby mode and when the bus is

released (Initial value)

1 The RAS, RAS2, WEn/CASn/DQMn, RD/CASS/FRAME, and RD2 signals

are driven in standby mode and when the bus is released

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Bits 13 to 11—Area 0 Burst ROM Control (A0BST2–A0BST0): These bits specify whether

burst ROM interface is used in area 0. When burst ROM interface is used, they also specify the

number of accesses in a burst. If area 0 is an MPX interface area, these bits are ignored.

Bit 13: A0BST2 Bit 12: A0BST1 Bit 11: A0BST0 Description

0 0 0 Area 0 is accessed as SRAM interface

(Initial value)

1 Area 0 is accessed as burst ROM

interface (4 consecutive accesses)

Can be used with 8-, 16-, 32-, or 64*-bit

bus width

1 0 Area 0 is accessed as burst ROM

interface (8 consecutive accesses)

Can only be used with 8-, 16-, or 32-bit

bus width

1 Area 0 is accessed as burst ROM

interface (16 consecutive accesses)

Can only be used with 8- or 16-bit bus

width. Do not specify for 32-bit bus width

1 0 0 Area 0 is accessed as burst ROM

interface (32 consecutive accesses)

Can only be used with 8-bit bus width

1 Reserved

1 0 Reserved

1 Reserved

Note: * Settable only for SH7750R.

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Bits 10 to 8—Area 5 Burst Enable (A5BST2–A5BST0): These bits specify whether burst ROM

interface is used in area 5. When burst ROM interface is used, they also specify the number of

accesses in a burst. If area 5 is an MPX interface area, these bits are ignored.

Bit 10: A5BST2 Bit 9: A5BST1 Bit 8: A5BST0 Description

0 0 0 Area 5 is accessed as SRAM interface

(Initial value)

1 Area 5 is accessed as burst ROM

interface (4 consecutive accesses)

Can be used with 8-, 16-, 32-, or 64*-bit

bus width

1 0 Area 5 is accessed as burst ROM

interface (8 consecutive accesses)

Can only be used with 8-, 16-, or 32-bit

bus width

1 Area 5 is accessed as burst ROM

interface (16 consecutive accesses)

Can only be used with 8- or 16-bit bus

width. Do not specify for 32-bit bus width

1 0 0 Area 5 is accessed as burst ROM

interface (32 consecutive accesses)

Can only be used with 8-bit bus width

1 Reserved

1 0 Reserved

1 Reserved

Notes: Clear to 0 when PCMCIA interface is set.

* Settable only for SH7750R.

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Bits 7 to 5—Area 6 Burst Enable (A6BST2–A6BST0): These bits specify whether burst ROM

interface is used in area 6. When burst ROM interface is used, they also specify the number of

accesses in a burst. If area 6 is an MPX interface area, these bits are ignored.

Bit 7: A6BST2 Bit 6: A6BST1 Bit 5: A6BST0 Description

0 0 0 Area 6 is accessed as SRAM interface

(Initial value)

1 Area 6 is accessed as burst ROM

interface (4 consecutive accesses)

Can be used with 8-, 16-, 32-, or 64*-bit

bus width

1 0 Area 6 is accessed as burst ROM

interface (8 consecutive accesses)

Can only be used with 8-, 16-, or 32-bit

bus width

1 Area 6 is accessed as burst ROM

interface (16 consecutive accesses)

Can only be used with 8- or 16-bit bus

width. Do not specify for 32-bit bus width

1 0 0 Area 6 is accessed as burst ROM

interface (32 consecutive accesses)

Can only be used with 8-bit bus width

1 Reserved

1 0 Reserved

1 Reserved

Notes: Clear to 0 when PCMCIA interface is set.

* Settable only for SH7750R.

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Bits 4 to 2—Area 2 and 3 Memory Type (DRAMTP2–DRAMTP0): These bits specify the type

of memory connected to areas 2 and 3. ROM, SRAM, flash ROM, etc., can be connected as

SRAM interface. DRAM and synchronous DRAM can also be connected.

Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description

0 0 0 Areas 2 and 3 are SRAM interface or MPX

interface*1

(Initial value)

1 Reserved (Cannot be set)

1 0 Area 2 is SRAM interface or MPX

interface*1, area 3 is synchronous DRAM

interface

1 Areas 2 and 3 are synchronous DRAM

interface

1 0 0 Area 2 is SRAM interface or MPX

interface*1, area 3 is DRAM interface

1 Areas 2 and 3 are DRAM interface*2

1 0 Reserved (Cannot be set)

1 Reserved (Cannot be set)

Notes: 1. Selection of SRAM interface or MPX interface is determined by the setting of the

MEMMPX bit

2. When this mode is selected, 16 or 32 bits should be specified as the bus width for areas

2 and 3. In this mode the MD5 pin is designated for output as the RAS2 pin.

Bit 0—Area 5 and 6 Bus Type (A56PCM): Specifies whether areas 5 and 6 are accessed as

PCMCIA interface. The setting of these bits has priority over the MEMMPX bit settings.

Bit 0: A56PCM Description

0 Areas 5 and 6 are accessed as SRAM interface (Initial value)

1 Areas 5 and 6 are accessed as PCMCIA interface*

Note: * The MD3 pin is designated for output as the CE2A pin.

The MD4 pin is designated for output as the CE2B pin.

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13.2.2 Bus Control Register 2 (BCR2)

Bus control register 2 (BCR2) is a 16-bit readable/writable register that specifies the bus width for

each area, and whether a 16-bit port is used.

BCR2 is initialized to H'3FFC by a power-on reset, but is not initialized by a manual reset or in

standby mode. External memory space other than area 0 should not be accessed until register

initialization is completed.

Bit: 15 14 13 12 11 10 9 8

A0SZ1 A0SZ0 A6SZ1 A6SZ0 A5SZ1 A5SZ0 A4SZ1 A4SZ0

Initial value: 0/1* 0/1* 1 1 1 1 1 1

R/W: R R R/W R/W R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

A3SZ1 A3SZ0 A2SZ1 A2SZ0 A1SZ1 A0SZ0 — PORTEN

Initial value: 1 1 1 1 1 1 0 0

R/W: R/W R/W R/W R/W R/W R/W — R/W

Note: * These bits sample the values of the external pins that specify the area 0 bus size.

Bits 15 and 14—Area 0 Bus Width (A0SZ1, A0SZ0): These bits sample the external pins, MD4

and MD3 that specify the bus size in a power-on reset by the RESET pin. They are read-only bits.

Bit 15 Bit 14

A0SZ1 A0SZ0 Description

0 0 Bus width is 64 bits

1 Bus width is 8 bits

1 0 Bus width is 16 bits

1 Bus width is 32 bits

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Bits 2n + 1, 2n—Area n (1 to 6) Bus Width Specification (AnSZ1, AnSZ0): These bits specify

the bus width of area n (n = 1 to 6).

(Bit 0): PORTEN Bit 2n + 1: AnSZ1 Bit 2n: AnSZ0 Description

0 0 0 Bus width is 64 bits

1 Bus width is 8 bits

1 0 Bus width is 16 bits

1 Bus width is 32 bits (Initial value)

1 0 0 Reserved (Setting prohibited)

1 Bus width is 8 bits

1 0 Bus width is 16 bits

1 Bus width is 32 bits

Bit 1—Reserved: This bit is always read as 0, and should only be written with 0.

Bit 0—Port Function Enable (PORTEN): Specifies whether pins D51 to D32 are used as a 20-

bit port. When this function is used, a bus width of 8, 16, or 32 bits should be set for all areas.

Bit 0: PORTEN Description

0 D51 to D32 are not used as a port (Initial value)

1 D51 to D32 are used as a port

Section 13 Bus State Controller (BSC)

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13.2.3 Bus Control Register 3 (BCR3) (SH7750R Only)

Bus control register 3 (BCR3) is a 16-bit readable/writable register that specifies the selection of

either the MPX interface or the SRAM interface and specifies the burst length when the

synchronous DRAM interface is used.

BCR3 is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in

standby mode. No external memory space other than area 0 should be accessed before register

initialization has been completed.

Bit: 15 14 13 12 11 10 9 8

MEMMODE A1MPX A4MPX — — — — —

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R R R R R

Bit: 7 6 5 4 3 2 1 0

— — — — — — — SDBL

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R R R/W

Bit 15⎯A1MPX/A4MPX Enable (MEMMODE): Determines whether or not the selection of

either the MPX interface or the SRAM interface is by A1MPX and A4MPX rather than by

MEMMPX.

Bit 15: MEMMODE Description

0 MPX or SRAM interface is selected by MEMMPX (Initial value)

1 MPX or SRAM interface is selected by A1MPX and A4MPX

Section 13 Bus State Controller (BSC)

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Bits 14 and 13⎯MPX-Interface Specification for Area 1 and 4 (A1MPX, A4MPX): These

bits specify the types of memory connected to areas 1 and 4. These settings are validated by

MEMMODE.

Bit 14: A1MPX Description

0 SRAM/byte control SRAM interface is selected for area 1 (Initial value)

1 MPX interface is selected for area 1

Bit 13: A4MPX Description

0 SRAM/byte control SRAM interface is selected for area 4 (Initial value)

1 MPX interface is selected for area 4

Bits 12 to 1—Reserved: These bits are always read as 0, and should only be written with 0.

Bit 0⎯Burst Length (SDBL): Sets the burst length when the synchronous DRAM interface is

used. The burst-length setting is only valid when the bus width is 32 bits.

Bit 0: SDBL Description

0 Burst length is 8 (Initial value)

1 Burst length is 4

13.2.4 Bus Control Register 4 (BCR4) (SH7750R Only)

Bus control register 4 (BCR4) is a 32-bit readable/writable register that enables asynchronous

input to the pin corresponding to each bit.

BCR4 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or

in standby mode.

When asynchronous input is set (ASYNCn = 1), the sampling timing is one cycle earlier than

when synchronous input is set (ASYNCn = 0)* (see figure 13.4)

The timings shown in this section and section 22, Electrical Characteristics, are all for the case

where synchronous input is set (ASYNCn = 0).

Note: * With the synchronous input setting, ensure that setup and hold times are observed.

Section 13 Bus State Controller (BSC)

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T1 Tw Tw Twe T2

CKIO

RDY

(BCR4.ASYNC0 = 0)

(BCR4.ASYNC0 = 1)

Figure 13.4 Example of RDY Sampling Timing at which BCR4 Is Set

(Two Wait Cycles Are Inserted by WCR2)

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Bit: 31 30 29 28 27 26 25 24

— — — — — — — —

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R R R

Bit: 23 22 21 20 19 18 17 16

— — — — — — — —

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R R R

Bit: 15 14 13 12 11 10 9 8

— — — — — — — —

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R R R

Bit: 7 6 5 4 3 2 1 0

— — — ASYNC

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R/W R/W R/W R/W R/W

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Bits 31 to 5⎯Reserved: These bits are always read as 0, and should only be written with 0.

Bits 4 to 0⎯Asynchronous Input: These bits enable asynchronous input to the corresponding

pin.

Bits 4 to 0: ASYNCn Description

0 Input to corresponding pin is synchronous with CKIO (Initial value)

1 Input to corresponding pin can be asynchronous with CKIO

Bit Corresponding Pin

4 IOIS16

3 DREQ1

2 DREQ0

1 BREQ

0 RDY

Section 13 Bus State Controller (BSC)

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13.2.5 Wait Control Register 1 (WCR1)

Wait control register 1 (WCR1) is a 32-bit readable/writable register that specifies the number of

idle state insertion cycles for each area. With some kinds of memory, data bus drive does not go

off immediately after the read signal from off-chip goes off. As a result, there is a possibility of a

data bus collision when consecutive memory accesses are performed on memory in different areas,

or when a memory write is performed immediately after a read. In this LSI, the number of idle

cycles set in the WCR1 register are inserted automatically if there is a possibility of this kind of

data bus collision.

WCR1 is initialized to H'77777777 by a power-on reset, but is not initialized by a manual reset or

in standby mode.

Bit: 31 30 29 28 27 26 25 24

— DMAIW2 DMAIW1 DMAIW0 — A6IW2 A6IW1 A6IW0

Initial value: 0 1 1 1 0 1 1 1

R/W: R R/W R/W R/W R R/W R/W R/W

Bit: 23 22 21 20 19 18 17 16

— A5IW2 A5IW1 A5IW0 — A4IW2 A4IW1 A4IW0

Initial value: 0 1 1 1 0 1 1 1

R/W: R R/W R/W R/W R R/W R/W R/W

Bit: 15 14 13 12 11 10 9 8

— A3IW2 A3IW1 A3IW0 — A2IW2 A2IW1 A2IW0

Initial value: 0 1 1 1 0 1 1 1

R/W: R R/W R/W R/W R R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

— A1IW2 A1IW1 A1IW0 — A0IW2 A0IW1 A0IW0

Initial value: 0 1 1 1 0 1 1 1

R/W: R R/W R/W R/W R R/W R/W R/W

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Bits 31, 27, 23, 19, 15, 11, 7, and 3—Reserved: These bits are always read as 0, and should only

be written with 0.

Bits 30 to 28— DMAIW-DACK Device Inter-Cycle Idle Specification (DMAIW2–

DMAIW0): These bits specify the number of idle cycles between bus cycles to be inserted when

switching from a DACK device to another space, or from a read access to a write access on the

same device. The DMAIW bits are valid only for DMA single address transfer; with DMA dual

address transfer, inter-area idle cycles are inserted.

Bits 4n + 2 to 4n—Area n (6 to 0) Inter-Cycle Idle Specification (AnlW2–AnlW0): These bits

specify the number of idle cycles between bus cycles to be inserted when switching from external

memory space area n (n = 6 to 0) to another space, or from a read access to a write access in the

same space.

DMAIW2/AnIW2 DMAIW1/AnIW1 DMAIW0/AnIW0 Inserted Idle Cycles

0 0 0 0

1 1

1 0 2

1 3

1 0 0 6

1 9

1 0 12

1 15 (Initial value)

Section 13 Bus State Controller (BSC)

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• Idle Insertion between Accesses

Following Cycle

Same Area Different Area

Same

Area

Different

Area

Read Write Read Write

Preceding

Cycle CPU DMA CPU DMA CPU DMA CPU DMA

MPX

Address

Output

MPX

Address

Output

Read M M M M M M M (1) M (1)

Write M M M M

*2 M

DMA read

(memory →

device)

M M M M M M — M (1)

DMA write

(device →

memory)

D D D D*1 D D D D — D (1)

“DMA” in the table indicates DMA single-address transfer. DMA dual transfer is in accordance with

the CPU.

Legend:

M, D: Idle wait always inserted by WCR1

(M(1): One cycle inserted in MPX access even if WCR1 is cleared to 0)

M: Idle cycles according to setting of AnIW2-AnIW0 (area 0 to area 6)

D: Idle cycles according to setting of DMAIW2-DMAIW0

Notes: When synchronous DRAM is used in RAS down mode, set bits DMAIW2-DMAIW0 to 000

and bits A3IW2-A3IW0 to 000.

1. Inserted when device is switched

2. On the MPX interface, a WCR1 idle wait may be inserted before an access (either read

or write) to the same area after a write access. The specific conditions for idle wait

insertion in accesses to the same area are shown below.

(a) Synchronous DRAM set to RAS down mode

(b) Synchronous DRAM accessed by on-chip DMAC

Apart from use under above conditions (a) and (b), an idle wait is also inserted between

an MPX interface write access and a following access to the same area. Even under

the above conditions, an idle wait may be inserted in a same-area access following an

interface write access, depending on the synchronous DRAM pipeline access situation.

An idle wait is not inserted when the WCR1 register setting is 0. The setting for the

number of idle state cycles inserted after a power-on reset is the default value of 15 (the

maximum value), so ensure that the optimum value is set.

Section 13 Bus State Controller (BSC)

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13.2.6 Wait Control Register 2 (WCR2)

Wait control register 2 (WCR2) is a 32-bit readable/writable register that specifies the number of

wait states to be inserted for each area. It also specifies the data access pitch when performing

burst memory access. This enables low-speed memory to be connected without using external

circuitry.

WCR2 is initialized to H'FFFEEFFF by a power-on reset, but is not initialized by a manual reset

or in standby mode.

Bit: 31 30 29 28 27 26 25 24

A6W2 A6W1 A6W0 A6B2 A6B1 A6B0 A5W2 A5W1

Initial value: 1 1 1 1 1 1 1 1

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit: 23 22 21 20 19 18 17 16

A5W0 A5B2 A5B1 A5B0 A4W2 A4W1 A4W0 —

Initial value: 1 1 1 1 1 1 1 0

R/W: R/W R/W R/W R/W R/W R/W R/W R

Bit: 15 14 13 12 11 10 9 8

A3W2 A3W1 A3W0 — A2W2 A2W1 A2W0 A1W2

Initial value: 1 1 1 0 1 1 1 1

R/W: R/W R/W R/W R R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

A1W1 A1W0 A0W2 A0W1 A0W0 A0B2 A0B1 A0B0

Initial value: 1 1 1 1 1 1 1 1

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

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Bits 31 to 29—Area 6 Wait Control (A6W2—A6W0): These bits specify the number of wait

states to be inserted for area 6. For details on MPX interface setting, see table 13.6, MPX Interface

is Selected (Areas 0 to 6).

Description

First Cycle

Bit 31: A6W2 Bit 30: A6W1 Bit 29: A6W0 Inserted Wait States RDY Pin

0 0 0 0 Ignored

1 1 Enabled

1 0 2 Enabled

1 3 Enabled

1 0 0 6 Enabled

1 9 Enabled

1 0 12 Enabled

1 15 (Initial value) Enabled

Bits 28 to 26—Area 6 Burst Pitch (A6B2–A6B0): These bits specify the number of wait states to

be inserted from the second data access onward in a burst transfer with the burst ROM interface

selected.

Description

Burst Cycle (Excluding First Cycle)

Bit 28: A6B2 Bit 27: A6B1 Bit 26: A6B0

Wait States Inserted from

Second Data Access

Onward RDY Pin

0 0 0 0 Ignored

1 1 Enabled

1 0 2 Enabled

1 3 Enabled

1 0 0 4 Enabled

1 5 Enabled

1 0 6 Enabled

1 7 (Initial value) Enabled

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Bits 25 to 23—Area 5 Wait Control (A5W2–A5W0): These bits specify the number of wait

states to be inserted for area 5. For details on MPX interface setting, see table 13.6, MPX Interface

is Selected (Areas 0 to 6).

Description

First Cycle

Bit 25: A5W2 Bit 24: A5W1 Bit 23: A5W0 Inserted Wait States RDY Pin

0 0 0 0 Ignored

1 1 Enabled

1 0 2 Enabled

1 3 Enabled

1 0 0 6 Enabled

1 9 Enabled

1 0 12 Enabled

1 15 (Initial value) Enabled

Bits 22 to 20—Area 5 Burst Pitch (A5B2–A5B0): These bits specify the number of wait states to

be inserted from the second data access onward in a burst transfer with the burst ROM interface

selected.

Description

Burst Cycle (Excluding First Cycle)

Bit 22: A5B2 Bit 21: A5B1 Bit 20: A5B0

Wait States Inserted from Second

Data Access Onward RDY Pin

0 0 0 0 Ignored

1 1 Enabled

1 0 2 Enabled

1 3 Enabled

1 0 0 4 Enabled

1 5 Enabled

1 0 6 Enabled

1 7 (Initial value) Enabled

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Bits 19 to 17—Area 4 Wait Control (A4W2–A4W0): These bits specify the number of wait

states to be inserted for area 4. For details on MPX interface setting, see table 13.6, MPX Interface

is Selected (Areas 0 to 6).

Description

Bit 19: A4W2 Bit 18: A4W1 Bit 17: A4W0 Inserted Wait States RDY Pin

0 0 0 0 Ignored

1 1 Enabled

1 0 2 Enabled

1 3 Enabled

1 0 0 6 Enabled

1 9 Enabled

1 0 12 Enabled

1 15 (Initial value) Enabled

Bits 16 and 12—Reserved: These bits are always read as 0, and should only be written with 0.

Bits 15 to 13—Area 3 Wait Control (A3W2–A3W0): These bits specify the number of wait

states to be inserted for area 3. External wait input is only enabled when SRAM interface or MPX

interface is used, and is ignored when DRAM or synchronous DRAM is used. For details on MPX

interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6).

• When SRAM Interface is Set

Description

Bit 15: A3W2 Bit 14: A3W1 Bit 13: A3W0 Inserted Wait States RDY Pin

0 0 0 0 Ignored

1 1 Enabled

1 0 2 Enabled

1 3 Enabled

1 0 0 6 Enabled

1 9 Enabled

1 0 12 Enabled

1 15 (Initial value) Enabled

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• When DRAM or Synchronous DRAM Interface is Set*1

Description

Bit 15: A3W2

Bit 14: A3W1

Bit 13: A3W0

DRAM CAS

Assertion Width

Synchronous DRAM

CAS Latency Cycles

0 0 0 1 Inhibited

1 2 1*2

1 0 3 2

1 4 3

1 0 0 7 4*2

1 10 5*2

1 0 13 Inhibited

1 16 Inhibited

Notes: 1. External wait input is always ignored.

2. Inhibited in RAS down mode.

Bits 11 to 9—Area 2 Wait Control (A2W2–A2W0): These bits specify the number of wait states

to be inserted for area 2. External wait input is only enabled when the SRAM interface or MPX

interface is used, and is ignored when DRAM or synchronous DRAM is used. For details on MPX

interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6).

• When SRAM Interface is Set

Description

Bit 11: A2W2 Bit 10: A2W1 Bit 9: A2W0 Inserted Wait States RDY Pin

0 0 0 0 Ignored

1 1 Enabled

1 0 2 Enabled

1 3 Enabled

1 0 0 6 Enabled

1 9 Enabled

1 0 12 Enabled

1 15 (Initial value) Enabled

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• When DRAM or Synchronous DRAM Interface is Set*1

Description

Bit 11: A2W2

Bit 10: A2W1

Bit 9: A2W0

DRAM CAS

Assertion Width

Synchronous DRAM

CAS Latency Cycles

0 0 0 1 Inhibited

1 2 1*2

1 0 3 2

1 4 3

1 0 0 7 4*2

1 10 5*2

1 0 13 Inhibited

1 16 Inhibited

Notes: 1. External wait input is always ignored.

2. RAS down mode is prohibited.

Bits 8 to 6—Area 1 Wait Control (A1W2–A1W0): These bits specify the number of wait states

to be inserted for area 1. For details on MPX interface setting, see table 13.6, MPX Interface is

Selected (Areas 0 to 6).

Description

Bit 8: A1W2 Bit 7: A1W1 Bit 6: A1W0 Inserted Wait States RDY Pin

0 0 0 0 Ignored

1 1 Enabled

1 0 2 Enabled

1 3 Enabled

1 0 0 6 Enabled

1 9 Enabled

1 0 12 Enabled

1 15 (Initial value) Enabled

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Bits 5 to 3—Area 0 Wait Control (A0W2 to A0W0): These bits specify the number of wait

states to be inserted for area 0. For details on MPX interface setting, see table 13.6, MPX Interface

is Selected (Areas 0 to 6).

Description

First Cycle

Bit 5: A0W2 Bit 4: A0W1 Bit 3: A0W0 Inserted Wait States RDY Pin

0 0 0 0 Ignored

1 1 Enabled

1 0 2 Enabled

1 3 Enabled

1 0 0 6 Enabled

1 9 Enabled

1 0 12 Enabled

1 15 (Initial value) Enabled

Bits 2 to 0—Area 0 Burst Pitch (A0B2–A0B0): These bits specify the number of wait states to

be inserted afterwards the second data access in a burst transfer with the burst ROM interface

selected.

Description

Burst Cycle (Excluding First Cycle)

Bit 2: A0B2 Bit 1: A0B1 Bit 0: A0B0

Wait States Inserted from

Second Data Access Onward RDY Pin

0 0 0 0 Ignored

1 1 Enabled

1 0 2 Enabled

1 3 Enabled

1 0 0 4 Enabled

1 5 Enabled

1 0 6 Enabled

1 7 (Initial value) Enabled

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Table 13.6 MPX Interface is Selected (Areas 0 to 6)

Description

Inserted Wait States

1st Data

AnW2

AnW1

AnW0 Read Write

2nd Data

Onward RDY Pin

0 0 0 1 0 0 Enabled

1 1 Enabled

1 0 2 2 Enabled

1 3 3 Enabled

1 0 0 1 0 1 Enabled

1 1 Enabled

1 0 2 2 Enabled

1 3 3 Enabled

Note: n = 6 to 0

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13.2.7 Wait Control Register 3 (WCR3)

Wait control register 3 (WCR3) is a 32-bit readable/writable register that specifies the cycles

inserted in the setup time from the address until assertion of the write strobe, and the data hold

time from negation of the strobe, for each area. This enables low-speed memory to be connected

without using external circuitry.

WCR3 is initialized to H'07777777 by a power-on reset, but is not initialized by a manual reset or

in standby mode.

Bit: 31 30 29 28 27 26 25 24

— — — — — A6S0 A6H1 A6H0

Initial value: 0 0 0 0 0 1 1 1

R/W: R R R R R R/W R/W R/W

Bit: 23 22 21 20 19 18 17 16

— A5S0 A5H1 A5H0 A4RDH*A4S0 A4H1 A4H0

Initial value: 0 1 1 1 0 1 1 1

R/W: R R/W R/W R/W R/W* R/W R/W R/W

Bit: 15 14 13 12 11 10 9 8

— A3S0 A3H1 A3H0 — A2S0 A2H1 A2H0

Initial value: 0 1 1 1 0 1 1 1

R/W: R R/W R/W R/W R R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

A1RDH*A1S0 A1H1 A0H0 — A0S0 A0H1 A0H0

Initial value: 0 1 1 1 0 1 1 1

R/W: R/W* R/W R/W R/W R R/W R/W R/W

Note: * SH7750R only

Bits 31 to 27, 23, 19*, 15, 11, 7*, and 3—Reserved: These bits are always read as 0, and should

only be written with 0.

Note: * SH7750R only

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Bit 4n + 2—Area n (6 to 0) Write Strobe Setup Time (AnS0): Specifies the number of cycles

inserted in the setup time from the address until assertion of the read/write strobe. Valid only for

SRAM interface, byte control SRAM interface, and burst ROM interface.

Bit 4n + 2: AnS0 Waits Inserted in Setup

0 0

1 1 (Initial value)

Note: n = 6 to 0

Bits 4n + 1 and 4n—Area n (6 to 0) Data Hold Time (AnH1, AnH0): When writing, these bits

specify the number of cycles to be inserted in the hold time from negation of the write strobe.

When reading, they specify the number of cycles to be inserted in the hold time from the data

sampling timing. Valid only for SRAM interface, byte control SRAM interface, and burst ROM

interface.

Bit 4n + 1: AnH1 Bit 4n: AnH0 Waits Inserted in Hold

0 0 0

1 1

1 0 2

1 3 (Initial value)

Note: n = 6 to 0

Bits 4n+3⎯Area n (4 or 1) Read-Strobe Negate Timing (AnRDH) (Setting Only Possible in

the SH7750R): When reading, these bits specify the timing for the negation of read strobe. These

bits should be cleared to 0 when a byte control SRAM setting is made. Valid only for the SRAM

interface.

Bit 4n + 3: AnRDH Read-Strobe Negate Timing

0 Read strobe negated after hold wait cycles specified by WCR3.AnH bits

(Initial value)

1 Read strobe negated according to data sampling timing

Note: n = 4 or 1

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13.2.8 Memory Control Register (MCR)

The memory control register (MCR) is a 32-bit readable/writable register that specifies RAS and

CAS timing and burst control for DRAM and synchronous DRAM (areas 2 and 3), address

multiplexing, and refresh control. This enables DRAM and synchronous DRAM to be connected

without using external circuitry.

MCR is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in

standby mode. Bits RASD, MRSET, TRC2–0, TPC2–0, RCD1–0, TRWL2–0, TRAS2–0, BE,

SZ1–0, AMXEXT, AMX2–0, and EDOMODE are written in the initialization following a power-

on reset, and should not be modified subsequently. When writing to bits RFSH and RMODE, the

same values should be written to the other bits so that they remain unchanged. When using DRAM

or synchronous DRAM, areas 2 and 3 should not be accessed until register initialization is

completed.

Bit: 31 30 29 28 27 26 25 24

RASD MRSET TRC2 TRC1 TRC0 — — —

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R R R

Bit: 23 22 21 20 19 18 17 16

TCAS — TPC2 TPC1 TPC0 — RCD1 RCD0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R R/W R/W R/W R R/W R/W

Bit: 15 14 13 12 11 10 9 8

TRWL2 TRWL1 TRWL0 TRAS2 TRAS1 TRAS0 BE SZ1

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

SZ0 AMXEXT AMX2 AMX1 AMX0 RFSH RMODE EDO

MODE

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

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Bit 31—RAS Down (RASD): Sets RAS down mode. When DRAM/RAS down mode is used, set

BE to 1. Do not set RAS down mode in slave mode or partial-sharing mode, or when areas 2 and 3

are both designated as synchronous DRAM interface. See Connecting a 128-Mbit/256-Mbit

Synchronous DRAM with 64-bit Bus Width (SH7750R Only): in section 13.3.5, Synchronous

DRAM Interface.

Bit 31: RASD Description

0 Auto-precharge mode (Initial value)

1 RAS down mode

Note: When synchronous DRAM is used in RAS down mode, set bits DMAIW2–DMAIW0 to 000

and bits A3IW2–A3IW0 to 000.

Bit 30—Mode Register Set (MRSET): Set when a synchronous DRAM mode register setting is

used. See Power-On Sequence in section 13.3.5, Synchronous DRAM Interface.

Bit 30: MRSET Description

0 All-bank precharge (Initial value)

1 Mode register setting

Bits 29 to 27—RAS Precharge Time at End of Refresh (TRC2–TRC0)

(Synchronous DRAM: auto- and self-refresh both enabled; DRAM: auto- and self-refresh both

enabled)

Note: For setting values and the period during which no command is issued, see 22.3.3, Bus

Timing.

Bit 29: TRC2

Bit 28: TRC1

Bit 27: TRC0

RAS Precharge Interval

Immediately after Refresh

0 0 0 0 (Initial value)

1 3

1 0 6

1 9

1 0 0 12

1 15

1 0 18

1 21

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Bits 26 to 24, 22, and 18—Reserved: These bits are always read as 0, and should only be written

with 0.

Bit 23—CAS Negation Period (TCAS): This bit is valid only when DRAM interface is set.

Bit 23: TCAS CAS Negation Period

0 1 (Initial value)

1 2

Bits 21 to 19—RAS Precharge Period (TPC2–TPC0): When the DRAM interface is selected,

these bits specify the minimum number of cycles until RAS is asserted again after being negated.

When the synchronous DRAM interface is selected, these bits specify the minimum number of

cycles until the next bank active command after precharging.

Note: For setting values and the period during which no command is issued, see 22.3.3, Bus

Timing.

RAS Precharge Interval

Bit 21: TPC2 Bit 20: TPC1 Bit 19: TPC0 DRAM Synchronous DRAM

0 0 0 0 1* (Initial value)

1 1 2

1 0 2 3

1 3 4*

1 0 0 4 5*

1 5 6*

1 0 6 7*

1 7 8*

Note: * Inhibited in RAS down mode.

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Bits 17 and 16—RAS-CAS Delay (RCD1, RCD0): When the DRAM interface is set, these bits

set the RAS-CAS assertion delay time. When the synchronous DRAM interface is set, these bits

set the bank active-read/write command delay time.

Description

Bit 17: RCD1 Bit 16: RCD0 DRAM Synchronous DRAM

0 0 2 cycles Reserved (Setting prohibited)

1 3 cycles 2 cycles

1 0 4 cycles 3 cycles

1 5 cycles 4 cycles*

Note: * Inhibited in RAS down mode.

Bits 15 to 13—Write Precharge Delay (TRWL2–TRWL0): These bits set the synchronous

DRAM write precharge delay time. In auto-precharge mode, they specify the time until the next

bank active command is issued after a write cycle. After a write cycle, the next active command is

not issued for a period equivalent to the setting values of the TPC[2:0] and TRWL[2:0] bits.*

After a write cycle, the next precharge command is not issued for a period of TRWL. This setting

is valid only when synchronous DRAM interface is set.

Note: * For setting values and the period during which no command is issued, see 22.3.3, Bus

Timing.

Bit 15: TRWL2 Bit 14: TRWL1 Bit 13: TRWL0 Write Precharge ACT Delay Time

0 0 0 1 (Initial value)

1 2

1 0 3*

1 4*

1 0 0 5*

1 Reserved (Setting prohibited)

1 0 Reserved (Setting prohibited)

1 Reserved (Setting prohibited)

Note: * Inhibited in RAS down mode.

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Bits 12 to 10—CAS-Before-RAS Refresh RAS Assertion Period (TRAS2–TRAS0): When the

DRAM interface is set, these bits set the RAS assertion period in CAS-before-RAS refreshing.

When the synchronous DRAM interface is set, the bank active command is not issued for the

period set by the TRC[2:0]* and TRAS[2:0] bits after an auto-refresh command is issued.

Note: For setting values and the period during which no command is issued, see 22.3.3, Bus

Timing.

Bit 12: TRAS2 Bit 11: TRAS1 Bit 10: TRAS0

RAS/DRAM

Assertion Period

Command

Interval after

Synchronous

DRAM Refresh

0 0 0 2 4 + TRC

(Initial value)

1 3 5 + TRC

1 0 4 6 + TRC

1 5 7 + TRC

1 0 0 6 8 + TRC

1 7 9 + TRC

1 0 8 10 + TRC

1 9 11 + TRC

Note: TRC (Bits 29 to 27): RAS precharge interval at end of refresh.

Bit 9—Burst Enable (BE): Specifies whether burst access is performed on DRAM interface. In

synchronous DRAM access, burst access is always performed regardless of the specification of

this bit. The DRAM transfer mode depends on EDOMODE.

BE EDOMODE 8/16/32/64-Bit Transfer 32-Byte Transfer

0 0 Single Single

1 Setting prohibited Setting prohibited

1 0 Single/fast page* Fast page

1 EDO EDO

Note: * In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit

bus.

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Bits 8 and 7—Memory Data Size (SZ1, SZ0): These bits specify the bus width of DRAM and

synchronous DRAM. This setting has priority over the BCR2 register setting.

Description

Bit 8: SZ1 Bit 7: SZ0 DRAM SDRAM

0 0 64 bits 64 bits

1 Reserved (Setting prohibited) Reserved (Setting prohibited)

1 0 16 bits Reserved (Setting prohibited)

1 32 bits 32 bits

Bits 6 to 3—Address Multiplexing (AMXEXT, AMX2–AMX0): These bits specify address

multiplexing for DRAM and synchronous DRAM. The address shift value is different for the

DRAM interface and the synchronous DRAM interface.

• For DRAM Interface:

Description

Bit 6:

AMXEXT

Bit 5:

AMX2

Bit 4:

AMX1

Bit 3:

AMX0 DRAM

0* 0 0 0 8-bit column address product

(Initial value)

1 9-bit column address product

1 0 10-bit column address product

1 11-bit column address product

1 0 0 12-bit column address product

1 Reserved (Setting prohibited)

1 0 Reserved (Setting prohibited)

1 Reserved (Setting prohibited)

Note: * When the DRAM interface is used, clear the AMXEXT bit to 0.

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• For Synchronous DRAM Interface:

AMX AMXEXT SZ Example of Synchronous DRAM BANK*4

0 0 64 (16M: 512K × 16 bits × 2) × 4 a[22]*1

32 (16M: 512K × 16 bits × 2) × 2 a[21]*1

1 64 (16M: 512K × 16 bits × 2) × 4 a[21]*1

32 (16M: 512K × 16 bits × 2) × 2 a[20]*1

1 0 64 (16M: 1M × 8 bits × 2) × 8 a[23]*1

32 (16M: 1M × 8 bits × 2) × 4 a[22]*1

1 64 (16M: 1M × 8 bits × 2) × 8 a[22]*1

32 (16M: 1M × 8 bits × 2) × 4 a[21]*1

2 — 64 (64M: 1M × 16 bits × 4) × 4 a[24:23]*1

32 (64M: 1M × 16 bits × 4) × 2 a[23:22]*1

3 — 64 (64M: 2M × 8 bits × 4) × 8 a[25:24]*1

32 (64M: 2M × 8 bits × 4) × 4 a[24:23]*1

4 — 64 (64M: 512K × 32 bits × 4) × 2 a[23:22]*1

32 (64M: 512K × 32 bits × 4) × 1 a[22:21]*1

5 — 64 (64M: 1M × 32 bits × 2) × 2 a[23]*1

32 (64M: 1M × 32 bits × 2) × 1 a[22]*1

6 0 64 (128M: 4M × 8 bits × 4) × 8*2 a[26:25]*1

1 64 (256M: 4M × 16 bits × 4) × 4*2 a[26:25]*1

0 32 (128M: 4M × 8 bits × 4) × 4*3 a[25:24]*1

1 32 (256M: 4M × 16 bits × 4) × 2*3 a[25:24]*1

7 — 64 (16M: 256K × 32 bits × 2) × 2 a[21]*1

32 (16M: 256K × 32 bits × 2) × 1 a[20]*1

Notes: 1. a[*]: Not an address pin but an external address

2. Can only be set in the SH7750R.

3. Can only be set in the SH7750S/SH7750R (Setting prohibited in the SH7750).

4. For details on address multiplexing, refer to appendix F, Synchronous DRAM Address

Multiplexing Tables.

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Bit 2—Refresh Control (RFSH): Specifies refresh control. Selects whether refreshing is

performed for DRAM and synchronous DRAM. When the refresh function is not used, the refresh

request cycle generation timer can be used as an interval timer.

Bit 2: RFSH Description

0 Refreshing is not performed (Initial value)

1 Refreshing is performed

Bit 1—Refresh Mode (RMODE): Specifies whether normal refreshing or self-refreshing is

performed when the RFSH bit is set to 1. When the RFSH bit is 1 and this bit is cleared to 0, CAS-

before-RAS refreshing or auto-refreshing is performed for DRAM and synchronous DRAM, using

the cycle set by refresh-related registers RTCNT, RTCOR, and RTCSR. If a refresh request is

issued during an external bus cycle, the refresh cycle is executed when the bus cycle ends. When

the RFSH bit is 1 and this bit is set to 1, the self-refresh state is set for DRAM and synchronous

DRAM, after waiting for the end of any currently executing external bus cycle. All refresh

requests for memory in the self-refresh state are ignored.

Bit 1: RMODE Description

0 CAS-before-RAS refreshing is performed (when RFSH = 1) (Initial value)

1 Self-refreshing is performed (when RFSH = 1)

Bit 0—EDO Mode (EDOMODE): Used to specify the data sampling timing for data reads when

using EDO mode DRAM interface. The setting of this bit does not affect the operation timing of

memory other than DRAM. Set this bit to 1 only when DRAM is used.

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13.2.9 PCMCIA Control Register (PCR)

The PCMCIA control register (PCR) is a 16-bit readable/writable register that specifies the OE

and WE signal assertion/negation timing for the PCMCIA interface connected to areas 5 and 6.

The OE and WE signal assertion width is set by the wait control bits in the WCR2 register. For

details of access to PCMCIA, see section 13.3.7, PCMCIA Interface.

PCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in

standby mode.

Bit: 15 14 13 12 11 10 9 8

A5PCW1 A5PCW0 A6PCW1 A6PCW0 A5TED2 A5TED1 A5TED0 A6TED2

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

A6TED1 A6TED0 A5TEH2 A5TEH1 A5TEH0 A6TEH2 A6TEH1 A6TEH0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 and 14—PCMCIA Wait (A5PCW1, A5PCW0): These bits specify the number of waits

to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The

setting of these bits is selected when the PCMCIA interface access TC bit is cleared to 0.

Bit 15: A5PCW1 Bit 14: A5PCW0 Waits Inserted

0 0 0 (Initial value)

1 15

1 0 30

1 50

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Bits 13 and 12—PCMCIA Wait (A6PCW1, A6PCW0): These bits specify the number of waits

to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The

setting of these bits is selected when the PCMCIA interface access TC bit is set to 1.

Bit 13: A6PCW1 Bit 12: A6PCW0 Waits Inserted

0 0 0 (Initial value)

1 15

1 0 30

1 50

Bits 11 to 9—Address-OE/WE Assertion Delay (A5TED2–A5TED0): These bits set the delay

time from address output to OE/WE assertion on the connected PCMCIA interface. The setting of

these bits is selected when the PCMCIA interface access TC bit is cleared to 0.

Bit 11: A5TED2 Bit 10: A5TED1 Bit 9: A5TED0 Waits Inserted

0 0 0 0 (Initial value)

1 1

1 0 2

1 3

1 0 0 6

1 9

1 0 12

1 15

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Bits 8 to 6—Address-OE/WE Assertion Delay (A6TED2–A6TED0): These bits set the delay

time from address output to OE/WE assertion on the connected PCMCIA interface. The setting of

these bits is selected when the PCMCIA interface access TC bit is set to 1.

Bit 8: A6TED2 Bit 7: A6TED1 Bit 6: A6TED0 Waits Inserted

0 0 0 0 (Initial value)

1 1

1 0 2

1 3

1 0 0 6

1 9

1 0 12

1 15

Bits 5 to 3—OE/WE Negation-Address Delay (A5TEH2–A5TEH0): These bits set the address

hold delay time from OE/WE negation in a write on the connected PCMCIA interface or in an I/O

card read. The setting of these bits is selected when the PCMCIA interface access TC bit is cleared

to 0.

Bit 5: A5TEH2 Bit 4: A5TEH1 Bit 3: A5TEH0 Waits Inserted

0 0 0 0 (Initial value)

1 1

1 0 2

1 3

1 0 0 6

1 9

1 0 12

1 15

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Bits 2 to 0—OE/WE Negation-Address Delay (A6TEH2–A6TEH0): These bits set the address

hold delay time from OE/WE negation in a write on the connected PCMCIA interface or in an I/O

card read. In the case of a memory card read, the address hold delay time from the data sampling

timing is set. The setting of these bits is selected when the PCMCIA interface access TC bit is set

to 1.

Bit 2: A6TEH2 Bit 1: A6TEH1 Bit 0: A6TEH0 Waits Inserted

0 0 0 0 (Initial value)

1 1

1 0 2

1 3

1 0 0 6

1 9

1 0 12

1 15

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13.2.10 Synchronous DRAM Mode Register (SDMR)

The synchronous DRAM mode register (SDMR) is a write-only virtual 16-bit register that is

written to via the synchronous DRAM address bus, and sets the mode of the area 2 and area 3

synchronous DRAM.

Settings for the SDMR register must be made before accessing synchronous DRAM.

Bit: 15 14 13 12 11 10 9 8

Initial value: — — — — — — — —

R/W: W W W W W W W W

Bit: 7 6 5 4 3 2 1 0

Initial value: — — — — — — — —

R/W: W W W W W W W W

Since the address bus, not the data bus, is used to write to the synchronous DRAM mode register,

if the value to be set is “X” and the SDMR register address is “Y”, value “X” is written to the

synchronous DRAM mode register by performing a write to address X + Y. When the

synchronous DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to

A2 of this LSI, and A1 of the synchronous DRAM is connected to A3 of this LSI, the value

actually written to the synchronous DRAM is the value of “X” shifted 2 bits to the right.

For example, to write H'0230 to the area 2 SDMR register, arbitrary data is written to address

H'FF900000 (address “Y”) + H'08C0 (value “X”) (= H'FF9008C0). As a result, H'0230 is written

to the SDMR register. The range of value “X” is H'0000 to H'0FFC.

Similarly, to write H'0230 to the area 3 SDMR register, arbitrary data is written to address

H'FF940000 (address “Y”) + H'08C0 (value “X”) (= H'FF9408C0). As a result, H'0230 is written

to the SDMR register. The range of value “X” is H'0000 to H'0FFC.

The lower 16 bits of the address are set in the synchronous DRAM mode register.

When the bus width is 32 bits, the burst length is 4* and 8. When the bus width is 64 bits, the burst

length is fixed at 4. When a setting is made in SDMR, byte-size writes are performed at the

following addresses.

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 414 of 1074

REJ09B0366-0700

Bus Width Burst Length CAS Latency Area 2 Area 3

32 4* 1

H'FF900048

H'FF900088

H'FF9000C8

H'FF940048

H'FF940088

H'FF9400C8

32 8 1

H'FF90004C

H'FF90008C

H'FF9000CC

H'FF94004C

H'FF94008C

H'FF9400CC

64 4 1

H'FF900090

H'FF900110

H'FF900190

H'FF940090

H'FF940110

H'FF940190

For a 32-bit bus:

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address 0 0 0 0 0 0 0 0 0 LMO

DE2

LMO

DE1

LMO

DE0

WT BL2 BL1 BL0

←⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯→

10 bits set in case of 32-bit bus width

For a 64-bit bus:

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address 0 0 0 0 0 0 0 0 LMO

DE2

LMO

DE1

LMO

DE0

WT BL2 BL1 BL0

←⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯→

10 bits set in case of 64-bit bus width

LMODE: CAS latency

BL: Burst length

WT: Wrap type (0: Sequential)

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 415 of 1074

REJ09B0366-0700

BL LMODE

000: Reserved 000: Reserved

001: Reserved 001: 1

010: 4 010: 2

011: 8 011: 3

100: Reserved 100: Reserved

101: Reserved 101: Reserved

110: Reserved 110: Reserved

111: Reserved 111: Reserved

Note: * SH7750R only.

13.2.11 Refresh Timer Control/Status Register (RTCSR)

The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that

specifies the refresh cycle and whether interrupts are to be generated.

RTCSR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in

standby mode.

Bit: 15 14 13 12 11 10 9 8

— — — — — — — —

Initial value: 0 0 0 0 0 0 0 0

R/W: — — — — — — — —

Bit: 7 6 5 4 3 2 1 0

CMF CMIE CKS2 CKS1 CKS0 OVF OVIE LMTS

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 to 8—Reserved: These bits are always read as 0. For the write values, see section 13.2.15,

Notes on Accessing Refresh Control Registers.

Section 13 Bus State Controller (BSC)

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Bit 7—Compare-Match Flag (CMF): Status flag that indicates a match between the refresh

timer counter (RTCNT) and refresh time constant register (RTCOR) values.

Bit 7: CMF Description

0 RTCNT and RTCOR values do not match (Initial value)

[Clearing condition]

When 0 is written to CMF

1 RTCNT and RTCOR values match

[Setting condition]

When RTCNT = RTCOR*

Note: * If 1 is written, the original value is retained.

Bit 6—Compare-Match Interrupt Enable (CMIE): Controls generation or suppression of an

interrupt request when the CMF flag is set to 1 in RTCSR. Do not set this bit to 1 when CAS-

before-RAS refreshing or auto-refreshing is used.

Bit 6: CMIE Description

0 Interrupt requests initiated by CMF are disabled (Initial value)

1 Interrupt requests initiated by CMF are enabled

Bits 5 to 3—Clock Select Bits (CKS2–CKS0): These bits select the input clock for RTCNT. The

base clock is the external bus clock (CKIO). The RTCNT count clock is obtained by scaling CKIO

by the specified factor.

Bit 5: CKS2 Bit 4: CKS1 Bit 3: CKS0 Description

0 0 0 Clock input disabled (Initial value)

1 Bus clock (CKIO)/4

1 0 CKIO/16

1 CKIO/64

1 0 0 CKIO/256

1 CKIO/1024

1 0 CKIO/2048

1 CKIO/4096

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 417 of 1074

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Bit 2—Refresh Count Overflow Flag (OVF): Status flag that indicates that the number of

refresh requests indicated by the refresh count register (RFCR) has exceeded the number specified

by the LMTS bit in RTCSR.

Bit 2: OVF Description

0 RFCR has not overflowed the count limit indicated by LMTS (Initial value)

[Clearing condition]

When 0 is written to OVF

1 RFCR has overflowed the count limit indicated by LMTS

[Setting condition]

When RFCR overflows the count limit set by LMTS*

Note: * If 1 is written, the original value is retained.

Bit 1—Refresh Count Overflow Interrupt Enable (OVIE): Controls generation or suppression

of an interrupt request when the OVF flag is set to 1 in RTCSR.

Bit 1: OVIE Description

0 Interrupt requests initiated by OVF are disabled (Initial value)

1 Interrupt requests initiated by OVF are enabled

Bit 0—Refresh Count Overflow Limit Select (LMTS): Specifies the count limit to be compared

with the refresh count indicated by the refresh count register (RFCR). If the RFCR register value

exceeds the value specified by LMTS, the OVF flag is set.

Bit 0: LMTS Description

0 Count limit is 1024 (Initial value)

1 Count limit is 512

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 418 of 1074

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13.2.12 Refresh Timer Counter (RTCNT)

The refresh timer counter (RTCNT) is an 8-bit readable/writable counter that is incremented by

the input clock (selected by bits CKS2–CKS0 in the RTCSR register). When the RTCNT counter

value matches the RTCOR register value, the CMF bit is set in the RTCSR register and the

RTCNT counter is cleared.

RTCNT is initialized to H'0000 by a power-on reset, but continues to count when a manual reset is

performed. In standby mode, RTCNT is not initialized, and retains its contents.

Bit: 15 14 13 12 11 10 9 8

— — — — — — — —

Initial value: 0 0 0 0 0 0 0 0

R/W: — — — — — — — —

Bit: 7 6 5 4 3 2 1 0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 419 of 1074

REJ09B0366-0700

13.2.13 Refresh Time Constant Register (RTCOR)

The refresh time constant register (RTCOR) is a readable/writable register that specifies the upper

limit of the RTCNT counter. The RTCOR register and RTCNT counter values (lower 8 bits) are

constantly compared, and when they match the CMF bit is set in the RTCSR register and the

RTCNT counter is cleared to 0. If the refresh bit (RFSH) has been set to 1 in the memory control

cycle is generated when the CMF bit is set.

RTCOR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents,

in a manual reset and in standby mode.

Bit: 15 14 13 12 11 10 9 8

— — — — — — — —

Initial value: 0 0 0 0 0 0 0 0

R/W: — — — — — — — —

Bit: 7 6 5 4 3 2 1 0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 420 of 1074

REJ09B0366-0700

13.2.14 Refresh Count Register (RFCR)

The refresh count register (RFCR) is a 10-bit readable/writable counter that counts the number of

refreshes by being incremented each time the RTCOR register and RTCNT counter values match.

If the RFCR register value exceeds the count limit specified by the LMTS bit in the RTCSR

RFCR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents, in

a manual reset and in standby mode.

Bit: 15 14 13 12 11 10 9 8

— — — — — —

Initial value: 0 0 0 0 0 0 0 0

R/W: — — — — — — R/W R/W

Bit: 7 6 5 4 3 2 1 0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

13.2.15 Notes on Accessing Refresh Control Registers

When the refresh timer control/status register (RTCSR), refresh timer counter (RTCNT), refresh

time constant register (RTCOR), and refresh count register (RFCR) are written to, a special code

is added to the data to prevent inadvertent rewriting in the event of program runaway, etc. The

following procedures should be used for read/write operations.

Writing to RTCSR, RTCNT, RTCOR, and RFCR: A word transfer instruction must always be

used when writing to RTCSR, RTCNT, RTCOR, or RFCR. A write cannot be performed with a

byte transfer instruction.

When writing to RTCSR, RTCNT, or RTCOR, set B'10100101 in the upper byte and the write

data in the lower byte, as shown in figure 13.5. When writing to RFCR, set B'101001 in the 6 bits

starting from the MSB in the upper byte, and the write data in the remaining bits.

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 421 of 1074

REJ09B0366-0700

15 14 13 12 11 10 9 8

10 100 101

76543210

15 14 13 12 11 10 9 8

10 100 1

76543210

Write data

RTCSR,

RTCNT,

RTCOR

RFCR

Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR

Reading RTCSR, RTCNT, RTCOR, and RFCR: A 16-bit access must always be used when

reading RTCSR, RTCNT, RTCOR, or RFCR. Undefined bits are read as 0.

13.3 Operation

13.3.1 Endian/Access Size and Data Alignment

This LSI supports both big-endian mode, in which the most significant byte (MSByte) is at the 0

address end in a string of byte data, and little-endian mode, in which the least significant byte

(LSByte) is at the 0 address end. The mode is set by means of the MD5 external pin in a power-on

reset by the RESET pin, big-endian mode being set if the MD5 pin is low, and little-endian mode

if it is high.

A data bus width of 8, 16, 32, or 64 bits can be selected for normal memory, 16, 32, or 64 bits for

DRAM, 32 or 64 bits for synchronous DRAM, and 8 or 16 bits for the PCMCIA interface. Data

alignment is carried out according to the data bus width and endian mode of each device. If the

data bus width is smaller than the access size, a number of bus cycles will be generated

automatically until the access size is reached. In this case, address incrementing is performed

automatically according to the bus width as access is performed. For example, if longword access

is performed in an 8-bit bus width area using the SRAM interface, four accesses are executed, with

the address automatically incremented by 1 each time. In 32-byte transfer, a total of 32 bytes of

data are transferred consecutively according to the set bus width. The first access is performed on

the data for which there was an access request, and the remaining accesses are performed on 32-

byte boundary data using wraparound. Bus release or refresh operations are not performed

between these transfers. Data alignment and data length conversion between the different

interfaces is performed automatically. Quadword access is used only in transfer by the DMAC.

The relationship between the endian mode, device data length, and access unit, is shown in tables

13.7 to 13.14.

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 422 of 1074

REJ09B0366-0700

Data Configuration

MSB LSB

Byte Data 7 to 0

MSB LSB

Word Data 15 to 8 Data 7 to 0

MSB LSB

Longword Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0

MSB LSB

Quadword Data

63 to 56

Data

55 to 48

Data

47 to 40

Data

39 to 32

Data

31 to 24

Data

23 to 16

Data

15 to 8

Data

7 to 0

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 423 of 1074

REJ09B0366-0700

Table 13.7 (1) 64-Bit External Device/Big-Endian Access and Data Alignment

Operation Data Bus

Access

Size Address

No. D63–56 D55–48 D47–40 D39–32 D31–24 D23–16 D15–8 D7–0

Byte 8n 1 Data

7–0

— — — — — — —

8n + 1 1 — Data

7–0

— — — — — —

8n + 2 1 — — Data

7–0

— — — — —

8n + 3 1 — — — Data

7–0

— — — —

8n + 4 1 — — — — Data

7–0

— — —

8n + 5 1 — — — — — Data

7–0

— —

8n + 6 1 — — — — — — Data

7–0

—

8n + 7 1 — — — — — — — Data

7–0

Word 8n 1 Data

15–8

Data

7–0

— — — — — —

8n + 2 1 — — Data

15–8

Data

7–0

— — — —

8n + 4 1 — — — — Data

15–8

Data

7–0

— —

8n + 6 1 — — — — — — Data

15–8

Data

7–0

Long-

word

8n 1 Data

31–24

Data

23–16

Data

15–8

Data

7–0

— — — —

8n + 4 1 — — — — Data

31–24

Data

23–16

Data

15–8

Data

7–0

Quad-

word

8n 1 Data

63–56

Data

55–48

Data

47–40

Data

39–32

Data

31–24

Data

23–16

Data

15–8

Data

7–0

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 424 of 1074

REJ09B0366-0700

Table 13.7 (2) 64-Bit External Device/Big-Endian Access and Data Alignment

Operation Strobe Signals

Access

Size Address

No.

WE7,

CAS7,

DQM7

WE6,

CAS6,

DQM6

WE5,

CAS5,

DQM5

WE4,

CAS4,

DQM4

WE3,

CAS3,

DQM3

WE2,

CAS2,

DQM2

WE1,

CAS1,

DQM1

WE0,

CAS0,

DQM0

Byte 8n 1 Asserted

8n + 1 1 Asserted

8n + 2 1 Asserted

8n + 3 1 Asserted

8n + 4 1 Asserted

8n + 5 1 Asserted

8n + 6 1 Asserted

8n + 7 1 Asserted

Word 8n 1 Asserted Asserted

8n + 2 1 Asserted Asserted

8n + 4 1 Asserted Asserted

8n + 6 1 Asserted Asserted

8n 1 Asserted Asserted Asserted Asserted Long-

word 8n + 4 1 Asserted Asserted Asserted Asserted

Quad-

word

8n 1 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 425 of 1074

REJ09B0366-0700

Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment

Operation Data Bus Strobe Signals

Access

Size Address

No.

D31–D24

D23–D16

D15–D8

D7–D0

WE3,

CAS3,

DQM3

WE2,

CAS2,

DQM2

WE1,

CAS1,

DQM1

WE0,

CAS0,

DQM0

Byte 4n 1 Data

7–0

— — — Asserted

4n + 1 1 — Data

7–0

— — Asserted

4n + 2 1 — — Data

7–0

— Asserted

4n + 3 1 — — — Data

7–0

Asserted

Word 4n 1 Data

15–8

Data

7–0

— — Asserted Asserted

4n + 2 1 — — Data

15–8

Data

7–0

Asserted Asserted

Long-

word

4n 1 Data

31–24

Data

23–16

Data

15–8

Data

7–0

Asserted Asserted Asserted Asserted

Quad-

word

8n 1 Data

63–56

Data

55–48

Data

47–40

Data

39–32

Asserted Asserted Asserted Asserted

8n + 4 2 Data

31–24

Data

23–16

Data

15–8

Data

7–0

Asserted Asserted Asserted Asserted

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 426 of 1074

REJ09B0366-0700

Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment

Operation Data Bus Strobe Signals

Access

Size Address

No.

D31–D24

D23–D16

D15–D8

D7–D0

WE3,

CAS3,

DQM3

WE2,

CAS2,

DQM2

WE1,

CAS1,

DQM1

WE0,

CAS0,

DQM0

Byte 2n 1 — — Data

7–0

— Asserted

2n + 1 1 — — — Data

7–0

Asserted

Word 2n 1 — — Data

15–8

Data

7–0

Asserted Asserted

Long-

word

4n 1 — — Data

31–24

Data

23–16

Asserted Asserted

4n + 2 2 — — Data

15–8

Data

7–0

Asserted Asserted

Quad-

word

8n 1 — — Data

63–56

Data

55–48

Asserted Asserted

8n + 2 2 — — Data

47–40

Data

39–32

Asserted Asserted

8n + 4 3 — — Data

31–24

Data

23–16

Asserted Asserted

8n + 6 4 — — Data

15–8

Data

7–0

Asserted Asserted

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 427 of 1074

REJ09B0366-0700

Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment

Operation Data Bus Strobe Signals

Access

Size Address

No.

D31–D24

D23–D16

D15–D8

D7–D0

WE3,

CAS3,

DQM3

WE2,

CAS2,

DQM2

WE1,

CAS1,

DQM1

WE0,

CAS0,

DQM0

Byte n 1 — — — Data

7–0

Asserted

Word 2n 1 — — — Data

15–8

Asserted

2n + 1 2 — — — Data

7–0

Asserted

Long-

word

4n 1 — — — Data

31–24

Asserted

4n + 1 2 — — — Data

23–16

Asserted

4n + 2 3 — — — Data

15–8

Asserted

4n + 3 4 — — — Data

7–0

Asserted

Quad-

word

8n 1 — — — Data

63–56

Asserted

8n + 1 2 — — — Data

55–48

Asserted

8n + 2 3 — — — Data

47–40

Asserted

8n + 3 4 — — — Data

39–32

Asserted

8n + 4 5 — — — Data

31–24

Asserted

8n + 5 6 — — — Data

23–16

Asserted

8n + 6 7 — — — Data

15–8

Asserted

8n + 7 8 — — — Data

7–0

Asserted

Section 13 Bus State Controller (BSC)

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Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment

Operation Data Bus

Access

Size Address No. D63–56 D55–48 D47–40 D39–32 D31–24 D23–16 D15–8 D7–0

Byte 8n 1 — — — — — — — Data

7–0

8n + 1 1 — — — — — — Data

7–0

—

8n + 2 1 — — — — — Data

7–0

— —

8n + 3 1 — — — — Data

7–0

— — —

8n + 4 1 — — — Data

7–0

— — — —

8n + 5 1 — — Data

7–0

— — — — —

8n + 6 1 — Data

7–0

— — — — — —

8n + 7 1 Data

7–0

— — — — — — —

Word 8n 1 — — — — — — Data

15–8

Data

7–0

8n + 2 1 — — Data

15–8

Data

7–0

— —

8n + 4 1 — — Data

15–8

Data

7–0

— — — —

8n + 6 1 Data

15–8

Data

7–0

— — — — — —

Long-

word

8n 1 — — — — Data

31–24

Data

23–16

Data

15–8

Data

7–0

8n + 4 1 Data

31–24

Data

23–16

Data

15–8

Data

7–0

— — — —

Quad-

word

8n 1 Data

63–56

Data

55–48

Data

47–40

Data

39–32

Data

31–24

Data

23–16

Data

15–8

Data

7–0

Section 13 Bus State Controller (BSC)

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Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment

Operation Strobe Signals

Access

Size Address

No.

WE7,

CAS7,

DQM7

WE6,

CAS6,

DQM6

WE5,

CAS5,

DQM5

WE4,

CAS4,

DQM4

WE3,

CAS3,

DQM3

WE2,

CAS2,

DQM2

WE1,

CAS1,

DQM1

WE0,

CAS0,

DQM0

Byte 8n 1 Asserted

8n + 1 1 Asserted

8n + 2 1 Asserted

8n + 3 1 Asserted

8n + 4 1 Asserted

8n + 5 1 Asserted

8n + 6 1 Asserted

8n + 7 1 Asserted

Word 8n 1 Asserted Asserted

8n + 2 1 Asserted Asserted

8n + 4 1 Asserted Asserted

8n + 6 1 Asserted Asserted

8n 1 Asserted Asserted Asserted Asserted Long-

word 8n + 4 1 Asserted Asserted Asserted Asserted

Quad-

word

8n 1 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 430 of 1074

REJ09B0366-0700

Table 13.12 32-Bit External Device/Little-Endian Access and Data Alignment

Operation Data Bus Strobe Signals

Access

Size Address

No.

D31–D24

D23–D16

D15–D8

D7–D0

WE3,

CAS3,

DQM3

WE2,

CAS2,

DQM2

WE1,

CAS1,

DQM1

WE0,

CAS0,

DQM0

Byte 4n 1 — — Data

7–0

Asserted

4n + 1 1 — — Data

7–0

— Asserted

4n + 2 1 — Data

7–0

— — Asserted

4n + 3 1 Data

7–0

— — — Asserted

Word 4n 1 — — Data

15–8

Data

7–0

Asserted Asserted

4n + 2 1 Data

15–8

Data

7–0

— — Asserted Asserted

Long-

word

4n 1 Data

31–24

Data

23–16

Data

15–8

Data

7–0

Asserted Asserted Asserted Asserted

Quad-

word

8n 1 Data

31–24

Data

23–16

Data

15–8

Data

7–0

Asserted Asserted Asserted Asserted

8n + 4 2 Data

63–56

Data

55–48

Data

47–40

Data

39–32

Asserted Asserted Asserted Asserted

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 431 of 1074

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Table 13.13 16-Bit External Device/Little-Endian Access and Data Alignment

Operation Data Bus Strobe Signals

Access

Size Address

No.

D31–D24

D23–D16

D15–D8

D7–D0

WE3,

CAS3,

DQM3

WE2,

CAS2,

DQM2

WE1,

CAS1,

DQM1

WE0,

CAS0,

DQM0

Byte 2n 1 — — — Data

7–0

Asserted

2n + 1 1 — — Data

7–0

— Asserted

Word 2n 1 — — Data

15–8

Data

7–0

Asserted Asserted

Long-

word

4n 1 — — Data

15–8

Data

7–0

Asserted Asserted

4n + 2 2 — — Data

31–24

Data

23–16

Asserted Asserted

Quad-

word

8n 1 — — Data

15–8

Data

7–0

Asserted Asserted

8n + 2 2 — — Data

31–24

Data

23–16

Asserted Asserted

8n + 4 3 — — Data

47–40

Data

39–32

Asserted Asserted

8n + 6 4 — — Data

63–56

Data

55–48

Asserted Asserted

Section 13 Bus State Controller (BSC)

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Table 13.14 8-Bit External Device/Little-Endian Access and Data Alignment

Operation Data Bus Strobe Signals

Access

Size Address

No.

D31–D24

D23–D16

D15–D8

D7–D0

WE3,

CAS3,

DQM3

WE2,

CAS2,

DQM2

WE1,

CAS1,

DQM1

WE0,

CAS0,

DQM0

Byte n 1 — — — Data

7–0

Asserted

Word 2n 1 — — — Data

7–0

Asserted

2n + 1 2 — — — Data

15–8

Asserted

Long-

word

4n 1 — — — Data

7–0

Asserted

4n + 1 2 — — — Data

15–8

Asserted

4n + 2 3 — — — Data

23–16

Asserted

4n + 3 4 — — — Data

31–24

Asserted

Quad-

word

8n 1 — — — Data

7–0

Asserted

8n + 1 2 — — — Data

15–8

Asserted

8n + 2 3 — — — Data

23–16

Asserted

8n + 3 4 — — — Data

31–24

Asserted

8n + 4 5 — — — Data

39–32

Asserted

8n + 5 6 — — — Data

47–40

Asserted

8n + 6 7 — — — Data

55–48

Asserted

8n + 7 8 — — — Data

63–56

Asserted

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 433 of 1074

REJ09B0366-0700

13.3.2 Areas

Area 0: For area 0, external address bits A28 to A26 are 000.

SRAM, MPX, and burst ROM can be set to this area.

A bus width of 8, 16, 32, or 64 bits can be selected in a power-on reset by means of external pins

MD4 and MD3. For details, see Memory Bus Width in section 13.1.5, Overview of Areas.

When area 0 is accessed, the CS0 signal is asserted. In addition, the RD signal, which can be used

as OE, and write control signals WE0 to WE7, are asserted.

As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A0W2 to A0W0

in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means

of the external wait pin (RDY).

When the burst ROM interface is used, the number of burst cycle transfer states is selected in the

range 2 to 9 according to the number of waits.

The read/write strobe signal address and the CS setup/hold time can be set, respectively, to 0 or 1

and to 0 to 3 cycles using the A0S0, A0H1, and A0H0 bits in the WCR3 register.

Area 1: For area 1, external address bits A28 to A26 are 001.

SRAM, MPX and byte control SRAM can be set to this area.

A bus width of 8, 16, 32, or 64 bits can be selected with bits A1SZ1 and A1SZ0 in the BCR2

A1SZ1 and A1SZ0 in the BCR2 register. When byte control SRAM interface is set, select a bus

width of 16, 32, or 64 bits.

When area 1 is accessed, the CS1 signal is asserted. In addition, the RD signal, which can be used

as OE, and write control signals WE0 to WE7, are asserted.

As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A1W2 to A1W0

in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means

of the external wait pin (RDY).

The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1

and 0–3 cycles, respectively, by means of bit A1S0 and bits A1H1 and A1H0 in the WCR3

Section 13 Bus State Controller (BSC)

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REJ09B0366-0700

Area 2: For area 2, external address bits A28 to A26 are 010.

SRAM, MPX, DRAM, and synchronous DRAM can be set to this area.

When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A2SZ1

and A2SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 or 64 bits should

be selected with bits A2SZ1 and A2SZ0 in the BCR2 register. When synchronous DRAM

interface is set, select 32 or 64 bits with the SZ bits in the MCR register. When DRAM is

connected to area 2, select a bus width of 16 or 32 bits with the SZ bits in MCR. For details, see

Memory Bus Width in section 13.1.5, Overview of Areas.

When area 2 is accessed, the CS2 signal is asserted.

When SRAM interface is set, the RD signal, which can be used as OE, and write control signals

WE0 to WE7, are asserted.

As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A2W2 to A2W0

in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means

of the external wait pin (RDY).

The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1

and 0–3 cycles, respectively, by means of bit A2S0 and bits A2H1 and A2H0 in the WCR3

When synchronous DRAM interface is set, the RAS and CAS signals, RD/WR signal, and byte

control signals DQM0 to DQM7 are asserted, and address multiplexing is performed. RAS, CAS,

and data timing control, and address multiplexing control, can be set using the MCR register.

When DRAM is connected, the RAS2 signal, CAS4 to CAS7 signals, and RD/WR signal are

asserted, and address multiplexing is performed. RAS2, CAS, and data timing control, and address

multiplexing control, can be set using the MCR register.

Area 3: For area 3, external address bits A28 to A26 are 011.

SRAM, MPX, DRAM, and synchronous DRAM can be set to this area.

When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A3SZ1

and A3SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 or 64 bits should

be selected with bits A3SZ1 and A3SZ0 in the BCR2 register. When DRAM interface is set, 16,

32, or 64 bits can be selected with the SZ bits in the MCR register. When synchronous DRAM

interface is set, select 32 or 64 bits with the SZ bits in MCR. For details, see Memory Bus Width

in section 13.1.5, Overview of Areas.

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 435 of 1074

REJ09B0366-0700

When area 3 is accessed, the CS3 signal is asserted.

When SRAM interface is set, the RD signal, which can be used as OE, and write control signals

WE0 to WE7, are asserted.

As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A3W2 to A3W0

in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means

of the external wait pin (RDY).

The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1

and 0–3 cycles, respectively, by means of bit A3S0 and bits A3H1 and A3H0 in the WCR3

When synchronous DRAM interface is set, the RAS and CAS signals, RD/WR signal, and byte

control signals DQM0 to DQM7 are asserted, and address multiplexing is performed. When

DRAM interface is set, the RAS signal, CAS0 to CAS7 signals, and RD/WR signal are asserted,

and address multiplexing is performed. RAS, CAS, and data timing control, and address

multiplexing control, can be set using the MCR register.

Area 4: For area 4, external address bits A28 to A26 are 100.

SRAM, MPX, and byte control SRAM can be set to this area.

A bus width of 8, 16, 32, or 64 bits can be selected with bits A4SZ1 and A4SZ0 in the BCR2

A4SZ1 and A4SZ0 in the BCR2 register. When byte control SRAM interface is set, select a bus

width of 16, 32, or 64 bits. For details, see Memory Bus Width in section 13.1.5, Overview of

Areas.

When area 4 is accessed, the CS4 signal is asserted, and the RD signal, which can be used as OE,

and write control signals WE0 to WE7, are also asserted.

As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A4W2 to A4W0

in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means

of the external wait pin (RDY).

The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1

and 0–3 cycles, respectively, by means of bit A4S0 and bits A4H1 and A4H0 in the WCR3

Section 13 Bus State Controller (BSC)

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REJ09B0366-0700

Area 5: For area 5, external address bits A28 to A26 are 101.

SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area.

When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A5SZ1

and A5SZ0 in the BCR2 register. When burst ROM interface is set, a bus width of 8, 16 or 32 bits

can be selected with bits A5SZ1 and A5SZ0 in BCR2. When MPX interface is set, a bus width of

32 or 64 bits should be selected with bits A5SZ1 and A5SZ0 in BCR2. When a PCMCIA interface

is set, either 8 or 16 bits should be selected with bits A5SZ1 and A5SZ0 in BCR2. For details, see

Memory Bus Width in section 13.1.5, Overview of Areas.

When area 5 set is accessed with SRAM interface set, the CS5 signal is asserted. In addition, the

RD signal, which can be used as OE, and write control signals WE0 to WE7, are asserted. When a

PCMCIA interface is connected, the CE1A and CE2A signals, the RD signal, which can be used

as OE, and the WE1, WE2, WE3, and WE7 signals, which can be used as WE, ICIORD,

ICIOWR, and REG, respectively, are asserted.

As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A5W2 to A5W0

in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means

of the external wait pin (RDY).

When the burst function is used, the number of burst cycle transfer states is determined in the

range 2 to 9 according to the number of waits.

The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1

and 0–3 cycles, respectively, by means of bit A5S0 and bits A5H1 and A5H0 in the WCR3

When a PCMCIA interface is used, the address/CE1A/CE2A setup and hold times with respect to

the read/write strobe signals can be set in the range of 0 to 15 cycles with bits AnTED1 and

AnTED0, and bits AnTEH1 and AnTEH0, in the PCR register. In addition, the number of wait

cycles can be set in the range 0 to 50 with bits AnPCW1 and AnPCW0. The number of waits set in

PCR is added to the number of waits set in WCR2.

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 437 of 1074

REJ09B0366-0700

Area 6: For area 6, external address bits A28 to A26 are 110.

SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area.

When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A6SZ1

and A6SZ0 in the BCR2 register. When burst ROM interface is set, a bus width of 8, 16 or 32 bits

can be selected with bits A6SZ1 and A6SZ0 in BCR2. When MPX interface is set, a bus width of

32 or 64 bits should be selected with bits A6SZ1 and A6SZ0 in BCR2. When a PCMCIA interface

is set, either 8 or 16 bits should be selected with bits A6SZ1 and A6SZ0 in BCR2. For details, see

Memory Bus Width in section 13.1.5, Overview of Areas.

When area 6 is accessed with SRAM interface set, the CS6 signal is asserted. In addition, the RD

signal, which can be used as OE, and write control signals WE0 to WE7, are asserted. When a

PCMCIA interface is set, the CE1B and CE2B signals, the RD signal, which can be used as OE,

and the WE1, WE2, WE3, and WE7 signals, which can be used as WE, ICIORD, ICIOWR, and

REG, respectively, are asserted.

As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A6W2 to A6W0

in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means

of the external wait pin (RDY).

When the burst function is used, the number of burst cycle transfer states is determined in the

range 2 to 9 according to the number of waits.

The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1

and 0–3 cycles, respectively, by means of bit A6S0 and bits A6H1 and A6H0 in the WCR3

When a PCMCIA interface is used, the address/CE1B/CE2B setup and hold times with respect to

the read/write strobe signals can be set in the range of 0 to 15 cycles with bits AnTED1 and

AnTED0, and bits AnTEH1 and AnTEH0, in the PCR register. In addition, the number of wait

cycles can be set in the range 0 to 50 with bits AnPCW1 and AnPCW0. The number of waits set in

PCR is added to the number of waits set in WCR2.

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 438 of 1074

REJ09B0366-0700

13.3.3 SRAM Interface

Basic Timing: The SRAM interface of this LSI uses strobe signal output in consideration of the

fact that mainly SRAM will be connected. Figure 13.6 shows the basic timing of normal space

accesses. A no-wait normal access is completed in two cycles. The BS signal is asserted for one

cycle to indicate the start of a bus cycle. The CSn signal is asserted on the T1 rising edge, and

negated on the next T2 clock rising edge. Therefore, there is no negation period in case of access

at minimum pitch.

There is no access size specification when reading. The correct access address is output to the

address pins (A[25:0]), but since there is no access size specification, 32 bits are always read in

the case of a 32-bit device, and 16 bits in the case of a 16-bit device. When writing, only the WE

signal for the byte to be written is asserted. For details, see section 13.3.1, Endian/Access Size and

Data Alignment.

In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.

The first access is performed on the data for which there was an access request, and the remaining

accesses are performed in wrap around mode on the data at the 32-byte boundary. The bus is not

released during this transfer.

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 439 of 1074

REJ09B0366-0700

CKIO

A25–A0

CSn

RD/WR

D63–D0

(read)

WEn

D63–D0

(write)

RDY

DACKn

(SA: IO ← memory)

DACKn

(SA: IO → memory)

DACKn

(DA)

Legend:

SA: Single address DMA

DA: Dual address DMA

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.6 Basic Timing of SRAM Interface

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 440 of 1074

REJ09B0366-0700

Figures 13.7 to 13.10 show examples of connection to 64-, 32-, 16-, and 8-bit data width SRAM.

A19–A3

CSn

D63–D56

WE7

SH7750, SH7750S, SH7750R

128K

8-bit

SRAM

A16–A0

I/O7–I/O0

A16–A0

I/O7–I/O0

A16–A0

I/O7–I/O0

D55–D48

WE6

D47–D40

WE5

D39–D32

WE4

D31–D24

WE3

D23–D16

WE2

D15–D8

WE1

D7–D0

WE0

A16–A0

I/O7–I/O0

A16–A0

I/O7–I/O0

A16–A0

I/O7–I/O0

A16–A0

I/O7–I/O0

A16–A0

I/O7–I/O0

Figure 13.7 Example of 64-Bit Data Width SRAM Connection

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 441 of 1074

REJ09B0366-0700

••••••••••••••••••••

A16

I/O7

I/O0

••••••••

••••

A18

CSn

D31

D24

WE3

D23

D16

WE2

D15

WE1

WE0

SH7750, SH7750S, SH7750R

128K × 8-bit

SRAM

••••

A16

I/O7

I/O0

••••

••••••••

••••

A16

I/O7

I/O0

••••••••

••••

A16

I/O7

I/O0

••••

••••••••

Figure 13.8 Example of 32-Bit Data Width SRAM Connection

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 442 of 1074

REJ09B0366-0700

A16

I/O7

I/O0

A17

CSn

D15

WE1

WE0

SH7750, SH7750S, SH7750R

128K × 8-bit

SRAM

A16

I/O7

I/O0

••••

••••••••

••••

Figure 13.9 Example of 16-Bit Data Width SRAM Connection

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 443 of 1074

REJ09B0366-0700

A16

CSn

WE0

SH7750, SH7750S, SH7750R

128K × 8-bit

SRAM

A16

I/O7

I/O0

••••

Figure 13.10 Example of 8-Bit Data Width SRAM Connection

Wait State Control: Wait state insertion on the SRAM interface can be controlled by the WCR2

settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a

software wait is inserted in accordance with that specification. For details, see section 13.2.6, Wait

Control Register 2 (WCR2).

The specified number of Tw cycles are inserted as wait cycles using the SRAM interface wait

timing shown in figure 13.11.

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 444 of 1074

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CKIO

A25–A0

CSn

RD/WR

D63–D0

(read)

WEn

D63–D0

(write)

Tw T2

RDY

DACKn

(SA: IO ← memory)

DACKn

(SA: IO → memory)

DACKn

(DA)

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.11 SRAM Interface Wait Timing (Software Wait Only)

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 445 of 1074

REJ09B0366-0700

When software wait insertion is specified by WCR2, the external wait input RDY signal is also

sampled. RDY signal sampling is shown in figure 13.12. A single-cycle wait is specified as a

software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore,

the RDY signal has no effect if asserted in the T1 cycle or the first Tw cycle. The RDY signal is

sampled on the rising edge of the clock.

T1 Tw Twe T2

CKIO

A25–A0

CSn

RD/WR

(read)

D63–D0

(read)

WEn

(write)

D63–D0

(write)

RDY

DACKn

(SA: IO → memory)

DACKn

(SA: IO ← memory)

DACKn

(DA)

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.12 SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal)

Section 13 Bus State Controller (BSC)

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Read-Strobe Negate Timing (Setting Only Possible in the SH7750R): When the SRAM

interface is used, timing for the negation of the strobe during read operations can be specified by

the setting of the A1RDH and A4RDH bits of the WCR3 register. For information about this

setting, see the description of the WCR3 register. When a byte control SRAM setting is made,

AnRDH should be cleared to 0.

TS1

CKIO

A25−A0

CSn

RD/WR

D63−D0

T1 Tw Tw TwTw T2 TH1 TH2

TS1: Setup wait

WCR3.AnS

(0 to 1)

Tw: Access wait

WCR2.AnW

(0 to 15)

TH1, TH2: Hold wait

WCR3.AnH

(0 to 3)

Note: * When AnRDH is set to 1

Figure 13.13 SRAM Interface Read-Strobe Negate Timing (AnS = 1, AnW = 4, AnH = 2)

Section 13 Bus State Controller (BSC)

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13.3.4 DRAM Interface

Direct Connection of DRAM: When the memory type bits (DRAMTP2–0) in BCR1 are set to

100, area 3 becomes DRAM space; when set to 101, area 2 and area 3 become DRAM space. The

DRAM interface function can then be used to connect DRAM to this LSI.

16, 32, or 64 bits can be selected as the interface data width for area 3 when bits DRAMTP2–0 are

set to 100, and 16 or 32 bits can be used for both area 2 and area 3 when bits DRAMTP2–0 are set

to 101.

2-CAS 16-bit DRAMs can be connected, since CAS is used to control byte access.

Signals used for connection when DRAM is connected to area 3 are RAS, CAS0 to CAS7, and

RD/WR. CAS2 to CAS7 are not used when the data width is 16 bits. When DRAM is connected

to areas 2 and 3, the signals for area 2 DRAM connection are RAS2, CAS4 to CAS7, and RD/WR,

and those for area 3 DRAM connection are RAS, CAS0 to CAS3, and RD/WR.

In addition to normal read and write access modes, fast page mode is supported for burst access.

For DRAM connected to areas 2 and 3, EDO mode, which enables the DRAM access time to be

increased, is supported.

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 448 of 1074

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A12–A3

RAS

CS3

RD/WR

D63–D48

WE7

WE6

SH7750, SH7750S, SH7750R

1M × 16-bit

DRAM

A9–A0

RAS

I/O15–I/O0

UCAS

LCAS

D15–D0

WE1

WE0

A9–A0

RAS

I/O15–I/O0

UCAS

LCAS

A9–A0

RAS

I/O15–I/O0

UCAS

LCAS

A9–A0

RAS

I/O15–I/O0

UCAS

LCAS

D31–D16

WE3

WE2

D47–D32

WE5

WE4

Figure 13.14 Example of DRAM Connection (64-Bit Data Width, Area 3)

Section 13 Bus State Controller (BSC)

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A10

RAS

CS3

RD/WR

D31

D16

CAS3

CAS2

D15

CAS1

CAS0

SH7750, SH7750S, SH7750R

256K × 16-bit

DRAM

RAS

I/O15

I/O0

UCAS

LCAS

RAS

I/O15

I/O0

UCAS

LCAS

••••

Figure 13.15 Example of DRAM Connection (32-Bit Data Width, Area 3)

Section 13 Bus State Controller (BSC)

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CS3

CS2

RAS

RAS2

RD/WR

D15

CAS1

CAS0

CAS5

CAS4

SH7750, SH7750S, SH7750R

256K × 16-bit

DRAM

RAS

I/O15

I/O0

UCAS

LCAS

RAS

I/O15

I/O0

UCAS

LCAS

Area 3

Area 2

••••

Figure 13.16 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3)

Section 13 Bus State Controller (BSC)

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Address Multiplexing: When area 2 or area 3 is designated as DRAM space, address

multiplexing is always performed in accesses to DRAM. This enables DRAM, which requires row

and column address multiplexing, to be connected to this LSI without using an external address

multiplexer circuit. Any of the five multiplexing methods shown below can be selected, by setting

bits AMXEXT and AMX2–0 in MCR for area 2 or 3 DRAM. The relationship between the

AMXEXT and AMX2–0 bits and address multiplexing is shown in table 13.15. The address

output pins subject to address multiplexing are A17 to A1. The address signals output by pins A25

to A18 are undefined.

Table 13.15 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing

Setting

External Address Pins

AMXEXT AMX2 AMX1 AMX0

Number

of Column

Address

Bits Output Timing A1–A13 A14 A15 A16 A17

0 0 0 0 8 bits Column address A1–A13 A14 A15 A16 A17

Row address A9–A21 A22 A23 A24 A25

1 9 bits Column address A1–A13 A14 A15 A16 A17

Row address A10–A22 A23 A24 A25 A17

1 0 10 bits Column address A1–A13 A14 A15 A16 A17

Row address A11–A23 A24 A25 A16 A17

1 11 bits Column address A1–A13 A14 A15 A16 A17

Row address A12–A24 A25 A15 A16 A17

1 0 0 12 bits Column address A1–A13 A14 A15 A16 A17

Row address A13–A25 A14 A15 A16 A17

Other settings Reserved — — — — — —

Section 13 Bus State Controller (BSC)

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Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in

figure 13.17. Tpc is the precharge cycle, Tr the RAS assert cycle, Tc1 the CAS assert cycle, and

Tc2 the read data latch cycle.

Tr1 Tr2 Tc1 Tc2 Tpc

Row

CKIO

A25–A0

CSn

RD/WR

RAS

D63–D0

(read)

CAS

D63–D0

(write)

DACKn

(SA: IO → memory)

DACKn

(SA: IO ← memory)

Column

Legend:

IO: DACK device

SA: Single address DMA transfer

DA: Dual address DMA transfer

The DACK is in the high-active setting

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.17 Basic DRAM Access Timing

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Wait State Control: As the clock frequency increases, it becomes impossible to complete all

states in one cycle as in basic access. Therefore, provision is made for state extension by using the

setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in

figure 13.18. Additional Tpc cycles (cycles used to secure the RAS precharge time) can be

inserted by means of the TPC bit in MCR, giving from 1 to 7 cycles. The number of cycles from

RAS assertion to CAS assertion can be set to between 2 and 5 by inserting Trw cycles by means of

the RCD bit in MCR. Also, the number of cycles from CAS assertion to the end of the access can

be varied between 1 and 16 according to the setting of A2W2 to A2W0 or A3W2 to A3W0 in

WCR2.

Tr1

CKIO

A25–A0

CSn

RD/WR

RAS

D63

–

(read)

CAS

D63

–

(write)

Tr2 Trw Tc1 Tcw Tc2 Tpc Tpc

DACKn

(SA: IO ← memory)

DACKn

(SA: IO → memory)

ColumnRow

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.18 DRAM Wait State Timing

Section 13 Bus State Controller (BSC)

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Burst Access: In addition to the normal DRAM access mode in which a row address is output in

each data access, a fast page mode is also provided for the case where consecutive accesses are

made to the same row. This mode allows fast access to data by outputting the row address only

once, then changing only the column address for each subsequent access. Normal access or burst

access using fast page mode can be selected by means of the burst enable (BE) bit in MCR. The

timing for burst access using fast page mode is shown in figure 13.19.

If the access size exceeds the set bus width, burst access is performed. In a 32-byte burst transfer

(cache fill), the first access comprises a longword that includes the data requiring access. The

remaining accesses are performed on 32-byte boundary data that includes the relevant data. In

burst transfer (cache write-back), wraparound writing is performed for 32-byte data.

Tr2 Tc1 Tc2 Tc1 Tc2 Tc2Tr1

rc1c2c3c4

Tc1 TpcTc2Tc1

CKIO

A25–A0

CSn

RD/WR

RAS

CAS

D63–D0

(read)

D63–D0

(write)

DACKn

(SA: IO → memory)

DACKn

(SA: IO ← memory)

d3d2

d2d1 d3 d4

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.19 DRAM Burst Access Timing

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 455 of 1074

REJ09B0366-0700

EDO Mode: With DRAM, in addition to the mode in which data is output to the data bus only

while the CAS signal is asserted in a data read cycle, an EDO (extended data out) mode is also

provided in which, once the CAS signal is asserted while the RAS signal is asserted, even if the

CAS signal is negated, data is output to the data bus until the CAS signal is next asserted. In this

LSI, the EDO mode bit (EDOMODE) in MCR enables either normal access/burst access using fast

page mode, or EDO mode normal access/burst access, to be selected for DRAM. When EDO

mode is set, BE must be set to 1 in MCR. EDO mode normal access is shown in figure 13.20, and

burst access in figure 13.21.

CAS Negation Period: The CAS negation period can be set to 1 or 2 by means of the TCAS bit in

the MCR register.

Tr1

Row

Tc1 Tc2 Tce TpcTr2

CKIO

A25–A0

CSn

RD/WR

RAS

CASn

D63–D0

(read)

DACKn

(SA: IO ← memory)

Column

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.20 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1)

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 456 of 1074

REJ09B0366-0700

Tr1

rc1c2c3 c4

Tc1 Tc2 Tc1 Tc2 Tc1 Tc1Tr2 Tc2 Tc2 TpcTce

CKIO

A25–A0

CSn

RD/WR

RAS

CAS

D63–D0

(read)

DACKn

(SA: IO ← memory)

d4d3d2d1

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.21 Burst Access Timing in DRAM EDO Mode

RAS Down Mode: This LSI has an address comparator for detecting row address matches in burst

mode. By using this address comparator, and also setting RAS down mode specification bit RASD

to 1, it is possible to select RAS down mode, in which RAS remains asserted after the end of an

access. When RAS down mode is used, if the refresh cycle is longer than the maximum DRAM

RAS assert time, the refresh cycle must be decreased to or below the maximum value of tRAS.

RAS down mode can only be used when DRAM is connected in area 3.

In RAS down mode, in the event of an access to an address with a different row address, an access

to a different area, a refresh request, or a bus request, RAS is negated and the necessary operation

is performed. When DRAM access is resumed after this, since this is the start of RAS down mode,

the operation starts with row address output. Timing charts are shown in figures 13.22 (1) to (4).

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 457 of 1074

REJ09B0366-0700

Tr1 Tr2 Tc1 Tc2 Tc1 Tc1Tpc

rc1c2c3c4

Tc2 Tc2Tc1Tc2

CKIO

A25–A0

CSn

RD/WR

RAS

CAS

D63–D0

(read)

D63–D0

(write)

DACKn

(SA: IO → memory)

DACKn

(SA: IO ← memory)

d4d3d2d1

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.22 (1) DRAM Burst Bus Cycle, RAS Down Mode Start

(Fast Page Mode, RCD = 0, AnW = 0)

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 458 of 1074

REJ09B0366-0700

Tnop Tc1 Tc2 Tc1 Tc2 Tc1 Tc1

Tc2 Tc2

CKIO

A25–A0

CSn

RD/WR

RAS

CASn

D63–D0

(read)

D63–D0

(write)

DACKn

(SA: IO → memory)

DACKn

(SA: IO ← memory)

c0 c1 c2 c3

d0 d1 d2 d3

d1 d2 d3

End of RAS down mode

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.22 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation

(Fast Page Mode, RCD = 0, AnW = 0)

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 459 of 1074

REJ09B0366-0700

Tpc Tr2 Tc1 Tc2 Tc1 Tc2 Tc2Tr1

rc1c2c3 c4

Tc1 Tc1 TceTc2

CKIO

A25–A0

CSn

RD/WR

RAS

CAS

D63–D0

(read)

DACKn

(SA: IO ← memory)

d4d3d2d1

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.22 (3) DRAM Burst Bus Cycle, RAS Down Mode Start

(EDO Mode, RCD = 0, AnW = 0)

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 460 of 1074

REJ09B0366-0700

Tc2 Tc1 Tc2 Tc1 Tc2 Tc2Tc1

c1 c2 c3 c4

Tc1 Tce

CKIO

A25–A0

CSn

RD/WR

RAS

CAS

D63–D0

(read)

DACKn

(SA: IO ← memory)

d4d3d2d1

End of RAS down mode

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.22 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation

(EDO Mode, RCD = 0, AnW = 0)

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 461 of 1074

REJ09B0366-0700

Refresh Timing: The bus state controller includes a function for controlling DRAM refreshing.

Distributed refreshing using a CAS-before-RAS cycle can be performed for DRAM by clearing

the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. Self-refresh mode is also supported.

• CAS-before-RAS Refresh

When CAS-before-RAS refresh cycles are executed, refreshing is performed at intervals

determined by the input clock selected by bits CKS2–CKS0 in RTCSR, and the value set in

RTCOR. The value of bits CKS2–CKS0 in RTCOR should be set so as to satisfy the

specification for the DRAM refresh interval. First make the settings for RTCOR, RTCNT, and

the RMODE and RFSH bits in MCR, then make the CKS2–CKS0 setting. When the clock is

selected by CKS2–CKS0, RTCNT starts counting up from the value at that time. The RTCNT

value is constantly compared with the RTCOR value, and if the two values are the same, a

refresh request is generated and the BACK pin goes high. If this LSI's external bus can be

used, CAS-before-RAS refreshing is performed. At the same time, RTCNT is cleared to zero

and the count-up is restarted. Figure 13.23 shows the operation of CAS-before-RAS

refreshing.

RTCNT value

RTCOR-1

H'00000000

RTCSR.CKS2–0

External bus

Refresh request cleared

by start of refresh cycle

= 000 ≠ 000

RTCNT cleared to 0 when

RTCNT = RTCOR

CAS-before-RAS refresh cycle

Time

Refresh

request

Figure 13.23 CAS-Before-RAS Refresh Operation

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 462 of 1074

REJ09B0366-0700

Figure 13.24 shows the timing of the CAS-before-RAS refresh cycle.

The number of RAS assert cycles in the refresh cycle is specified by bits TRAS2–TRAS0 in

MCR. The specification of the RAS precharge time in the refresh cycle is determined by the

setting of bits TRC2–TRC0 in MCR.

TRr2 TRr3 TRr4 TRr5 TrcTRr1 Trc Trc

CKIO

A25–A0

CSn

RD/WR

RAS

CAS

D63–D0

Figure 13.24 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1)

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 463 of 1074

REJ09B0366-0700

• Self-Refresh

The self-refreshing supported by this LSI is shown in figure 13.25.

After the self-refresh is cleared, the refresh controller immediately generates a refresh request.

The RAS precharge time immediately after the end of the self-refreshing can be set by bits

TRC2–TRC0 in MCR.

CAS-before-RAS refreshing is performed in normal operation, in sleep mode, and in the case

of a manual reset.

Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the

case of a manual reset.

When the bus has been released in response to a bus arbitration request, or when a transition is

made to standby mode, signals generally become high-impedance, but whether the RAS and

CAS signals become high-impedance or continue to be output can be controlled by the

HIZCNT bit in BCR1. This enables the DRAM to be kept in the self-refreshing state.

As the DRAM CAS signal is multiplexed with WEn for normal memory (SRAM, etc.), access

to memory that uses the WEn signals must be disabled during self-refreshing.

• Relationship between Refresh Requests and Bus Cycle Requests

If a refresh request is generated during execution of a bus cycle, execution of the refresh is

deferred until the bus cycle is completed. Refresh operations are deferred during multiple bus

cycles generated because the data bus width is smaller than the access size (for example, when

performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as

a cache fill or write-back, and also between read and write cycles during execution of a TAS

instruction, and between read and write cycles when DMAC dual address transfer is executed.

If a refresh request occurs when the bus has been released by the bus arbiter, refresh execution

is deferred until the bus is acquired. If a match between RTCNT and RTCOR occurs while a

refresh is waiting to be executed, so that a new refresh request is generated, the previous

refresh request is eliminated. In order for refreshing to be performed normally, care must be

taken to ensure that no bus cycle or bus mastership occurs that is longer than the refresh

interval. When a refresh request is generated, the BACK pin is negated (driven high).

Therefore, normal refreshing can be performed by having the BACK pin monitored by a bus

master other than this LSI requesting the bus, or the bus arbiter, and returning the bus to this

LSI.

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 464 of 1074

REJ09B0366-0700

TRr2 TRr3 TRr4 TRr5 TrcTRr1 Trc Trc

CKIO

A25–A0

CSn

RD/WR

RAS

CAS

D63–D0

Figure 13.25 DRAM Self-Refresh Cycle Timing

Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time

(at least 100 μs or 200 μs) during which no access can be performed be provided, followed by at

least the prescribed number (usually 8) of dummy CAS-before-RAS refresh cycles. As the bus

state controller does not perform any special operations for a power-on reset, the necessary power-

on sequence must be carried out by the initialization program executed after a power-on reset.

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 465 of 1074

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13.3.5 Synchronous DRAM Interface

Connection of Synchronous DRAM: Since synchronous DRAM can be selected by the CS

signal, it can be connected to physical space areas 2 and 3 using RAS and other control signals in

common. If the memory type bits (DRAMTP2–0) in BCR1 are set to 010, area 2 is normal

memory space and area 3 is synchronous DRAM space; if set to 011, areas 2 and 3 are both

synchronous DRAM space.

With this LSI, burst read/burst write mode is supported as the synchronous DRAM operating

mode. The data bus width is 32 or 64 bits, and the SZ size bits in MCR must be set to 00 or 11.

The burst enable bit (BE) in MCR is ignored, a 32-byte burst transfer is performed in a cache

fill/copy-back cycle, and in a write-through area write or a non-cacheable area read/write, 32-byte

data is read even in a single read in order to access synchronous DRAM with a burst read/write

access. 32-byte data transfer is also performed in a single write, but DQMn is not asserted when

unnecessary data is transferred. For details on the burst length, see section 13.2.10, Synchronous

DRAM Mode Register (SDMR), and Power-On Sequence in section 13.3.5, Synchronous DRAM

Interface. The SH7750R Group supports burst read and burst write operations with a burst length

of 4 as a synchronous DRAM operating mode when using a 32-bit data bus. The burst enable (BE)

bit in MCR is ignored, and a 32-byte burst transfer is performed in a cache fill or copy-back cycle.

In write-through area write operations and non-cacheable area read or write operations, 16 bytes of

data is read even in a single read because burst read or write accesses to synchronous DRAM use a

burst length of 4. Sixteen bytes of data is transferred in the case of a single write also, but DQMn

is not asserted when unnecessary data is transferred.

For changing the burst length (a function only available in the SH7750R) for a 32-bit bus, see

Notes on Changing the Burst Length (SH7750R Only) in section 13.3.5, Synchronous DRAM

Interface.

The control signals for connection of synchronous DRAM are RAS, CAS, RD/WR, CS2 or CS3,

DQM0 to DQM7, and CKE. All the signals other than CS2 and CS3 are common to all areas, and

signals other than CKE are valid and latched only when CS2 or CS3 is asserted. Synchronous

DRAM can therefore be connected in parallel to a number of areas. CKE is negated (driven low)

when the frequency is changed, when the clock is unstable after the clock supply is stopped and

restarted, or when self-refreshing is performed, and is always asserted (high) at other times.

Commands for synchronous DRAM are specified by RAS, CAS, RD/WR, and specific address

signals. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks

(PALL), precharge specified bank (PRE), row address strobe bank active (ACTV), read (READ),

read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register

setting (MRS).

Section 13 Bus State Controller (BSC)

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Byte specification is performed by DQM0 to DQM7. A read/write is performed for the byte for

which the corresponding DQM signal is low. When the bus width is 64 bits, in big-endian mode

DQM7 specifies an access to address 8n, and DQM0 specifies an access to address 8n + 7. In

little-endian mode, DQM7 specifies an access to address 8n + 7, and DQM0 specifies an access to

address 8n.

Figures 13.26 and 13.27 show examples of the connection of 16M × 16-bit synchronous DRAMs.

A12–A3

CKIO

CKE

CS3

RAS

CASS

RD/WR

D63–D48

DQM7

DQM6

SH7750, SH7750S, SH7750R 512K × 16-bit × 2-ban

synchronous DRAM

A9–A0

CLK

CKE

RAS

CAS

I/O15–I/O0

DQMU

DQML

D47–D32

DQM5

DQM4

D31–D16

DQM3

DQM2

D15–D0

DQM1

DQM0

A9–A0

CLK

CKE

RAS

CAS

I/O15–I/O0

DQMU

DQML

A9–A0

CLK

CKE

RAS

CAS

I/O15–I/O0

DQMU

DQML

A9–A0

CLK

CKE

RAS

CAS

I/O15–I/O0

DQMU

DQML

Figure 13.26 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3)

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 467 of 1074

REJ09B0366-0700

A11–A2

CKIO

CKE

CS3

RAS

CASS

RD/WR

D31–D16

DQM3

DQM2

SH7750, SH7750S, SH7750R

512K × 16-bit × 2-ban

synchronous DRAM

A9–A0

CLK

CKE

RAS

CAS

I/O15–I/O0

DQMU

DQML

D15–D0

DQM1

DQM0

A9–A0

CLK

CKE

RAS

CAS

I/O15–I/O0

DQMU

DQML

Figure 13.27 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3)

Address Multiplexing: Synchronous DRAM can be connected without external multiplexing

circuitry in accordance with the address multiplex specification bits AMXEXT and AMX2–

AMX0 in MCR. Table 13.16 shows the relationship between the address multiplex specification

bits and the bits output at the address pins. See Appendix F, Synchronous DRAM Address

Multiplexing Tables.

Address pin output at A25–A18, A1, and A0 are undefined.

When A0, the LSB of the synchronous DRAM address, is connected to this LSI, with a 32-bit bus

width it makes a longword address specification. Connection should therefore be made in this

order: connect pin A0 of the synchronous DRAM to pin A2 of this LSI, then connect pin A1 to pin

A3.

With a 64-bit bus width, the LSB makes a quadword address specification. Connection should

therefore be made in this order: connect pin A0 of the synchronous DRAM to pin A3 of this LSI,

then connect pin A1 to pin A4.

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 468 of 1074

REJ09B0366-0700

Table 13.16 Example of Correspondence between this LSI and Synchronous DRAM

Address Pins (64-Bit Bus Width, AMX2–AMX0 = 011, AMXEXT = 0)

LSI Address Pin Synchronous DRAM Address Pin

RAS Cycle CAS Cycle Function

A14 A22 A22 A11 BANK select bank address

A13 A21 H/L A10 Address precharge setting

A12 A20 0 A9

A11 A19 0 A8

A10 A18 A10 A7

A9 A17 A9 A6

A8 A16 A8 A5

A7 A15 A7 A4

A6 A14 A6 A3

A5 A13 A5 A2

A4 A12 A4 A1

A3 A11 A3 A0

A2 — A2 Not used

A1 — A1 Not used

A0 — A0 Not used

Burst Read: The timing chart for a burst read is shown in figure 13.28. In the following example

it is assumed that four 512K × 16-bit × 2-bank synchronous DRAMs are connected, and a 64-bit

data width is used. The burst length is 4. Following the Tr cycle in which ACTV command output

is performed, a READA command is issued in the Tc1 cycle, and the read data is accepted on the

rising edge of the external command clock (CKIO) from cycle Td1 to cycle Td4. The Tpc cycle is

used to wait for completion of auto-precharge based on the READA command inside the

synchronous DRAM; no new access command can be issued to the same bank during this cycle. In

this LSI, the number of Tpc cycles is determined by the specification of bits TPC2–TPC0 in MCR,

and commands are not issued for synchronous DRAM during this interval.

The example in figure 13.28 shows the basic cycle. To connect slower synchronous DRAM, the

cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV

command output cycle, Tr, to the READA command output cycle, Tc1, can be specified by bits

RCD1 and RCD0 in MCR, with a value of 0 to 3 specifying 2 to 4 cycles, respectively. In the case

of 2 or more cycles, a Trw cycle, in which an NOP command is issued for the synchronous

DRAM, is inserted between the Tr cycle and the Tc cycle. The number of cycles from READA

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 469 of 1074

REJ09B0366-0700

command output cycle Tc1 to the first read data latch cycle, Td1, can be specified as 1 to 5 cycles

independently for areas 2 and 3 by means of bits A2W2–A2W0 and A3W2–A3W0 in WCR2. This

number of cycles corresponds to the number of synchronous DRAM CAS latency cycles.

Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td3

Td2 Td4

CKIO

Bank

Precharge-sel

Address

CSn

RD/WR

RAS

CASS

D63–D0

(read)

DQMn

DACKn

(SA: IO ← memory)

CKE

H/L

d0 d1 d2 d3

Row

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.28 Basic Timing for Synchronous DRAM Burst Read

Section 13 Bus State Controller (BSC)

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In a synchronous DRAM cycle, the BS signal is asserted for one cycle at the start of the bus cycle.

The access sequence is as follows: in a fill operation in the event of a cache miss, 64-bit boundary

data including the missed data is read first, then 32-byte boundary data including the missed data

is read in wraparound mode.

Single Read: With this LSI, as synchronous DRAM is set to burst read/burst write mode, read

data output continues after the required data has been read. To prevent data collisions, after the

required data is read in Td1, empty read cycles Td2 to Td4 are performed, and this LSI waits for

the end of the synchronous DRAM operation. The BS signal is asserted only in Td1.

When the data width is 64 bits, there are 4 burst transfers in a read. In cache-through and other

DMA read cycles, of cycles Td1 to Td4, BS is asserted and data latched only in the Td1 cycle.

Since such empty cycles increase the memory access time, and tend to reduce program execution

speed and DMA transfer speed, it is important both to avoid unnecessary cache-through area

accesses, and to use a data structure that will allow data to be placed at a 32-byte boundary, and to

be transferred in 32-byte units, when carrying out DMA transfer with synchronous DRAM

specified as the source.

Section 13 Bus State Controller (BSC)

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Tr Tc1 Tc2

Tc3 Tc4/Td1 Td2 Td4Trw

H/L

Td3 Tpc TpcTpc

CKIO

Bank

Precharge-sel

Address

CSn

DQMn

RD/WR

RAS

CASS

D63–D0

(read)

CKE

DACKn

(SA: IO ← memory)

Row

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.29 Basic Timing for Synchronous DRAM Single Read

Section 13 Bus State Controller (BSC)

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Burst Write: The timing chart for a burst write is shown in figure 13.30. In this LSI, a burst write

occurs only in the event of cache copy-back or a 32-byte transfer by the DMAC. In a burst write

operation, the WRITA command is issued in the Tc1 cycle following the Tr cycle in which the

ACTV command is output. In the write cycle, the write data is output at the same time as the write

command. In the case of the write with auto-precharge command, precharging of the relevant bank

is performed in the synchronous DRAM after completion of the write command, and therefore no

command can be issued for the same bank until precharging is completed. Consequently, in

addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait

interval until precharging is started following the write command. Issuance of a new command for

synchronous DRAM is postponed during this interval. The number of Trwl cycles can be specified

by bits TRWL2–TRWL0 in MCR. 32-byte boundary data is written in wraparound mode. DACK

is asserted two cycles before the data write cycle.

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 473 of 1074

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Tr Tc1 Tc2 Tc3 Tc4 Trwl TpcTrw

H/L

Trwl

CKIO

Bank

Precharge-sel

Address

CSn

DQMn

RD/WR

RAS

CASS

D63–D0

(read)

CKE

DACKn

(SA: IO → memory)

c1 c2 c3 c4

Row

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.30 Basic Timing for Synchronous DRAM Burst Write

Single Write: The basic timing chart for write access is shown in figure 13.31. In a single write

operation, following the Tr cycle in which ACTV command output is performed, a WRITA

command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data

is output at the same time as the write command. In the case of a write with auto-precharge,

precharging of the relevant bank is performed in the synchronous DRAM after completion of the

write command, and therefore no command can be issued for synchronous DRAM until

precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a

read access, cycle Trwl is also added as a wait interval until precharging is started following the

write command. Issuance of a new command for synchronous DRAM is postponed during this

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 474 of 1074

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interval. The number of Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR. DACK is

asserted two cycles before the data write cycle.

As this LSI supports burst read/burst write operations for synchronous DRAM, there are empty

cycles in a single write operation.

Tr Tc1 Tc2 Tc3 Tc4 Trwl TpcTrw

H/L

Trwl

CKIO

Bank

Precharge-sel

Address

CSn

DQMn

RD/WR

RAS

CASS

D63–D0

(read)

CKE

DACKn

(SA: IO → memory)

Row

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.31 Basic Timing for Synchronous DRAM Single Write

Section 13 Bus State Controller (BSC)

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RAS Down Mode: The synchronous DRAM bank function is used to support high-speed accesses

to the same row address. When the RASD bit in MCR is 1, read/write command accesses are

performed using commands without auto-precharge (READ, WRIT). In this case, precharging is

not performed when the access ends. When accessing the same row address in the same bank, it is

possible to issue the READ or WRIT command immediately, without issuing an ACTV command,

in the same way as in the DRAM RAS down state. As synchronous DRAM is internally divided

into two or four banks, it is possible to activate one row address in each bank. If the next access is

to a different row address, a PRE command is first issued to precharge the relevant bank, then

when precharging is completed, the access is performed by issuing an ACTV command followed

by a READ or WRIT command. If this is followed by an access to a different row address, the

access time will be longer because of the precharging performed after the access request is issued.

In a write, when auto-precharge is performed, a command cannot be issued for a period of Trwl +

Tpc cycles after issuance of the WRIT command. When RAS down mode is used, READ or

WRIT commands can be issued successively if the row address is the same. The number of cycles

can thus be reduced by Trwl + Tpc cycles for each write. The number of cycles between issuance

of the precharge command and the row address strobe command is determined by bits TPC2–

TPC0 in MCR.

There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee

that there will not be a cache hit and another row address will be accessed within the period in

which this value is maintained by program execution, it is necessary to set auto-refresh and set the

refresh cycle to no more than the maximum value of tRAS. In this way, it is possible to observe the

restrictions on the maximum active state time for each bank. If auto-refresh is not used, measures

must be taken in the program to ensure that the banks do not remain active for longer than the

prescribed time.

A burst read cycle without auto-precharge is shown in figure 13.32, a burst read cycle for the same

row address in figure 13.33, and a burst read cycle for different row addresses in figure 13.34.

Similarly, a burst write cycle without auto-precharge is shown in figure 13.35, a burst write cycle

for the same row address in figure 13.36, and a burst write cycle for different row addresses in

figure 13.37.

When synchronous DRAM is read, there is a 2-cycle latency for the DMQn signal that performs

the byte specification. As a result, when the READ command is issued in figure 13.32, if the Tc

cycle is executed immediately, the DMQn signal specification for Td1 cycle data output cannot be

carried out. Therefore, the CAS latency should not be set to 1.

When RAS down mode is set, if only accesses to the respective banks in area 3 are considered, as

long as accesses to the same row address continue, the operation starts with the cycle in figure

13.32 or 13.35, followed by repetition of the cycle in figure 13.33 or 13.36. An access to a

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 476 of 1074

REJ09B0366-0700

different area during this time has no effect. If there is an access to a different row address in the

bank active state, after this is detected the bus cycle in figure 13.34 or 13.37 is executed instead of

that in figure 13.33 or 13.36. In RAS down mode, too, a PALL command is issued before a refresh

cycle or before bus release due to bus arbitration.

c2 c3 c4

Tr Tc1 Tc2

Tc3

Tc4/Td1

Td2 Td4Trw

H/L

Td3

CKIO

Bank

Precharge-sel

Address

CSn

DQMn

RD/WR

RAS

CASS

D63–D0

(read)

CKE

DACKn

(SA: IO ← memory)

Row

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.32 Burst Read Timing

Section 13 Bus State Controller (BSC)

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REJ09B0366-0700

c2 c3 c4

Tc1 Tc3

Tc4/Td1

Td2 Td3 Td4Tc2

H/L

CKIO

Bank

Precharge-sel

Address

CSn

DQMn

RD/WR

RAS

CASS

D63–D0

(read)

CKE

DACKn

(SA: IO ← memory)

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.33 Burst Read Timing (RAS Down, Same Row Address)

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 478 of 1074

REJ09B0366-0700

Tpr Tr Trw

c1 c2 c3 c4

Tc1 Tc2 Tc3 Td2Tpc

H/L

Tc4/Td1

Td3 Td4

CKIO

Bank

Precharge-sel Row

Row

Address

CSn

DQMn

RD/WR

RAS

CASS

D63–D0

(read)

CKE

DACKn

(SA: IO ← memory)

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.34 Burst Read Timing (RAS Down, Different Row Addresses)

Section 13 Bus State Controller (BSC)

Rev.7.00 Oct. 10, 2008 Page 479 of 1074

REJ09B0366-0700

Tr Tc1 Tc2 Tc3 Tc4 TrwlTrw

H/L

Trwl

CKIO

Bank

Precharge-sel

Address

CSn

DQMn

RD/WR

RAS

CASS

D63–D0

(read)

CKE

c1 c2 c3 c4

Row

DACKn

(SA: IO → memory)

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.35 Burst Write Timing

Section 13 Bus State Controller (BSC)

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REJ09B0366-0700

Tnop Tc2 Tc3 Tc4 Trwl TrwlTc1

H/L

Tncp

CKIO

Bank

Precharge-sel

Address

CSn

DQMn

RD/WR

RAS

CASS

D63–D0

(read)

CKE

c1 c2 c3 c4

Row

DACKn

(SA: IO → memory)

Single-address DMA

Normal write

Note: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as

shown by the solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal

is output as shown by the dotted line. DACKn shows an example where DMAC, CHCRn,

and AL (acknowledge level) are 0.

Figure 13.36 Burst Write Timing (Same Row Address)

Section 13 Bus State Controller (BSC)

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REJ09B0366-0700

Tpr Tr Trw Tc1 Tc2 Tc3Tpc

H/LH/L

Tc4 Trwl Trwl Trwl

CKIO

Bank

Precharge-sel

Address

CSn

DQMn

RD/WR

RAS

CASS

D63–D0

(read)

CKE

DACKn

(SA: IO → memory)

c1 c2 c3 c4

RowRow

Row

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.37 Burst Write Timing (Different Row Addresses)

Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between

an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the

DMAC, to provide faster access to synchronous DRAM. As synchronous DRAM is internally

divided into two or four banks, after a READ or WRIT command is issued for one bank it is

possible to issue a PRE, ACTV, or other command during the CAS latency cycle or data latch

cycle, or during the data write cycle, and so shorten the access cycle.

Section 13 Bus State Controller (BSC)

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When a read access is followed by another read access to the same row address, after a READ

command has been issued, another READ command is issued before the end of the data latch

cycle, so that there is read data on the data bus continuously. When an access is made to another

row address and the bank is different, the PRE command or ACTV command can be issued during

the CAS latency cycle or data latch cycle. If there are consecutive access requests for different row

addresses in the same bank, the PRE command cannot be issued until the last-but-one data latch

cycle. If a read access is followed by a write access, it may be possible to issue a PRE or ACT

command, depending on the bank and row address, but since the write data is output at the same

time as the WRIT command, the PRE, ACTV, and WRIT commands are issued in such a way that

one or two empty cycles occur automatically on the data bus. Similarly, with a read access

following a write access, or a write access following a write access, the PRE, ACTV, READ, or

WRIT command is issued during the data write cycle for the preceding access; however, in the

case of different row addresses in the same bank, a PRE command cannot be issued, and so in this

case the PRE command is issued following the number of Trwl cycles specified by the TRWL bits

in MCR, after the end of the last data write cycle.

Figure 13.38 shows a burst read cycle for a different bank and row address following a preceding

burst read cycle.

Pipelined access is enabled only for consecutive access to area 3, and will be discontinued in the

event of an access to another area. Pipelined access is also discontinued in the event of a refresh

cycle, or bus release due to bus arbitration. The cases in which pipelined access is available are

shown in table 13.17. In this table, “DMAC dual” indicates transfer in DMAC dual address mode,

and “DMAC single”, transfer in DMAC single address mode.

Section 13 Bus State Controller (BSC)

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Tc1_A Tc1_B

H/L

c_B

CKIO

Bank

Precharge-sel

Address

CSn

DQMn

RD/WR

RAS

CASS

D63–D0

(read)

CKE

a1 a2 a3 a4 b1 b2

c_A

H/L

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.38 Burst Read Cycle for Different Bank and Row Address Following Preceding

Burst Read Cycle

Section 13 Bus State Controller (BSC)

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Table 13.17 Cycles for which Pipeline Access is Possible

Succeeding Access

CPU DMAC Dual DMAC Single

Preceding Access Read Write Read Write Read Write

CPU Read X X O X O O

Write X X O X O O

DMAC dual Read X X X X X X

Write O O O X O O

DMAC single Read O O X X O O

Write O O O X O O

Legend:

O: Pipeline access possible

X: Pipeline access not possible

Refreshing: The bus state controller is provided with a function for controlling synchronous

DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting

the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh

mode, in which the power consumption for data retention is low, can be activated by setting both

the RMODE bit and the RFSH bit to 1.

• Auto-Refreshing

Refreshing is performed at intervals determined by the input clock selected by bits CKS2–

CKS0 in RTCSR, and the value set in RTCOR. The value of bits CKS2–CKS0 in RTCOR

should be set so as to satisfy the refresh interval specification for the synchronous DRAM

used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR,

then make the CKS2–CKS0 setting last of all. When the clock is selected by CKS2–CKS0,

RTCNT starts counting up from the value at that time. The RTCNT value is constantly

compared with the RTCOR value, and if the two values are the same, a refresh request is

generated and an auto-refresh is performed. At the same time, RTCNT is cleared to zero and

the count-up is restarted. Figure 13.40 shows the auto-refresh cycle timing.

First, an REF command is issued in the TRr cycle. After the TRr cycle, new command output

cannot be performed for the duration of the number of cycles specified by bits TRAS2–TRAS0

in MCR plus the number of cycles specified by bits TRC2–TRC0 in MCR. The TRAS2–

TRAS0 and TRC2–TRC0 bits must be set so as to satisfy the synchronous DRAM refresh

cycle time specification (active/active command delay time).

Auto-refreshing is performed in normal operation, in sleep mode, and in the case of a manual

reset.

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When both areas 2 and 3 are set to the synchronous DRAM, auto-refreshing of area 2 is

performed subsequent to area 3.

RTCNT value

RTCOR-1

H'00000000

RTCSR.CKS2–0

External bus

Refresh request cleared

by start of refresh cycle

= 000 ≠ 000

RTCNT cleared to 0 when

RTCNT = RTCOR

Auto-refresh cycle

Time

Refresh

request

Figure 13.39 Auto-Refresh Operation

Section 13 Bus State Controller (BSC)

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TRr2 TRr3 TRr4 TRr5 TrcTRr1 TrcTRrw Trc

CKIO

CSn

RD/WR

RAS

DQMn

CKE

D63–D0

CASS

Figure 13.40 Synchronous DRAM Auto-Refresh Timing

• Self-Refreshing

Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses

are generated within the synchronous DRAM. Self-refreshing is activated by setting both the

RMODE bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal

is low. Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh

mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared,

command issuance is disabled for the number of cycles specified by bits TRC2–TRC0 in

MCR. Self-refresh timing is shown in figure 13.41. Settings must be made so that self-refresh

clearing and data retention are performed correctly, and auto-refreshing is performed at the

correct intervals. When self-refreshing is activated from the state in which auto-refreshing is

set, or when exiting standby mode other than through a power-on reset, auto-refreshing is

restarted if RFSH is set to 1 and RMODE is cleared to 0 when self-refresh mode is cleared. If

the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this

time should be taken into consideration when setting the initial value of RTCNT. Making the

RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately.

After self-refreshing has been set, the self-refresh state continues even if the chip standby state

is entered using this LSI's standby function, and is maintained even after recovery from

standby mode other than through a power-on reset.

Section 13 Bus State Controller (BSC)

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In the case of a power-on reset, the bus state controller's registers are initialized, and therefore

the self-refresh state is cleared.

Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the

case of a manual reset.

TRs2 TRs3 TRs4 TRs5 TrcTRs1 Trc Trc

CKIO

CSn

RD/WR

RAS

DQMn

CKE

D63–D0

CASS

Figure 13.41 Synchronous DRAM Self-Refresh Timing

Section 13 Bus State Controller (BSC)

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