32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Features Async/Page CellularRAMTM 1.0 Memory MT45W2MW16PGA Features Figure 1: * Asynchronous and page mode interface * Random access time: 70ns * VCC, VCCQ voltages: - 1.7-1.95V VCC - 1.7-3.6V VCCQ * Page mode read access: - 16-word page size - Interpage read access: 70ns - Intrapage read access: 20ns * Low power consumption: - Asynchronous READ: <20mA - Intrapage READ: <15mA - Standby: <110A - Deep power-down: <10A (TYP at 25C) * Low-power features: - Temperature-compensated refresh (TCR) - On-chip temperature sensor - Partial-array refresh (PAR) - Deep power-down (DPD) mode Options Designator 1 2 3 4 5 6 A LB# OE# A0 A1 A2 ZZ# B DQ8 UB# A3 A4 CE# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VssQ DQ11 A17 A7 DQ3 Vcc E VccQ DQ12 NC A16 DQ4 Vss F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 Top View (Ball Down) * Configuration * 2 Meg x 16 MT45W2MW16P * Package * 48-ball VFBGA (green) GA * Access time * 70ns -70 * Operating temperature range * Wireless (-30C to +85C)1 WT * Industrial (-40C to +85C) IT Notes: 1. -30C exceeds the CellularRAM Workgroup 1.0 specification of -25C. PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_1.fm - Rev. B 5/07 EN 48-Ball VFBGA Ball Assignment Part Number Example: MT45W2MW16PGA-70WT 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Part-Numbering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Temperature-Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Partial-Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Configuration Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Access Using ZZ# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Software Access to the Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Maximum and Typical Standby Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24zTOC.fm - Rev. B 5/07 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: 48-Ball VFBGA Ball Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Functional Block Diagram 2 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Power-Up Initialization Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Page READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Software Access PAR Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Load Configuration Register Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Software Access Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Software Access Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Configuration Register Bit Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Typical Refresh Current vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Power-Up Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Deep Power-Down Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Single READ Operation (WE# = VIH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Page Mode READ Operation (WE# = VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 WRITE Cycle (WE# Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 WRITE Cycle (CE# Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 WRITE Cycle (LB#/UB# Control). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 48-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24zLOF.fm - Rev. B 5/07 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 32Mb Address Patterns for PAR (CR[4] = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Partial-Array Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Deep Power-Down Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Capacitance Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Load Configuration Register Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Deep Power-Down Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24zLOT.fm - Rev. B 5/07 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory General Description General Description Micron(R) CellularRAMTM products are high-speed, CMOS PSRAM memories developed for low-power, portable applications. The MT45W2MW16P is a 32Mb DRAM core device organized as 2 Meg x 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or pseudo-SRAM offerings. A user-accessible configuration register (CR) defines how the CellularRAM device performs on-chip refresh and whether page mode read accesses are permitted. This register is automatically loaded with a default setting during power-up and can be updated at any time during normal operation. For seamless operation on an asynchronous memory bus, CellularRAM products incorporate a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Special attention has been focused on current consumption during self refresh. CellularRAM products include three system-accessible mechanisms to minimize refresh current. Temperature-compensated refresh (TCR) uses an on-chip sensor to adjust the refresh rate to match the device temperature. The refresh rate decreases at lower temperatures to minimize current consumption during standby. Setting sleep enable (ZZ#) to LOW enables one of two low-power modes: partial-array refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the DRAM array that contains essential data. DPD halts refresh operation altogether and is used when no vital information is stored in the device. The system-configurable refresh mechanisms are accessed through the CR. Functional Block Diagram Figure 2: Functional Block Diagram 2 Meg x 16 A[20:0] Address Decode Logic Configuration Register (CR) 2,048K x 16 DRAM Memory Array Input/ Output MUX and Buffers DQ[7:0] DQ[15:8] CE# WE# OE# UB# Control Logic LB# ZZ# Note: PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN Functional block diagrams illustrate simplified device operation. See ball description table, bus operations table, and timing diagrams for detailed information. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Ball Descriptions Ball Descriptions Table 1: VFBGA Ball Descriptions VFBGA Ball Assignment Symbol Type Description H6, G2, H1, D3, E4, F4, F3, G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4, A3 B5 A[20:0] Input Address inputs: Inputs for the address accessed during READ or WRITE operations. The address lines are also used to define the value to be loaded into the CR. CE# Input A1 A2 LB# OE# Input Input B2 G5 A6 UB# WE# ZZ# Input Input Input G1, F1, F2, E2, D2, C2, C1, B1, G6, F6, F5, E5, D5, C6, C5, B6 E3 D6 E1 E6 D1 DQ[15:0] Input/ Output Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. Lower byte enable: DQ[7:0]. Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Upper byte enable: DQ[15:8]. Write enable: Enables WRITE operations when LOW. Sleep enable: When ZZ# is LOW, the CR can be loaded or the device can enter one of two low-power modes (DPD or PAR). Data inputs/outputs. NC VCC VCCQ VSS VSSQ PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN Supply Supply Supply Supply Not internally connected. Device power supply: (1.7-1.95V) Power supply for device core operation. I/O power supply: (1.7-3.6V) Power supply for input/output buffers. VSS must be connected to ground. VSSQ must be connected to ground. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Bus Operations Bus Operations Table 2: Bus Operations Mode Standby Read Write No operation PAR DPD Load configuration register Notes: PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN Power CE# WE# OE# LB#/UB# ZZ# DQ[15:0]1 Notes Standby Active Active Idle Partial-array refresh Deep power-down Active H L L L H H L X H L X X X L X L X X X X X X L L X X X X H H H H L L L High-Z Data-out Data-in X High-Z High-Z High-Z 2, 5 1, 4 1, 3, 4 4, 5 6 6 1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# alone is in select mode, only DQ[7:0] are affected. When UB# alone is in the select mode, only DQ[15:8] are affected. 2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data inputs/outputs are internally isolated from any external influence. 3. When WE# is active, the OE# input is internally disabled and has no effect on the I/Os. 4. The device will consume active power in this mode whenever addresses are changed. 5. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve minimum standby current. 6. DPD is enabled when configuration register bit CR[4] is "0"; otherwise, PAR is enabled. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Part-Numbering Information Part-Numbering Information Micron CellularRAM devices are available in several different configurations and densities (see Figure 3). Figure 3: Part Number Chart MT 45 W 2M W Micron Technology 16 P GA -70 WT ES Production Status Blank = Production Product Family ES = Engineering Sample 45 = PSRAM/CellularRAM Memory MS = Mechanical Sample Operating Core Voltage Operating Temperature W = 1.7V-1.95V WT = 30C to +85C (see Note 1) IT = 40C to +85C Address Locations Standby Power Options M = Megabits Blank = Standard Operating Voltage W = 1.7V-3.6V Access/Cycle Time Bus Configuration 70 = 70ns 16 = x16 READ/WRITE Operation Mode P = Asynchronous/Page Package Codes GA = VFBGA "Green" (6 x 8 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 48-ball Notes: 1. -30C exceeds the CellularRAM Workgroup 1.0 specification of -25C. Valid Part Number Combinations After building the part number from the part numbering chart, visit the Micron Web site at www.micron.com/psram to verify that the part number is offered and valid. If the device required is not on this list, contact the factory. Device Marking Due to the size of the package, the Micron standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a five-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site, http://www.micron.com/decoder. To view the location of the abbreviated mark on the device, refer to customer service note, CSN-11, "Product Mark/Label," at www.micron.com/csn. PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Functional Description Functional Description In general, the MT45W2MW16P device is a high-density alternative to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The MT45W2MW16P contains a 33,554,432-bit DRAM core organized as 2,097,152 addresses by 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or Pseudo SRAM offerings. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. Power-Up Initialization CellularRAM products include an on-chip voltage sensor that is used to launch the power-up initialization process. Initialization will load the CR with its default setting. VCC and VCCQ must be applied simultaneously, and when they reach a stable level above 1.7V, the device will require 150s to complete its self-initialization process (see Figure 4). During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. Figure 4: Power-Up Initialization Timing Vcc (MIN) Vcc, VccQ = 1.7V tPU Device ready for normal operation Bus Operating Modes The MT45W2MW16P CellularRAM product incorporates the industry-standard, asynchronous interface found on other low-power SRAM or Pseudo SRAM offerings. This bus interface supports asynchronous READ and WRITE operations as well as the bandwidth-enhancing page mode READ operation. The specific interface that is supported is defined by the value loaded into the CR. Asynchronous Mode CellularRAM products power up in the asynchronous operating mode. This mode uses the industry-standard SRAM control interface (CE#, OE#, WE#, LB#/UB#). READ operations (Figure 5) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations (Figure 6) occur when CE#, WE#, and LB#/UB# are driven LOW. During WRITE operations, the level of OE# is a "Don't Care"; WE# will override OE#. The data to be written will be latched on the rising edge of CE#, WE#, or LB#/UB#, whichever occurs first. WE# LOW time must be limited to tCEM. PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Bus Operating Modes Figure 5: READ Operation CE# OE# WE# ADDRESS Valid address DATA Valid data LB#/UB# tRC = READ cycle time Don't Care Figure 6: WRITE Operation CE# OE# < tCEM WE# ADDRESS Valid address DATA Valid data LB#/UB# tWC = WRITE cycle time Don't Care PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Bus Operating Modes Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be quickly read by simply changing the loworder address. Addresses A[3:0] are used to determine the members of the 16-address CellularRAM page. Any change in addresses A[4] or higher will initiate a new tAA access. Figure 7 shows the timing diagram for a page mode access. Page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. WRITE operations do not include comparable page mode functionality. The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. Figure 7: Page READ Operation < tCEM CE# OE# WE# ADDRESS Address[0] tAA DATA Address Address Address [1] [3] [2] tAPA D[0] tAPA D[1] tAPA D[2] D[3] LB#/UB# Don't Care LB#/UB# Operation The lower byte (LB#) enable and upper byte (UB#) enable signals allow for byte-wide data transfers. During READ operations, enabled bytes are driven onto the DQs. The DQs associated with a disabled byte are put into a High-Z state during a READ operation. During WRITE operations, any disabled bytes will not be transferred to the memory array and the internal value will remain unchanged. During a WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, the device remains in an active mode as long as CE# remains LOW. PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Low-Power Operation Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM REFRESH operation on the full array. Standby operation occurs when CE# and ZZ# are HIGH. The device will enter a reduced power state upon completion of READ and WRITE operations where the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the address or control inputs. Temperature-Compensated Refresh Temperature-compensated refresh (TCR) allows for adequate refresh at different temperatures. This CellularRAM device includes an on-chip temperature sensor. It continually adjusts the refresh rate according to the operating temperature. Partial-Array Refresh Partial-array refresh (PAR) restricts REFRESH operation to a portion of the total memory array. This feature enables the system to reduce refresh current by only refreshing that part of the memory array that is absolutely necessary. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. Data stored in addresses not receiving refresh will become corrupted. The mapping of these partitions can start at either the beginning or the end of the address map (Table 3 on page 17). READ and WRITE operations are ignored during PAR operation. The device only enters PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1). PAR can be initiated by bring the ZZ# ball to the LOW state for longer than 10s. Returning ZZ# to HIGH will cause an exit from PAR and the entire array will be immediately available for READ and WRITE operations. Alternatively, PAR can be initiated using the CR software access sequence (see "Software Access to the Configuration Register" on page 14). PAR is enabled immediately upon setting CR[4] to "1" using this method. However, using software access to write to the CR alters the function of ZZ# so that ZZ# LOW no longer initiates PAR, although ZZ# continues to enable WRITEs to the CR. This functional change persists until the next time the device is powered up (see Figure 8 on page 13). PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Low-Power Operation Figure 8: Software Access PAR Functionality Powe r-Up To enable PAR, bring ZZ# LOW for 10s. NO Software LOAD executed? YES Change to ZZ# functionality; PAR permanently enabled independent of ZZ# level. Deep Power-Down Operation Deep power-down (DPD) operation disables all refresh-related activity. This mode is used when the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is entered. When refresh activity has been re-enabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. READ and WRITE operations are ignored during DPD operation. The device can only enter DPD if the SLEEP bit in the CR has been set LOW (CR[4] = 0). DPD is initiated by bringing ZZ# to the LOW state for longer than 10s. Returning ZZ# to HIGH will cause the device to exit DPD and begin a 150s initialization process. During this 150s period, the current consumption will be higher than the specified standby levels but considerably lower than the active current specification. Driving ZZ# LOW will place the device in the PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1). The device should not be put into DPD using CR software access. PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Configuration Register Operation Configuration Register Operation The configuration register (CR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the CR. This register can be updated any time the device is operating in a standby state. Figure 12 on page 16 describes the control bits used in the CR. At power-up, the CR is set to 0010h. Access Using ZZ# The CR can be loaded using a WRITE operation immediately after ZZ# makes a HIGHto-LOW transition (see Figure 9). The values placed on addresses A[19:0] are latched into the CR on the rising edge of CE# or WE#, whichever occurs first. LB#/UB# are "Don't Care." Access using ZZ# is WRITE only. Figure 9: Load Configuration Register Operation ADDRESS Valid address CE# WE# t < 500ns ZZ# Software Access to the Configuration Register The contents of the CR can either be read or modified using a software sequence. The nature of this access mechanism may eliminate the need for the ZZ# ball. If the software mechanism is used, ZZ# can simply be tied to VCCQ. The port line typically used for ZZ# control purposes will no longer be required. However, ZZ# should not be tied to VCCQ if the system will use DPD; DPD cannot be enabled or disabled using the software access sequence. The CR is loaded using a four-step sequence consisting of two READ operations followed by two WRITE operations (see Figure 10 on page 15). The read sequence is virtually identical except that an asynchronous READ is performed during the fourth operation (see Figure 11 on page 15). Note that a third READ cycle of the highest address will cancel the access sequence until a different address is read. The address used during all READ and WRITE operations is the highest address of the CellularRAM device being accessed (1FFFFFh for 32Mb); the content of this address is not changed by using this sequence. The data bus is used to transfer data into or out of bits 15-0 of the CR. Writing to the CR using the software sequence modifies the function of the ZZ# ball. After the software sequence loads the CR, the level of the ZZ# ball no longer enables PAR operation. PAR operation will be updated whenever the software sequence loads a new value into the CR. This ZZ# functionality will continue until the next time the device is powered-up. The operation of the ZZ# ball is not affected if the software sequence is only used to read the contents of the CR. The use of the software sequence does not affect the ability to perform the standard (ZZ#-controlled) method of loading the CR. PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Configuration Register Operation Figure 10: Software Access Load Configuration Register ADDRESS READ READ WRITE WRITE Address (MAX) Address (MAX) Address (MAX) Address (MAX) 0000h CR value in CE# OE# WE# LB#/UB# DATA XXXXh XXXXh Don't Care Figure 11: Software Access Read Configuration Register ADDRESS READ READ WRITE READ Address (MAX) Address (MAX) Address (MAX) Address (MAX) CE# OE# WE# LB#/UB# DATA XXXXh XXXXh 0000h CR value out Don't Care PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Configuration Register Operation Figure 12: Configuration Register Bit Mapping A[20:8] 20-8 Reserved All must be set to "0" CR[7] A7 7 Page A6 A5 6 5 Ignored A4 4 3 Sleep Setting is ignored (default 00b) A3 A2 2 Reserved Must be set to "0" A1 A0 Address Bus 0 1 PAR CR[2] CR[1] CR[0] PAR Refresh Coverage 0 0 0 Full array (default) Page Mode Enable/Disable 0 0 1 Bottom 1/2 array 0 Page mode disabled (default) 0 1 0 Bottom 1/4 array 1 Page mode enabled 0 1 1 Bottom 1/8 array 1 0 0 None of array CR[4] Sleep Mode 1 0 1 Top 1/2 array 0 DPD enabled 1 1 0 Top 1/4 array 1 PAR enabled (default) 1 1 1 Top 1/8 array Partial-Array Refresh (CR[2:0]) Default = Full-Array Refresh The PAR bits restrict REFRESH operation to a portion of the total memory array. This feature allows the system to reduce current by only refreshing that part of the memory array required by the host system. The refresh options are full array, one-half array, onequarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Table 3 on page 17). Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled The sleep mode bit determines which low-power mode is to be entered when ZZ# is driven LOW. If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is enabled. PAR can also be enabled directly by writing to the CR using the software access sequence. Note that this then disables ZZ# initiation of PAR. DPD cannot be enabled or disabled using the software access sequence; this should only be done using ZZ# to access the CR. DPD operation disables all refresh-related activity. This mode will be used when the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operation can resume. DPD should not be enabled using CR software access. PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Electrical Characteristics Page Mode READ Operation (CR[7]) Default = Disabled The page mode operation bit determines whether page mode READ operations are enabled. In the power-up default state, page mode is disabled. Table 3: 32Mb Address Patterns for PAR (CR[4] = 1) CR[2] CR[1] CR[0] Active Section Address Space Size Density 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Full die One-half of die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die 000000h-1FFFFFh 000000h-0FFFFFh 000000h-07FFFFh 000000h-03FFFFh 0 100000h-1FFFFFh 180000h-1FFFFFh 1C0000h-1FFFFFh 2 Meg x 16 1 Meg x 16 512K x 16 256K x 16 0 Meg x 16 1 Meg x 16 512K x 16 256K x 16 32Mb 16Mb 8Mb 4Mb 0Mb 16Mb 8Mb 4Mb Electrical Characteristics Stresses greater than those listed in Table 4 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 4: Absolute Maximum Ratings Parameter Rating -0.5V to (4.0V or VCCQ + 0.3V, whichever is less) -0.2V to +2.45V -0.2V to +4.0V -55C to +150C Voltage to any ball except VCC, VCCQ relative to VSS Voltage on VCC supply relative to VSS Voltage on VCCQ supply relative to VSS Storage temperature Operating temperature (case) Wireless1 Industrial Soldering temperature and time 10 seconds (solder ball only) Notes: PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN -30C to +85C -40C to +85C 260C 1. -30C exceeds the CellularRAM Workgroup 1.0 specification of -25C. 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Electrical Characteristics Table 5: Electrical Characteristics and Operating Conditions Wireless temperature1 (-30C TC +85 C), Industrial temperature (-40C < TC < +85C) Description Conditions Supply voltage I/O supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current Symbol VCC VCCQ VIH VIL VOH VOL ILI ILO IOH = -0.2mA IOL = 0.2mA VIN = 0 to VCCQ OE# = VIH or Chip disabled Operating Current Asynchronous random READ/WRITE Asynchronous page READ Standby current VIN = VCCQ or 0V Chip enabled; IOUT = 0 VIN = VCCQ or 0V CE# = VCCQ Notes: Min Max Units 1.7 1.7 1.4 -0.2 0.8 VCCQ 1.95 3.6 VCCQ + 0.2 +0.4 0.2 VCCQ 1 1 V V V V V V A A Notes 2, 3 4 ICC1 -70 20 mA 5 ICC1P ISB -70 15 110 mA A 5 6 1. -30C exceeds the CellularRAM Workgroup 1.0 specification of -25C. 2. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions. 3. VIH (MIN) value is not aligned with CellularRAM Workgroup 1.0 specification of VCCQ - 0.4V. 4. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions. 5. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. 6. ISB (MAX) values measured with PAR set to FULL ARRAY and at +85C. In order to achieve low standby current, all inputs must be driven to VCCQ or VSS. ISB may be slightly higher for up to 500ms after power-up or when entering standby mode. Maximum and Typical Standby Currents The following table and figure refer to the maximum and typical standby currents for the MT45W2MW16PGA device. The typical values shown in Figure 13 on page 19 are measured with the default on-chip temperature sensor control enabled. Table 6: Partial-Array Refresh Specifications and Conditions Description Conditions Partial-array refresh standby current VIN = VCCQ or 0V; CE# = VCCQ Notes: PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN Symbol IPAR Standard power (no designation) Array Partition Max Unit Full 1/2 1/4 1/8 0 110 105 95 95 70 A 1. IPAR (MAX) values measured at 85C. IPAR might be slightly higher for up to 500ms after changes to the PAR array partition or when entering standby mode. In order to achieve low standby current, all inputs must be driven to either VCCQ or VSS. 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Electrical Characteristics Figure 13: Typical Refresh Current vs. Temperature 70 60 PAR FULL PAR 1/2 PAR 1/4 PAR 0 ISB (A) 50 40 30 20 10 C 85 95 C C C 75 65 55 C C 45 C 35 C 25 C 15 C 05 5C -0 5C -1 5C -2 5C -3 -4 5C 0 Temperature (C) Table 7: Deep Power-Down Specifications and Conditions Description Deep power-down Table 8: Symbol TYP Units VIN = VCCQ or 0V; +25C ZZ# = 0V CR[4] = 0 IZZ 10 A Capacitance Specifications and Conditions Description Input capacitance Input/output capacitance (DQ) Notes: Figure 14: Conditions Conditions Symbol Min Max Units Notes TC = +25C; f = 1 MHz; VIN = 0V CIN CIO 2.0 3.0 6.5 6.5 pF pF 1 1 1. These parameters are verified in device characterization and are not 100-percent tested. AC Input/Output Reference Waveform VCC Input 1 2 VCC/2 Test Points 3 VCCQ/2 Output VSSQ Notes: PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10 percent to 90 percent) < 1.6ns. 2. Input timing begins at VCC/2. Due to the possibility of a difference between VCC and VCCQ, the input test point may not be shown to scale. 3. Output timing ends at VCCQ/2. 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Electrical Characteristics Figure 15: Output Load Circuit Test Point 50 DUT VccQ/2 30pF Table 9: READ Cycle Timing Requirements -70 Parameter Symbol Address access time Page access time LB#/UB# access time LB#/UB# disable to High-Z output LB#/UB# enable to Low-Z output Maximum CE# pulse width Chip select access time Chip disable to High-Z output Chip enable to Low-Z output Output enable to valid output Output hold from address change Output disable to High-Z output Output enable to Low-Z output Page cycle time Read cycle time tAA Notes: PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN Min tAPA tBA tBHZ tBLZ Max Units 70 20 70 8 ns ns ns ns ns s ns ns ns ns ns ns ns ns ns 10 tCEM 8 70 8 tCO tHZ tLZ 10 tOE 20 tOH 5 tOHZ 8 tOLZ 5 20 70 tPC tRC Notes 2 1 3 2 1 2 1 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 15 on page 20. The LowZ timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 15 on page 20. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. Page mode enabled only. 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Electrical Characteristics Table 10: WRITE Cycle Timing Requirements -70 Parameter Symbol Address setup time Address valid to end of write Byte select to end of write CE# HIGH time during write Chip enable to end of write Data hold from write time Data write setup time Chip enable to Low-Z output End write to Low-Z output WRITE cycle time Write to High-Z output Write pulse width Write pulse width HIGH Write recovery time tAS Notes: Table 11: Min Max Units 0 70 70 5 70 0 23 10 5 70 t AW BW tCPH t CW tDH t DW t LZ tOW tWC tWHZ tWP tWPH tWR t ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 46 10 0 Notes 1 1 2 3 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 15 on page 20. The LowZ timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 15 on page 20. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. WE# LOW time must be limited to tCEM (8s). Load Configuration Register Timing Requirements -70 Description Symbol Address setup time Address valid to end of write Chip deselect to ZZ# LOW Chip enable to end of write WRITE cycle time Write pulse width Write recovery time ZZ# LOW to WE# LOW tAS Table 12: Min 0 70 5 70 70 40 0 10 tAW t CDZZ tCW tWC tWP t t WR ZZWE Max Units 500 ns ns ns ns ns ns ns ns Max Units Deep Power-Down Timing Requirements -70 Description Symbol Min Chip deselect to ZZ# LOW Deep power-down recovery Minimum ZZ# pulse width tCDZZ 5 150 10 PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN tR tZZ (MIN) 21 ns s s Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Timing Diagrams Timing Diagrams Figure 16: Power-Up Initialization Period Vcc (MIN) Vcc, VccQ = 1.7V Table 13: tPU Device ready for normal operation Initialization Timing Parameters -70 Parameter Symbol Min Initialization period (required before normal operations) tPU 150 Figure 17: Max Units s Load Configuration Register tWC ADDRESS OPCODE tAW tWR tCW CE# LB#/UB# tAS tWP WE# OE# tCDZZ tZZWE ZZ# Don't Care Figure 18: Deep Power-Down Entry and Exit tCDZZ tZZ (MIN) ZZ# tR CE# Device ready for normal operation Don't Care PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Timing Diagrams Figure 19: Single READ Operation (WE# = VIH) tRC Valid address ADDRESS tAA tHZ CE# tCO tBA tBHZ LB#/UB# tLZ tBLZ tOHZ tOE OE# tOLZ DATA-OUT High-Z Valid data High-Z Don't Care Figure 20: Undefined Page Mode READ Operation (WE# = VIH) tRC ADDRESS A[20:4] Valid address ADDRESS A[3:0] tAA tPC tCEM tHZ CE# tCO tBHZ tBA LB#/UB# tBLZ tLZ tOHZ tOE OE# tAPA tOH tOLZ DATA-OUT Valid data High-Z Valid data Valid data Don't Care PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 23 Valid data High-Z Undefined Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Timing Diagrams Figure 21: WRITE Cycle (WE# Control) tWC ADDRESS Valid address tWR tAW tCW CE# tBW LB#/UB# tWPH tWP tAS WE# OE# tDW DATA-IN tDH Valid data tWHZ tOW High-Z DATA-OUT Don't Care Figure 22: WRITE Cycle (CE# Control) tWC Valid address ADDRESS tWR tAW tCPH tCW CE# tAS tBW LB#/UB# tWP WE# OE# tDW DATA-IN tLZ tDH Valid data tWHZ High-Z DATA-OUT Don't Care PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Timing Diagrams Figure 23: WRITE Cycle (LB#/UB# Control) tWC Valid address ADDRESS tAW tWR tCW CE# tAS tBW LB#/UB# WE# OE# tDW DATA-IN tLZ tDH Valid data tWHZ DATA-OUT High-Z Don't Care PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Package Dimensions Package Dimensions Figure 24: 48-Ball VFBGA 0.70 0.05 SEATING PLANE A 0.10 A 48X O0.37 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. PRE-REFLOW BALL DIAMETER IS 0.35 ON A 0.30 SMD BALL PAD. SOLDER BALL MATERIAL: 96.5% Sn, 3% Ag, 0.5% Cu SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC 3.75 0.75 TYP BALL A1 ID BALL A1 BALL A1 ID 4.00 0.05 BALL A6 CL 5.25 8.00 0.10 2.625 0.75 TYP CL 1.875 1.00 MAX 3.00 0.05 6.00 0.10 Notes: 1. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W2MW16PGA uses "green" packaging. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc., inside the U.S. and a trademark of Qimonda AG outside the U.S. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved.