MT45W2MW16PGA-70IT - Micron Technology, Inc.

Products and specifications discussed herein are subject to change by Micron without notice.

32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

Features

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Async/Page CellularRAM™ 1.0 Memory

MT45W2MW16PGA

Features

• Asynchronous and page mode interface

• Random access time: 70ns

•V

CC, VCCQ voltages:

–1.7–1.95V VCC

–1.7–3.6V VCCQ

• Page mode read access:

–16-word page size

–Interpage read access: 70ns

–Intrapage read access: 20ns

• Low power consumption:

–Asynchronous READ: <20mA

–Intrapage READ: <15mA

–Standby: <110µA

–Deep power-down: <10µA (TYP at 25°C)

•Low-power features:

–Temperature-compensated refresh (TCR)

–On-chip temperature sensor

–Partial-array refresh (PAR)

–Deep power-down (DPD) mode

Notes: 1. –30°C exceeds the CellularRAM Workgroup

1.0 specification of –25°C.

Options Designator

•Configuration

• 2 Meg x 16 MT45W2MW16P

•Package

• 48-ball VFBGA (green) GA

•Access time

• 70ns –70

• Operating temperature range

• Wireless (–30°C to +85°C)1WT

• Industrial (–40°C to +85°C) IT

Figure 1: 48-Ball VFBGA Ball Assignment

Part Num ber Example:

MT45W2MW16PGA-70WT

1 2 3 4 5 6

Top View

(Ball Down)

LB#

DQ8

DQ9

VssQ

VccQ

DQ14

DQ15

A18

OE#

UB#

DQ10

DQ11

DQ12

DQ13

A19

A17

A14

A12

CE#

DQ1

DQ3

DQ4

DQ5

WE#

A11

A16

A15

A13

A10

ZZ#

DQ0

DQ2

Vcc

Vss

DQ6

DQ7

A20

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32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Part-Numbering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Device Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Bus Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

LB#/UB# Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Temperature-Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Partial-Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Deep Power-Down Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Configuration Register Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Access Using ZZ# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Software Access to the Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Maximum and Typical Standby Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

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32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

List of Figur es

List of Figures

Figure 1: 48-Ball VFBGA Ball Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2: Fun cti onal Block Diag ram 2 Me g x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 3: Part Number Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 4: Power-Up Initialization Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 5: READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 6: WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 7: Page READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 8: Software Access PAR Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 9: Load Configuration Register Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 10: Software Access Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 11: Software Access Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 12: Configuration Register Bit Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Figure 13: Typical Refresh Curre n t vs. Te m perature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 14: AC Input/Output Reference Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 15: Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 16: Power-Up Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 17: Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 18: Deep Power-Down Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 19: Single READ Operation (WE# = VIH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 20: Page Mode READ Operation (WE# = VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 21: WRITE Cycle (WE# Control). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 22: WRITE Cycle (CE# Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 23: WRITE Cycle (LB#/UB# Control). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 24: 48-Ball VFBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

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32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

List of Tables

Table 1: VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 2: Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3: 32Mb Address Patterns for PAR (CR[4] = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 4: Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 5: Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 6: Partial-Array Refresh Spec if ic ati o ns and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 7: Deep Power-Down Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 8: Capacitance Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 9: READ Cycle Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 10: WRITE Cycle Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 11: Load Configuration Register Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 12: Deep Power-Down Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 13: Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

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32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

General Description

Micron® CellularRAM™ products are high-speed, CMOS PSRAM memories dev eloped

for lo w-power, portable applications. The MT45W2MW16P is a 32Mb DRAM core device

organized as 2 Meg x 16 bits. These devices include the industry-standard, asynchronous

memory interface found on other low-power SRAM or pseudo-SRAM offerings.

A user-accessible configuration register (CR) defines how the CellularRAM device

performs on-chip refresh and whether page mode read accesses ar e permitted. This

updated at any time during normal operation.

Fo r seamless operation on an asynchronous memory bus, CellularRAM products incor-

porate a transparent self-refresh mechanism. The hidden refresh requires no additional

support from the system memory controller and has no significant impact on device

read/w rite performance.

S p ecial attention has been focused on current consumption during self refresh. Cellu-

larRAM products include three system-acces s ible mechanism s to mi nimize refresh

current. Temperature-compensated refresh (TCR) uses an on-chip sensor to adjust the

refresh rate to match the device temperature. The refresh rate decr eases at lower

temperatures to minimize current consumption during standby. Setting sleep enable

(ZZ#) to LOW enables one of two low-po wer modes: partial-array r efresh (PAR) or deep

po wer-down (DPD). PAR limits refresh to only that part of the DRAM array that contains

essential data. DPD halts refr esh operation altogether and is used when no vital infor-

mation is stored in the device. The system-configurable refresh mechanisms are

accessed through the CR.

Functional Block Diagram

Figure 2: Functional Block Diagram 2 Meg x 16

Note: Functional block diagrams illustrate simplified device operation. See ball description table,

bus operation s table, and timing diagrams for detailed information.

A[20:0]

DQ[7:0]

DQ[15:8]

LB#

UB#

CE#

WE#

OE#

ZZ#

Control

Logic

Input/

Output

MUX

and

Buffers

2,048K x 16

DRAM

Memory

Array

Configuration

Address Decode

Logic

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32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

Ball Descriptions

Table 1: VFBGA Ball Descriptions

VFBGA Ball

Assignment Symbol Type Description

H6, G2, H1, D3,

E4, F4, F3, G4,

G3, H5, H4, H3,

H2, D4, C4, C3,

B4, B3, A5, A4,

A[20:0] Input Address inputs: Inputs for the address accessed during READ or WRITE operations.

The address lines are also used to define the value to be loaded into the CR.

B5 CE# Input Chip enable: Activates the device when LOW. When CE# is HIGH, the device is

disabled and goes into standby power mode.

A1 LB# Input Lower byte enable: DQ[7:0].

A2 OE# Input Output enable: Enables the output buffers when LOW. When OE# is HIGH, the

output buffers are disabled.

B2 UB# Input Upper byte enable: DQ[15:8].

G5WE#Input

Write enable: Enables WRITE operations when LOW.

A6ZZ# Input Sleep enable: When ZZ# is LOW, the CR can be loaded or the device can en ter one

of two low-power modes (DPD or PAR).

G1, F1, F2, E2,

D2, C2, C1, B1,

G6, F6, F5, E5,

D5, C6, C5, B6

DQ[15:0] Input/

Output Data inputs/outputs.

E3 NCNot internally connected.

D6VCC Supply Device power supply: (1.7–1.95V) Power supply for device co re operation.

E1 VCCQ Supply I/O power supply: (1.7–3.6V) Power supply for input/output buffers.

E6VSS Supply VSS must be connected to ground.

D1 VSSQ Supply VSSQ must be connected to ground.

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32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

Bus Operations

Notes: 1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# alone is in

select mode, only DQ[7:0] are affected. When UB# alone is in the select mode, only DQ[15:8]

are affecte d .

2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data

inputs/outputs are internally isolated fr om any external influence.

3. When WE# is active, the OE# input is internally disabled and has no effect on the I/Os.

4. The device will consume active power in this mode whenever addresses are changed.

5. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve minimum

standby current.

6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.

Ta ble 2: Bus Operations

Mode Power CE# WE# OE# LB#/UB# ZZ# DQ[15:0]1Notes

Standby Standby H X X X H High-Z 2, 5

Read Active L H L L H Data-out 1, 4

Write Active L L X L H Data-in 1, 3, 4

No operation Idle L X X X H X 4, 5

PAR Partial-array refresh H X X X L High-Z 6

DPD Deep power-down H X X X L High-Z 6

Load configuration register Active L L X X L High-Z

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32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

Part-Numbering Information

Micron CellularRAM devices are available in several different configurations and densi-

ties (see Figure 3).

Figure 3: Part Number Chart

Notes: 1. –30°C exceeds the CellularRAM Workgroup 1.0 specification of –25°C.

Valid Part Number Combinations

After building the part number from the part numbering chart, visit the Micron Web site

at www.micron.com/psram to verify that the part number is offered and valid. If the

device required is not on this list, contact the factor y.

Device Marking

Due to the size of the package, the Micron standard part number is not printed on the

top of the device. Instead, an abbreviated device mark consisting of a five-digit alphanu-

meric code is used. The abbreviated device marks are cr oss-referenced to the Micron

part numbers a t the FBGA P art M arking D ecoder sit e, http://www.micron.com/decoder .

To view the location of the abbreviated mark on the device, refer to customer service

note, CSN-11, “Product Mark/Label,” at www.micron.com/csn.

MT 45 W 2M W 16 P GA -70 WT ES

Micron Technology

Product Family

45 = PSRAM/CellularRAM Memory

Operating Core Voltage

W = 1.7V–1.95V

Address Locations

M = Megabits

Operating Voltage

W = 1.7V–3.6V

Bus Configuration

16 = x16

READ/WRITE Operation Mode

P = Asynchronous/Page

Package Codes

GA = VFBGA “Green” (6 x 8 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 48-ball

Production Status

Blank = Production

ES = Engineering Sample

MS = Mechanical Sample

Operating Temperature

WT = 30°C to +85°C (see Note 1)

IT = 40°C to +85°C

Standby Power Options

Blank = Standard

Access/Cycle Time

70 = 70ns

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32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

Functional Description

In ge neral, the MT45W2MW16P device i s a high-density alternative to SRAM and P seudo

SRAM products, popular in low-power, portable applications. The MT45W2MW16P

contains a 33,554,432-bit DRAM core organized as 2,097,152 addresses by 16 bits. These

devices include the ind u s try-standard, asynchronous memory interface fo und on othe r

low-power SRAM or Pseudo SRAM offerings. Page mode accesses ar e also included as a

bandwidth-enhancing extension to the asynchronous read protocol .

Power-Up Initialization

CellularRAM products include an on-chip voltage sensor that is used to launch the

power-up initialization process. Initialization will load the CR with its default setting.

VCC and VCCQ must be applied simultaneously, and when they reach a stable level abo v e

1.7V, the device will require 150µs to complete its self-initialization process (see

Figur e4). During the initialization period, CE # should r emain HIGH. When initialization

is complete, the device is ready for normal operation.

Figure 4: Power-Up Initialization Timing

Bus Operating Modes

The MT45W2MW16P Cel lularRAM product incor porates the industry-standar d, asyn-

chronous interface found on other low-po wer SRAM or Pseudo SRAM offerings. This bus

interface supports asynchronous READ and WRITE operations as well as the band-

width-enhancing page mode READ operation. The specific interface that is supported is

defined by the value loaded into the CR.

Asynchronous Mode

CellularRAM products power up in the asynchronous operating mode. This mode uses

the industry-standard SRAM control interface (CE#, OE#, WE#, LB#/UB#). READ opera-

tions (Figure5) are initiated by bringing CE#, OE#, and LB#/ UB # LOW while keeping

WE# HIGH. Valid data will be dri ven out of the I/Os after the specified access time has

elapsed. WRITE operations (Figure 6) occur when CE#, WE#, and LB#/UB# are driven

LOW. During WRITE operatio ns, the level of OE# is a “Don't Care”; WE# will override

OE#. The data to be written will be latched on the rising edge of CE#, WE#, or LB#/UB#,

whichever occurs first. WE# LOW time must be limited to tCEM.

Device ready for

normal operation

Vcc, VccQ = 1.7V tPU

Vcc (MIN)

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Bus Operating Modes

Figure 5: READ Operation

Figure 6: WRITE Operation

Valid address

DATA

CE#

Don’t Care

OE#

WE#

LB#/UB#

tRC = READ cycle time

ADDRESS

Valid data

Valid address

DATA

CE#

Don’t Care

OE#

WE#

LB#/UB#

tWC = WRITE cycle time

< tCEM

ADDRESS

Valid data

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32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

Bus Operating Modes

Page Mode READ Operation

Page mode is a performance-enhancing extension to the legacy asynchronous READ

operation. In page-mode-capable products, an initial asynchronous read access is

performed, then adjacent addresses can be quickly read by simply changing the low-

order address. Addresses A[3:0] are used to determi ne the member s of the 16-address

CellularRAM page. Any change in addresses A[4] or higher will initiate a new tAA access.

Figure 7 shows the ti ming diagram for a page mode access.

Page mode takes advantage of the fact that adjacent addresses can be read in a shorter

period of time than random addresses. WRITE operations do not include comparable

page mode functionality.

The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer

than tCEM.

Figure 7: Page READ Operation

LB#/UB# Operation

The lower byte (LB#) enable and upper byte (UB#) enable signals allow for byte-wide

data transfers. During READ operations, enabled bytes are driven onto the DQs. The

DQs associated with a disabled byte ar e put into a High-Z state during a READ opera-

tion. During WRITE operations, any disabled b ytes will not be transferr ed to the memory

array and the internal value will remain unchanged. During a WRITE cycle, the data to

be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.

When both the LB# and UB# are disabled (HIGH) during an operation, the device will

disable the data bus from receiving or transmitting data. Although the device will seem

to be deselected, the device remains in an active mode as long as CE# remains LOW.

DATA

CE#

OE#

WE#

LB#/UB#

ADDRESS Address[0]

D[1] D[2] D[3]

tAA tAPA tAPA tAPA

D[0]

< tCEM

Address

[2]

Don't Care

Address

[1] Address

[3]

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Low-Power Operation

Standby Mode Operation

During standby, the device current consumption is reduced to the level necessary to

perform the DRAM REFRESH operation on the full array. Standby operation occurs

when CE# and ZZ# are HIGH.

The device will enter a reduced power state upon completion of READ and WRITE oper-

ations where the address and control inputs remain static for an extended period of

time. This mode will continue until a change occurs to the address or control inputs.

Temperature-Compensated Refresh

Temperature-compensated refresh (TCR) allows for adequate refresh at differe nt

temperatures. This CellularRAM device includes an on-chip temperature sensor. It

continually adjusts the refresh rate according to the operating temperature.

Partial-Array Refresh

P artial-array r efresh (P AR) r estricts REFRESH operation to a portion of the total memory

array. This feature enables the system to r educe refresh current b y only refreshing that

part of the memory array that is absolutely necessary. The refresh options ar e full array,

one-half array, one-quarter array, one-eighth array, or none of the array. Data stored in

addresses not receiving refresh will become corrupted. The mapping of these partitions

can start at either the beginning or the en d of the address map (Table 3 on page 17).

READ and WRITE operations are ignored during PAR operation.

The device only enters PAR mode if the SLEEP bit in the CR has been set HIGH

(CR[4] = 1). PAR can be initiated by bring the ZZ# ball to the LOW state for longer than

10µs. Returning ZZ# to HIGH will cause an exit from PAR and the entir e array will be

immediately available for READ and WRITE operations.

Alternatively, PAR can be initiated using the CR software access s equence (s ee “Software

Access to the Configuration Register” on page 14). PAR is enabled immediately upon

setting CR[4] to “1” using this method. Ho wever, using software access to write to the CR

alters the function of ZZ# so that ZZ# LOW no longer initiates PAR, although ZZ#

continues to enable WRITEs to the CR. This functional change persists until the next

time the device is powered up (see Figure8 on page 13).

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Low-Power Operation

Figure 8: Software Access PAR Functionality

Deep Power-Down Operation

Deep power-down (DPD) operation disables all refresh-related activity. This mode is

used when the system does not require the storage provided by the Ce llularRAM device.

Any stored data will become corrupted when DPD is entered. When refresh activity has

been re-enabled, the CellularRAM device will require 150µs to perform an initialization

procedure before normal operations can resume. READ and WRITE operations are

ignored during DPD operation.

The device can only enter DPD if the SLEEP bit in the CR has been set LOW (CR[4] = 0).

DPD is initiated by bringing ZZ# to the LOW state for longer than 10µs. Returning ZZ# to

HIGH will cause the device to exit DPD and begin a 150µs initialization process. During

this 150µs period, the current consumption will be higher than the specified standby

levels but consi derably lower than the active current specification.

Driving ZZ# LOW will place the device in the PAR mode if the SLEEP bit in the CR has

been set HIGH (CR[4] = 1).

The device should not be put into DPD using CR software access.

YES

Powe

r-Up

To enable PAR,

bring ZZ# LOW

for 10µs.

Change to ZZ#

functionality;

PAR permanently

enabled

independent of

ZZ# level.

Software

LOAD

executed?

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Configuration Register Operation

The configuration register (CR) defines how the CellularRAM device performs its trans-

parent self refresh. Altering the refresh parameters can dramatically reduce current

consumption during standby mode. Page mode control is also embedded into the CR.

This register can be updated any time the device is operating in a standby state.

Figure 12 on page 16 describes the control bits used in the CR. At power-up, the CR is set

to 0010h.

Access Using ZZ#

The CR can be loaded using a WRITE operation immediately after ZZ# makes a HIGH-

to-LOW transition (see Figur e9). The values placed on addr esses A[19:0] ar e latche d into

the CR on the rising edge of CE# or WE#, whichever occurs first. LB#/UB# are “Don’t

Care.” Access using ZZ# is WRITE only.

Figure 9: Load Configuration Register Operation

Software Access to the Configuration Register

The contents of the CR can either be read or modified using a software sequence. The

nature of this access mechanism may eliminate the need for the ZZ# ball.

If the software mechanism is used, ZZ# can simply be tied to VCCQ. The port line typi-

cally used for ZZ# control purposes will no longer be required. However, ZZ# should not

be tied to VCCQ if the s ystem will use DPD; DPD cannot be enabled or disabled usi ng the

software access sequen ce.

The CR is loaded using a four -step sequence consisting of two READ operations foll o wed

b y two WRITE operations (see Figur e10 on page 15). The read s equence is virtually i den-

tical except that an asynchronous READ is performed during the fourth operation (see

Figure 11 on page 15). Note that a third READ cycle of the highest ad dr ess will cancel the

access sequence until a different address is read.

The address used during all READ and WRITE operations is the highest address of the

CellularRAM device being accessed (1FFFFFh for 32Mb); the content of this address is

not changed by using this sequence. The data bus is used to transfe r data into or out of

bits 15–0 of the CR.

Writing to the CR using the softwar e sequence modifies the function of the ZZ# ball.

After the software sequence loads the CR, the level of the ZZ# ball no longer enabl es PAR

operation. PAR operation will be updated whenever the software sequence loads a new

value into the CR. This ZZ# functionality will continue until the next time the device is

po wered-up. The operation of the ZZ# ball is not affected if the software sequence is only

used to re ad the contents of the CR. The use of the software sequence does not affect the

ability to perform the standard (ZZ#-controlled) method of loading the CR.

Valid address

CE#

ZZ#

WE# t < 500ns

ADDRESS

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Configuration Register Operation

Figure 10: Software Access Load Configuration Register

Figure 11: Software Access Read Configuration Register

Address

(MAX) Address

(MAX)

XXXXh XXXXh CR value

ADDRESS

CE#

OE#

WE#

LB#/UB#

DATA

Don't Care

READ READ WRITE WRITE

Address

(MAX)

0000h

Address

(MAX) Address

(MAX)

XXXXh XXXXh CR value

out

ADDRESS

CE#

OE#

WE#

LB#/UB#

DATA

Don't Care

READ READ WRITE READ

Address

(MAX)

0000h

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32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

Configuration Register Operation

Figure 12: Configuration Register Bit Mapping

Partial-Array Refresh (CR[2:0]) Default = Full-Array Refresh

The PAR bits restrict REFRESH operation to a portion of the total memory array. This

feature allows the system to reduce current by only refreshing that part of the memory

array required by the host system. The refresh options are full array, one-half array, one-

quarter array, one-eighth array, or none of the array. The mapping of these partitions can

start at either th e be g inni ng or th e end of the address map (see Table 3 on page 17).

Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled

The sleep mode bit determines which low-power mode is to be entered when ZZ# is

driven LOW. If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is

enabled. PAR can also be enabled directly by writing to the CR using the software access

sequence. Note that this then disables ZZ# initiation of PAR. DPD cannot be enabled or

disabled using the software access sequence; this should only be done using ZZ# to

access the CR.

DPD operation disables all refresh-related activity. This mode will be used when the

system does not r equire the s torage pro vided b y the CellularRAM device . Any store d data

will become corrupted when DPD is enabled. When refr esh activity has been r e-enabled,

the CellularRAM device will require 150µs to perform an initialization procedure before

normal operation can resume. DPD should not be enabled using CR software access.

PAR

A4 A3 A2 A1 A0 Address Bus

4 1

3 0

Reserved

6 5

Sleep Mode

DPD enabled

PAR enabled (default)

CR[4]

Ignored

20–8

Reserved

A[20:8]

CR[1] CR[0] PAR Refresh Coverage

CR[2]

Sleep

Setting is ignored

(default 00b)Must be set to "0" All must be set to "0"

Page

Page Mode Enable/Disable

Page mode disabled (default)

Page mode enabled

CR[7]

Full array (default)

Bottom 1/2 array

Bottom 1/4 array

Bottom 1/8 array

None of array

Top 1/2 array

Top 1/4 array

Top 1/8 array

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Electrical Characteristics

Page Mode READ Operation (CR[7]) Default = Disabled

The page mode operation bit determines whether page mode READ ope rations are

enabled. In the po wer-up defaul t state, page mode is disabled.

Electrical Characteristics

S tresses greater than those listed in Table 4 may cause permanent damage to the devi ce.

This is a stress rating only, and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may

affect reli ability.

Notes: 1. –30°C exceeds the CellularRAM Workgroup 1.0 specification of –25°C.

Table 3: 32Mb Address Patterns for PAR (CR[4] = 1)

CR[2] CR[1] CR[0] Active Section Address Space Size Density

0 0 0 Full die 000000h–1FFFFFh 2 Meg x 1632Mb

0 0 1 One-half of die 000000h–0FFFFFh 1 Meg x 1616Mb

0 1 0 One-quar ter of die 000000h–07 FFFFh 512K x 168Mb

0 1 1 One-eighth of die 000000h–03FFFFh 256K x 164Mb

1 0 0 None of die 0 0 Meg x 160Mb

1 0 1 One-half of die 100000h–1FFFFFh 1 Meg x 1616Mb

1 1 0 One-quarter of die 180000h–1FFFFFh 512K x 168Mb

1 1 1 One-eighth of die 1C0000h–1FFFFFh 256K x 164Mb

Ta ble 4: Absolute Maximum Ratings

Parameter Rating

Voltage to any ball except VCC, VCCQ relative to VSS –0 .5V to (4.0V or VCCQ + 0.3V, whichever is less)

Voltage on VCC supply relative to VSS –0.2V to +2.45V

Voltage on VCCQ supply relative to VSS –0.2V to +4.0V

Storage temperature –55°C to +150°C

Operating temperature (case)

Wireless1

Industrial –30°C to +85°C

–40°C to +85°C

Soldering temperature and time

10 seconds (solder ball only) 260°C

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Electrical Characteristics

Notes: 1. –30°C exceeds the CellularRAM Workgroup 1.0 specification of –25°C.

2. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions.

3. VIH (MIN) value is not aligned with CellularRAM Workgroup 1.0 specification of

VCCQ - 0.4V.

4. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions.

5. This parameter is specified with the outputs disabled to avoid external loading effects. The

user must add the current required to drive output capacitance expected in the actual sys-

tem.

6.I

SB (MAX) values measured with PAR set to FULL ARRAY and at +85°C. In order to achieve

low standby current, all inputs must be driven to VCCQ or VSS. ISB may be slightly higher for

up to 500ms after power-up or when en te r i n g standby mode .

Maximum and Typical Standby Currents

The follo wing table and figur e r efer to the maximu m and typical standb y cur re nts for the

MT45W2MW16PGA device. The typical values shown in Figure 13 on page 19 are

measured with the default on-chip temperature sensor control enabled.

Notes: 1. IPAR (MAX) values measured at 85°C. IPAR might be slightly higher for up to 500ms after

changes to the PAR array partition or when entering standby mode. In order to achieve low

standby current, all inputs must be driven to either VCCQ or VSS.

Table 5: Electrical Characteristics and Operating Conditions

Wireless temperature1 (–30ºC ≤ TC ≤ +85 ºC), Industrial temperature (–40ºC < TC < +85ºC)

Description Conditions Symbol Min Max Units Notes

Supply voltage VCC 1.7 1.95 V

I/O supply voltage VCCQ1.73.6V

Input high volt ag e VIH 1.4 VCCQ + 0.2 V 2, 3

Input low voltage VIL -0.2 +0.4 V 4

Output high voltage IOH = –0.2mA VOH 0.8 VCCQV

Output low voltage IOL = 0.2mA VOL 0.2 VCCQV

Input leakage current VIN = 0 to VCCQILI 1μA

Output leakage current OE# = VIH or

Chip disabled ILO 1μA

Operating Current

Asynchronous random

READ/WRITE VIN = VCCQ or 0V

Chip enabled; IOUT = 0 ICC1 –70 20 mA 5

Asynchronous page READ ICC1P –70 15 mA 5

Standby current VIN = VCCQ or 0V

CE# = VCCQISB 110 μA6

Table 6: Partial-Array Refresh Specifications and Conditions

Description Conditions Symbol Array Partit ion Max Unit

Partial-array refresh

standby current VIN = VCCQ or 0V;

CE# = VCCQIPAR Standard power

(no designation) Full 110 µA

1/2 105

1/4 95

1/8 95

070

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Electrical Characteristics

Figure 13: Typical Refresh Current vs. Temperature

Notes: 1. These parameters are verified in device characterization and are not 100-percent tested.

Figure 14: AC Input/Output Reference Waveform

Notes: 1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall

times (10 percent to 90 percent) < 1.6ns.

2. Input timing begins at VCC/2. Due to the possibility of a difference between VCC and VCCQ,

the input test point may not be shown to scale.

3. Output timing ends at VCCQ/2.

Table 7: Deep Power-Down Specifications and Conditions

Description Conditions Symbol TYP Units

Deep power-down VIN = VCCQ or 0V; +25°C

ZZ# = 0V

CR[4] = 0

IZZ 10 µA

Table 8: Capacitance Specifications and Conditions

Description Conditions Symbol Min Max Units Notes

Input capacitance TC = +25ºC; f = 1 MHz;

VIN = 0V CIN 2.0 6.5 pF 1

Input/output capacitance (DQ) CIO 3.0 6.5 pF 1

-45C

-35C

-25C

-15C

-05C

05C

15C

25C

35C

45C

55C

65C

75C

85C

Temperature (°C)

ISB (µA)

95C

PAR FULL

PAR 1/2

PAR 1/4

PAR 0

Output

Test Points

Input

VCC

VSS

VCCQ/2

VCC/2

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Electrical Characteristics

Figure 15: Output Load Circuit

Notes: 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 15 on page 20. The Low-

Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either

VOH or VOL.

2. Low-Z to High-Z timings are tested with the circuit shown in Figure 15 on page 20. The

High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.

3. Page mode enabled only.

Table 9: READ Cycle Timing Requirements

Parameter Symbol

–70

Units NotesMin Max

Address access time tAA 70 ns

Page access time tAPA 20 ns

LB#/UB# access time tBA 70 ns

LB#/UB# disable to High-Z output tBHZ 8ns2

LB#/UB# enable to Low-Z output tBLZ 10 ns 1

Maximum CE# pulse width tCEM 8µs3

Chip select access time tCO70 ns

Chip disable to High-Z output tHZ 8ns2

Chip enable to Low-Z output tLZ 10 ns 1

Output enable to valid output tOE 20 ns

Output hold from address change tOH 5ns

Output disable to High-Z output tOHZ 8ns2

Output enable to Low-Z output tOLZ 5ns1

Page cycle time tPC20 ns

Read cycle time tRC70 ns

DUT

VccQ/2

30pF

Test Point

50Ω

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Electrical Characteristics

Notes: 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 15 on page 20. The Low-

Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either

VOH or VOL.

2. Low-Z to High-Z timings are tested with the circuit shown in Figure 15 on page 20. The

High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.

3. WE# LOW time must be limited to tCEM (8µs).

Table 10: WRITE Cycle Timing Requirements

Parameter Symbol

–70

Units NotesMin Max

Address setup time tAS 0ns

Address valid to end of write tAW 70 ns

Byte select to end of write tBW 70 ns

CE# HIGH time during write tCPH 5ns

Chip enable to end of write tCW70 ns

Data hold from write time tDH 0ns

Data write setup time tDW 23 ns

Chip enable to Low-Z output tLZ 10 ns 1

End write to Low-Z output tOW 5ns1

WRITE cycle time tWC 70 ns

Write to High-Z output tWHZ 8ns2

Write pulse width tWP 46ns 3

Write pulse width HIGHtWPH 10 ns

Write recovery time tWR 0ns

Ta ble 11: Load Configuration Register Timing Requirements

Description Symbol

–70

Units Min Max

Address setup time tAS 0ns

Address valid to end of write tAW 70 ns

Chip deselect to ZZ# LOW tCDZZ 5ns

Chip enable to end of write tCW70 ns

WRITE cycle time tWC70 ns

Write pulse width tWP 40 ns

Write recovery time tWR 0ns

ZZ# LOW to WE# LOW tZZWE 10 500 ns

Table 12: Deep Power-Down Timing Requirements

Description Symbol

–70

Units Min Max

Chip deselect to ZZ# LOW tCDZZ 5ns

Deep power-down recovery tR150 µs

Minimum ZZ# pulse width tZZ (MIN) 10 µs

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Timing Diagrams

Figure 16: Power-Up Initialization Period

Figure 17: Load Configuration Register

Figure 18: Deep Power-Down Entry and Exit

Table 13: Initia lization Timing Parameters

Parameter Symbol

-70

UnitsMin Max

Initialization period (required before normal operations) tPU 150 µs

Device ready for

normal operation

Vcc, VccQ = 1.7V tPU

Vcc (MIN)

ADDRESS

ZZ#

tWC

tAW tWR

tAS

CE#

LB#/UB#

tZZWE

Don’t Care

WE#

tWP

tCDZZ

OPCODE

tCW

OE#

ZZ#

CE#

tZZ (M IN)

Don’t Care

tCDZZ

Device ready for

normal operation

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32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

Timing Diagrams

Figure 19: Single READ Operation (WE# = VIH)

Figure 20: Page Mode READ Operation (WE# = VIH)

ADDRESS

OE#

tRC

tAA

DATA-OUT

CE#

LB#/UB#

tOLZ

Don’t Care Undefined

High-Z High-Z

Valid data

tOHZ

tBA tBHZ

tHZ

tBLZ

tCO

Valid address

tOE

tLZ

ADDRESS

A[20:4]

OE#

tAA

DATA-OUT

CE#

LB#/UB#

tOLZ

tLZ

Don’t Care Undefined

High-Z High-Z

Valid

data

tOHZ

tBA tBHZ

tHZ

tCEM

tBLZ

tCO

ADDRESS

A[3:0]

tRC

tOH

tPC

Valid address

tAPA

tOE

Valid

data Valid

data

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32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

Timing Diagrams

Figure 21: WRITE Cycle (WE# Control)

Figure 22: WRITE Cycle (CE# Control)

ADDRESS

WE#

tWC

tAW tWR

DATA-IN

CE#

LB#/UB#

tBW

tWHZ tOW

tDH

tDW

tAStWP tWPH

Don’t Care

High-Z

DATA-OUT

Valid data

tCW

OE#

Valid address

ADDRESS

WE#

tWC

tAW

tCW

tWR

tCPH

DATA-IN

CE#

LB#/UB#

tBW

tWHZ

tLZ

tAS

tDH

tDW

tWP

Don’t Care

High-Z

DATA-OUT

Valid data

Valid address

OE#

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32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

Timing Diagrams

Figure 23: WRITE Cycle (LB#/UB# Control)

ADDRESS

WE#

tWC

tAW tWR

DATA-IN

CE#

LB#/UB#

tBW

tWHZ

tDH

tAS

tDW

tLZ

Don’t Care

DATA-OUT

Valid data

Valid address

tCW

OE#

High-Z

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prodmktg@micron.com www.micron.com Customer Comm en t Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron

Technology, Inc., inside the U.S. and a trademark of Qimonda AG outside the U.S. All other trademarks are the property of

their respective owners. This data sheet contains minimum and maximum limits specified over the compl ete power supply

and temperature range for production devices. Although considered final, these specifications are subject to change, as fur-

ther product development and data characterization sometimes occur.

32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

Package Dimensions

PDF: 09005aef82832fa7 / Source: 09005aef82832f97 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

Package Dimensions

Figure 24: 48-Ball VFBGA

Notes: 1. All dimensions are in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is

0.25mm per side.

3. The MT45W2MW16PGA uses “green” packaging.

BALL A1 ID

1.00 MAX

4.00 ±0.05

3.00 ±0.051.875

6.00 ±0.10

SOLDER BALL MATERIAL:

96.5% Sn, 3% Ag, 0.5% Cu

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE MATERIAL: PLASTIC LAMINATE

0.75

TYP

0.75 TYP

8.00 ±0.10

5.25

2.625

BALL A1

BALL A1 ID

3.75

0.70 ±0.05

SEATING

PLANE

0.10 A

BALL A6

DIMENSIONS APPLY

TO SOLDER BALLS

POST REFLOW.

PRE-REFLOW BALL

DIAMETER IS 0.35

ON A 0.30 SMD

BALL PAD.

48X Ø0.37