ADS5220RGZ - Texas Instruments High-Performance Analog

ADS5220

12-Bit, 40MSPS Sampling, +3.3V

ANALOG-TO-DIGITAL CONVERTER

FEATURES

●HIGH SNR: 70dB

●HIGH SFDR: 88dBFS

●LOW POWER: 195mW

●INTERNAL/EXTERNAL REFERENCE OPTION

●SINGLE-ENDED OR

FULLY DIFFERENTIAL ANALOG INPUT

●PROGRAMMABLE INPUT RANGE

●LOW DNL: 0.3LSB

●SINGLE +3.3V SUPPLY OPERATION

●TQFP-48 PACKAGE

APPLICATIONS

●WIRELESS LOCAL LOOP

●COMMUNICATIONS

●MEDICAL IMAGING

● PORTABLE INSTRUMENTATION

DESCRIPTION

The ADS5220 is a pipeline, CMOS Analog-to-Digital Con-

verter (ADC) that operates from a single +3.3V power

supply. This converter can be operated with a single-ended

input or differential input. The ADS5220 includes a 12-bit

quantizer, high bandwidth track-and-hold, and an internal

reference. It also allows the user to disable the internal

reference and utilize external references which provide ex-

cellent gain and offset matching when used in multi-channel

applications or in applications where full-scale range adjust-

ment is required.

The ADS5220 employs digital error correction techniques to

provide excellent differential linearity for demanding imag-

ing applications. Its low distortion and high SNR give the

extra margin needed for medical imaging, communications,

video, and test instrumentation. The ADS5220 offers power

dissipation of 195mW and also provides two power-down

modes.

The ADS5220 is specified at a maximum sampling fre-

quency of 40MSPS and a differential input range of

1V to 2V. The ADS5220 is available in a TQFP-48 package.

ADS5220

SBAS261A – APRIL 2003 – REVISED MARCH 2004

12-Bit

Pipelined

ADC

Internal

Reference

Timing/Duty Cycle

Adjust

Circuitry

Error

Correction

Logic

3-State

Output

S/H

CLK VDRV

ADS5220

OERSELREFBREFT

OVR

QPDSTPD

D11

•

VREF

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PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

ADS5220

2SBAS261A

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SPECIFIED

PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE-LEAD DESIGNATOR(1) RANGE MARKING NUMBER MEDIA, QUANTITY

ADS5220 TQFP-48 PFB –40°C to +85°C ADS5220PFB ADS5220PFBT Tape and Reel, 250

" " " " " ADS5220IPFBR Tape and Reel, 2000

ADS5220 QFN-48(2) RGZ –40°C to +85°C ADS5220RGZ ADS5220RGZ Rails, 52

" " " " " ADS5220IRGZR Tape and Reel, 1000

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

(2) This package available Q2 2004.

ADS5220

PARAMETER CONDITIONS MIN TYP MAX UNITS

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may be

more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

AVDD, DVDD, VDRV........................................................................... +3.8V

Analog Input............................................................. –0.3V to (+VS + 0.3V)

Logic Input ............................................................... –0.3V to (+VS + 0.3V)

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature..................................................................... +150°C

NOTE: (1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods may degrade

device reliability.

ABSOLUTE MAXIMUM RATINGS(1)

PACKAGE/ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS: AVDD = 3.3V

TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3, VDRV = 2.5V, –1dBFS, DCA

off, internal reference voltage, and 2VPP differential input, unless otherwise noted.

RESOLUTION 12 Tested Bits

SPECIFIED TEMPERATURE RANGE Ambient Air –40 to +85 °C

ANALOG INPUT

Single-Ended Input Range 2VPP 0.5 2.5 V

Optional Single-Ended Input Range 1VPP 12V

Differential Input Range 2VPP 12V

Analog Input Bias Current 1µA

Input Impedance Static, No Clock 1.25 || 5 MΩ || pF

Analog Input Bandwidth –3dBFS Input 300 MHz

CONVERSION CHARACTERISTICS

Sample Rate 1M 40M Samples/s

Data Latency 5 Clock Cycle

Clock Duty Cycle Mode Select Enabled 35 to 65 %

DYNAMIC CHARACTERISTICS

Differential Linearity Error (largest code error)

f = 2.4MHz ±0.3 ±0.75 LSB

f = 9.7MHz ±0.35 LSB

No Missing Codes Tested

Integral Nonlinearity Error, f = 2.4MHz ±0.7 ±1.5 LSBs

Spurious-Free Dynamic Range(1) Referred to Full-Scale

f = 2.4MHz 88 dBFS(2)

f = 9.7MHz 83 88 dBFS

f = 19.8MHz 76 dBFS

2-Tone Intermodulation Distortion(3)

f = 9.5MHz and 10.5MHz (–7dB each tone) 86.3 dBc

Signal-to-Noise Ratio (SNR) Referred to Full-Scale

f = 2.4MHz 70 dBFS

f = 9.7MHz 68.5 70 dBFS

f = 19.8MHz 69 dBFS

Signal-to-(Noise + Distortion) (SINAD) Referred to Full-Scale

f = 2.4MHz 69 dBFS

f = 9.7MHz 68 69 dBFS

f = 19.8MHz 68 dBFS

Effective Number of Bits(4), f = 2.4MHz 11.2 Bits

Output Noise Input Tied to Common-Mode 0.3 LSBrms

Aperture Delay Time 3ns

Aperture Jitter 1.2 ps rms

Over-Voltage Recovery Time 1.0 Clock Cycle

Full-Scale Step Acquisition Time 5ns

ADS5220 3

SBAS261A www.ti.com

DIGITAL INPUTS

Logic Family

Convert Command Start Conversion

High Level Input Current(5) (VIN = 3VDD)100 µA

Low Level Input Current (VIN = 0V) 10 µA

High Level Input Voltage +1.7 V

Low Level Input Voltage +0.7 V

Input Capacitance 5pF

DIGITAL OUTPUTS

Logic Family

Logic Coding

Low Output Voltage (IOL = 50µA to 1.5mA) VDRV = 2.5V +0.1 V

High Output Voltage (IOH = 50µA to 0.5mA) +2.4 V

3-State Enable Time

= H 20 40 ns

3-State Disable Time

= L 2 10 ns

Output Capacitance 5pF

ACCURACY (Internal Reference, 2VPP,

unless otherwise noted)

Zero Error (referred to midscale) fIN = 2.4MHz, at 25°C±0.75 ±1.5 %FS

Zero Error Drift (referred to midscale) fIN = 2.4MHz 5 ppm/°C

Gain Error(6) at 25°C±0.4 ±3.0 %FS

Gain Error Drift 38 ppm/°C

Power-Supply Rejection of Gain ∆ VS = ±5% 52 dB

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1V) ±10mV mV

Load Regulation at 1mA 0.15%

Output Voltage Error (0.5V) ±5mV mV

Load Regulation at 0.5mA 0.1%

POWER-SUPPLY REQUIREMENTS

Supply Voltage: AVDD, DVDD Operating +3.0 +3.3 +3.6 V

Driver Supply Voltage +2.3 2.5 +3.6 V

Supply Current: +ISOperating (External Reference) 59 mA

Power Dissipation: VDRV = 2.5V 195 215 mW

VDRV = 3.3V 200 mW

Standard Power-Down 15 mW

Quasi-Power-Down 75 mW

Thermal Resistance,

TQFP-48 63.7 °C/W

QFN-48 26.1 °C/W

NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic.

(2) dBFS means dB relative to Full-Scale.

(3) 2-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-

tone fundamental envelope.

(4) Effective Number of Bits (ENOB) is defined by (SINAD – 1.76)/6.02.

(5) A 50kΩ pull-down resistor is inserted internally on the

pin.

(6) Includes internal reference.

ELECTRICAL CHARACTERISTICS: AVDD = 3.3V

TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3, VDRV = 2.5V, –1dBFS, DCA

off, internal reference voltage, and 2VPP differential input, unless otherwise noted.

ADS5220

PARAMETER CONDITIONS MIN TYP MAX UNITS

CMOS-Compatible

Rising Edge of Convert Clock

CMOS-Compatible

Straight Offset Binary or BTC

ADS5220

4SBAS261A

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25 NC No Internal Connection

26 NC No Internal Connection

27 AGND Analog Ground

28 AGND Analog Ground

29 AGND Analog Ground

30 VREF Internal Reference Voltage (1/2V Reference)

31 RSEL Reference Mode Select (see Table I for

settings)

32 REFB Bottom Reference Bypass

33 NC No Internal Connection

34 REFT Top Reference Bypass

35 NC No Internal Connection

36 AVDD Analog Supply

37 AVDD Analog Supply

38 AGND Analog Ground

39 AGND Analog Ground

40 AGND Analog Ground

41 I IN Analog Input

42 I IN Complementary Analog Input

43 DGND Digital Ground

44 DGND Digital Ground

45 DGND Digital Ground

46 I CLK Convert Clock Input

47 I DVDD Digital Supply

48 I DVDD Digital Supply

PIN I/O NAME DESCRIPTION

1 MSBI Most Significant Bit Invert (HI = Binary Two’s

Complement, LO = Straight Offset Binary)

2 OE Tri-State (LO = Enabled, HI = Tri-State)

3 Mode Select Duty Cycle Stablilizer (HI = Enabled,

LO = Normal Operation)

4 STPD Standard Power Down (LO = Normal

Operation, HI = Enabled)

5 QPD Quasi Power Down (LO = Normal Operation,

HI = Enabled)

6 GDRV Output Driver Ground

7 GDRV Output Driver Ground

8 VDRV Output Driver Supply

9 VDRV Output Driver Supply

10 O D11 (MSB) Data Bit 12

11 O D10 Data Bit 11

12 O D9 Data Bit 10

13 O D8 Data Bit 9

14 O D7 Data Bit 8

15 O D6 Data Bit 7

16 O D5 Data Bit 6

17 O D4 Data Bit 5

18 O D3 Data Bit 4

19 O D2 Data Bit 3

20 O D1 Data Bit 2

21 O D0 (LSB) Data Bit 1

22 NC No Internal Connection

23 NC No Internal Connection

24 OVR Over-Range Indicator

PIN ASSIGNMENTS

PIN I/O NAME DESCRIPTION

PIN CONFIGURATION

REFT

REFB

RSEL

REF

AGND

CLK

DGND

AGND

D0 (LSB)

OVR

MSBI

Mode Select

STPD

QPD

GDRV

VDRV

D11 (MSB)

D10

48 47 46 45 44 43 42 41 40 39 38

13 14 15 16 17 18 19 20 21 22 23

ADS5220

ADS5220 5

SBAS261A www.ti.com

TIMING DIAGRAM

SYMBOL DESCRIPTION MIN TYP MAX UNITS

tCONV Convert Clock Period 25 1µsns

tLClock Pulse LOW 8.75 12.5 ns

tHClock Pulse HIGH 8.75 12.5 ns

tDAperture Delay 3 ns

t1Data Hold Time, CL = 0pF 3.9 ns

t2New Data Delay Time, CL = 15pF max 12 ns

5 Clock Cycles

Data Invalid

CONV

N – 5N – 4N – 3N – 2N – 1 N N + 1 N + 2

Data Out

Clock

Analog In N

N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7

ADS5220

6SBAS261A

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TYPICAL CHARACTERISTICS: AVDD = 3.3V

TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3V, VDRV = 2.5V, –1dBFS,

DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted.

SPECTRAL PERFORMANCE

(Differential, 2V

)

Amplitude (dB)

Frequency (MHz)

−20

−40

−60

−80

−100

−120 0 2 4 6 8 101214161820

= 2.4MHz (−1dBFS)

SFDR = 88.2dBFS

SNR = 70.0dBFS

SINAD = 69.9dBFS

SPECTRAL PERFORMANCE

(Differential, 2VPP)

Amplitude (dB)

Frequency (MHz)

−20

−40

−60

−80

−100

−120 0 2 4 6 8 101214161820

fIN = 9.7MHz (−1dBFS)

SFDR = 88.4dBFS

SNR = 69.8dBFS

SINAD = 69.7dBFS

SPECTRAL PERFORMANCE

EXTERNAL REFERENCE

(Differential, 2V

)

Amplitude (dB)

Frequency (MHz)

−20

−40

−60

−80

−100

−120 0 2 4 6 8 101214161820

= 9.7MHz (−1dBFS)

SFDR = 88.7dBFS

SNR = 69.3dBFS

SINAD = 69.1dBFS

SPECTRAL PERFORMANCE

PROGRAMMED REFERENCE

(Differential, 1.5V

)

Amplitude (dB)

Frequency (MHz)

−20

−40

−60

−80

−100

−120 0 2 4 6 8 101214161820

= 2.4MHz (−1dBFS)

SFDR = 88.8dBFS

SNR = 70.0dBFS

SINAD = 70.0dBFS

SPECTRAL PERFORMANCE

(Differential, 1V

)

Amplitude (dB)

Frequency (MHz)

−20

−40

−60

−80

−100

−120 0 2 4 6 8 101214161820

= 9.7MHz (−1dBFS)

SFDR = 84.9dBFS

SNR = 67.4dBFS

SINAD = 67.3dBFS

SPECTRAL PERFORMANCE

(Single-Ended, 1V

)

Amplitude (dB)

Frequency (MHz)

−20

−40

−60

−80

−100

−120 0 2 4 6 8 101214161820

= 9.7MHz (−1dBFS)

SFDR = 84.0dBFS

SNR = 67.1dBFS

SINAD = 66.9dBFS

ADS5220 7

SBAS261A www.ti.com

TYPICAL CHARACTERISTICS: AVDD = 3.3V (Cont.)

TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3V, VDRV = 2.5V, –1dBFS,

DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted.

DIFFERENTIAL LINEARITY ERROR

EXTERNAL REFERENCE

DLE (LSB)

Code

0 1024 2048 3072 4096

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

= 9.7MHz

SPECTRAL PERFORMANCE

(Single-Ended, 2VPP)

Amplitude (dB)

Frequency (MHz)

−20

−40

−60

−80

−100

−120 0 2 4 6 8 101214161820

fIN = 9.7MHz (−1dBFS)

SFDR = 80.2dBFS

SNR = 69.6dBFS

SINAD = 69.1dBFS

TWO-TONE INTERMODULATION DISTORTION

Amplitude (dB)

Frequency (MHz)

−20

−40

−60

−80

−100

−120 0 2 4 6 8 101214161820

= 9.5MHz (−7dBFS)

= 10.5MHz (−7dBFS)

SFDR = 93.3dBFS

INTEGRAL LINEARITY ERROR

ILE (LSB)

Code

0 1024 2048 3072 4096

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

= 9.7MHz

INTEGRAL LINEARITY ERROR

EXTERNAL REFERENCE

ILE (LSB)

Code

0 1024 2048 3072 4096

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

fIN = 9.7MHz

DIFFERENTIAL LINEARITY ERROR

DLE (LSB)

Code

0 1024 2048 3072 4096

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

= 9.7MHz

ADS5220

8SBAS261A

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TYPICAL CHARACTERISTICS: AVDD = 3.3V (Cont.)

TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3V, VDRV = 2.5V, –1dBFS,

DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted.

SFDR/SNR vs CLOCK DUTY CYCLE

(DCA = Duty Cycle Adjust)

SFDR, SNR (dBFS)

Duty Cycle (%)

30 50 55 60 6540 4535 70

SFDR: DCA on

SNR: DCA on

SFDR: DCA off

SNR: DCA off

SWEPT POWER (SNR)

EXTERNAL REFERENCE

SNR (dBc, dBFS)

Analog Input Level (dBFS)

–80 –40 –30 –20 –10–50–60–70 0

dBc

−10

−20

dBFS

= 9.7MHz

SWEPT POWER (SFDR)

SFDR (dBc, dBFS)

Analog Input Level (dBFS)

–80 –40 –30 –20 –10–50–60–70 0

dBc

100

dBFS

= 9.7MHz

SNR, SFDR vs INPUT FREQUENCY

SNR, SFDR (dBFS)

Frequency (MHz)

110

100

SFDR

SNR

DYNAMIC PERFORMANCE vs TEMPERATURE

SFDR, SNR (dBFS)

Temperature (°C)

−50 25 50 750−25 100

SFDR

SNR

fIN = 2.4MHz

DYNAMIC PERFORMANCE vs TEMPERATURE

SFDR, SNR (dBFS)

Temperature (°C)

−50 25 50 750−25 100

SFDR

SNR

fIN = 9.7MHz

ADS5220 9

SBAS261A www.ti.com

OUTPUT NOISE HISTOGRAM (DC Output)

Counts

Code

60000

50000

40000

30000

20000

10000

N – 2N – 1 N N + 1 N + 2

TYPICAL CHARACTERISTICS: AVDD = 3.3V (Cont.)

TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3V, VDRV = 2.5V, –1dBFS,

DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted.

APPLICATION INFORMATION

THEORY OF OPERATION

The ADS5220 is a 12-bit, 40MSPS, CMOS ADC designed

with a fully differential pipeline architecture. The pipeline

consists of three sections: a 3-bit quantizer, eight middle

stages with a 1.5-bit quantizer for each stage, and a 4-bit

flash. The output of each pipeline stage is processed and

formed into 12-bit data in the digital error correction logic

section to ensure good differential linearity of the ADC. The

converter includes a high bandwidth track-and-hold amplifier

in the input stage as shown in Figure 1. The rising edge of

the input clock initiates the conversion process. Once the

signal is captured by the input track-and-hold, the bits are

sequentially encoded starting with the Most Significant Bit

(MSB). This process results in a data latency of 5 clock

cycles. The ADS5220 includes a high accuracy internal

reference and also allows the use of an external reference.

The input full-scale range is up to 2VPP and is selectable

based on the reference voltage setting. For normal opera-

tion, both analog inputs (IN,

) require an external common-

mode voltage as a bias. The output data of the ADS5220 is

available as a 12-bit parallel word, either coded in a Straight

Offset Binary or Binary Two’s Complement format. The

ADS5220 includes an on-chip duty-cycle adjust (DCA)

circuit, controlled through the state of the

Mode Select

T&H

CIN

VBIAS

CIN

Tracking Phase: S1, S2, S3, S4closed; S5, S6 open

Hold Phase: S1, S2, S3, S4open; S5, S6 closed

FIGURE 1. Simplified Circuit of Input Track-and-Hold Amplifier

of ADS5220.

(3). When activated, this duty-cycle adjust circuit can accom-

modate for an incoming clock duty-cycle range of 35% to

65%, and re-time it to a 50% duty-cycle, which allows for

optimum internal clock timing. The ADS5220 has low power

dissipation in normal mode and has two power-down modes.

The device operates from a single +3.3V power supply and

has a separate digital output driver supply pin.

ADS5220

10 SBAS261A

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INPUT COMMON-MODE VOLTAGE

The ADS5220 operates from a single +3.3V supply, and

requires an external common-mode voltage. This allows a

symmetrical signal swing while maintaining sufficient head-

room to the supply rails. The common-mode voltage can be

generated from an external DC voltage source (for example,

an analog +3.3V supply with a simple resistor divider), or

from the input signal source with DC-coupling. For a single-

ended input configuration, the common-mode voltage is

typically +1.25V. When the input configuration is differential,

the common-mode voltage is +1.5V.

INPUT FULL-SCALE RANGE

The input full-scale range (FSR) of the ADS5220 is select-

able from 1VPP to 2VPP and any value within this range, by

the configuration of the reference select pin RSEL and

reference voltage pin VREF (see Table I). The input FSR

(differential) is always twice VREF (the voltage at the VREF pin)

for all reference modes.

By choosing different signal input ranges, trade-offs can be

made between noise and distortion performance. For ex-

ample, applications requiring the maximum signal-to-noise

performance (SNR) will benefit from the 2VPP input range

while lower distortion may be obtain with the reduced input

range of 1VPP. Depending on the input driver configuration

the 1VPP range may also relax the requirements for the

driver, particularly for single-ended, single supply applica-

tions.

DIFFERENTIAL INPUTS

The ADS5220 input structure is designed to accept both a

single-ended or differential analog signal. However, the

ADS5220 will achieve its optimum performance when the

analog inputs are driven differentially.

Differential operation of the ADS5220 requires that an input

signal at the inputs (IN,

) has the same amplitude and is

180 degrees out-of-phase. Differential signals offer a number

of advantages:

• The signal amplitude is half that required for the single-

ended operation, and is therefore less demanding to achieve,

while maintaining good linearity performance from the

signal source.

• The reduced signal swing allows for more headroom of the

interface circuitry, and therefore also allows a wider selec-

tion of the most suitable driver amplifier.

• Minimization of even-order harmonics.

• Improved noise immunity based on the common-mode

input rejection of the converter.

ANALOG INPUT

Depending on the application and the desired level of perfor-

mance, the analog input of the ADS5220 can be configured

in various ways and driven with different circuits. In any case,

the analog interface requirements should be carefully exam-

ined before selecting the appropriate circuit configuration.

The circuit definition should include considerations on the

input frequency band and amplitude, as well as the available

power supplies.

INPUT IMPEDANCE

The input impedance of the ADS5220 is capacitive due to the

input stray and sampling capacitors. These capacitors effec-

tively result in a dynamic input impedance that is a function

of the sampling and input frequency. Figure 2 depicts the

differential input impedance of the ADS5220 as a function of

the signal input frequency. For applications that use op amps

to drive the ADC, it is recommended that a series resistor be

added between the amplifier output and the converter inputs.

This will isolate the capacitive input of the converter from the

driving source and avoid gain peaking, or instability; further-

more, it will create a 1st-order, low-pass filter (LPF) in

conjunction with the specified input capacitance of the

ADS5220. The cutoff frequency of this LPF can be further

adjusted by adding an external shunt capacitor. In any case,

the use of the RC network is optional, but optimizing the

values to adapt to the specific application is encouraged.

DIFFERENTIAL INPUT IMPEDANCE

Ω

Input Frequency (Hz)

1M 10M 100M

50k

40k

30k

20k

10k

100

FIGURE 2. Differential Input Impedance vs Input Frequency.

ADS5220 11

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ANALOG INPUT DRIVEN BY TRANSFORMER

The ADS5220 can be driven by a transformer, which pro-

vides signal AC-coupling and allows a signal conversion from

single-ended input to differential output, or from single-ended

input to single-ended output. Using a transformer offers a

number of advantages. As a passive component, it does not

add to the total noise and has better harmonics in wide

frequency bands, compared to an op amp driver. By using a

step-up transformer, further signal amplification can be real-

ized; as a result, the signal swing from the source can be

reduced. For transformer selection, it is important to carefully

examine the application requirements and determine the

correct model, the desired impedance ratio, and frequency

characteristics. Furthermore, the appropriate model must

support the targeted distortion level and should not exhibit

any core saturation at full-scale voltage levels. A variety of

miniature RF transformers from different manufacturers (such

as Mini-Circuits, Coilcraft, or Trak) can be selected.

Figure 3 shows a transformer-coupled input configuration of

the ADS5220. The ADS5220 receives a differential AC signal

from the output of the transformer and common-mode volt-

age of +1.5V from the center tap. A source termination

resistor, RT , is required, which may be placed at the primary

or secondary side of the transformer to satisfy the termina-

tion requirements of the source impedance, RS. The circuit

also shows the use of an additional RC low-pass filter placed

in series with each converter input to attenuate some of the

wideband noise. The resistor values are typically in the range

of 10Ω to 50Ω, and capacitors are in the range of 10pF to

100pF for individual application requirements.

ADS5220

24.9Ω

24.9Ω22pF

0.1µF

1:n

1.7kΩ1.5kΩ

1.5V

3.3V

FIGURE 3. Transformer-Coupled Differential Input Configura-

tion of ADS5220.

ANALOG INPUT DRIVEN BY AMPLIFIER

The ADS5220 can be driven by an operational amplifier with

DC or AC signal coupling, as shown in Figure 4 and Figure

5. In Figure 4, the THS4503, a differential amplifier, is used

to convert a single-ended input into a differential output with

a gain of 2. The THS4503 provides an output common-mode

voltage set by VOCM pin, and is DC-coupled to the input of

ADS5220. A low-pass filter can be created by adding small

capacitors (for example, 10pF) in parallel with the feedback

resistors of the THS4503 as needed for some applications.

0.1µF

10pF(1)

THS4503

24.9Ω

392Ω

187Ω

392Ω

24.9Ω22pF

215Ω

VOCM

+5V

–5V

ADS5220

NOTE: (1) optional.

60.4Ω

50Ω

Source

1.7kΩ1.5kΩ

1.5V

3.3V

FIGURE 4. Using the THS4503 Differential Amplifier (Gain = 2) to Drive the ADS5220 in a DC-Coupled Configuration.

ADS5220

12 SBAS261A

www.ti.com

Due to the THS4503 driving a capacitive load, small series

resistors in the output ensure stable operation. Further de-

tails of this and other functions of the THS4503 may be found

in its product datasheet, located on the Texas Instruments

web site (www.ti.com). In general, differential amplifiers pro-

vide a high-performance driver solution for applications that

require DC signal coupling.

As shown in Figure 5, an AC-coupled, single-ended input

configuration is realized with TI’s OPA695 for wideband

applications. For narrowband applications, the OPA2822 can

be used. In Figure 5, the OPA695 is configured for a single

supply +5V and noninverting operation. The AC gain of the

amplifier is 2 and the DC bias of the amplifier is +2.5V, set

by the voltage divider from the op amp power supply. The

OPA695 is a very high bandwidth, current-feedback op amp

that combines 4200V/µs slew rate and low input voltage

noise. The OPA695’s high slew-rate and output drive capa-

bility can support the maximum full-scale input range of the

ADS5220 up to high input frequencies.

Further details of the OPA695 can be found in the OPA695

data sheet. The common-mode voltage at the ADS5220

input is +1.25V, set by a voltage divider from +3.3V power

supply. The +3.3V power supply must be decoupled, as

shown in Figure 11.

CLOCK INPUT

The clock input of the ADS5220 is designed to operate with

a single-ended pulse clock with CMOS/TTL level and DC-

coupling. There is no external common-mode voltage re-

quirement at the clock input pin (see Figure 6).

CLK

ADS5220

Mode Select

CMOS/TTL

Clock Source

50Ω

3.3V

A = DCA enabled

B = DCA disabled

50Ω

FIGURE 6. General Input Clock Interface of ADS5220.

6.8µF0.1µF

0.1µF

1.6kΩ

30Ω

47pF

1kΩ

ADS5220

OPA695 IN

3.3V

+5V

57.6Ω

50Ω

Source 806Ω

806Ω

487Ω

0.1µF

487Ω

47pF0.1µF

1.6kΩ1kΩ

1.25V

3.3V

FIGURE 5. Single-Ended Input of ADS5220 Driven by OPA695 with Gain = 2.

The clock input of the ADS5220 is referenced to the digital

supply (DVDD) and the applied logic levels should comply

with the specified levels (LV-logic). To obtain the specified

level of performance the clock signal applied to the ADS5220

should have as close of a 50% duty cycle as possible. This is

particularly important when the ADS5220 is operated at its

maximum sampling rate. Since this condition cannot always

easily be met, the ADS5220 features an on-chip duty-cycle

adjust (DCA) circuit that allows for additional design flexibil-

ity. The function of this duty cycle adjust circuit is controlled

through the

Mode Select

pin. Its default configuration is for a

logic low (internal pull-down) which has the DCA circuit

disabled. Applying a logic high, the DCA circuit becomes

activated. Now the incoming clock duty cycle can be in the

range of 35% to 65% and the DCA circuit will adjust this to be

50% for the internal timing. There may be situations where

ADS5220 13

SBAS261A www.ti.com

remains the same for the internal or external reference

modes. The bypassing should consist of two pairs of 2.2µF

ceramic and 15µF tantalum capacitors, and a 10µF tantalum

capacitor, as depicted in Figure 7.

In addition to the bypassing the top- and bottom reference

pin (REFT, REFB) require a pull-up and a pull-down resistor,

respectively. As shown in Figure 7, the pull-up resistor

should be connected from the REFT pin to the analog supply

(+3.3V AVDD), while the pull-down resistor on the REFB pin

should be connected to ground. For proper operation the

value of those resistors should be maintained as shown, that

is, 402Ω. Also, to ensure optimal settling of the internal

reference amplifiers the external configuration must include

two low value resistors located in series with each the REFT

and REFB pins (see Figure 7). For best results, use small

surface mount chip resistors and position them as close to

the pins as possible.

INTERNAL REFERENCE

There are two internal fixed reference modes and one

internal programmable reference mode as shown in Table I

and Figure 7 through Figure 9. Setting RSEL to ground (or

< 0.2V) provides an internal reference voltage of +1.0V at

VREF pin, +2V at REFT, and +1V at REFB pin. In this case,

the input FSR is +2V peak-to-peak. Connecting RSEL to the

VREF pin provides an internal reference voltage of +0.5V at

VREF, +1.75V at REFT, and +1.25V at REFB. In this case, the

input FSR is +1V peak-to-peak. Setting the resistor divider as

in Figure 9 provides an internal voltage between +0.5V and

+1V at VREF, which is as follows:

VREF = 0.5 • (1+R2/R1)

In this case, the voltage at REFT and REFB and input FSR

is calculated based on Table I.

the user may prefer to disable the DCA function; for example,

during asynchronous clocking (that is, when the sampling

period is purposely not constant).

In any case, a very low jitter clock is fundamental to preserv-

ing the excellent AC performance of the ADS5220. Gener-

ally, as input frequency increases, clock jitter becomes more

critical to maintain a good signal-to-noise ratio. The following

equation can be used to calculate the achievable SNR for a

given input frequency and clock jitter (tJA in ps rms):

SNRJA = 20 log [1/(2 • π • fIN • tJA)]

Here, the tJA is the rms aperture jitter from all jitter sources,

such as clock edge, input signal and the device. The fIN is

input frequency. The crystal oscillator has very low jitter, but

if using a clock conditioning circuit (gate, divider, logic level

converter, and so forth), the extra jitter and timing variation

must be considered. In addition, the input clock is treated as

an analog signal and its power supply should be separated

from the power supply of the digital output driver to limit the

digital noise.

MINIMUM SAMPLING RATE

The pipeline architecture of the ADS5220 uses a switched-

capacitor technique in its internal track-and-hold stages. The

high sampling speed necessitates the use of very small

capacitor values. In order to hold droop errors low, the

capacitors require a minimum refresh rate. To maintain

accuracy of the acquired sample charge, the sampling clock

on the ADS5220 must not drop below the specified minimum

of 1MSPS.

REFERENCE

The ADS5220 provides both an internal and an external

reference mode through the configuration of pins RSEL and

VREF (see Table 1). The input full-scale range (FSR) of the

ADS5220 is always twice the voltage at the VREF pin. The

REFT and REFB pins are internally buffered, and drive the

ADC core for both the external and internal reference modes.

When the internal reference mode is selected the voltage at

VREF is generated by an internal 0.5V bandgap voltage

through a VREF amplifier. This internal buffer amplifier can be

used to supply up to 2mA to external circuitry. Selecting the

external reference mode will power-down this reference

amplifier, and the VREF pin becomes the input for the external

reference voltage. In the power-down mode, the impedance

of the VREF pin is approximately 6kΩ.

Shown in Table I are the values for VREFT, VREFB, and VREF

for the various modes and full-scale input ranges.

The ADS5220 requires its reference pins to be bypassed as

outlined in Figure 7 through Figure 10. The configuration

RSEL PIN INPUT FSR (VPP)

SELECTED MODE CONNECT TO VREF PIN (V) (Differential) REFT (V) REFB (V)

Internal Fixed GND to 0.2V 1.0 2 2 1

Internal Fixed VREF Pin 0.5 1 1.75 1.25

Internal Program 0.2V to VREF 0.5 • (1+R2/R1)2 • VREF VREF/2 + 1.5 1.5 – VREF/2

External AVDD (3.3V) Ext. 0.5V to 1V 2 • VREF VREF/2 + 1.5 1.5 – VREF/2

TABLE I. Reference Configuration.

ADS5220

RSEL

VREF

REFT

REFB

2.2µF

0.1µF

2Ω10µF

402Ω

2.2µF 15µF

2Ω

2.2µF15µF

402Ω

+3.3V

Output

FIGURE 7. Internal Reference Mode for VREF = 1V.

ADS5220

14 SBAS261A

www.ti.com

EXTERNAL REFERENCE

For even more design flexibility, the ADS5220 can be oper-

ated with external references. Utilization of an external refer-

ence voltage may be considered for applications requiring

higher accuracy, improved temperature stability, or flexible

full-scale range. Particularly in multi-channel applications,

the use of a common external reference offers the benefit of

improving gain matching between converters. Setting RSEL

to AVDD (+3.3V) provides an external reference mode for the

ADS5220. In this case, the internal VREF amplifier is powered

down, and the VREF pin requires an external reference

voltage between +0.5V to +1V to provide an input full-scale

range of 1VPP to 2VPP. The REFT and REFB will appear with

the voltage as shown in Table I, and input FSR is always

twice the voltage at the VREF pin. A voltage reference

(REF1004 or TPS79225) and a single-supply amplifier

(OPA2234 or OPA4227) can be used to generate a precision

external reference.

ADS5220

RSEL

VREF

REFT

REFB

2.2µF

0.1µF

10µF 2.2µF

2Ω

2.2µF15µF

0.5V

Output

402Ω

15µF

402Ω

+3.3V

ADS5220

RSEL

VREF

REFT

REFB

2.2µF

0.1µF

2Ω10µF2.2µF

2Ω

2.2µF

402Ω

15µF

402Ω

+3.3V

ADS5220

RSEL

VREF

REFT

REFB

2.2µF

0.1µF

2Ω10µF2.2µF

2Ω

2.2µF

Input

0.5V to 1V

AVDD

402Ω

15µF

402Ω

+3.3V

FIGURE 8. Internal Reference Mode for VREF = 0.5V.

FIGURE 9. Internal Reference Mode for VREF = 0.5 • (1 + R2/R1).

FIGURE 10. External Reference Configuration.

BINARY TWO’S

STRAIGHT OFFSET COMPLEMENT

DIFFERENTIAL INPUT BINARY (SOB) (BTC)

+FS – 1LSB 1111 1111 1111 0111 1111 1111

(+FS: IN = 2V,

= 1V)

+1/2 FS 1100 0000 0000 0100 0000 0000

(IN = 1.75V,

= 1.25V)

Bipolar Zero 1000 0000 0000 0000 0000 0000

(IN =

= 1.5V)

–1/2 FS 0100 0000 0000 1100 0000 0000

(

= 1.75V, IN = 1.25V)

–FS 0000 0000 0000 1000 0000 0000

(

= 2V, IN = 1V)

TABLE II. Coding Table for Differential Input Configuration

with FSR of 2VPP.

DIGITAL OUTPUTS

DATA OUTPUT FORMAT

The ADS5220 makes two data output formats available,

either the Straight Offset Binary (SOB) code or the Binary

Two’s Complement (BTC) code. The selection of the output

coding is controlled through the MSBI pin. Applying a logic

high will enable the BTC coding, whereas a logic low will

enable the SOB code. In its default configurations the MSBI

pin assumes a logic low level (internal pull-down) and the

ADS5220 will operate with the SOB output coding. The two

code structures are identical with one exception: the MSB is

inverted for the BTC format, as shown in Table II. If the input

signal exceeds the FSR, the output code will remain at all 1s

or all 0s.

ADS5220 15

SBAS261A www.ti.com

OUTPUT ENABLE (

)

The digital outputs including the OVR pin of the ADS5220

can be set to output enable or output high impedance (tri-

state) by the

pin. For normal operation, this pin must be

at a logic low (default is internal pull-down), whereas a logic

high disables the outputs or sets the output tri-state.

OUTPUT LOADING

It is recommended to keep the capacitive loading on the data

output lines as low as possible, preferably below 10pF.

Higher capacitive loading will cause larger dynamic currents

as the digital outputs are changing. These high current

surges can feed back to the analog portion of the ADC and

adversely affect device performance. If necessary, external

buffers or latches (for example, the SN74LVTH16374) close

to the converter output pins can be used to minimize capaci-

tive loading. Buffers or latches also provide the added benefit

of isolating the ADS5220 from any digital activities on the bus

to limit the high-frequency noise.

OVER-RANGE INDICATOR

The ADS5220 has control functions for the input voltage over

full-scale that includes output data code control and over-

range indication. The output data code control of over full-

scale is shown in Table II. In SOB format, for example, when

the input voltage is (+FS – 1 LSB) or above this value, the

ADS5220 outputs all 1s at 12 data bits; when the input

voltage is –FS or below this value, the ADS5220 outputs all

0s at 12 data bits. When the input voltage is 0 (mid-scale) or

only the common-mode voltage at the input, the ADS5220

outputs 1 at MSB and 0s at the remaining 11 data bits.

Another over-range control function of the ADS5220 is over-

range indication, which is output by the OVR pin. The OVR

pin is the function of the reference voltage and the output

data bits, and has the same pipeline delay as the output data

bits. OVR is at logic low if the input voltage is within the FSR,

and is at logic high if the input voltage is over full-scale or

under full-scale. OVR changes from logic low to high or logic

high to low immediately following the change of the output

data, when the input voltage changes from normal value to

over FS or from over FS to normal value. The OVR signal

remains high for as long as the input signal exceeds the input

range limits of the ADS5220. The OVR pin is tri-stated by the

use of the output enable pin (

TIMING

The ADS5220 samples the analog signal at the rising edge

of its input clock, and outputs the digital data at the rising

edge of the input clock after a pipeline delay of 5 clocks.

There is an aperture delay (typically 3ns) between the

sampling edge and the actual sampling time. There is also a

propagation delay between the rising edge of the clock and

the time that data is valid on the data bus (see the timing

diagram on page 5). The output data of the ADS5220 is

latched data.

POWER SUPPLIES AND

POWER DISSIPATION

ANALOG AND DIGITAL POWER SUPPLY

The ADS5220 includes power-supply pins of AVDD, DVDD

and VDRV. The analog supply AVDD and digital supply DVDD

is +3.3V. The digital output driver supply, VDRV, can be set

between +2.5V and +3.3V. AVDD, DVDD and VDRV are not

tied together internally. Each of these supply pins must be

bypassed separately with at least one 0.1µF ceramic chip

capacitor. The analog supply (AVDD) and the digital supply

(DVDD or VDRV) may be tied together externally with a ferrite

bead or inductor between the supply pins. The ADS5220 is

specified with the digital output driver supply, VDRV, set to

+2.5V. It is highly recommended to consider linear supplies

instead of switching types. Even with good filtering, switching

supplies can radiate noise that could interfere with any high-

frequency input signal and cause unwanted modulation prod-

ucts. The supply voltage should stay within the tolerance

given in the specification table. A basic application configu-

ration with the power supply decoupling is shown in Figure

11.

ADS5220

16 SBAS261A

www.ti.com

POWER DISSIPATION

In normal operating mode (STPD = low and QPD = low), the

typical total power dissipation of the ADS5220 is 195mW.

The majority of the power consumption is due to biasing;

therefore, this part of the total power dissipation is indepen-

dent of the applied clock frequency. The current on the

VDRV supply is directly related to the capacitive loading of

the data output pins; care must be taken to minimize such

24.9Ω

2Ω402Ω

402Ω2Ω

NC 26

NC 25

OVR 24

NC 23

NC 22

D11 (MSB)

LATCH

SN74LVTH16374

ADS5220

D10 11

D9 12

D8 13

D7 14

D6 15

D5 16

D4 17

D3 18

D2 19

D1 20

D0 (LSB)

VREF

RSEL

REFT

REFB

AGND

DGND

AGND

CLK

0.10µF

2.2µF

PULSE

49.9Ω

NC = No Connection.

–

+15µF 2.2µF

0.10µF

10µF3.3V

1.5V

+3.3V

(AV

)10µF

2.2µF

22pF

15µF

0.10µF

MSBI

Mode Select

ST PD

Q PD

10µF

0.10µF

3.3V

VDRV

GNDRV

VDRV

FIGURE 11. General Configuration for the ADS5220.

POWER DOWN

The ADS5220 provides two power-down modes for different

application requirements. One is the Standard Power-Down

(STPD); the second is the Quasi-Power-Down (QPD). Both

pins will assume a logic low level (internal pull-down) and

configure the ADS5220 for normal operation. Setting STPD

to logic high (and QPD to logic low or high) will shut down the

internal ADC core and power down the reference circuit. In

ADS5220 17

SBAS261A www.ti.com

this case the power dissipation is typically 15mW. With 10µF

external decoupling capacitor at REFT and REFB, it takes

about 800µs to fully restore normal operation after the normal

mode is enabled. Setting QPD to logic high (and STPD to

logic low) will shut down the internal ADC core while the

internal reference circuit power remains on. In this case,

power dissipation is typically 75mW. It takes about 2µs to

fully restore normal operation after the normal mode is

enabled. During power-down, data in the converter pipeline

will be lost and new valid data will be subject to the specified

pipeline delay.

LAYOUT AND DECOUPLING

Proper grounding and bypassing, short lead length, and the

use of ground planes are particularly important for high-

frequency designs. Achieving optimum performance with a

fast sampling converter like the ADS5220 requires careful

attention to the PC board layout in order to minimize the

effect of board parasitics and optimize component place-

ment. A multi-layer board usually ensures best results and

allows convenient component placement. The ADS5220 must

be treated as an analog component, and the AVDD pins

connected to a clean analog supply. This ensures the most

consistent results, because digital supplies often carry a high

level of switching noise that could couple into the converter

and degrade the performance. The driver supply pins (VDRV)

must also be connected to a low-noise supply. Supplies of

adjacent digital circuits can carry substantial current tran-

sients. The supply voltage must be thoroughly filtered before

connecting to the VDRV supply of the converter. All ground

connections on the ADS5220 are internally bonded to the

metal flag (bottom of package) that forms a large ground

plane. All ground pins must directly connect to an analog

ground plane that covers the PC board area under the

converter. Due to its high sampling frequency, the ADS5220

generates high frequency current transients and noise (clock

feedthrough) that are fed back into the supply and reference

lines. If not sufficiently bypassed, this adds noise to the

conversion process. See Figure 11 for the recommended

supply decoupling scheme for the ADS5220. All AVDD pins

should be bypassed with a combination of 0.1µF ceramic

chip capacitors (0805, low ESR) and a 10µF tantalum tank

capacitor. A similar approach may be used on the digital

supply pins DVDD and driver supply pins, VDRV. In order to

minimize the lead and trace inductance, the capacitors must

be located as close to the supply pins as possible. They are

best placed directly under the package where double-sided

component mounting is allowed. In addition, larger bipolar

decoupling capacitors (2.2µF to 10µF), effective at lower

frequencies, may also be used on the main supply pins. They

can be placed on the PC board in close proximity

(< 0.5 inches) to the ADC. If the analog inputs to the

ADS5220 are driven differentially, it is especially important to

optimize towards a highly symmetrical layout. Small trace

length differences can create phase shifts compromising a

good distortion performance. For this reason, the use of two

single op amps rather than one dual amplifier enables a more

symmetrical layout and a better match of parasitic capaci-

tances. The pin orientation of the ADS5220 package follows

a flow-through design with the analog inputs located on one

side of the package, whereas the digital outputs are located

on the opposite side of the quad-flat package. This provides

a good physical isolation between the analog and digital

connections. While designing the layout, it is important to

keep the analog signal traces separated from any digital lines

to prevent noise coupling onto the analog portion. Try to

match trace length for the differential clock signal (if used) to

avoid mismatches in propagation delays. Single-ended clock

lines must be short and should not cross any other signal

traces. Short circuit traces on the digital outputs will minimize

capacitive loading. Trace length must be kept short to the

receiving gate (< 2 inches) with only one CMOS gate con-

nected to one digital output. If possible, the digital data

outputs should be buffered (with the TI SN74LTH16374, for

example). Dynamic performance can also be improved with

the insertion of series resistors at each data output line. This

sets a defined time constant and reduces the slew rate that

would otherwise flow as the fast edge rate. The resistor value

may be chosen to give a time constant of 15% to 25% of the

used data.

PACKAGING INFORMATION

ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY

ADS5220PFBR ACTIVE TQFP PFB 48 2500

ADS5220PFBT ACTIVE TQFP PFB 48 250

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

PACKAGE OPTION ADDENDUM

www.ti.com 31-Mar-2004

MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK

4073176/B 10/96

Gage Plane

0,13 NOM

0,25

0,45

0,75

Seating Plane

0,05 MIN

0,17

0,27

7,20

6,80

5,50 TYP

8,80

9,20

1,05

0,95

1,20 MAX 0,08

0,50 M

0,08

0°–7°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

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