100355
Low Power Quad Multiplexer/Latch
General Description
The 100355 contains four transparent latches, each of which
can accept and store data from two sources. When both En-
able (E
n
) inputs are LOW, the data that appears at an output
is controlled by the Select (S
n
) inputs, as shown in the Oper-
ating Mode table. In addition to routing data from either D
0
or
D
1
, the Select inputs can force the outputs LOW for the case
where the latch is transparent (both Enables are LOW) and
can steer a HIGH signal from either D
0
or D
1
to an output.
The Select inputs can be tied together for applications re-
quiring only that data be steered from either D
0
or D
1
.A
positive-going signal on either Enable input latches the out-
puts. A HIGH signal on the Master Reset (MR) input over-
rides all the other inputs and forces the Q outputs LOW. All
inputs have 50 kΩpulldown resistors.
Features
nGreater than 40%power reduction of the 100155
n2000V ESD protection
nPin/function compatible with 100155
nVoltage compensated operating range =−4.2V to −5.7V
nStandard Microcircuit Drawing
(SMD) 5962-9165401
Logic Symbol
Pin Names Description
E
1
,E
2
Enable Inputs (Active LOW)
S
0
,S
1
Select Inputs
MR Master Reset
D
na
–D
nd
Data Inputs
Q
a
–Q
d
Data Outputs
Q
a
–Q
d
Complementary Data Outputs
Connection Diagrams
DS100294-1
24-Pin DIP
DS100294-2
24-Pin Quad Cerpak
DS100294-3
August 1998
100355 Low Power Quad Multiplexer/Latch
© 1998 National Semiconductor Corporation DS100294 www.national.com
Logic Diagram
DS100294-5
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Operating Mode Table
Controls Outputs
E
1
E
2
S
1
S
0
Q
n
H X X X Latched (Note 1)
X H X X Latched (Note 1)
LLLL D
0x
LLHL D
0x
+D
1x
LLLH L
LLHH D
1x
H=HIGH Voltage Level
L=LOW Voltage Level
X=Don’t Care
Note 1: Stores data present before E went HIGH
Truth Table
Inputs Outputs
MR E
1
E
2
S
1
S
0
D
1x
D
0x
Q
x
Q
x
HXXXXXX H L
LLLHHHX L H
LLLHHLX H L
LLLLLXH L H
LLLLLXL H L
LLLLHXX H L
LLLHLHX L H
LLLHLXH L H
LLLHLL L H L
L H X X X X X Latched (Note 1)
L X H X X X X Latched (Note 1)
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Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications. Above
which the useful life may be impaired.
Storage Temperature (T
STG
) −65˚C to +150˚C
Maximum Junction Temperature (T
J
)
Ceramic +175˚C
V
EE
Pin Potential to Ground Pin −7.0V to +0.5V
Input Voltage (DC) V
EE
to +0.5V
Output Current (DC Output HIGH) −50 mA
ESD (Note 3) ≥2000V
Recommended Operating
Conditions
Case Temperature (T
C
)
Military −55˚C to +125˚C
Supply Voltage (V
EE
) −5.7V to −4.2V
Note 2: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
V
EE
=−4.2V to −5.7V, V
CC
=V
CCA
=GND, T
C
=−55˚C to +125˚C
Symbol Parameter Min Max Units T
C
Conditions Notes
V
OH
Output HIGH Voltage −1025 −870 mV 0˚C to +125˚C
−1085 −870 mV −55˚C V
IN
=V
IH (Max)
Loading with (Notes 4, 5,
6)
V
OL
Output LOW Voltage −1830 −1620 mV 0˚C to +125˚C or V
IL (Min)
50Ωto −2.0V
−1830 −1555 mV −55˚C
V
OHC
Output HIGH Voltage −1035 mV 0˚C to +125˚C
−1085 mV −55˚C V
IN
=V
IH (Min)
Loading with (Notes 4, 5,
6)
V
OLC
Output LOW Voltage −1610 mV 0˚C to +125˚C or V
IL (Max)
50Ωto −2.0V
−1555 mV −55˚C
V
IH
Input HIGH Voltage −1165 −870 mV −55˚C to Guaranteed HIGH Signal (Notes 4, 5,
6, 7)
+125˚C for ALL Inputs
V
IL
Input LOW Voltage −1830 −1475 mV −55˚C to Guaranteed LOW Signal (Notes 4, 5,
6, 7)
+125˚C for ALL Inputs
I
IL
Input LOW Current 0.50 µA −55˚C to V
EE
=−4.2V (Notes 4, 5,
6)
+125˚C V
IN
=V
IL (Min)
I
IH
Input HIGH Current
S
0
,S
1
220
E
1
,E
2
350 µA 0˚C to +125˚C
D
na
–D
nd
340 V
EE
=−5.7V
MR 430 V
IN
=V
IH (Max)
(Notes 4, 5,
6)
S
0
,S
1
320
E
1
,E
2
500 µA −55˚C
D
na
–D
nd
490
MR 630
I
EE
Power Supply Current −95 −32 mA −55˚C to +125˚C Inputs Open (Notes 4, 5,
6)
Note 4: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 5: Screen tested 100%on each device at −55˚C, +25˚C, and +125˚C Temp., Subgroups 1, 2, 3, 7, and 8.
Note 6: Sample tested (Method 5005, Table 1) on each Mfg. lot at +25˚, +125˚C, and −55˚C Temp., Subgroups 1, 2, 3, 7, and 8.
Note 7: Guaranteed by applying specified input condition and testing VOH/VOL.
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Military Version
AC Electrical Characteristics
V
EE
=−4.2V to −5.7V, V
CC
=V
CCA
=GND
Symbol Parameter T
C
=−55˚C T
C
=+25˚C T
C
=+125˚C Units Conditions Notes
Min Max Min Max Min Max
t
PLH
Propagation Delay
t
PHL
D
na
–D
nd
to Output 0.40 2.30 0.50 2.20 0.50 2.60 ns
(Transparent Mode)
t
PLH
Propagation Delay
Figures 1, 2
(Notes 8, 9,
10)
t
PHL
S
0
,S
1
to Output 0.60 3.00 0.80 2.70 0.80 3.20 ns
(Transparent Mode)
t
PLH
Propagation Delay 0.50 2.60 0.60 2.30 0.70 2.70 ns
t
PHL
E
1
,E
2
to Output
t
PLH
Propagation Delay 0.60 2.80 0.70 2.60 0.70 2.90 ns
Figures 1, 3
(Notes 8, 9,
10)
t
PHL
MR to Output
t
TLH
Transition Time 0.40 1.90 0.40 1.90 0.40 1.90 ns
Figures 1, 2
(Note 11)
t
THL
20%to 80%,80
%to 20%
t
S
Setup Time
D
na
–D
nd
0.90 0.90 0.90 ns
Figure 4
(Note 11)
S
0
,S
1
2.40 2.40 2.40
MR (Release Time) 1.50 1.50 1.50
Figure 3
t
H
Hold Time
D
na
–D
nd
0.40 0.40 0.40 ns
Figure 4
(Note 11)
S
0
,S
1
0.00 0.00 0.00
t
pw
(L) Pulse Width LOW E
1
,E
2
2.00 2.00 2.00 ns
Figure 2
(Note 11)
t
pw
(H) Pulse Width HIGH MR 2.00 2.00 2.00 ns
Figure 3
(Note 11)
Note 8: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 9: Screen tested 100%on each device at +25˚C, Temperature only, Subgroup A9.
Note 10: Sample tested (Method 5005, Table 1) on each Mfg. lot at +25˚, Subgroup A9, and at +125˚C, and −55˚C Temp., Subgroups A10 & A11.
Note 11: Not tested at +25˚C, +125˚C and −55˚C Temperature (design characterization data).
5 www.national.com
Test Circuit
Switching Waveforms
DS100294-6
Notes:
VCC,V
CCA =+2V, VEE =−2.5V
L1 and L2 =equal length 50Ωimpedance lines
RT=50Ωterminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 50Ωto GND
CL=Fixture and stray capacitance ≤3pF
Pin numbers shown are for flatpak; for DIP see logic symbol
FIGURE 1. AC Test Circuit
(Using Quad Cerpak)
DS100294-7
FIGURE 2. Enable Timing
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Switching Waveforms (Continued)
DS100294-8
FIGURE 3. Reset Timing
DS100294-9
Notes:
tsis the minimum time before the transition of the enable that information must be present at the data input.
this the minimum time after the transition of the enable that information must remain unchanged at the data input.
FIGURE 4. Data Setup and Hold Times
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8
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J24E
24-Lead Ceramic Flatpak (F)
NS Package Number W24C
9 www.national.com
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CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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100355 Low Power Quad Multiplexer/Latch
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
