ACPL-K71T, ACPL-K72T, ACPL-K74T and ACPL-K75T Automotive High Speed Low Power Digital Optocouplers with R2CouplerTM Isolation and AEC-Q100 Grade 1 Qualification Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The ACPL-K71T and ACPL-K72T are high speed digital CMOS optocouplers package suitable for emerging electric vehicle applications. The ACPL-K74T and ACPL-K75T are dual channel equivalent of the ACPL-K71T and ACPL-K72T respectively. All products are available in the stretched SO-8 package outline, designed to be compatible with standard surface mount processes. Qualified to AEC-Q100 Grade 1 Test Guidelines ACPL-K71T and ACPL-K74T are high speed mode with fastest propagation delay (max 35ns at IF=10mA) while ACPL-K72T and ACPL-K75T are low power mode with lowest LED drive current of 4mA for standard digital isolation switching. Low Propagation Delay : Each channel of the digital optocoupler has a CMOS detector IC with an integrated photodiode, a high speed trans-impedance amplifier, and a voltage comparator with an output driver. Automotive Wide Temperature Range: -40C to 125C High Temperature and Reliability, High Speed Digital Interface for Automotive Application. 5 V CMOS compatibility 40 kV/s Common-Mode Rejection at VCM=1000V Typ. - ACPL-K71T, ACPL-K74T: 25ns Typ.@ IF = 10mA - ACPL-K72T, ACPLK75T: 60ns Typ.@ IF = 4mA Worldwide Safety Approval: - UL 1577 approval, 5kVRMS /1 min. - CSA Approval - IEC/EN/DIN EN 60747-5-5 Avago R2Coupler provides with reinforced insulation and reliability that delivers safe signal isolation critical in automotive and high temperature industrial applications. Applications Functional Diagram Automotive IPM Driver for DC-DC converters and motor inverters ACPL-K71/K72T ACPL-K74/K75T 1 8 1 8 2 7 2 7 3 6 3 6 4 5 4 5 CAN Bus and SPI Communications Interface High Temperature Digital/Analog Signal Isolation Power Transistor Isolation Truth Table LED Vo ON LOW OFF HIGH Note: The connection of a 0.1 F bypass capacitor between pins 5 and 8 is recommended. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Ordering Information Part number Option (RoHS Compliant) ACPL-K71T -000E -060E ACPL-K72T Tape & Reel UL 5000 VRMS / 1 Minute rating X X X X X X X -560E X X X -000E Stretched SO-8 X X X X X X -560E X X X -000E Stretched SO-8 X X X X X X -560E X X X -060E Stretched SO-8 X X X X -500E X X X -560E X X X Quantity 80 per tube X 80 per tube 1000 per reel X 1000 per reel 80 per tube X 80 per tube 1000 per reel X X -500E -000E IEC/EN/DIN EN 60747-5-5 X -500E -060E ACPL-K75T Stretched SO-8 Surface Mount -500E -060E ACPL-K74T Package 1000 per reel 80 per tube X 80 per tube 1000 per reel X 1000 per reel 80 per tube X 80 per tube 1000 per reel X 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-K71T-560E to order product of SSO-8 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. 2 Package Outline Dimensions (Stretched SO8) RECOMMENDED LAND PATTERN 5.850 0.254 (0.230 0.010) PART NUMBER DATE CODE 8 7 6 5 KXXT YWW EE RoHS-COMPLIANCE INDICATOR 1 2 12.650 (0.498) 6.807 0.127 (0.268 0.005) 1.905 (0.075) 3 4 EXTENDED DATECODE FOR LOT TRACKING 0.64 (0.025) 7 0.450 (0.018) 1.590 0.127 (0.063 0.005) 45 3.180 0.127 (0.125 0.005) 0.200 0.100 (0.008 0.004) 0.381 0.127 (0.015 0.005) 1.270 (0.050) BSG 0.750 0.250 (0.0295 0.010) 11.50 0.250 (0.453 0.010) 0.254 0.100 (0.010 0.004) Dimensions in millimeters and (inches). Note: Lead coplanarity = 0.1 mm (0.004 inches). Floating lead protrusion = 0.25mm (10mils) max. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Note: Non-halide flux should be used. Regulatory Information The ACPL-K71T, ACPL-K72T, ACPL-K74T and ACPL-K75T are approved by the following organizations: UL Approval under UL 1577, component recognition program up to VISO = 5kVRMS. CSA Approval under CSA Component Acceptance Notice #5. IEC/EN/DIN EN 60747-5-5 Approval under IEC/EN/DIN EN 60747-5-5. 3 Insulation and Safety Related Specifications Parameter Symbol Units Conditions Minimum External Air Gap (Clearance) L(101) 8 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 8 mm Measured from input terminals to output terminals, shortest distance path along body. 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. 175 V DIN IEC 112/VDE 0303 Part 1 Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group (DIN VDE0109) IIIa Material Group (DIN VDE 0109) IEC/EN/DIN EN 60747-5-5 Insulation Related Characteristic (Option 060 only) Description Symbol Characteristic Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 600 V rms for rated mains voltage 1000 V rms I-IV I-III Climatic Classification 40/125/21 Pollution Degree (DIN VDE 0110/1.89) Units 2 Maximum Working Insulation Voltage VIORM 1140 VPEAK Input to Output Test Voltage, Method b VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec Partial Discharge < 5 pC VPR 2137 VPEAK Input to Output Test Voltage, Method a VIORM x 1.6 = VPR, Type and sample test, tm = 10 sec, Partial Discharge < 5 pC VPR 1824 VPEAK Highest Allowable Overvoltage (Transient Overvoltage, tini = 60 sec) VIOTM 8000 VPEAK Safety Limiting Values (Maximum values allowed in the event of a failure) Case Temperature Input Current Output Power TS IS,INPUT PS,OUTPUT 175 230 600 C mA mW Insulation Resistance at TS, VIO = 500 V RS 109 4 Absolute Maximum Ratings Parameter Symbol Min. Max. Units Test Conditions Storage Temperature TS -55 130 C Ambient Operating Temperature TA -40 125 C Supply Voltages VDD 0 6.5 V Output Voltage VO -0.5 VDD +0.5 V Average Forward Input Current IF 20.0 mA Peak Transient Input Current IF( TRAN) 1 A 1s Pulse Width, 300pps 80 mA 1s Pulse Width, <10% Duty Cycle Reverse Input Voltage Vr 5 V Input Power Dissipation PI 40 mW Output Power Dissipation Po 30 mW Lead Solder Temperature 260C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile See Solder Reflow Temperature Profile Section Recommended Operating Conditions Parameter Symbol Min. Max. Units Supply Voltage VCC 3.0 5.5 V Operating Temperature TA -40 125 C Forward Input Current IF(ON) 4 15 mA Forward Off State Voltage VF(OFF) 0.8 V Input Threshold Current ITH 3.5 mA Note Electrical Specifications Over recommended temperature TA = -40C to 125C, 3.0 V VDD 5.5 V. All typical specifications are at TA=25C, VDD= 5V. Parameter Symbol Min. Typ. Max. Units Test Conditions LED Forward Voltage VF 1.45 1.25 1.5 1.5 1.75 1.85 V V IF=10 mA, TA=25C IF=10 mA Vf Temperature Coefficient Input Capacitance CIN Input Reverse Breakdown Voltage BVR 5.0 Logic High Output Voltage VOH VDD -0.6 Logic Low Output Voltage VOL Logic Low Output Supply Current (per channel) IDDL Logic High Output Supply Current (per channel) IDDH 5 -1.5 mV/C 90 pF V IR = 10 A Fig V IOH = -3.2 mA 4 0.6 V IOL = 4 mA 3 0.9 1.5 mA 0.9 1.5 mA Notes ACPL-K71T, ACPL-K74T High Speed Mode Switching Specifications Over recommended temperature TA = -40C to 125C, 4.5 V VDD 5.5 V. All typical specifications are at TA=25C, VDD= 5V. Parameter Symbol Propagation Delay Time to Logic Low Output Propagation Delay Time to Logic High Output Min. Typ. Max. Units Test Conditions Fig Notes tPHL 25 35 ns VIN = 4.5V-5.5V, RIN = 3905%, CIN = 100pF, CL = 15pF V THL = 0.8V V TLH = 80% of VDD 5,6,11 1,2,3 tPLH 25 35 ns Pulse Width Distortion PWD 0 Propagation Delay Skew tPSK Output Rise Time (10% - 90%) tR Output Fall Time (90% - 10%) tF 10 ns Common Mode Transient Immunity at Logic High Output | CMH | 15 25 kV/s VIN = 0V, RIN = 390 5%, CIN = 100pF, VCM = 1000V, TA = 25C 12 4 Common Mode Transient Immunity at Logic High Output | CML | 15 25 kV/s VIN = 4.5V-5.5V , RIN = 390 5%, CIN = 100pF, VCM = 1000V, TA = 25C 12 5 12 ns 15 ns 10 ns ACPL-K72T, ACPL-K75T Low Power Mode Switching Specifications Over recommended temperature TA = -40C to 125C, 3.0 V VDD 5.5 V. All typical specifications are at TA=25C, VDD= 5V. Parameter Symbol Typ. Max. Units Test Conditions Fig Notes Propagation Delay Time to Logic Low Output tPHL Min. 60 100 ns IF = 4mA, CL= 15pF V THL = 0.8V V TLH = 80% of VDD 7, 8, 9, 10, 13 1,2,3 Propagation Delay Time to Logic High Output tPLH 35 100 ns Pulse Width Distortion PWD 25 50 ns 60 ns Propagation Delay Skew tPSK Output Rise Time (10% - 90%) tR 10 ns Output Fall Time (90% - 10%) tF 10 ns Common Mode Transient Immunity at Logic High Output | CMH | 25 40 kV/s LED Driving Circuit Fig 13, VIN = 0V, R1 = 3505%, R2 = 3505%, VCM = 1000V, TA = 25C 14 4 Common Mode Transient Immunity at Logic High Output | CML | 25 40 kV/s LED Driving Circuit Fig 14, VIN = 4.5-5.5V, R1 = 3505%, R2 = 3505%, VCM = 1000V, TA = 25C 14 5 6 Package Characteristics All Typical at TA = 25C. Parameter Symbol Min. Input-Output Momentary Withstand Voltage VISO 5000 Input-Output Resistance R I-O Input-Output Capacitance C I-O Typ. Max. Units Test Conditions Notes VRMS RH 50%, t = 1 minute, TA = 25C 6, 7 1014 V I-O = 500 V dc 6 0.6 pF f = 1 MHz, TA = 25C 6 Notes: 1. tPHL propagation delay is measured from the 50% (VIN or IF) on the rising edge of the input pulse to the 0.8V of VDD of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% (VIN or IF) on the falling edge of the input pulse to the 80% level of the rising edge of the VO signal. 2. PWD is defined as |tPHL - tPLH|. 3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 5. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state. 6. Device considered a two terminal device: pins 1, 2, 3 and 4 shorted together, and pins 5, 6, 7 and 8 shorted together. 7. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 6000VRMS for 1 second. 7 Performance Plots 100.00 5 Vo - Output Voltage (V) IF - Forward Current (mA) Ta = 25C 10.00 1.00 0.10 0.01 1.2 1.3 1.4 1.5 VF - Forward Voltage - V 1 0.600 0.500 0.400 0.300 0.200 0.100 0 2 4 6 8 IOL - Logic Low Output Current - mA 10 Figure 3 Typical Logic Low Output Voltage vs Low Low Output Current 2 4.6 4.4 4.2 4.0 0 -2 -4 -6 -8 IOH - Logic High Output Current - mA -10 40 Tp - Propagation Delay, PWD - Pulse Width Distortion - ns Tp - Propagation Delay, PWD - Pulse Width Distortion - ns 1 1.5 IF - Forward Current - mA Figure 4. Typical Logic High Output Voltage vs Logic High Output Current 35 30 25 20 TPHL Vin=4.5V, Rin=390:, Cin=100pF TPLH PWD 15 10 5 -40 -20 0 20 40 60 80 Temperature - C 100 120 140 Figure 5. ACPL-K71T/K74T (High Speed) Typical Propagation Delay vs Temperature 8 0.5 4.8 40 0 0 5.0 VOH - Logic High Output Voltage - V VOL - Logic Low Output Voltage - V 2 Figure 2. Typical Output Voltage vs Input Forward Current 0.700 0.000 3 0 1.6 Figure 1. Typical Diode Input Forward Current Characteristic 4 35 30 25 20 15 TPHL Rin=390:, Cin=100pF TPLH Ta=25C PWD 10 5 0 -5 3 4 5 6 7 8 9 10 11 12 13 14 15 IF - Forward Current - mA Figure 6. ACPL-K71T/K74T (High Speed) Typical Propagation Delay vs Input Forward Current 60 70 40 30 20 TPHL TPLH PWD 10 0 -40 -20 0 20 40 60 TA - TEMPERATURE - C 80 100 120 TPHL TPLH PWD 30 20 10 3 4 5 6 7 8 9 10 11 12 IF - FORWARD CURRENT - mA 13 60 50 40 30 20 14 15 Figure 8. ACPL-K72T/K75T (5V) Typical Propagation Delay vs Input Forward Current TPHL TPLH PWD TA=25C, V DD =3V 70 60 50 40 30 20 10 10 -20 0 20 40 60 TA - TEMPERATURE - C 80 100 120 Figure 9. ACPL-K72T/K75T (3V) Typical Propagation Delay vs Temperature 9 40 80 IF = 4mA, V DD =3V 70 0 -40 50 -10 TP - PROPAGATION DELAY - ns TP - PROPAGATION DELAY - ns 80 TPHL TPLH PWD 0 Figure 7. ACPL-K72T/K75T (5V) Typical Propagation Delay vs Temperature 90 TA=25C, V DD =5V 60 50 TP - PROPAGATION DELAY - ns TP - PROPAGATION DELAY - ns IF = 4mA, V DD =5V 0 3 4 5 6 7 8 9 10 11 IF - FORWARD CURRENT - mA 12 13 14 15 Figure 10. ACPL-K72T/K75T (3V) Typical Propagation Delay vs Input Forward Current ACPL-K71T/K74T High Speed Mode: C IN 100pF V IN 4.5V to 5.5V + ACPL-K71T VDD 5V 1 8 2 7 3 6 R 1 3905% _ 0.1 F V IN VO monitoring node VO V TLH V THL C L = 15pF 4 VIN /2 V IN /2 tPLH tPHL 5 GND2 GND1 Figure 11. High Speed Mode Switching Test Circuit and Typical Waveform C IN 100pF ACPL-K71T V DD 5V 1 V IN 4.5V to 5.5V 8 R 1 3905% T r = tf 80 ns 0.1 F 2 7 3 1000V VO monitoring node 6 tr C L = 15pF 4 _ + GND1 V OH 5 90% 10% 90% 10% V CM tf Switch at LED=Off V OL Switch at LED=On GND2 High Voltage Pulse VCM Figure 12. High Speed Mode CMR Test Circuit and Typical Waveform ACPL-K72T/K75T Low Power Mode: ACPL-K72T V IN 4.5V to 5.5V + _ V DD 3V to5V 1 8 2 7 3 6 0.1 F R IN 700 VO monitoring node C L = 15pF 4 GND1 V IN /2 VO V THL V IN /2 V TLH 5 GND2 Figure 13. Low Power Mode Switching Test Circuit and Typical Waveform 10 V IN tPHL tPLH ACPL-K72T V DD 5V 1 V IN 4.5V to 5.5V 8 R 1 350 T r =t f 80 ns 0.1 F 2 7 3 6 1000V VO monitoring node C L = 15pF R 2 350 4 + GND1 tr V OH 5 V OL _ 90% 10% V CM tf Switch at LED=Off Switch at LED=On GND2 High Voltage Pulse V CM Figure 14. Low Power Mode CMR Test Circuit Recommended Application Circuits C IN 100pF ACPL-K71T V IN 1 V DD 8 R1 GND1 Truth Table 0.1 F 2 7 3 6 4 5 VO VIN LED Vo LOW ON LOW HIGH OFF HIGH GND2 Figure 15. Recommended Application Circuit for ACPL-K71T/K74T High Speed Performance ACPL-K72T V IN 1 V DD 8 R1 R1 = R 2 Truth Table 0.1 F 2 7 3 6 4 5 VO R2 GND1 GND2 Figure 16. Recommended Application Circuit for ACPL-K72T/K75T Low Power Performance 11 90% 10% VIN LED Vo LOW ON LOW HIGH OFF HIGH Thermal Resistance Model for ACPL-K71T/K72T The diagram of ACPL-K71T/K72T for measurement is shown in Figure 17. Here, one die is heated first and the temperatures of all the dice are recorded after thermal equilibrium is reached. Then, the 2nd die is heated and all the dice temperatures are recorded. With the known ambient temperature, the die junction temperature and power dissipation, the thermal resistance can be calculated. The thermal resistance calculation can be cast in matrix form. This yields a 2 by 2 matrix for our case of two heat sources. R11 R21 R11 R12 R21 R22 R12 R22 X P1 P2 = T1 T2 1 2 : Thermal Resistance of Die1 due to heating of Die1 (C/W) : Thermal Resistance of Die1 due to heating of Die2 (C/W) : Thermal Resistance of Die2 due to heating of Die1 (C/W) : Thermal Resistance of Die2 due to heating of Die2 (C/W) P1 : Power dissipation of Die1 (W) P2 : Power dissipation of Die2 (W) 8 Die1: LED 7 Die2: Detector 3 6 4 5 Figure 17. Diagram of ACPL-K71T/K72T for measurement T1 : Junction temperature of Die1 due to heat from all dice (C) T2 : Junction temperature of Die2 due to heat from all dice (C) Ta : Ambient temperature (C) T1 : Temperature difference between Die1 junction and ambient (C) T2 : Temperature deference between Die2 junction and ambient (C) T1 = (R11 x P1 + R12 x P2) + Ta T2 = (R21 x P1 + R22 x P2) + Ta Measurement data on a low K board: R11 = 160 C/W, R12= R21 = 74 C/W, R22 = 115 C/W Thermal Resistance Model for ACPL-K74T/K75T The diagram of ACPL-K74T/K75T for measurement is shown in Figure 18. Here, one die is heated first and the temperatures of all the dice are recorded after thermal equilibrium is reached. Then, the 2nd, 3rd and 4th die is heated and all the dice temperatures are recorded. With the known ambient temperature, the die junction temperature and power dissipation, the thermal resistance can be calculated. The thermal resistance calculation can be cast in matrix form. This yields a 4 by 4 matrix for our case of two heat sources. R11 R21 R31 R41 12 R12 R22 R32 R42 R13 R23 R33 R43 R14 R24 R34 R44 X P1 P2 P3 P4 = T1 T2 T3 T4 R11 R12 R13 R14 : Thermal Resistance of Die1 due to heating of Die1 (C/W) : Thermal Resistance of Die1 due to heating of Die2 (C/W) : Thermal Resistance of Die1 due to heating of Die3 (C/W) : Thermal Resistance of Die1 due to heating of Die4 (C/W) R21 R22 R23 R24 : Thermal Resistance of Die2 due to heating of Die1 (C/W) : Thermal Resistance of Die2 due to heating of Die2 (C/W) : Thermal Resistance of Die2 due to heating of Die3 (C/W) : Thermal Resistance of Die2 due to heating of Die4 (C/W) 1 8 Die1: LED 1 Die2: Detector 1 2 3 4 7 Die3: LED 1 Die4: Detector 2 6 5 Figure 18. Diagram of ACPL-K74T/K75T for measurement R31 R32 R33 R34 : Thermal Resistance of Die3 due to heating of Die1 (C/W) : Thermal Resistance of Die3 due to heating of Die2 (C/W) : Thermal Resistance of Die3 due to heating of Die3 (C/W) : Thermal Resistance of Die3 due to heating of Die4 (C/W) R41 R42 R43 R44 : Thermal Resistance of Die4 due to heating of Die1 (C/W) : Thermal Resistance of Die4 due to heating of Die2 (C/W) : Thermal Resistance of Die4 due to heating of Die3 (C/W) : Thermal Resistance of Die4 due to heating of Die4 (C/W) P1 P2 P3 P4 : Power dissipation of Die1 (W) : Power dissipation of Die2. : Power dissipation of Die3 (W) : Power dissipation of Die4. T1 T2 T3 T4 : Junction temperature of Die1 due to heat from all dice (C) : Junction temperature of Die2 due to heat from all dice (C) : Junction temperature of Die3 due to heat from all dice (C) : Junction temperature of Die4 due to heat from all dice (C) Ta : Ambient temperature (C) T1 : Temperature difference between Die1 junction and ambient (C) T2 : Temperature deference between Die2 junction and ambient (C) T3 : Temperature difference between Die3 junction and ambient (C) T4 : Temperature deference between Die4 junction and ambient (C) T1 T2 T3 T4 = (R11 x P1 + R12 x P2 + R13 x P3 + R14 x P4 ) + Ta -- (1) = (R21 x P1 + R22 x P2 + R23 x P3 + R24 x P4) + Ta -- (2) = (R31 x P1 + R32 x P2 + R33 x P3 + R34 x P4) + Ta -- (3) = (R41 x P1 + R42 x P2 + R43 x P3 + R44 x P4 ) + Ta -- (4) Measurement data on a low K board: R11 R12 R13 R14 R21 R22 R23 R24 R31 R32 R33 R34 R41 R42 R43 R44 160 76 76 76 76 115 76 76 76 76 160 76 76 76 76 115 For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright (c) 2005-2012 Avago Technologies. All rights reserved. AV02-3786EN - September 26, 2012 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Avago Technologies: ACPL-K74T-060E ACPL-K75T-560E ACPL-K75T-000E ACPL-K74T-560E ACPL-K72T-500E ACPL-K72T-560E ACPL-K72T-060E ACPL-K72T-000E ACPL-K74T-000E ACPL-K75T-060E ACPL-K71T-000E ACPL-K74T-500E ACPL-K75T-500E ACPL-K71T-500E ACPL-K71T-060E ACPL-K71T-560E