Preliminary MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor Features 1/4-Inch SOC VGA CMOS Digital Image Sensor MT9V131I29STC (iCSP) MT9V131C12STC (CLCC) Features Table 1: * Micron(R) DigitalClarity(R) CMOS imaging technology * System-On-a-Chip (SOC)--Completely integrated camera system * Ultra low-power, high fidelity CMOS image sensor * Superior low-light performance * Up to 30 fps progressive scan at 27 MHz for highquality video at VGA resolution * On-chip image flow processor (IFP) performs sophisticated processing: color recovery and correction, sharpening, gamma, lens shading correction, on-the-fly defect correction, 2X fixed zoom * Automatic exposure, white balance and black compensation, flicker avoidance, color saturation, and defect identification and correction, auto frame rate, back light compensation * Xenon and LED-type flash support * Two-wire serial programming interface * Progressive scan ITU_R BT.656 (YCbCr), YUV, 565RGB, 555RGB, and 444RGB output data formats Parameter Typical Value Optical format Active imager size Active pixels Pixel size Color filter array Shutter type Maximum data rate master clock VGA (640 x 480) Frame rate CIF (352 x 288) QVGA (320 x 240) ADC resolution Responsivity Dynamic range SNRMAX Supply voltage Power consumption Operating temperature Packaging Applications * * * * Key Performance Parameters Security Biometrics Network cameras Toys and other battery-powered products 1/4-inch (4:3) 3.58mm(H) x 2.69mm(V) 4.48mm (diagonal) 640H x 480V (VGA) 5.6m x 5.6m RGB Bayer pattern Electronic rolling shutter (ERS) 12-13.5 Mp/s 24-27 MHz 15 fps at 12 MHz (default), programmable up to 30 fps at 27 MHz Programmable up to 60 fps Programmable up to 90 fps 10-bit, on-chip 1.9 V/lux-sec (550nm) 60dB 45dB 2.8V +0.25V <80mW at 2.8V, 15 fps at 12MHz -20C to +60C 44-Ball iCSP, 48-Pin CLCC The sensor is a complete camera-on-a-chip solution and is designed specifically to meet the demands of battery-powered products such as security cameras, PDAs, and toys. It incorporates sophisticated camera functions on-chip and is programmable through a simple two-wire serial interface. Ordering Information Table 2: Available Part Numbers Part Number MT9V131I29STC MT9V131C12STC ES MT9V131C12STCD ES MT9V131C12STCH ES PDF: 09005aef824c99b3/Source: 009005aef824c99bb MT9V131_LDS_1.fm - Rev. B 3/07 EN 1 Description 44-ball iCSP 48-pin CLCC ES (color) Demo kit (color) Demo kit headboard (color) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications. Preliminary MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor General Description General Description This SOC VGA CMOS image sensor features DigitalClarityMicron's breakthrough, low-noise CMOS imaging technology that achieves CCD image quality (based on signalto-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. The MT9V131 is a fully-automatic, single-chip camera, requiring only a power supply, lens, and clock source for basic operation. Output video is streamed through a parallel 8-bit port, as shown in Figure 2 on page 3. Output pixel clock is used to latch the data, while FRAME_VALID and LINE_VALID signals indicate the active video. The sensor can be put in an ultra-low power sleep mode by asserting the STANDBY pin. Output pads can also be tri-stated by de-asserting the OE# pin. The MT9V131 internal registers can be configured using a two-wire serial interface. The MT9V131 can be programmed to output progressive scan images up to 30 fps in an 8-bit ITU_R BT.656 (YCbCr) formerly CCIR656, YUV, 565RGB, 555RGB, or 444RGB formats. The FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a pixel clock that is synchronous with valid data. Table 3 lists typical values of MT9V131 performance parameters. Table 3: MT9V131 Detailed Performance Parameters Parameter Pixel count Active pixel Resolution Optical format Power consumption Dynamic range Shutter type Output gain Read noise Dark current Responsivity Operating frequency Master clock Data rate Operating temperature PDF: 09005aef824c99b3/Source: 009005aef824c99bb MT9V131_LDS_2.fm - Rev. B 3/07 EN 2 Typ Unit 0.31 640 x 480 1/4 <80 60 Rolling 28 6 150 2.5 Million Pixels HXV Inches mW dB Type e-/LSB e-RMS at 16X e-/pix/sec at 55C V/lux-sec 24 to 27 12 to 13.5 -20 to +60 MHz Mp/s C Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor General Description Figure 1 illustrates the MT9V131 quantum efficiency in relation to wavelength. Figure 1: MT9V131 Quantum Efficiency vs. Wavelength 50 Blue Green Red Quantum Efficiency (%) 45 40 35 30 25 20 15 10 5 0 350 400 450 500 550 600 650 700 750 800 Wavelength (nm) Figure 2: Chip Block Diagram SCLK SDATA SADDR CLK STANDBY OE# VDD/DGND VAA/AGND VAAPIX Communication Bus Image Flow Processor Sensor Core . Based on MT9V011 . 668H x 496V (VGA+ Reference) . 1/4-inch optical format . Auto Black compensation . Programmable analog gain . Programmable exposure . Low power, 10-bit ADCs . Color correction, gamma, DOUT(7:0) lens shading correction . Auto exposure, white balance . Interpolation and defect correction . Flicker avoidance PIXCLK FRAME_VALID LINE_VALID FLASH SRAM Line Buffers The MT9V131 can accept the input clock of up to 27 MHz, delivering 30 fps. With power-on defaults, the camera is configured to deliver 15 fps at 12 MHz and automatically slows down the frame rate in low-light conditions to achieve longer exposures and better image quality. Internally, the MT9V131 consists of a sensor core and an image flow processor. The sensor core functions to capture raw Bayer-encoded images that are input into the IFP as shown in Figure 2. The IFP processes the incoming stream to create interpolated, color-corrected output and controls the sensor core to maintain the desirable exposure and color balance. PDF: 09005aef824c99b3/Source: 009005aef824c99bb MT9V131_LDS_2.fm - Rev. B 3/07 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor General Description Figure 3 shows MT9V131 typical connections. For low-noise operation, the MT9V131 requires separate supplies for analog and digital power. Incoming digital and analog ground conductors can be tied together right next to the die. Both power supply rails should be decoupled to ground using capacitors. The use of inductance filters is not recommended. Figure 3: Typical Configuration (Connection) VDD VDD VAA VAAPIX ADC_TEST VAA 1.5K SADDR 1.5K 1K RESET# Two-wire serial bus { Master Clock DOUT(7:0) FRAME_VALID LINE_VALID PIXCLK SDATA SCLK { 10F To CMOS camera port CLKIN FLASH To Xenon flash trigger or LED enable SCAN_EN DGND Note: PDF: 09005aef824c99b3/Source: 009005aef824c99bb MT9V131_LDS_2.fm - Rev. B 3/07 EN AGND STANDBY DGND OE# AGND For two-wire serial interface, a 1.5K resistor is recommended, but may be greater for slower two-wire speed. 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor Ball Assignment Ball Assignment Figure 4: 44-Ball iCSP Pinout Diagram 1 2 3 4 5 6 7 A DGND DOUT2 DOUT4 DGND DOUT6 VDD DGND B DOUT1 VDD DOUT3 VDD DOUT7 VDD VDD C NC DOUT0 DOUT5 VDD SCAN DGND D DGND _EN OE# NC E PIXCLK FLASH F FRAME_ VALID VDD SCLK G DGND CLKIN SDATA DGND VDD RESET# STAND SADDR AGND ADC_ TEST VAAPIX DGND VAA VAA AGND LINE_ VALID BY Top View (Ball Down) 47 46 DGND 48 DOUT7 1 VDD 2 DOUT6 3 VDD DOUT4 4 DOUT5 DOUT3 5 DGND DGND 6 DOUT2 NC 48-Pin CLCC Pinout Diagram 45 44 43 NC VDD 7 42 DOUT1 8 41 VDD DOUT0 9 40 VDD DOUT_LSB1 10 39 SCAN_EN DOUT_LSB0 11 38 DGND DGND 12 37 VDD FLASH 13 36 DGND PIXCLK 14 35 OE# STANDBY PDF: 09005aef824c99b3/Source: 009005aef824c99bb MT9V131_LDS_2.fm - Rev. B 3/07 EN CLKIN 20 21 22 23 24 25 26 27 28 29 30 NC ADC_TEST 19 AGND NC 31 VAA VAAPIX 18 AGND 32 VAA 17 VDD RESET# VDD DGND 33 SADDR 16 SDATA 15 FRAME_VALID SCLK LINE_VALID 34 DGND Figure 5: 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor Ball Assignment Table 4: Ball and Pin Description Symbol CLCC Pin iCSP Ball Type Description CLKIN 20 G2 Input SCLK SADDR 21 23 F3 F4 Input Input ADC_TEST RESET# 31 33 F6 E6 Input Input STANDBY 34 E7 Input OE# 35 D6 Input SCAN_EN SDATA FLASH PIXCLK 39 22 13 14 C6 G3 E2 E1 Input I/O Output Output LINE_VALID FRAME_VALID DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 VDD 15 16 45 46 1 2 3 4 8 9 7, 17, 25, 40, 41, 44, 47 26, 28 32 27, 29 5, 12, 24, 36, 38, 43, 48 6, 18, 30, 42 E3 F1 B5 A5 C3 A3 B3 A2 B1 C2 A6, B2, B4, B6, B7, C5, E5, F2 G5, G6 F7 F5, G7 A1, D1, A4, A7, C7, D7, G1, G4 C1, D2 Output Output Output Output Output Output Output Output Output Output Supply Master clock into sensor. Default is 12 MHz (27 MHz maximum). Serial clock. Serial interface address select: Reg0xB8 when HIGH (default). Reg0x90 when LOW. Tie to VAAPIX (factory use only). Asynchronous reset of sensor when LOW. All registers assume factory defaults. When HIGH, puts the imager in ultra-low power standby mode. Output_Enable_Bar pin. When HIGH, tri-state all outputs except SDATA (tie LOW for normal operation). Tie to digital ground. Serial data I/O. Flash strobe. Pixel clock out. Pixel data output are valid during rising edge of this clock. IFP Reg0x08 [9] inverts polarity. Frequency = Master clock. Active HIGH during line of selectable valid pixel data. Active HIGH during frame of valid pixel data. ITU_R BT.656/RGB data bit 7 (MSB). ITU_R BT.656/RGB data bit 6. ITU_R BT.656/RGB data bit 5. ITU_R BT.656/RGB data bit 4. ITU_R BT.656/RGB data bit 3. ITU_R BT.656/RGB data bit 2. ITU_R BT.656/RGB data bit 1. ITU_R BT.656/RGB data bit 0 (LSB). Digital power (2.8V). Supply Supply Supply Supply Analog power (2.8V). Pixel array power (2.8V). Analog ground. Digital ground. VAA VAAPIX AGND DGND NC PDF: 09005aef824c99b3/Source: 009005aef824c99bb MT9V131_LDS_2.fm - Rev. B 3/07 EN - 6 No connect. Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor Image Flow Processor Image Flow Processor Overview of Architecture The image flow processor consists of a color processing pipeline and a measurement and control logic block, as shown in Figure 6 on page 8. The stream of raw data from the sensor enters the pipeline and undergoes a number of transformations. Image stream processing starts from conditioning the black level and applying a digital gain. The lens shading block compensates for signal loss caused by the lens. Next, the data is interpolated to recover missing color components for each pixel and defective pixels are corrected. The resulting interpolated RGB data passes through the current color correction matrix (CCM), gamma, and saturation corrections and is formatted for final output. The measurement and control logic continuously accumulates statistics about image brightness and color. Indoor 50/60Hz flicker is detected and automatically updated when possible. Based on these measurements, the IFP calculates updated values for exposure time and sensor analog gains, which are sent to the sensor core through the communication bus. Color correction is achieved through linear transformation of the image with a 3 x 3 color correction matrix. Color saturation can be adjusted in the range from zero (black and white) to 1.25 (125% of full color saturation). Gamma correction compensates for nonlinear dependence of the display device output versus driving signal (monitor brightness versus CRT voltage). Output and Formatting Processed video can be output in the form of a progressive scan ITU_R BT.656 or RGB stream. ITU_R BT.656 (default) stream contains 4:2:2 data with optional embedded synchronization codes. This kind of output is typically suitable for subsequent display by standard video equipment. For JPEG/MPEG compression, YUV/ encoding is suitable. RGB functionality is provided to support LCD devices. The MT9V131 can be configured to output 16-bit RGB (RGB565) and 15-bit RGB (RGB555), as well as two types of 12-bit RGB (RGB444). The user can configure internal registers to swap odd and even bytes, chrominance channels, and luminance and chrominance components to facilitate interface to application processors. PDF: 09005aef824c99b3/Source: 009005aef824c99bb MT9V131_LDS_2.fm - Rev. B 3/07 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor Image Flow Processor Figure 6: Image Flow Processor Block Diagram IMAGE SENSOR LENS CORRECTION DEMOSAICING AE, AWB, FLICKER AVOIDANCE COLOR CORRECTION FLASH CONTROL GAMMA CORRECTION OUTPUT FORMATTING The MT9V131 features smooth, continuous zoom and pan. This functionality is available when the IFP output is downsized in the decimation block. The decimation block can downsize the original VGA image to any integer size, including QVGA, QQVGA, CIF, and QCIF with no loss to the field of view. The user can program the desired size of the output image in terms of horizontal and vertical pixel count. In addition, the user can program the size of a region for downsizing. Continuous zoom is achieved every time the region of interest is less than the entire VGA image. The maximum zoom factor is equal to the ratio of VGA to the size of the region of interest. For example, an image rendered on a 160 x 120 display can be zoomed by 640/160 = 480/120 = 4 times. Continuous pan is achieved by adjusting the starting coordinates of the region of interest. Also, a fixed 2X up-zoom is implemented by means of windowing down the sensor core. In this mode, the IFP receives a QVGA-sized input data and outputs a VGA-size image. The sub-window can be panned both vertically and horizontally by programming sensor core registers. The MT9V131 supports both LED and Xenon-type flash light sources using a dedicated output pad. For Xenon devices, the pad generates a strobe to fire when the imager's shutter is fully open. For LED, the pad can be asserted or de-asserted asynchronously. Flash modes are configured and engaged over the two-wire serial interface using IFP. PDF: 09005aef824c99b3/Source: 009005aef824c99bb MT9V131_LDS_2.fm - Rev. B 3/07 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor Sensor Core Overview Sensor Core Overview The sensor consists of a pixel array of 668 x 496 total, analog readout chain, 10-bit ADC with programmable gain and black offset, and timing and control. Figure 7: Sensor Core Block Diagram Control Register Active Pixel Sensor Array Communication Bus to IFP Timing and Control Clock Sync. Signals Analog Processing ADC 10-bit Data to IFP The sensor core image data is read-out in a progressive scan. Valid image data is surrounded by horizontal and vertical blanking, as shown in Figure 8. Figure 8: Spatial Illustration of Image Readout P0,0 P0,1 P0,2.....................................P0,n-1 P0,n P1,0 P1,1 P1,2.....................................P1,n-1 P1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VALID IMAGE HORIZONTAL BLANKING Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00 Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00 PDF: 09005aef824c99b3/Source: 009005aef824c99bb MT9V131_LDS_2.fm - Rev. B 3/07 EN 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL BLANKING VERTICAL/HORIZONTAL BLANKING 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor Electrical Specifications Electrical Specifications The recommended die operating temperature ranges from -20C to +40C. The sensor image quality may degrade above +40C. Table 5: DC Electrical Characteristics VDD = VAA = 2.8 0.25V; TA = 25C Symbol Definition VIH VIL IIN Input high voltage Input low voltage Input leakage current VOH VOL IOH IOL IOZ IAA Output high voltage Output low voltage Output high current Output low current Tri-state output leakage current Analog operating supply current IDD Digital operating supply current IAA Standby Analog standby supply current IDD Standby Digital standby supply current Notes: Condition Min Typ VDD - 0.25 -0.3 No pull-up resistor; VIN = VDD or -5 DGND VDD - 0.2 Default settings, CLOAD = 10pF CLKIN = 12 MHz CLKIN = 27 MHz Default settings, CLOAD = 10pF CLKIN = 12 MHz CLKIN = 27 MHz STDBY = VDD STDBY = VDD Max Unit VDD + 0.25 0.8 5.0 V V A 0.2 15.0 20.0 5.0 V V mA mA A 10.0 10.0 20.0 20.0 25.0 25.0 mA 5.0 10.0 0.0 0.0 8.0 15.0 2.5 2.5 20.0 20.0 5.0 5.0 mA A A 1. To place the chip in standby mode, first raise STANDBY to VDD, then wait two master clock cycles before turning off the master clock. Two master clock cycles are required to place the analog circuitry into standby, low-power mode. 2. When STANDBY is de-asserted, standby mode is exited immediately (within several master clocks), but the current frame and the next two frames will be invalid. The fourth frame will contain a valid image. PDF: 09005aef824c99b3/Source: 009005aef824c99bb MT9V131_LDS_2.fm - Rev. B 3/07 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor Electrical Specifications Table 6: AC Electrical Characteristics VDD = VAA = 2.8 0.25V; TA = 25C Definition Symbol Input clock frequency Clock duty cycle Input clock rise time Input clock fall time CLKIN to PIXCLK propagation delay PIXCLK to DOUT[7:0] at 27 MHz PIXCLK to FRAME_VALID and LINE_VALID propagation delay Output rise time Output fall time Notes: Condition f CLKIN 50:50 t R tF LOW-to-HIGH HIGH-to-LOW Setup time Hold time LOW-to-HIGH HIGH-to-LOW t PLHP PHLP t DSETUP t DHOLD tPLH F,L tPHL F,L t OUTR t OUTF CLOAD = 10pF t CLOAD = 10pF CLOAD = 10pF CLOAD = 10pF CLOAD = 10pF Min Typ Max Unit 10 45 1 1 6 6 11 11 4 4 5 5 12 50 2 2 12 10 18 18 9.0 7.5 7.0 9.0 27 55 5 5 14 14 - - 13 13 15 15 MHz % ns ns ns ns ns ns ns ns ns ns Notes 1 3 2 1. For 30 fps operation with a 27 MHz clock, the user must have a precise duty cycle equal to 50%. With a slower frame rate and a slower clock, the clock duty cycle can be relaxed. 2. Typical is 1/2 of CLKIN period. 3. PIXCLK can be programmed to be inverted or non-inverted. PDF: 09005aef824c99b3/Source: 009005aef824c99bb MT9V131_LDS_2.fm - Rev. B 3/07 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor Electrical Specifications Figure 9: 44-Ball iCSP Package Outline 0.95 (FOR REFERENCE ONLY) 1.17 0.10 B SEATING PLANE 0.10 A A 0.22 (FOR REFERENCE ONLY) 0.175 (FOR REFERENCE ONLY) 0.575 0.050 4.50 0.375 0.075 44X O0.35 BALL A1 CORNER BALL A1 BALL A1 ID 0.75 TYP BALL A7 5.30 CTR PIXEL (0,0) 3.500 0.075 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE PREREFLOW DIAMETER IS O0.33 3.400 0.075 3.50 0.05 CL 4.50 2.688 5.30 CTR CTR 7.00 0.075 0.100 (FOR REFERENCE ONLY) OPTICAL CENTER PACKAGE CENTER 2.25 0.75 TYP CL 2.25 3.50 0.05 OPTICAL AREA 3.584 CTR MAXIMUM ROTATION OF OPTICAL AREA RELATIVE TO PACKAGE EDGES: 1 MAXIMUM TILT OF OPTICAL AREA RELATIVE TO B : 0.3 MAXIMUM TILT OF OPTICAL AREA RELATIVE TO TOP OF COVER GLASS: 0.3 7.00 0.075 LID MATERIAL: BOROSILICATE GLASS 0.40 THICKNESS IMAGE SENSOR DIE SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2%Ag OR 96.5% Sn, 3%Ag, 0.5% Cu SOLDER MASK DEFINED BALL PADS: O 0.27 SUBSTRATE MATERIAL: PLASTIC LAMINATE ENCAPSULANT: EPOXY Notes: 1. All dimensions in millimeters. 2. iCSP package information is preliminary. PDF: 09005aef824c99b3/Source: 009005aef824c99bb MT9V131_LDS_2.fm - Rev. B 3/07 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor Electrical Specifications Figure 10: 48-Pin CLCC Package Outline 2.3 0.2 D 1.7 Seating plane Substrate material: alumina ceramic 0.7 thickness Wall material: alumina ceramic A Lid material: borosilicate glass 0.55 thickness 8.8 47X 1.0 0.2 0.8 TYP 4.4 48 48X 0.40 0.05 48X R 0.15 H CTR 1.75 O0.20 A B C 1 First clear pixel 5.215 4.84 4.4 O0.20 A B C 5.715 0.8 TYP 4X 10.9 0.1 CTR V CTR 11.43 8.8 Image sensor die: 0.675 thickness 0.2 5.215 5.715 11.43 Lead finish: Au plating, 0.50 microns minimum thickness over Ni plating, 1.27 microns minimum thickness Notes: C Optical area A B 0.05 0.10 A 1.400 0.125 0.90 for reference only 0.35 for reference only 10.9 0.1 CTR Optical center1 Optical area: Maximum rotation of optical area relative to package edges: 1 Maximum tilt of optical area relative to seating plane A : 50 microns Maximum tilt of optical area relative to top of cover glass D : 100 microns 1. Optical center = package center. 2. All dimensions are in millimeters. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, the Micron logo, and DigitalClarity are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. PDF: 09005aef824c99b3/Source: 009005aef824c99bb MT9V131_LDS_2.fm - Rev. B 3/07 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor Revision History Revision History Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/28/2007 * Updated package diagram PDF: 09005aef824c99b3/Source: 009005aef824c99bb MT9V131_LDS_2.fm - Rev. B 3/07 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved.