RT8168B Dual Single-Phase PWM Controller for CPU and GPU Core Power Supply General Description Features The RT8168B is a dual single-phase PWM controller with integrated MOSFET drivers, compliant with Intel IMVP7 Pulse Width Modulation Specification to support both CPU core and GPU core power. This part adopts G-NAVPTM (Green-Native AVP), which is a Richtek proprietary topology derived from finite DC gain compensator in constant ontime control mode. G-NAVPTM makes this part an easy setting PWM controller to meet all Intel AVP (Active Voltage Positioning) mobile CPU/GPU requirements. The RT8168B uses SVID interface to control an 8-bit DAC for output voltage programming. The built-in high accuracy DAC converts the received VID code into a voltage value ranging from 0V to 1.52V with 5mV step voltage. The system accuracy of the controller can reach 0.8%. The RT8168B operates in continuous conduction mode or diode emulation mode, according to the SVID command. The maximum efficiency can reach up to 90% in different operating modes according to different load conditions. The droop function (load line) can be easily programmed by setting the DC gain of the error amplifier. With proper compensation, the load transient response can achieve optimized AVP performance. z The output voltage transition slew rate is set via the SVID interface. The RT8168B supports both DCR and sense resistor current sensing. The RT8168B provides VR_READY and thermal throttling output signals for IMVP7 CPU and GPU core. This part also features complete fault protection functions including over voltage, under voltage, negative voltage, over current and thermal shutdown. z z z z z z z z z z z z z z z z Dual Single-Phase PWM Controller for CPU Core and GPU Core Power IMVP7 Compatible Power Management States Serial VID Interface G-NAVPTM Topology AVP for CPU VR Only 0.5% DAC Accuracy 0.8% System Accuracy Differential Remote Voltage Sensing Built-in ADC for Platform Programming SETINI/SETINIA for CPU/GPU Core VR Initial Startup Voltage TMPMAX to Set Platform Maximum Temperature ICCMAX/ICCMAXA for CPU/GPU Core VR Maximum Current Power Good Indicator : VR_READY/VRA_READY for CPU/GPU Core Power Thermal Throttling Indicator : VRHOT Diode Emulation Mode at Light Load Condition Fast Line/Load Transient Response Switching Frequency up to 1MHz per Phase OVP, UVP, NVP, OTP, UVLO, OCP Small 40-Lead WQFN Package RoHS Compliant and Halogen Free Applications z z z IMVP7 Intel CPU/GPU Core Power Supply Laptop Computers AVP Step-Down Converter The RT8168B is available in a WQFN-40L 5x5 small footprint package. DS8168B-00 November 2011 www.richtek.com 1 RT8168B Ordering Information Pin Configurations (TOP VIEW) UGATE1 PHASE1 LGATE1 PVCC LGATEA PHASEA UGATEA BOOTA EN TONSETA RT8168B Package Type QW : WQFN-40L 5x5 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Marking Information RT8168BGQW : Product Number RT8168B GQW YMDNN YMDNN : Date Code 40 39 38 37 36 35 34 33 32 31 BOOT1 TONSET ISEN1P ISEN1N COMP FB RGND GFXPS2 VCC SETINIA 1 30 2 29 3 28 4 27 5 26 GND 25 6 24 7 8 41 23 22 9 21 10 ISENAP ISENAN COMPA FBA RGNDA VCLK VDIO ALERT VRA_READY VR_READY 11 12 13 14 15 16 17 18 19 20 SETINI TMPMAX ICCMAX ICCMAXA TSEN OCSET TSENA OCSETA IBIAS VRHOT Note : WQFN-40L 5x5 www.richtek.com 2 DS8168B-00 November 2011 RT8168B Typical Application Circuit R1 2.2 RT8168B VCC 5V C1 1F 9 VCC VCCP R6 R7 R8 R9 TONSET 2 BOOT1 VCLK VDIO ALERT VRA_READY VR_READY VRHOT 130 130 150 10k 10k 75 25 VCLK 24 VDIO 23 ALERT 22 VRA_READY 21 VR_READY 20 VRHOT VCC R17 27k R18 8.7k R19 10k R20 10k 18 OCSETA 16 OCSET 10 SETINIA 11 SETINI OCSETA OCSET SETINIA SETINI R24 10k R25 10k R26 NC PHASE1 LGATE1 PVCC 40 R4 0 1 R5 R31 R32 100k NC 38 ICCMAX ICCMAXA GFXPS2 R37 33k R38 5.1k R39 1.6k R40 10k NTCT1 10k = 3380 R47 12k R71 750 R72 750 R52 1k 3 ISEN1P ISEN1N 4 6 FB R14 3.9k Optional Optional C10 C9 Optional C11 COMP 5 R21 R22 R23 7 71k 10k 100 VCORE CORE VSS SENSE BOOTA PHASEA R34 5.1 R33 130k 33 R36 0 VIN 5V to 25V C12 0.1F Q3 C13 0.1F 35 C14 10F DCR = 14.6m L2 2H Optional R42 Q4 R43 11k 15 TSEN 19 IBIAS C17 330F /15m C16 0.1F R45 1.2k C18 Optional Optional C19 VGFX C27 330F /15m C15 R44 1k NTCA 1k = 3650 Optional C20 GFX VCC SENSE 17 TSENA 28 R48 R49 R50 RGNDA 26 42k 10k 100 COMPA R54 53.6k November 2011 NTC1 4.7k = 3500 R15 4.7k R16 2.4k C26 330F /9m C5 330F /9m C6 0.068F 5V ISENAP 30 ISENAN 29 NTCTA 10k = 3380 Chip Enable VCORE CORE VCC SENSE GND DS8168B-00 R13 C7 37 FBA 27 R53 1k DCR = 7.6m L1 1H Optional Q2 R41 0 LGATEA 36 VCC R46 12k R12 0 R35 0 UGATEA 34 12 TMPMAX 13 ICCMAX 14 ICCMAXA 8 GFXPS2 TMPMAX C4 0.1F 0 R28 100 VCC R30 150k C3 10F Q1 39 TONSETA 31 R29 51k VIN 5V to 25V C8 1F RGND R27 NC R3 5.1 C2 0.1F UGATE1 R10 R11 R2 130k 41 (Exposed Pad) VGFX GFX VSS SENSE R51 100 32 EN www.richtek.com 3 RT8168B Table 1. IMVP7/VR12 Compliant VID Table VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 VDAC Voltage 0 0 0 0 0 0 0 0 0 0 0.000 0 0 0 0 0 0 0 1 0 1 0.250 0 0 0 0 0 0 1 0 0 2 0.255 0 0 0 0 0 0 1 1 0 3 0.260 0 0 0 0 0 1 0 0 0 4 0.265 0 0 0 0 0 1 0 1 0 5 0.270 0 0 0 0 0 1 1 0 0 6 0.275 0 0 0 0 0 1 1 1 0 7 0.280 0 0 0 0 1 0 0 0 0 8 0.285 0 0 0 0 1 0 0 1 0 9 0.290 0 0 0 0 1 0 1 0 0 A 0.295 0 0 0 0 1 0 1 1 0 B 0.300 0 0 0 0 1 1 0 0 0 C 0.305 0 0 0 0 1 1 0 1 0 D 0.310 0 0 0 0 1 1 1 0 0 E 0.315 0 0 0 0 1 1 1 1 0 F 0.320 0 0 0 1 0 0 0 0 1 0 0.325 0 0 0 1 0 0 0 1 1 1 0.330 0 0 0 1 0 0 1 0 1 2 0.335 0 0 0 1 0 0 1 1 1 3 0.340 0 0 0 1 0 1 0 0 1 4 0.345 0 0 0 1 0 1 0 1 1 5 0.350 0 0 0 1 0 1 1 0 1 6 0.355 0 0 0 1 0 1 1 1 1 7 0.360 0 0 0 1 1 0 0 0 1 8 0.365 0 0 0 1 1 0 0 1 1 9 0.370 0 0 0 1 1 0 1 0 1 A 0.375 0 0 0 1 1 0 1 1 1 B 0.380 0 0 0 1 1 1 0 0 1 C 0.385 0 0 0 1 1 1 0 1 1 D 0.390 0 0 0 1 1 1 1 0 1 E 0.395 0 0 0 1 1 1 1 1 1 F 0.400 0 0 1 0 0 0 0 0 2 0 0.405 0 0 1 0 0 0 0 1 2 1 0.410 0 0 1 0 0 0 1 0 2 2 0.415 To be continued www.richtek.com 4 DS8168B-00 November 2011 RT8168B VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 0 0 1 0 0 0 1 1 2 3 0.420 0 0 1 0 0 1 0 0 2 4 0.425 0 0 1 0 0 1 0 1 2 5 0.430 0 0 1 0 0 1 1 0 2 6 0.435 0 0 1 0 0 1 1 1 2 7 0.440 0 0 1 0 1 0 0 0 2 8 0.445 0 0 1 0 1 0 0 1 2 9 0.450 0 0 1 0 1 0 1 0 2 A 0.455 0 0 1 0 1 0 1 1 2 B 0.460 0 0 1 0 1 1 0 0 2 C 0.465 0 0 1 0 1 1 0 1 2 D 0.470 0 0 1 0 1 1 1 0 2 E 0.475 0 0 1 0 1 1 1 1 2 F 0.480 0 0 1 1 0 0 0 0 3 0 0.485 0 0 1 1 0 0 0 1 3 1 0.490 0 0 1 1 0 0 1 0 3 2 0.495 0 0 1 1 0 0 1 1 3 3 0.500 0 0 1 1 0 1 0 0 3 4 0.505 0 0 1 1 0 1 0 1 3 5 0.510 0 0 1 1 0 1 1 0 3 6 0.515 0 0 1 1 0 1 1 1 3 7 0.520 0 0 1 1 1 0 0 0 3 8 0.525 0 0 1 1 1 0 0 1 3 9 0.530 0 0 1 1 1 0 1 0 3 A 0.535 0 0 1 1 1 0 1 1 3 B 0.540 0 0 1 1 1 1 0 0 3 C 0.545 0 0 1 1 1 1 0 1 3 D 0.550 0 0 1 1 1 1 1 0 3 E 0.555 0 0 1 1 1 1 1 1 3 F 0.560 0 1 0 0 0 0 0 0 4 0 0.565 0 1 0 0 0 0 0 1 4 1 0.570 0 1 0 0 0 0 1 0 4 2 0.575 0 1 0 0 0 0 1 1 4 3 0.580 0 1 0 0 0 1 0 0 4 4 0.585 0 1 0 0 0 1 0 1 4 5 0.590 To be continued DS8168B-00 November 2011 www.richtek.com 5 RT8168B VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 0 1 0 0 0 1 1 0 4 6 0.595 0 1 0 0 0 1 1 1 4 7 0.600 0 1 0 0 1 0 0 0 4 8 0.605 0 1 0 0 1 0 0 1 4 9 0.610 0 1 0 0 1 0 1 0 4 A 0.615 0 1 0 0 1 0 1 1 4 B 0.620 0 1 0 0 1 1 0 0 4 C 0.625 0 1 0 0 1 1 0 1 4 D 0.630 0 1 0 0 1 1 1 0 4 E 0.635 0 1 0 0 1 1 1 1 4 F 0.640 0 1 0 1 0 0 0 0 5 0 0.645 0 1 0 1 0 0 0 1 5 1 0.650 0 1 0 1 0 0 1 0 5 2 0.655 0 1 0 1 0 0 1 1 5 3 0.660 0 1 0 1 0 1 0 0 5 4 0.665 0 1 0 1 0 1 0 1 5 5 0.670 0 1 0 1 0 1 1 0 5 6 0.675 0 1 0 1 0 1 1 1 5 7 0.680 0 1 0 1 1 0 0 0 5 8 0.685 0 1 0 1 1 0 0 1 5 9 0.690 0 1 0 1 1 0 1 0 5 A 0.695 0 1 0 1 1 0 1 1 5 B 0.700 0 1 0 1 1 1 0 0 5 C 0.705 0 1 0 1 1 1 0 1 5 D 0.710 0 1 0 1 1 1 1 0 5 E 0.715 0 1 0 1 1 1 1 1 5 F 0.720 0 1 1 0 0 0 0 0 6 0 0.725 0 1 1 0 0 0 0 1 6 1 0.730 0 1 1 0 0 0 1 0 6 2 0.735 0 1 1 0 0 0 1 1 6 3 0.740 0 1 1 0 0 1 0 0 6 4 0.745 0 1 1 0 0 1 0 1 6 5 0.750 0 1 1 0 0 1 1 0 6 6 0.755 0 1 1 0 0 1 1 1 6 7 0.760 0 1 1 0 1 0 0 0 6 8 0.765 0 1 1 0 1 0 0 1 6 9 0.770 To be continued www.richtek.com 6 DS8168B-00 November 2011 RT8168B VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 0 1 1 0 1 0 1 0 6 A 0.775 0 1 1 0 1 0 1 1 6 B 0.780 0 1 1 0 1 1 0 0 6 C 0.785 0 1 1 0 1 1 0 1 6 D 0.790 0 1 1 0 1 1 1 0 6 E 0.795 0 1 1 0 1 1 1 1 6 F 0.800 0 1 1 1 0 0 0 0 7 0 0.805 0 1 1 1 0 0 0 1 7 1 0.810 0 1 1 1 0 0 1 0 7 2 0.815 0 1 1 1 0 0 1 1 7 3 0.820 0 1 1 1 0 1 0 0 7 4 0.825 0 1 1 1 0 1 0 1 7 5 0.830 0 1 1 1 0 1 1 0 7 6 0.835 0 1 1 1 0 1 1 1 7 7 0.840 0 1 1 1 1 0 0 0 7 8 0.845 0 1 1 1 1 0 0 1 7 9 0.850 0 1 1 1 1 0 1 0 7 A 0.855 0 1 1 1 1 0 1 1 7 B 0.860 0 1 1 1 1 1 0 0 7 C 0.865 0 1 1 1 1 1 0 1 7 D 0.870 0 1 1 1 1 1 1 0 7 E 0.875 0 1 1 1 1 1 1 1 7 F 0.880 1 0 0 0 0 0 0 0 8 0 0.885 1 0 0 0 0 0 0 1 8 1 0.890 1 0 0 0 0 0 1 0 8 2 0.895 1 0 0 0 0 0 1 1 8 3 0.900 1 0 0 0 0 1 0 0 8 4 0.905 1 0 0 0 0 1 0 1 8 5 0.910 1 0 0 0 0 1 1 0 8 6 0.915 1 0 0 0 0 1 1 1 8 7 0.920 1 0 0 0 1 0 0 0 8 8 0.925 1 0 0 0 1 0 0 1 8 9 0.930 1 0 0 0 1 0 1 0 8 A 0.935 1 0 0 0 1 0 1 1 8 B 0.940 1 0 0 0 1 1 0 0 8 C 0.945 1 0 0 0 1 1 0 1 8 D 0.950 To be continued DS8168B-00 November 2011 www.richtek.com 7 RT8168B VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 1 0 0 0 1 1 1 0 8 E 0.955 1 0 0 0 1 1 1 1 8 F 0.960 1 0 0 1 0 0 0 0 9 0 0.965 1 0 0 1 0 0 0 1 9 1 0.970 1 0 0 1 0 0 1 0 9 2 0.975 1 0 0 1 0 0 1 1 9 3 0.980 1 0 0 1 0 1 0 0 9 4 0.985 1 0 0 1 0 1 0 1 9 5 0.990 1 0 0 1 0 1 1 0 9 6 0.995 1 0 0 1 0 1 1 1 9 7 1.000 1 0 0 1 1 0 0 0 9 8 1.005 1 0 0 1 1 0 0 1 9 9 1.010 1 0 0 1 1 0 1 0 9 A 1.015 1 0 0 1 1 0 1 1 9 B 1.020 1 0 0 1 1 1 0 0 9 C 1.025 1 0 0 1 1 1 0 1 9 D 1.030 1 0 0 1 1 1 1 0 9 E 1.035 1 0 0 1 1 1 1 1 9 F 1.040 1 0 1 0 0 0 0 0 A 0 1.045 1 0 1 0 0 0 0 1 A 1 1.050 1 0 1 0 0 0 1 0 A 2 1.055 1 0 1 0 0 0 1 1 A 3 1.060 1 0 1 0 0 1 0 0 A 4 1.065 1 0 1 0 0 1 0 1 A 5 1.070 1 0 1 0 0 1 1 0 A 6 1.075 1 0 1 0 0 1 1 1 A 7 1.080 1 0 1 0 1 0 0 0 A 8 1.085 1 0 1 0 1 0 0 1 A 9 1.090 1 0 1 0 1 0 1 0 A A 1.095 1 0 1 0 1 0 1 1 A B 1.100 1 0 1 0 1 1 0 0 A C 1.105 1 0 1 0 1 1 0 1 A D 1.110 1 0 1 0 1 1 1 0 A E 1.115 1 0 1 0 1 1 1 1 A F 1.120 1 0 1 1 0 0 0 0 B 0 1.125 1 0 1 1 0 0 0 1 B 1 1.130 To be continued www.richtek.com 8 DS8168B-00 November 2011 RT8168B VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 1 0 1 1 0 0 1 0 B 2 1.135 1 0 1 1 0 0 1 1 B 3 1.140 1 0 1 1 0 1 0 0 B 4 1.145 1 0 1 1 0 1 0 1 B 5 1.150 1 0 1 1 0 1 1 0 B 6 1.155 1 0 1 1 0 1 1 1 B 7 1.160 1 0 1 1 1 0 0 0 B 8 1.165 1 0 1 1 1 0 0 1 B 9 1.170 1 0 1 1 1 0 1 0 B A 1.175 1 0 1 1 1 0 1 1 B B 1.180 1 0 1 1 1 1 0 0 B C 1.185 1 0 1 1 1 1 0 1 B D 1.190 1 0 1 1 1 1 1 0 B E 1.195 1 0 1 1 1 1 1 1 B F 1.200 1 1 0 0 0 0 0 0 C 0 1.205 1 1 0 0 0 0 0 1 C 1 1.210 1 1 0 0 0 0 1 0 C 2 1.215 1 1 0 0 0 0 1 1 C 3 1.220 1 1 0 0 0 1 0 0 C 4 1.225 1 1 0 0 0 1 0 1 C 5 1.230 1 1 0 0 0 1 1 0 C 6 1.235 1 1 0 0 0 1 1 1 C 7 1.240 1 1 0 0 1 0 0 0 C 8 1.245 1 1 0 0 1 0 0 1 C 9 1.250 1 1 0 0 1 0 1 0 C A 1.255 1 1 0 0 1 0 1 1 C B 1.260 1 1 0 0 1 1 0 0 C C 1.265 1 1 0 0 1 1 0 1 C D 1.270 1 1 0 0 1 1 1 0 C E 1.275 1 1 0 0 1 1 1 1 C F 1.280 1 1 0 1 0 0 0 0 D 0 1.285 1 1 0 1 0 0 0 1 D 1 1.290 1 1 0 1 0 0 1 0 D 2 1.295 1 1 0 1 0 0 1 1 D 3 1.300 1 1 0 1 0 1 0 0 D 4 1.305 1 1 0 1 0 1 0 1 D 5 1.310 To be continued DS8168B-00 November 2011 www.richtek.com 9 RT8168B VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 1 1 0 1 0 1 1 0 D 6 1.315 1 1 0 1 0 1 1 1 D 7 1.320 1 1 0 1 1 0 0 0 D 8 1.325 1 1 0 1 1 0 0 1 D 9 1.330 1 1 0 1 1 0 1 0 D A 1.335 1 1 0 1 1 0 1 1 D B 1.340 1 1 0 1 1 1 0 0 D C 1.345 1 1 0 1 1 1 0 1 D D 1.350 1 1 0 1 1 1 1 0 D E 1.355 1 1 0 1 1 1 1 1 D F 1.360 1 1 1 0 0 0 0 0 E 0 1.365 1 1 1 0 0 0 0 1 E 1 1.370 1 1 1 0 0 0 1 0 E 2 1.375 1 1 1 0 0 0 1 1 E 3 1.380 1 1 1 0 0 1 0 0 E 4 1.385 1 1 1 0 0 1 0 1 E 5 1.390 1 1 1 0 0 1 1 0 E 6 1.395 1 1 1 0 0 1 1 1 E 7 1.400 1 1 1 0 1 0 0 0 E 8 1.405 1 1 1 0 1 0 0 1 E 9 1.410 1 1 1 0 1 0 1 0 E A 1.415 1 1 1 0 1 0 1 1 E B 1.420 1 1 1 0 1 1 0 0 E C 1.425 1 1 1 0 1 1 0 1 E D 1.430 1 1 1 0 1 1 1 0 E E 1.435 1 1 1 0 1 1 1 1 E F 1.440 1 1 1 1 0 0 0 0 F 0 1.445 1 1 1 1 0 0 0 1 F 1 1.450 1 1 1 1 0 0 1 0 F 2 1.455 1 1 1 1 0 0 1 1 F 3 1.460 1 1 1 1 0 1 0 0 F 4 1.465 1 1 1 1 0 1 0 1 F 5 1.470 1 1 1 1 0 1 1 0 F 6 1.475 1 1 1 1 0 1 1 1 F 7 1.480 1 1 1 1 1 0 0 0 F 8 1.485 To be continued www.richtek.com 10 DS8168B-00 November 2011 RT8168B VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 1 1 1 1 1 0 0 1 F 9 1.490 1 1 1 1 1 0 1 0 F A 1.495 1 1 1 1 1 0 1 1 F B 1.500 1 1 1 1 1 1 0 0 F C 1.505 1 1 1 1 1 1 0 1 F D 1.510 1 1 1 1 1 1 1 0 F E 1.515 1 1 1 1 1 1 1 1 F F 1.520 DS8168B-00 November 2011 www.richtek.com 11 RT8168B Functional Pin Description Pin No. Pin Name Pin Function CPU VR Bootstrap Power Pin. This pin powers the high side MOSFET drivers. Connect this pin to the PHASE1 pin with a bootstrap capacitor. 1 BOOT1 2 TONSET 3 ISEN1P Single-Phase CPU VR On-Time Setting Pin. Connect this pin to VIN with a resistor to set ripple size in PWM mode. Positive Current Sense Input Pin of CPU VR. 4 ISEN1N Negative Current Sense Input Pin of CPU VR. 5 COMP CPU VR Compensation Pin. This pin is the output of the error amplifier. 6 FB 7 RGND 8 GFXPS2 9 VCC 10 11 12 13 14 15 SETINIA SETINI TMPMAX ICCMAX ICCMAXA TSEN 16 OCSET 17 TSENA 18 OCSETA 19 IBIAS 20 VRHOT CPU VR Feedback Pin. This pin is the inverting input node of the error amplifier. Return Ground for CPU VR. This pin is the inverting input node for differential remote voltage sensing. Set Pin for GPU VR Operation Mode. Logic-high on this pin will force the GPU VR to enter DCM. Controller Power Supply Pin. Connect this pin to GND via a ceramic capacitor larger than 1F. ADC Input for Single-Phase GPU VR VBOOT Voltage Setting. ADC Input for Single-Phase CPU VR VBOOT Voltage Setting. ADC Input for Single-Phase CPU VR Maximum Temperature Setting. ADC Input for Single-Phase CPU VR Maximum Current Setting. ADC Input for Single-Phase GPU VR Maximum Current Setting. Thermal Monitor Sense Input Pin for CPU VR. Set Pin for Single-Phase CPU VR Over Current Protection Threshold. Connect a resistive voltage divider from VCC to ground, and connect the joint of the voltage divider to the OCSET pin. The voltage, VOCSET , at this pin sets the over current threshold, ILIMIT, for CPU VR. Thermal Monitor Sense Input for GPU VR. Set Pin for Single-Phase GPU VR Over Current Protection Threshold. Connect a resistive voltage divider from VCC to ground, and connect the joint of the voltage divider to the OCSETA pin. The voltage, VOCSETA, at this pin sets the over current threshold, ILIMIT, for GPU VR. Internal Bias Current Setting. Connect a 53.6k resistor from this pin to GND to set the internal bias current. Thermal Monitor Output Pin (active low). 21 VR_READY CPU VR Voltage Ready Indicator. This pin has an open drain output. 22 VRA_READY GPU VR Voltage Ready Indicator. This pin has an open drain output. 23 24 25 ALERT VDIO VCLK 26 RGNDA 27 FBA 28 COMPA 29 30 ISENAN ISENAP 31 TONSETA Alert Line of SVID Interface (active low). This pin has an open drain output. Data Transmission Line of SVID Interface. Clock Signal Line of SVID Interface. Return Ground for Single-Phase GPU VR. This pin is the inverting input node for differential remote voltage sensing. GPU VR Feedback Pin. This pin is the inverting input node of the error amplifier. Single-Phase GPU VR Compensation Pin. This pin is the output of the error amplifier. Negative Current Sense Input Pin of Single-Phase GPU VR. Positive Current Sense Input Pin of Single-Phase GPU VR. Single-Phase GPU VR On-Time Setting Pin. Connect this pin to VIN with a resistor to set ripple size in PWM mode. To be continued www.richtek.com 12 DS8168B-00 November 2011 RT8168B Pin No. 32 33 34 35 36 37 38 39 40 41 (Exposed Pad) DS8168B-00 Pin Name Pin Function EN Voltage Regulator Enable Signal Input Pin. GPU VR Bootstrap Power Pin. This pin powers the high side MOSFET drivers. BOOTA Connect this pin to the PHASEA pin with a bootstrap capacitor. Upper Gate Driver of GPU VR. This pin drives the high side MOSFET of GPU UGATEA VR. Switch Node of GPU VR. This pin is the return node of the high side MOSFET PHASEA driver for GPU VR. Connect this pin to the joint of the source of high side MOSFET, drain of the low side MOSFET, and the output inductor. Lower Gate Driver of GPU VR. This pin drives the low side MOSFET of GPU LGATEA VR. MOSFET Driver Power Supply Pin. Connect this pin to GND via a ceramic PVCC capacitor larger than 1F. Lower Gate Driver of CPU VR. This pin drives the low side MOSFET of CPU LGATE1 VR. Switch Node of CPU VR. This pin is the return node of the high side driver for PHASE1 CPU VR. Connect this pin to the joint of the source of high side MOSFET, drain of the low side MOSFET, and the output inductor. Upper Gate Driver of CPU VR. This pin drives the high side MOSFET of CPU UGATE1 VR. Ground of Low Side MOSFET Driver. The exposed pad must be soldered to a GND large PCB and connected to GND for maximum power dissipation. November 2011 www.richtek.com 13 RT8168B VR_READY VRA_READY VRHOT VCC EN ICCMAXA ICCMAX TSEN TSENA SETINI SETINIA TMPMAX ALERT VDIO VCLK Function Block Diagram UVLO MUX From Control Logic ADC SVID XCVR Control & Protection Logic GFXPS2 DAC RGNDA Soft-Start & Slew Rate Control VREFA FBA ERROR AMP + - PWM CMP Offset Cancellation TON Time Generator TONSETA + - BOOTA COMPA UGATEA Driver Logic Control IBIAS From Control Logic LGATEA To Protection Logic DAC RGND OVP/UVP/NVP OCP PHASEA PVCC 10 + ISENAP - ISENAN OCSETA Soft-Start & Slew Rate Control FB VREF ERROR AMP + Offset Cancellation - PWM CMP + TON Time Generator TONSET - COMP BOOT1 UGATE1 To Protection Logic ISEN1P ISEN1N + 10 - OCP Driver Logic Control PHASE1 LGATE1 OVP/UVP/NVP OCSET www.richtek.com 14 DS8168B-00 November 2011 RT8168B Absolute Maximum Ratings z z z z z z z z z z z z z z (Note 1) PVCC, VCC to GND ------------------------------------------------------------------------------------RGNDx to GND ------------------------------------------------------------------------------------------TONSETx to GND ---------------------------------------------------------------------------------------Others ------------------------------------------------------------------------------------------------------BOOTx to PHASEx -------------------------------------------------------------------------------------PHASEx to GND DC -----------------------------------------------------------------------------------------------------------<20ns ------------------------------------------------------------------------------------------------------UGATEx to PHASEx DC -----------------------------------------------------------------------------------------------------------<20ns ------------------------------------------------------------------------------------------------------LGATEx to GND DC -----------------------------------------------------------------------------------------------------------<20ns ------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25C WQFN-40L 5x5 ------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WQFN-40L 5x5, JA ------------------------------------------------------------------------------------WQFN-40L 5x5, JC ------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ----------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------- Recommended Operating Conditions z z z z -0.3V to 6.5V -0.3V to 0.3V -0.3V to 28V -0.3V to (VCC + 0.3V) -0.3V to 6.5V -3V to 28V -8V to 32V -0.3V to (BOOTx - PHASEx) -5V to 7.5V -0.3V to (PVCC + 0.3V) -2.5V to 7.5V 2.778W 36C/W 6C/W 150C 260C -65C to 150C 2kV 200V (Note 4) Supply Voltage, VCC ------------------------------------------------------------------------------------Input Voltage, VIN ----------------------------------------------------------------------------------------Junction Temperature Range --------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------- 4.5V to 5.5V 5V to 25V -40C to 125C -40C to 85C Electrical Characteristics (VCC = 5V, TA = 25C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit VCC /VPVCC VEN = 1.05V, Not Switching 4.5 5 5.5 V VIN Battery Input Voltage 5 -- 25 V IVCC + IPVCC VEN = 1.05V, Not Switching -- 12 20 mA ITONSETx VFB =1V, V IN = 12V, RTON = 100k -- 110 -- A Supply Input Input Voltage Range Supply Current (VCC + PVCC) Supply Current (TONSETx) To be continued DS8168B-00 November 2011 www.richtek.com 15 RT8168B Parameter Shutdown Current (PVCC + VCC ) Symbol Test Conditions Min Typ Max Unit I VCC_SHDN + IPVCC_SHDN VEN = 0V -- -- 5 A I TONSETx_SHDN VEN = 0V -- -- 5 A TONSETx Voltage VTONSETx IRTON = 80A, VFBx = 1V 0.95 1.075 1.2 0V On-Time t ON IRTON = 80A, VFBx = 1V 315 350 385 ns TONSETx Input Current Range I RTON VFBx = 1.1V 25 -- 280 A Minimum Off-Time TOFF_MIN -- 350 -- ns 4.3 -- -- V -- -- 0.7 V VID SVID Setting = 1.000V~1.520V OFSSVID Setting = 0V VID SVID Setting = 0.800V~1.000V OFSSVID Setting = 0V -0.5 0 0.5 %VID -5 0 5 VID SVID Setting = 0.500V~0.800V OFSSVID Setting = 0V -8 0 8 VID SVID Setting = 0.250V~0.500V OFSSVID Setting = 0V VID SVID Setting = 1.100V OFSSVID Setting = -0.640V~0.635V -8 0 8 -10 0 10 0 0.3125 0.5125 VINI_CORE = 0.9V, VINI_GFX = 0.9V 0.7375 0.9375 1.1375 VINI_CORE = 1V, VINI_GFX = 1V 1.3625 1.5625 1.7625 VINI_CORE = 1.1V, VINI_GFX = 1.1V 2.6125 -- 5 RIBIAS = 53.6k 2.09 2.14 2.19 SetVID Slow 2.5 3.125 3.75 SetVID Fast 10 12.5 15 70 80 -- dB -- 10 -- MHz -- 5 -- V/s 0.5 -- 3.6 V -- 250 -- A 1 -- -- M Shutdown Current (TONSETx) TON Setting GFX VR Forced DEM GFXPS2x Enable VGFXPS Threshold GFXPS2x Disable VGFXPS Threshold References and System Output Voltage DAC Accuracy (PS0/PS1) VFBx VINI_CORE = 0V, VINI_GFX = 0V SETINIx Voltage VSETINIx IBIAS Pin Voltage VIBIAS Dynamic VID Slew Rate SRDVID mV V V mV/s Error Amplifier DC Gain Gain-Bandwidth Product ADC RL = 47k GBW CLOAD = 5pF Slew Rate SRCOMP CLOAD = 10pF (Gain = -4, RLOAD_COMP = 47k, VCOMPx = 0.5V to 3V) VCOMP RL = 47k I COMP VCOMP = 2V Output Voltage Range MAX Source/Sink Current Impedance of FBx R FBx (Note5) (Note5) To be continued www.richtek.com 16 DS8168B-00 November 2011 RT8168B Parameter Symbol Test Conditions Min Typ Max Unit -1 -- 1 mV Impedance of Neg. Input RISENxN 1 -- -- M Impedance of Pos. Input 1 -- -- M -50 -- 100 mV Current Sense Amplifier Input Offset Voltage Current Sense Differential Input Range Current Sense DC Gain (Loop) VISEN Linearity VOFS_CSA RISENxP VCSDIx VFBx = 1.1V, VCSDIx = VISENxP - VISENxN AI VFBx = 1.1V, -30mV < VCSDIx < 50mV -- 10 -- V/V VISEN_ACC VDAC = 1.1V -30mV < VISEN_IN < 50mV -1 -- 1 % Upper Driver Source RUGATEx_sr VBOOTx - VPHASEx = 5V VBOOTx - VUGATEx = 0.1V -- 1 -- Upper Driver Sink RUGATEx_sk VUGATEx = 0.1V -- 1 -- Lower Driver Source RLGATEx_sr PVCC = 5V, PVCC - VLGATEx = 0.1V -- 1 -- Lower Driver Sink RLGATEx_sk VLGATEx = 0.1V -- 0.5 -- Internal Boot Charging Switch On-Resistance RBOOTx PVCC to BOOTx -- 30 -- Zero Current Detection Threshold VZCD_TH VZCD_TH = GND - VPHASEx -- 10 -- mV Under Voltage Lock-out Threshold VUVLO VCC Falling edge 4.04 4.24 -- V Under Voltage Lock-out Hysteresis VUVLO -- 100 -- mV Over Voltage Protection Threshold VOVP 100 150 200 mV Gate Driver Protection Respect to VOUT_MAXSVID, with 1s filter time Under Voltage Protection VUVP Threshold VUVP = VISENxN - VREFx, 0.8V < VREFx -350 <1.52V, with 3s filter time -300 -250 mV Negative Voltage Protection Threshold VNVP VNVP = VISENxN - GND -100 -50 -- mV Current Sense Gain for Over Current Protection AOC VOCSET = 2.4V VISENxP - VISENxN = 50mV -- 48 -- V/V Logic-High VIH With respect to 1V, 70% 0.7 -- -- Logic-Low VIL With respect to 1V, 30% -- -- 0.3 -1 -- 1 Logic Inputs EN Input Threshold Voltage V Leakage Current of EN VCLK,VDIO Input Threshold Voltage Leakage Current of VCLK, VDIO VIH With respect to Intel Spec. 0.65 -- -- VIL With respect to Intel Spec. -- -- 0.45 -1 -- 1 ILEAK_IN A V A To be continued DS8168B-00 November 2011 www.richtek.com 17 RT8168B Parameter Symbol Test Conditions Min Typ Max Unit -- -- 0.4 V -- -- 0.4 V 70 100 160 s -- 0.4 -- V -1 -- 1 A 100C -- 1.8725 -- V 97C -- 1.8175 -- V 94C -- 1.7625 -- V 91C -- 1.7075 -- V 88C -- 1.6525 -- V 85C -- 1.5975 -- V 82C -- 1.5425 -- V 75C -- 1.4875 -- V ALERT ALERT Low Voltage VALERT I ALERT_ SINK = 4mA VR Ready VRx_READY Low Voltage VVRx_READY I VRx_READY_ SINK = 4mA VRx_READY Delay tVRx_READY VISENxN = VBOOT to VVRx_READY high Thermal Throttling VRHOT Output Voltage VVRHOT I VRHOT_SINK = 40mA High Impedance Output ALERT, VRx_READY, VRHOT ILEAK_OUT Temperature Zone TSEN Threshold for Tmp_Zone [7] transition TSEN Threshold for Tmp_Zone [6] transition TSEN Threshold for Tmp_Zone [5] transition VTSENx TSEN Threshold for Tmp_Zone [4] transition TSEN Threshold for Tmp_Zone [3] transition TSEN Threshold for Tmp_Zone [2] transition TSEN Threshold for Tmp_Zone [1] transition VTSENx TSEN Threshold for Tmp_Zone [0] transition Update Period ADC t TSEN -- 1600 -- s Latency tLAT -- -- 400 s Digital Code of ICCMAX Digital Code of ICCMAXA Digital Code of TMPMAX www.richtek.com 18 CICCMAX1 VICCMAX = 0.637V 29 32 35 decimal CICCMAX2 VICCMAX = 1.2642V 61 64 67 decimal CICCMAX3 VICCMAX = 2.5186V 125 128 131 decimal CICCMAXA1 VICCMAXA = 0.1666V 5 8 11 decimal CICCMAXA2 VICCMAXA = 0.3234V 13 16 19 decimal CICCMAXA3 VICCMAXA = 0.637V 29 32 35 decimal CTMPMAX1 VTMPMAX = 1.6758V 82 85 88 decimal CTMPMAX2 VTMPMAX = 1.9698V 97 100 103 decimal CTMPMAX3 VTMPMAX = 2.4598V 122 125 128 decimal DS8168B-00 November 2011 RT8168B Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. JA is measured in the natural convection at TA = 25C on a high effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. The measurement case position of JC is on the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design. DS8168B-00 November 2011 www.richtek.com 19 RT8168B Typical Operating Characteristics CORE VR Power Off from EN CORE VR Power On from EN V CORE (500mV/Div) EN (2V/Div) VR_READY (2V/Div) V CORE (500mV/Div) EN (2V/Div) VR_READY (2V/Div) UGATE (20V/Div) UGATE (20V/Div) Boot VID = 1V Boot VID = 1V Time (100s/Div) Time (100s/Div) CORE VR OCP CORE VR OVP and NVP V CORE (1V/Div) V CORE (1V/Div) I LOAD (10A/Div) LGATE (10V/Div) VR_READY (1V/Div) VR_READY (1V/Div) UGATE (20V/Div) UGATE (20V/Div) VID = 1.1V VID = 1.1V Time (100s/Div) Time (40s/Div) CORE VR Dynamic VID Up CORE VR Dynamic VID Down V CORE (500mV/Div) V CORE (500mV/Div) VCLK (2V/Div) VDIO (2V/Div) VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) 0.7V to 1.2V, Slew Rate = Slow, ILOAD = 4A Time (40s/Div) www.richtek.com 20 ALERT (2V/Div) 1.2V to 0.7V, Slew Rate = Slow, ILOAD = 4A Time (40s/Div) DS8168B-00 November 2011 RT8168B CORE VR Dynamic VID Down CORE VR Dynamic VID Up V CORE (500mV/Div) V CORE (500mV/Div) VCLK (2V/Div) VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) VDIO (2V/Div) ALERT (2V/Div) 0.7V to 1.2V, Slew Rate = Fast, ILOAD = 4A Time (10s/Div) Time (10s/Div) CORE VR Load Transient CORE VR Load Transient V CORE (20mV/Div) V CORE (20mV/Div) 8 I LOAD (A/Div) 1 8 I LOAD (A/Div) 1 VID = 1.1V, ILOAD = 1A to 8A, Slew Time = 150ns VID = 1.1V, ILOAD = 8A to 1A, Slew Time = 150ns Time (100s/Div) Time (100s/Div) CORE VR Mode Transition CORE VR Mode Transition V CORE (20mV/Div) V CORE (20mV/Div) VCLK (1V/Div) LGATE (10V/Div) VCLK (1V/Div) LGATE (10V/Div) UGATE (20V/Div) UGATE (20V/Div) DS8168B-00 1.2V to 0.7V, Slew Rate = Fast, ILOAD = 4A VID = 1.1V, PS0 to PS2, ILOAD = 0.2A VID = 1.1V, PS2 to PS0, ILOAD = 0.2A Time (100s/Div) Time (100s/Div) November 2011 www.richtek.com 21 RT8168B CORE VR Thermal Monitoring CORE VR VREF vs. Temperature 1.006 1.9 1.004 TSEN (V/Div) 1.002 VREF (V) 1.7 1.000 0.998 0.996 0.994 VRHOT (500mV/Div) 0.992 TSEN Sweep from 1.7V to 1.9V 0.990 Time (10ms/Div) -50 -25 0 25 50 75 100 125 Temperature (C) GFX VR Power On from EN GFX VR Power Off from EN VGFX (500mV/Div) EN (2V/Div) VRA_READY (2V/Div) VGFX (500mV/Div) EN (2V/Div) VRA_READY (2V/Div) UGATEA (20V/Div) UGATEA (20V/Div) Boot VID = 1V Boot VID = 1V Time (100s/Div) Time (100s/Div) GFX VR OCP GFX VR OVP and NVP VGFX (1V/Div) VGFX (1V/Div) I LOAD (5A/Div) VRA_READY (1V/Div) LGATEA (10V/Div) VRA_READY (1V/Div) UGATEA (20V/Div) UGATEA (20V/Div) VID = 1.1V Time (100s/Div) www.richtek.com 22 Time (40s/Div) DS8168B-00 November 2011 RT8168B GFX VR Dynamic VID GFX VR Dynamic VID VGFX (500mV/Div) VGFX (500mV/Div) VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) 0.7V to 1.2V, Slew Rate = Slow, ILOAD = 1.25A Time (40s/Div) Time (40s/Div) GFX VR Dynamic VID GFX VR Dynamic VID VGFX (500mV/Div) VGFX (500mV/Div) VCLK (2V/Div) VDIO (2V/Div) VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) ALERT (2V/Div) 0.7V to 1.2V, Slew Rate = Fast, ILOAD = 1.25A 1.2V to 0.7V, Slew Rate = Fast, ILOAD = 1.25A Time (10s/Div) Time (10s/Div) GFX VR Load Transient GFX VR Load Transient VGFX (20mV/Div) VGFX (20mV/Div) I LOAD 4 (A/Div) 1 I LOAD 4 (A/Div) 1 VID = 1.1V, ILOAD = 1A to 4A, Slew Time = 150ns Time (100s/Div) DS8168B-00 1.2V to 0.7V, Slew Rate = Slow, ILOAD = 1.25A November 2011 VID = 1.1V, ILOAD = 4A to 1A, Slew Time = 150ns Time (100s/Div) www.richtek.com 23 RT8168B GFX VR Mode Transition GFX VR Mode Transition VGFX (20mV/Div) VGFX (20mV/Div) VCLK (1V/Div) VCLK (1V/Div) LGATEA (10V/Div) LGATEA (10V/Div) UGATEA (20V/Div) UGATEA (20V/Div) VID = 1.1V, PS0 to PS2, ILOAD = 0.1A VID = 1.1V, PS2 to PS0, ILOAD = 0.1A Time (100s/Div) Time (100s/Div) GFX VR VREF vs. Temperature GFX VR Thermal Monitoring 1.006 1.004 1.9 TSENA (V/Div) 1.002 1.000 VREF (V) 1.7 0.998 0.996 0.994 0.992 VRHOT (500mV/Div) 0.990 TSENA Sweep from 1.7V to 1.9V Time (10ms/Div) 0.988 -50 -25 0 25 50 75 100 125 Temperature (C) www.richtek.com 24 DS8168B-00 November 2011 RT8168B Application Information The RT8168B is a VR12/IMVP7 compliant, dual singlephase synchronous Buck PWM controller for the CPU CORE VR and GFX VR. The gate drivers are embedded to facilitate PCB design and reduce the total BOM cost. A serial VID (SVID) interface is built-in in the RT8168B to communicate with Intel VR12/IMVP7 compliant CPU. The RT8168B adopts G-NAVPTM (Green Native AVP), which is Richtek's proprietary topology derived from finite DC gain compensator, making it an easy setting PWM controller to meet AVP requirements. The load line can be easily programmed by setting the DC gain of the error amplifier. The RT8168B has fast transient response due to the G-NAVP TM commanding variable switching frequency. G-NAVPTM topology also represents a high efficiency system with green power concept. With G-NAVPTM topology, the RT8168B becomes a green power controller with high efficiency under heavy load, light load, and very light load conditions. The RT8168B supports mode transition function between CCM and DEM. These different operating states allow the overall power system to have low power loss. By utilizing the G-NAVPTM topology, the operating frequency of RT8168B varies with output voltage, load and VIN to further enhance the efficiency even in CCM. The built-in high accuracy DAC converts the SVID code ranging from 0.25V to 1.52V with 5mV per step. The differential remote output voltage sense and high accuracy DAC allow the system to have high output voltage accuracy. DS8168B-00 November 2011 The RT8168B supports VR12/IMVP7 compatible power management states and VID on-the-fly function. The power management states include DEM in PS2/PS3 and ForcedCCM in PS1/PS0. The VID on-the-fly function has three different slew rates : Fast, Slow and Decay. The RT8168B integrates a high accuracy ADC for platform setting functions, such as no-load offset and over current level. The controller supports both DCR and sense-resistor current sensing. The RT8168B provides VR ready output signals of both CORE VR and GFX VR. It also features complete fault protection functions including over voltage, under voltage, negative voltage, over current and under voltage lockout. The RT8168B is available in a WQFN48L 6x6 small foot print package. Design Tool To help users reduce efforts and errors caused by manual calculations, a user-friendly design tool is now available on request. This design tool calculates all necessary design parameters by entering user's requirements. Please contact Richtek's representatives for details. Serial VID (SVID) Interface SVID is a three-wire serial synchronous interface defined by Intel. The three wire bus includes VDIO, VCLK and ALERT signals. The master (Intel's VR12/IMVP7 CPU) initiates and terminates SVID transactions and drives the VDIO, VCLK, and ALERT during a transaction. The slave (RT8168B) receives the SVID transactions and acts accordingly. www.richtek.com 25 RT8168B Standard Serial VID Command Master Payload Slave Payload Contents Contents Code Commands 00h not supported N/A N/A 01h SetVID_Fast VID code N/A 02h SetVID_Slow VID code N/A 03h SetVID_Decay VID code N/A 04h SetPS Byte indicating power states N/A Set power state 05h SetRegADR Pointer of registers in data table N/A Set the pointer of the data register 06h SetReg DAT New data register content N/A Write the contents to the data register 07h GetReg Pointer of registers in data table Specified Register Contents Slave returns the contents of the specified register as the payload 08h 1Fh not supported N/A N/A N/A www.richtek.com 26 Description N/A Set new target VID code, VR jumps to new VID target with controlled default "fast" slew rate 12.5mV/s. Set new target VID code, VR jumps to new VID target with controlled default "slow" slew rate 3.125mV/s. Set new target VID code, VR jumps to new VID target, but does not control the slew rate. The output voltage decays at a rate proportional to the load current DS8168B-00 November 2011 RT8168B Index 00h 01h 02h 05h Register Name Vendor ID Product ID Product Revision Protocol ID 06h VR_Capability 10h Status_1 11h Status-2 Temperature Zone 12h 15h Output_Current 1Ch Status_2_lastread 21h ICC_Max 22h Temp_Max 24h SR-Fast 25h SR-Slow 30h VOUT_Max 31h Data and Configuration Register Description Vendor ID, default 1Eh. Product ID. Product Revision. SVID Protocol ID. Bit mapped register, identifies the SVID VR capabilities and which of the optional telemetry register are supported. Data register containing the status of VR. Access RO, Vendor RO, Vendor RO, Vendor RO, Vendor Default 1Eh 65h 01h 01h RO, Vendor 81h R-M, W-PWM 00h Data register containing the status of transmission. Data register showing temperature zone that have been entered. Data register showing direct ADC conversion of averaged output current. R-M, W-PWM 00h R-M, W-PWM 00h R-M, W-PWM 00h The register contains a copy of the status_2. R-M, W-PWM 00h RO, Platform -- RO, Platform -- RO 0Ah RO 02h Data register containing the maximum ICC of platform supports. Binary format in Amp, IE 64h = 100A. Data register containing the temperature max the platform supports. Binary format in C, IE 64h = 100C Only for CORE VR Data register containing the capability of fast slew rate the platform can sustains. Binary format in mV/s, IE 0Ah = 10mV/s. Data register containing the capability of slow slew rate. Binary format in mV/s IE 02h = 2.5mV/s. RW, Master BFh VID Setting The register is programmed by the master and sets the maximum VID. Data register containing currently programmed VID. RW, Master 00h 32h Power State Register containing the current programmed power state. RW, Master 00h 33h Offset Set offset in VID steps. RW, Master 00h 34h Multi VR Config Bit mapped data register which configures multiple VRs behavior on the same bus. RW, Master 00h 35h Pointer Scratch pad register for temporary storage of the SetRegADR pointer register. RW, Master 30h Notes : RO = Read Only RW = Read/Write R-M = Read by Master W-PWM = Write by PWM only Vendor = hard coded by VR vendor Platform = programmed by platform Master = programmed by the master PWM = programmed by the VR control IC DS8168B-00 November 2011 www.richtek.com 27 RT8168B Power Ready Detection and Power On Reset (POR) ICCMAX, ICCMAXA and TMPMAX During start-up, the RT8168B detects the voltage on the voltage input pins : VCC and EN. When VCC > VUVLO, the RT8168B will recognize the power state of system to be ready (POR = high) and wait for enable command at EN pin. After POR = high and EN > VENTH, the RT8168B will enter start-up sequence for both CORE VR and GFX VR. If the voltage on any voltage pin drops below POR threshold (POR = low), the RT8168B will enter power down sequence and all the functions will be disabled. SVID will be invalid within 300s after chip becomes enabled. All the protection latches (OVP, OCP, UVP, OTP) will be cleared only after POR = low. EN = low will not clear these latches. The RT8168B provides ICCMAX, ICCMAXA and TMPMAX pins for platform users to set the maximum level of output current or VR temperature: ICCMAX for CORE VR maximum current, ICCMAXA for GFX VR maximum current, and TMPMAX for CORE VR maximum temperature. VCC + VUVLO POR - EN Chip EN + VENTH - Figure 3. Power Ready Detection and Power On Reset (POR) Precise Reference Current Generation The RT8168B includes extensive analog circuits inside the controller. These analog circuits need very precise reference voltage/current to drive these analog devices. The RT8168B will auto-generate a 2.14V voltage source at IBIAS pin, and a 53.6k resistor is required to be connected between IBIAS and analog ground. Through this connection, the RT8168B generates a 40A current from IBIAS pin to analog ground and this 40A current will be mirrored inside the RT8168B for internal use. Other types of connection or other values of resistance applied at the IBIAS pin may cause failure of the RT8168B's analog circuits. Thus a 53.6k resistor is the only recommended component to be connected to the IBIAS pin. The resistance accuracy of this resistor is recommended to be at least 1%. Current Mirror 2.14V + - + - IBIAS 53.6k Figure 4. IBIAS Setting www.richtek.com 28 To set ICCMAX, ICCMAXA and TMPMAX, platform designers should use resistive voltage dividers on these three pins. The current of the divider should be several milli-Amps to avoid noise effect. The three items share the same algorithms : the ADC divides 5V into 255 levels. Therefore, LSB = 5/255 = 19.6mV, which means 19.6mV applied to ICCMAX pin equals to 1A setting. For example, if a platform designer wants to set TMPMAX to 120C, the voltage applied to TMPMAX should be 120 x 19.6mV = 2.352V. The ADC circuit inside these three pins will decode the voltage applied and store the maximum current/ temperature setting into ICC_MAX and Temp_Max registers. The ADC monitors and decodes the voltage at these three pins only after EN = high. If EN = low, the RT8168B will not take any action even when the VR output current or temperature exceeds its maximum setting at these ADC pins. The maximum level settings at these ADC pins are different from over current protection or over temperature protection. That means, these maximum level setting pins are only for platform users to define their system operating conditions and these messages will only be utilized by the CPU. V CC ICCMAX A/D Converter ICCMAXA TMPMAX Figure 5. ADC Pins Setting VINI_CORE and VINI_GFX Setting The initial start up voltage (VINI_CORE, VINI_GFX) of the RT8168B can be set by platform users through SETINI and SETINIA pins. Voltage divider circuit is recommended to be applied to SETINI and SETINIA pins. The VINI_CORE/ VINI_GFX relate to SETINI/SETINIA pin voltage setting as shown in Figure 6. Recommended voltage setting at SETINI and SETINIA pins are also shown in Figure 6. DS8168B-00 November 2011 RT8168B VCC (5V) VINI_CORE = 1.1V VINI_GFX = 1.1V VINI_CORE V INI_GFX Recommended SETINI/SETINIA Pin Voltage 1.1V 5 x VCC3.125V or VCC 8 3 x VCC1.875V 8 3 x VCC0.9375V 16 1/2 VCC VINI_CORE = 1V VINI_GFX = 1V VINI_CORE = 0.9V VINI_GFX = 0.9V VINI_CORE = 0V VINI_GFX = 0V 1V 0.9V 1/4 VCC 1/8 VCC 0V 1 x VCC0.3125V or GND 16 GND Figure 6. SETINI and SETINIA Pin Voltage Setting Start Up Sequence Power Down Sequence The RT8168B utilizes internal soft-start sequence which strictly follows Intel VR12/IMVP7 start up sequence specifications. After POR = high and EN = high, a 300s delay is needed for the controller to determine whether all the power inputs are ready for entering start up sequence. If pin voltage of SETINI/SETINIA is zero, the output voltage of CORE/GFX VR is programmed to stay at 0V. If pin voltage of SETINI/SETINIA is not zero, VR output voltage will ramp up to initial boot voltage (VINI_CORE, VINI_GFX) after both POR = high and EN = high. After the output voltage of CORE/GFX VR reaches target initial boot voltage, the controller will keep the output voltage at the initial boot voltage and wait for the next SVID commands. After the RT8168B receives valid VID code (typically SetVID_Slow command), the output voltage will ramp up/down to the target voltage with specified slew rate. After the output voltage reaches the target voltage, the RT8168B will send out VR_READY signal to indicate the power state of the RT8168B is ready. The VR_READY circuit is an opendrain structure so a pull-up resistor is recommended for connecting to a voltage source. Similar to the start up sequence, the RT8168B also utilizes a soft shutdown mechanism during turn-off. After POR = low, the internal reference voltage (positive terminal of compensation EA) starts ramping down with 3.125mV/s slew rate, and output voltage will follow the reference voltage to 0V. After output voltage drops below 0.2V, the RT8168B shuts down and all functions are disabled. The VR_READY will be pulled down immediately after POR = low. DS8168B-00 November 2011 www.richtek.com 29 RT8168B VCC POR EN EN Chip (Internal Signal) SVID Valid XX xx 300s 0.2V VCORE CORE VR Operation Mode Off VGFX GFX VR Operation Mode CCM SVID defined Off CCM 0.2V Off CCM SVID defined Off CCM 100s VR_READY VRA_READY 100s Figure 7 (a). Power sequence for RT8168B (VINI_CORE = VINI_GFX = 0V) VCC POR EN EN Chip (Internal Signal) SVID 300s xx Valid XX 250s VINI_CORE 0.2V VCORE CORE VR Operation Mode Off CCM SVID defined Off CCM 100s VR_READY 50s VINI_GFX VGFX GFX VR Operation Mode 0.2V Off CCM SVID defined Off CCM 100s VRA_READY Figure 7 (b). Power sequence for RT8168B (VINI_CORE 0, VINI_GFX 0V) www.richtek.com 30 DS8168B-00 November 2011 RT8168B Disable GFX VR : Before EN = High GFX VR enable or disable is determined by the internal circuitry that monitors the ISENAN voltage during start up. Before EN = high, GFX VR detects whether the voltage of ISENAN is higher than "VCC - 1V" to disable GFX VR. The unused driver pins can be connected to GND or left floating. GFX VR Forced-DEM Function Enable : After VRA_Ready = High The GFX VR's forced-DEM function can be enabled or disabled with GFXPS2 pin. The RT8168B detects the voltage of GFXPS2 for forced-DEM function. If the voltage at GFXPS2 pin is higher than 4.3V, the GFX VR operates in forced-DEM. If this voltage is lower than 0.7V, the GFX VR follows SVID power state command. Loop Control Both CORE and GFX VR adopt Richtek's proprietary GNAVPTM topology. G-NAVPTM is based on the finite-gain valley current mode with CCRCOT (Constant Current Ripple Constant On Time) topology. The output voltage, VCORE or VGFX, will decrease with increasing output load current. The control loop consists of PWM modulator with power stage, current sense amplifier and error amplifier as shown in Figure 8. Similar to the valley current mode control with finite compensator gain, the high side MOSFET on-time is determined by the CCRCOT PWM generator. When load current increases, VCS increases, the steady state COMP voltage also increases which makes the output voltage decrease, thus achieving AVP. Droop Setting (with Temperature Compensation) It's very easy to achieve the Active Voltage Positioning (AVP) by properly setting the error amplifier gain due to the native droop characteristics. The target is to have VOUT = VREFx - ILOAD x RDROOP (1) Then solving the switching condition VCOMPx = VCSx in Figure 8 yields the desired error amplifier gain as A x RSENSE (2) A V = R2 = I R1 RDROOP where AI is the internal current sense amplifier gain and RSENSE is the current sense resistance. If no external sense resistor is present, the DCR of the inductor will act as RSENSE. RDROOP is the resistive slope value of the converter output and is the desired static output impedance. V OUT A V2 > A V1 A V2 VIN High Side MOSFET UGATEx GFX/CORE VR CCRCOT PWM Generator Driver Logic Control A V1 L PHASEx VOUT (VCORE/VGFX) RC Low Side MOSFET RX CX + - + - ISENxP ISENxN CByp C2 C1 COMPx R2 R1 CORE/GFX VR VCC_SENSE EA + + - FBx RGNDx Accuracy C CMP Ai Load Current Figure 9. Error Amplifier Gain (AV) Influence on VOUT LGATEx VCSx 0 Since the DCR of inductor is temperature dependent, it affects the output accuracy in high temperature conditions. Temperature compensation is recommended for the lossless inductor DCR current sense method. Figure 10 shows a simple but effective way of compensating the temperature variations of the sense resistor using an NTC thermistor placed in the feedback path. C2 CORE/GFX VR VSS_SENSE VREFx EA + R2 R1b FBx + Figure 8. Simplified Schematic for Droop and Remote Sense in CCM COMPx C1 RGNDx R1a VCC_SENSE NTC VSS_SENSE VREFx Figure 10. Loop Setting with Temperature Compensation DS8168B-00 November 2011 www.richtek.com 31 RT8168B Usually, R1a is set to equal RNTC (25C), while R1b is selected to linearize the NTC's temperature characteristic. For a given NTC, the design would be to obtain R1b and R2 and then C1 and C2. According to (2), to compensate the temperature variations of the sense resistor, the error amplifier gain (AV) should have the same temperature coefficient with RSENSE. Hence A V, HOT RSENSE, HOT = A V, COLD RSENSE, COLD (3) From (2), we can have Av at any temperature (T) as A V, T = R2 R1a / /RNTC, T + R1b (4) The standard formula for the resistance of NTC thermistor as a function of temperature is given by : RNTC, T = RNTC, 25 {( e ) ( )} 1 - 1 T+273 298 (5) where RNTC, 25 is the thermistor's nominal resistance at room temperature, (beta) is the thermistor's material constant in Kelvins, and T is the thermistor's actual temperature in Celsius. The DCR value at different temperatures can be calculated using the equation below : DCRT = DCR25 x [1+0.00393 x (T-25)] (6) where 0.00393 is the temperature coefficient of copper. For a given NTC thermistor, solving (4) at room temperature (25C) yields R2 = AV, 25 x (R1b + R1a // RNTC, 25) (7) where AV, 25C is the error amplifier gain at room temperature obtained from (2). R1b can be obtained by substituting (7) to (3), R1b = RSENSE, HOT x (R1a // RNTC, HOT ) - (R1a // RNTC, COLD ) RSENSE, COLD RSENSE, HOT 1 - R SENSE, COLD (8) Loop Compensation Optimized compensation of the CORE VR allows for best possible load step response of the regulator's output. A type-I compensator with one pole and one zero is adequate for a proper compensation. Figure 10 shows the compensation circuit. It was previously mentioned that to determine the resistive feedback components of error amplifier gain, C1 and C2 must be calculated for the compensation. The target is to achieve constant resistive output impedance over the widest possible frequency range. The pole frequency of the compensator must be set to compensate the output capacitor ESR zero : fP = 1 2 x x C x RC (9) where C is the capacitance of the output capacitor and RC is the ESR of the output capacitor. C2 can be calculated as follows : C x RC (10) C2 = R2 The zero of compensator has to be placed at half of the switching frequency to filter the switching-related noise. Such that, 1 C1 = (11) + R1b R1a // R ( )x x f NTC, 25C SW TON Setting High frequency operation optimizes the application by trading off efficiency due to higher switching losses with smaller component size. This may be acceptable in ultraportable devices where the load currents are lower and the controller is powered from a lower voltage supply. Low frequency operation offers the best overall efficiency at the expense of component size and board space. Figure 11 shows the on-time setting circuit. Connect a resistor (RTONSETx) between VIN and TONSETx to set the on-time of UGATEx : tONx (VREFx < 1.2V) = -12 28 x 10 x RTONSETx VIN - VREFx (12) where tONx is the UGATEx turn on period, VIN is the input voltage of converter, and VREFx is the internal reference voltage. www.richtek.com 32 DS8168B-00 November 2011 RT8168B When VREFx is larger than 1.2V, the equivalent switching frequency may be over the maximum design range, making it unacceptable. Therefore, the VR implements a pseudoconstant-frequency technology to avoid this disadvantage of CCRCOT topology. When VREFx is larger than 1.2V, the on-time equation will be modified to : tONx (VREFx 1.2V) = 23.33 x 10 -12 x RTONSETx x VREFx VIN - VREFx (13) On-time translates roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics are influenced by switching delays in external high side MOSFET. Also, the dead-time effect increases the effective on-time, reducing the switching frequency. It occurs only in CCM during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, PHASEx goes high earlier than normal, extending the on-time by a period equal to the high side MOSFET rising dead time. For better efficiency of the given load range, the maximum switching frequency is suggested to be : fS(MAX) (kHz) = Differential Remote Sense Setting The CORE/GFX VR includes differential, remote-sense inputs to eliminate the effects of voltage drops along the PC board traces, CPU internal power routes and socket contacts. The CPU contains on-die sense pins CORE/ GFX VCC_SENSE and VSS_SENSE. Connect RGNDx to CORE/ GFX VSS_SENSE. Connect FBx to CORE/GFX VCC_SENSE with a resistor to build the negative input path of the error amplifier. The precision voltage reference VREFx is referred to RGND for accurate remote sensing. Current Sense Setting The current sense topology of the CORE/GFX VR is continuous inductor current sensing. Therefore, the controller can be less noise sensitive. Low offset amplifiers are used for loop control and over current detection. The internal current sense amplifier gain (AI) is fixed to be 10. The ISENxP and ISENxN denote the positive and negative input of the current sense amplifier. Users can either use a current sense resistor or the inductor's DCR for current sensing. Using inductor's DCR allows higher efficiency as shown in Figure 12. To let 1 x tON - tHS-Delay (15) L = R xC X X DCR VREFx(MAX) + ILOAD(MAX) x RON _ LS-FET + DCR - RDROOP then the transient performance will be optimum. For example, choose L = 0.36H with 1m DCR and VIN(MAX) + ILOAD(MAX) x RON _ LS-FET - RON _ HS-FET CX = 100nF, to yields for RX : (14) 0.36H RX = = 3.6k (16) 1m x 100nF where fS(MAX) is the maximum switching frequency, tHSVOUT (VCORE/VGFX) Delay is the turn on delay of high side MOSFET, VREFx(MAX) is the maximum application DAC voltage of application, V IN(MAX) is the maximum application input voltage, ILOAD(MAX) is the maximum load of application, RON_LS-FET is the low side MOSFET RDS(ON), RON_HS-FET is the high side MOSFET RDS(ON), DCRL is the inductor DCR, and RDROOP is the load line setting. GFX/CORE VR CCRCOT PWM Generator TONSETx RTONSETx VREFx PHASEx L RX VCSx AI + - DCR CX ISENxP ISENxN CByp Figure 12. Lossless Inductor Sensing R1 VIN C1 On-Time Figure 11. On-Time Setting with RC Filter DS8168B-00 November 2011 www.richtek.com 33 RT8168B Considering the inductance tolerance, the resistor RX has to be tuned on board by examining the transient voltage. If the output voltage transient has an initial dip below the minimum load line requirement with a slow recovery, RX is too small. Vice versa, if the resistance is too large the output voltage transient will only have a small initial dip and the recovery will be too fast, causing a ring-back. Using current-sense resistor in series with the inductor can have better accuracy, but the efficiency is a trade-off. Considering the equivalent inductance (LESL) of the current sense resistor, a RC filter is recommended. The RC filter calculation method is similar to the above-mentioned inductor DCR sensing method. Operation Mode Transition The RT8168B supports operation mode transition function in CORE/GFX VR for the SetPS command of Intel's VR12/ IMVP7 CPU. The default operation mode of the RT8168B's CORE/GFX VR is PS0, which is CCM operation. The other operation mode is PS2 (DEM operation). After receiving SetPS command, the CORE/GFX VR will immediately change to the new operation state. When VR receives SetPS command of PS2 operation mode, the VR operates as a DEM controller. If VR receives dynamic VID change command (SetVID), VR will automatically enter PS0 operation mode. After output voltage reaches target voltage, VR will stay at PS0 state and ignore former SetPS command. Only by re-sending SetPS command after SetVID command will VR be forced into PS2 operation state again. Thermal Monitoring and Temperature Reporting CORE/GFX VR provides thermal monitoring function via sensing TSEN pin voltage. Through the voltage divider resistors R1, R2, R3 and RNTC, the voltage of TSEN will be proportional to VR temperature. When VR temperature rises, the TSENx voltage also rises. The ADC circuit of VR monitors the voltage variation at TSENx pin from 1.47V to 1.89V with 55mV resolution, and this voltage is decoded into digital format and stored into the Temperature Zone register. www.richtek.com 34 VCC R1 RNTC R2 TSENx R3 Figure 13. Thermal Monitoring Circuit To meet Intel's VR12/IMVP7 specification, platform users have to set the TSEN voltage to meet the temperature variation of VR from 75% to 100% VR max temperature. For example, if the VR max temperature is 100C, platform users have to set the TSEN voltage to be 1.4875V when VR temperature reaches 75C and 1.8725V when VR temperature reaches 100C. Detailed voltage setting versus temperature variation is shown in Table 2. Thermometer code is implemented in the Temperature Zone register. Table 2. Temperature Zone Register Comparator Trip Points SVID Temperatures Scaled to maximum = VRHOT Thermal 100% Alert Voltage Represents Assert bit Minimum Level b7 b6 b5 b4 b3 b2 b1 b0 100% 97% 94% 91% 88% 85% 82% 75% 1.745 1.69 1.635 1.58 1.52 1.47 1.855V 1.8V V V V V 5V V 1.855 VTSEN 1.800 V TSEN 1.835 1.745 V TSEN 1.780 Temperature_Zone Register Content 1111_1111 0111_1111 0011_1111 1.690 V TSEN 1.725 1.635 V TSEN 1.670 1.580 V TSEN 1.615 1.525 V TSEN 1.560 0001_1111 0000_1111 0000_0111 0000_0011 1.470 V TSEN 1.505 V TSEN < 1.470 0000_0001 0000_0000 TSEN Pin Voltage DS8168B-00 November 2011 RT8168B The RT8168B supports two temperature reporting, VRHOT(hardware reporting) and ALERT(software reporting), to fulfill VR12/IMVP7 specification. VRHOT is an open-drain structure which sends out active-low VRHOT signals. When TSEN voltage rises above 1.855V (100% of VR temperature), the VRHOT signal will be set to low. When TSEN voltage drops below 1.8V (97% of VR temperature), the VRHOT signal will be reset to high. When TSEN voltage rises above 1.8V (97% of VR temperature), The RT8168B will update the bit1 data from 0 to 1 in the Status_1 register and assert ALERT. When TSEN voltage drops below 1.745V (94% of VR temperature), VR will update the bit1 data from 1 to 0 in the Status_1 register and assert ALERT. The temperature reporting function for the GFX VR can be disabled by pulling TSENA pin to VCC in case the temperature reporting function for the GFX VR is not used or the GFX VR is disabled. When the GFX VR's temperature reporting function is disabled, the RT8168B will reject the SVID command of getting the Temperature_Zone register content of the GFX VR. However, note that the temperature reporting function for the CORE VR is always active. CORE VR's temperature reporting function can not be disabled by pulling TSEN pin to VCC. VCC ROC1 OCSETx ROC2 Figure 14. OCP Setting without Temperature Compensation The current limit is triggered when inductor current exceeds the current limit threshold ILIMIT, defined by VOCSET. The driver will be forced to turn off UGATE until the over current condition is cleared. If the over current condition remains valid for 15 PWM cycles, VR will trigger OCP latch. Latched OCP forces both UGATE and LGATE to go low. When OCP is triggered in one of VRs, the other VR will enter into soft shutdown sequence. The OCP latch mechanism will be masked when VRx_READY = low, which means that only the current limit will be active when VOUT is ramping up to initial voltage (or VREFx). If inductor DCR is used as the current sense component, then temperature compensation is recommended for protection under all conditions. Figure 15 shows a typical OCP setting with temperature compensation. VCC ROC1a Over Current Protection The CORE/GFX VR compares a programmable current limit set point to the voltage from the current sense amplifier output for Over Current Protection (OCP). The voltage applied to OCSETx pin defines the desired peak current limit threshold ILIMIT : VOCSET = 48 x ILIMIT x RSENSE DS8168B-00 November 2011 ROC1b OCSETx ROC2 Figure 15. OCP Setting with Temperature Compensation (17) Connect a resistive voltage divider from VCC to GND, with the joint of the resistive divider connected to OCSET pin as shown in Figure 14. For a given ROC2, then VCC ROC1 = ROC2 x - 1 V OCSET NTC (18) Usually, ROC1a is selected to be equal to the thermistor's nominal resistance at room temperature. Ideally, VOCSET is assumed to have the same temperature coefficient as RSENSE (Inductor DCR) : VOCSET, HOT RSENSE, HOT = VOCSET, COLD RSENSE, COLD (19) www.richtek.com 35 RT8168B According to the basic circuit calculation, VOCSET can be obtained at any temperature : VOCSET, T = VCC x ROC2 ROC1a / /RNTC, T + ROC1b + ROC2 (20) Re-write (19) from (20), to get VOCSET at room temperature ROC1a // RNTC, COLD + ROC1b + ROC2 RSENSE, HOT = ROC1a // RNTC, HOT + ROC1b + ROC2 RSENSE, COLD (21) VOCSET, 25 = VCC x ROC2 ROC1a / /RNTC, 25 + ROC1b + ROC2 (22) Solving (21) and (22) yields ROC1b and ROC2 ROC2 = x REQU, HOT - REQU, COLD + (1 - ) x REQU, 25 VCC x (1 - ) VOCSET, 25 (23) ROC1b = ( - 1) x R2 + x REQU, HOT - REQU, COLD (1 - ) During OVP latch state, both CORE/GFX VRs also monitor ISENxN pin for negative voltage protection. Since the OVP latch will continuously turn on low side MOSFET of VR, VR may suffer negative output voltage. Therefore, when the voltage of ISENxN drops below -0.05V after triggering OVP, VR will turn off low side MOSFETs while high side MOSFETs remain off. The NVP function will be active only after OVP is triggered. Under Voltage Protection (UVP) Both CORE/GFX VR implement Under Voltage Protection (UVP). If ISENxN is less than VREFx by 300mV + VOFFSET, VR will trigger UVP latch. The UVP latch will turn off both high side and low side MOSFETs. When UVP is triggered by one of the VRs, the other VR will enter into soft shutdown sequence. The UVP mechanism is masked when VRx_READY = low. Under Voltage Lock Out (UVLO) (24) where = RSENSE, HOT DCR25 x [1 + 0.00393 x (THOT - 25)] = RSENSE, COLD DCR25 x [1 + 0.00393 x (TCOLD - 25)] (25) REQU, T = ROC1a // RNTC, T Negative Voltage Protection (NVP) (26) During normal operation, if the voltage at the VCC pin drops below UVLO falling edge threshold, both VR will trigger UVLO. The UVLO protection forces all high side MOSFETs and low side MOSFETs off to turn off. Inductor Selection The switching frequency and ripple current determine the inductor value as follows : V - VOUT LMIN = IN xt (27) IRipple(MAX) ON Over Voltage Protection (OVP) The over voltage protection circuit of CORE/GFX VR monitors the output voltage via the ISENxN pin. The supported maximum operating VID of VR (V(MAX)) is stored in the Vout_Max register. Once VISENxN exceeds "V(MAX) + 200mV", OVP is triggered and latched. VR will try to turn on low side MOSFETs and turn off high side MOSFETs to protect CPU. When OVP is triggered by the one of the VRs, the other VR will enter soft shutdown sequence. A 10s delay is used in OVP detection circuit to prevent false trigger. www.richtek.com 36 where tON is the UGATE turn on period. Higher inductance induces less ripple current and hence higher efficiency. However, the tradeoff is a slower transient response of the power stage to load transients. This might increase the need for more output capacitors, thus driving up the cost. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. The core must be large enough not to be saturated at the peak inductor current. DS8168B-00 November 2011 RT8168B Output Capacitor Selection Output capacitors are used to obtain high bandwidth for the output voltage beyond the bandwidth of the converter itself. Usually, the CPU manufacturer recommends a capacitor configuration. Two different kinds of output capacitors can be found, bulk capacitors closely located to the inductors and ceramic output capacitors in close proximity to the load. Latter ones are for mid-frequency decoupling with very small ESR and ESL values while the bulk capacitors have to provide enough stored energy to overcome the low-frequency bandwidth gap between the regulator and the CPU. The capacitor connected to the ISEN1N/ISENAN for noise decoupling is optional and it should also be placed close to the ISEN1N/ISENAN pin. The NTC thermistor should be placed physically close to the inductor for better DCR thermal compensation. Layout Consideration Careful PC board layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all of the power components on the top side of the board with their ground terminals flushed against one another. Follow these guidelines for optimum PC board layout : Keep the high current paths short, especially at the ground terminals. Keep the power traces and load connections short. This is essential for high efficiency. When trade-offs in trace lengths must be made, it's preferable to allow the inductor charging path to be made longer than the discharging path. Place the current sense component close to the controller. ISENxP and ISENxN connections for current limit and voltage positioning must be made using Kelvin sense connections to guarantee the current sense accuracy. The PCB trace from the sense nodes should be parallel to the controller. Route high-speed switching nodes away from sensitive analog areas (COMPx, FBx, ISENxP, ISENxN, etc...) Special attention should be paid in placing the DCR current sensing components. The DCR current sensing capacitor and resistors must be placed close to the controller. DS8168B-00 November 2011 www.richtek.com 37 RT8168B Outline Dimension D SEE DETAIL A D2 L 1 E2 E e b 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A3 A1 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 4.950 5.050 0.195 0.199 D2 3.250 3.500 0.128 0.138 E 4.950 5.050 0.195 0.199 E2 3.250 3.500 0.128 0.138 e L 0.400 0.350 0.016 0.450 0.014 0.018 W-Type 40L QFN 5x5 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: marketing@richtek.com Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 38 DS8168B-00 November 2011