RT8168BGQW - Richtek - Datasheet.Directory

RT8168B

DS8168B-00 November 2011 www.richtek.com

General Description

The RT8168B is a dual single-pha se PWM controller with

integrated MOSFET drivers, compliant with Intel IMVP7

Pulse Width Modulation Specification to support both

CPU core and GPU core power. This part adopts G-NA VPTM

(Green-Native A VP), which is a Richtek proprietary topology

derived from finite DC gain compen sator in consta nt on-

time control mode. G-NAVPTM makes this part an easy

setting PWM controller to meet all Intel AVP (Active

V oltage Positioning) mobile CPU/GPU requirements. The

RT8168B uses SVID interfa ce to control an 8-bit DAC for

output voltage programming. The built-in high accuracy

DAC converts the received VID code into a voltage value

ranging from 0V to 1.52V with 5mV step voltage. The

system accuracy of the controller can reach 0.8%. The

RT8168B operates in continuous conduction mode or

diode emulation mode, according to the SVID command.

The maximum efficiency can rea ch up to 90% in different

operating modes according to different load conditions.

The droop function (load line) ca n be ea sily progra mmed

by setting the DC gain of the error a mplif ier. With proper

compensation, the load transient response can achieve

optimized A VP performance.

The output voltage transition slew rate is set via the SVID

interface. The RT8168B supports both DCR and sense

resistor current sensing. The RT8168B provides

VR_READY and thermal throttling output signals for

IMVP7 CPU and GPU core. This part also features

complete fault protection functions including over voltage,

under voltage, negative voltage, over current and thermal

shutdown.

The RT8168B is available in a WQFN-40L 5x5 small

footprint pa ckage.

Dual Single-Phase PWM Controller for CPU and GPU Core

Power Supply

Applications

zIMVP7 Intel CPU/GPU Core Power Supply

zLa ptop Computers

zA VP Step-Down Converter

Features

zDual Single-Phase PWM Controller for CPU Core

and GPU Core Power

zIMVP7 Compatible Power Management States

zSerial VID Interface

zG-NAVPTM Topology

zAVP f or CPU V R Only

z0.5% DAC Accuracy

z0.8% System Accuracy

zDifferential Remote Voltage Sensing

zBuilt-in ADC for Platform Programming

`SETINI/SETINIA for CPU/GPU Core VR Initial

Startup Voltage

`TMPMAX to Set Platform Maximum Temperature

`ICCMAX/ICCMAXA for CPU/GPU Core VR

Maximum Current

zPower Good Indicator : VR_READY/VRA_READY for

CPU/GPU Core Power

zThermal Throttling Indicator : VRHOT

zDiode Emulation Mode at Light Load Condition

zFast Line/Load Transient Response

zSwitching Frequency up to 1MHz per Phase

zOVP, UVP, NVP, OTP, UVLO, OCP

zSmall 40-Lead WQFN Package

zRoHS Compliant and Halogen Free

RT8168B

2DS8168B-00 November 2011www.richtek.com

Ordering Information

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

Pin Configurations

(TOP VIEW)

WQFN-40L 5x5

BOOT1

ISEN1N

ISEN1P

SETINIA

VCC

GFXPS2

RGND

COMP

TONSET ISENAP

FBA

COMPA

VR_READY

VRA_READY

VDIO

RGNDA

VCLK

ISENAN

SETINI

TMPMAX

ICCMAX

ICCMAXA

TSEN

OCSET

TSENA

OCSETA

IBIAS

UGATE1

PHASE1

LGATE1

PVCC

LGATEA

PHASEA

UGATEA

BOOTA

TONSETA

20191817161514131211

31323334353637383940

GND

VRHOT

ALERT

Marking Information

Package Type

QW : WQFN-40L 5x5 (W-Type)

RT8168B

Lead Plating System

G : Green (Halogen Free and Pb Free)

RT8168BGQW : Product Number

YMDNN : Date Code

RT8168B

GQW

YMDNN

RT8168B

DS8168B-00 November 2011 www.richtek.com

Typical Application Circuit

CORE

ISEN1N

RT8168B

TONSET

VCC

ISEN1P3

R14C6C5

R13

GND41 (Exposed Pad)

COMP

R21

C11

C10CORE V

SENSE

R23

PVCCC8

RGND7

R12

NTC

R15

R28

ISENAN

TONSETA

ISENAP30

C14

R43C16C17

R35

5V to 25V

R42

C15

R33

COMPA

FBA

R48

C20

C19

R50

C18

RGNDA26

C12

R34

R41

NTC

R44

R51

25VCLK

VCLK24VDIO

VDIO23

ALERT

CCP

22VRA_READY

VRA_READY21VR_READY

VR_READY

R9R10R11

VRHOT20

18OCSETA

R17

10SETINIA

R18R19R20

SETINI

R25R26R27

R24

OCSET

OCSETA

SETINIA

SETINI

OCSET

8GFXPS2

13ICCMAX

R29R30R31

ICCMAXA

R37R38R39

TMPMAX

ICCMAX

TMPMAX

IBIAS

R54

R47

NTC

R46

TSENA

TSEN

NTC

R16

R22

R45

R52R53

R49

BOOT1

GFX

R32

R40

ALERT

VRHOT

UGATEA

PHASEA

LGATEA

5V to 25V

UGATE1

PHASE1

LGATE1

Chip Enable

GFX V

SENSE

GFX V

SENSE

33C13

BOOTAR36

CORE VSS SENSE

VCORE

GFXPS2

ICCMAXA

2.2

1µF

13013015010k

10k75

27k8.7k10k10k

10k

10kNCNC

51k150k100kNC

33k5.1k1.6k10k

12k10k

ß = 338012k10k

ß = 3380

R71

750R72

750

1k1k53.6k

130k

0.1µF

5.1

10µF

00.1µF1µH

DCR = 7.6m

Optional

3.9k0.068µF

2.4k4.7k4.7k

ß = 3500

330µF

/9m

C26

330µF

/9m

OptionalOptional

71k10k100

100

Optional

1µF

130k5.1

0.1µF

10µF

00.1µF

Optional

11k0.1µF

1.2k1k1k

ß = 3650

330µF

/15m

C27

330µF

/15m

Optional

OptionalOptional

42k10k100

100

2µH

DCR = 14.6m

RT8168B

4DS8168B-00 November 2011www.richtek.com

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 VDAC Voltage

0 0 0 0 0 0 0 0 0 0 0.000

0 0 0 0 0 0 0 1 0 1 0.250

0 0 0 0 0 0 1 0 0 2 0.255

0 0 0 0 0 0 1 1 0 3 0.260

0 0 0 0 0 1 0 0 0 4 0.265

0 0 0 0 0 1 0 1 0 5 0.270

0 0 0 0 0 1 1 0 0 6 0.275

0 0 0 0 0 1 1 1 0 7 0.280

0 0 0 0 1 0 0 0 0 8 0.285

0 0 0 0 1 0 0 1 0 9 0.290

0 0 0 0 1 0 1 0 0 A 0.295

0 0 0 0 1 0 1 1 0 B 0.300

0 0 0 0 1 1 0 0 0 C 0.305

0 0 0 0 1 1 0 1 0 D 0.310

0 0 0 0 1 1 1 0 0 E 0.315

0 0 0 0 1 1 1 1 0 F 0.320

0 0 0 1 0 0 0 0 1 0 0.325

0 0 0 1 0 0 0 1 1 1 0.330

0 0 0 1 0 0 1 0 1 2 0.335

0 0 0 1 0 0 1 1 1 3 0.340

0 0 0 1 0 1 0 0 1 4 0.345

0 0 0 1 0 1 0 1 1 5 0.350

0 0 0 1 0 1 1 0 1 6 0.355

0 0 0 1 0 1 1 1 1 7 0.360

0 0 0 1 1 0 0 0 1 8 0.365

0 0 0 1 1 0 0 1 1 9 0.370

0 0 0 1 1 0 1 0 1 A 0.375

0 0 0 1 1 0 1 1 1 B 0.380

0 0 0 1 1 1 0 0 1 C 0.385

0 0 0 1 1 1 0 1 1 D 0.390

0 0 0 1 1 1 1 0 1 E 0.395

0 0 0 1 1 1 1 1 1 F 0.400

0 0 1 0 0 0 0 0 2 0 0.405

0 0 1 0 0 0 0 1 2 1 0.410

0 0 1 0 0 0 1 0 2 2 0.415

Table 1. IMVP7/VR12 Compliant VID Table

To be continued

RT8168B

DS8168B-00 November 2011 www.richtek.com

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

0 0 1 0 0 0 1 1 2 3 0.420

0 0 1 0 0 1 0 0 2 4 0.425

0 0 1 0 0 1 0 1 2 5 0.430

0 0 1 0 0 1 1 0 2 6 0.435

0 0 1 0 0 1 1 1 2 7 0.440

0 0 1 0 1 0 0 0 2 8 0.445

0 0 1 0 1 0 0 1 2 9 0.450

0 0 1 0 1 0 1 0 2 A 0.455

0 0 1 0 1 0 1 1 2 B 0.460

0 0 1 0 1 1 0 0 2 C 0.465

0 0 1 0 1 1 0 1 2 D 0.470

0 0 1 0 1 1 1 0 2 E 0.475

0 0 1 0 1 1 1 1 2 F 0.480

0 0 1 1 0 0 0 0 3 0 0.485

0 0 1 1 0 0 0 1 3 1 0.490

0 0 1 1 0 0 1 0 3 2 0.495

0 0 1 1 0 0 1 1 3 3 0.500

0 0 1 1 0 1 0 0 3 4 0.505

0 0 1 1 0 1 0 1 3 5 0.510

0 0 1 1 0 1 1 0 3 6 0.515

0 0 1 1 0 1 1 1 3 7 0.520

0 0 1 1 1 0 0 0 3 8 0.525

0 0 1 1 1 0 0 1 3 9 0.530

0 0 1 1 1 0 1 0 3 A 0.535

0 0 1 1 1 0 1 1 3 B 0.540

0 0 1 1 1 1 0 0 3 C 0.545

0 0 1 1 1 1 0 1 3 D 0.550

0 0 1 1 1 1 1 0 3 E 0.555

0 0 1 1 1 1 1 1 3 F 0.560

0 1 0 0 0 0 0 0 4 0 0.565

0 1 0 0 0 0 0 1 4 1 0.570

0 1 0 0 0 0 1 0 4 2 0.575

0 1 0 0 0 0 1 1 4 3 0.580

0 1 0 0 0 1 0 0 4 4 0.585

0 1 0 0 0 1 0 1 4 5 0.590

To be continued

RT8168B

6DS8168B-00 November 2011www.richtek.com

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

0 1 0 0 0 1 1 0 4 6 0.595

0 1 0 0 0 1 1 1 4 7 0.600

0 1 0 0 1 0 0 0 4 8 0.605

0 1 0 0 1 0 0 1 4 9 0.610

0 1 0 0 1 0 1 0 4 A 0.615

0 1 0 0 1 0 1 1 4 B 0.620

0 1 0 0 1 1 0 0 4 C 0.625

0 1 0 0 1 1 0 1 4 D 0.630

0 1 0 0 1 1 1 0 4 E 0.635

0 1 0 0 1 1 1 1 4 F 0.640

0 1 0 1 0 0 0 0 5 0 0.645

0 1 0 1 0 0 0 1 5 1 0.650

0 1 0 1 0 0 1 0 5 2 0.655

0 1 0 1 0 0 1 1 5 3 0.660

0 1 0 1 0 1 0 0 5 4 0.665

0 1 0 1 0 1 0 1 5 5 0.670

0 1 0 1 0 1 1 0 5 6 0.675

0 1 0 1 0 1 1 1 5 7 0.680

0 1 0 1 1 0 0 0 5 8 0.685

0 1 0 1 1 0 0 1 5 9 0.690

0 1 0 1 1 0 1 0 5 A 0.695

0 1 0 1 1 0 1 1 5 B 0.700

0 1 0 1 1 1 0 0 5 C 0.705

0 1 0 1 1 1 0 1 5 D 0.710

0 1 0 1 1 1 1 0 5 E 0.715

0 1 0 1 1 1 1 1 5 F 0.720

0 1 1 0 0 0 0 0 6 0 0.725

0 1 1 0 0 0 0 1 6 1 0.730

0 1 1 0 0 0 1 0 6 2 0.735

0 1 1 0 0 0 1 1 6 3 0.740

0 1 1 0 0 1 0 0 6 4 0.745

0 1 1 0 0 1 0 1 6 5 0.750

0 1 1 0 0 1 1 0 6 6 0.755

0 1 1 0 0 1 1 1 6 7 0.760

0 1 1 0 1 0 0 0 6 8 0.765

0 1 1 0 1 0 0 1 6 9 0.770

To be continued

RT8168B

DS8168B-00 November 2011 www.richtek.com

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

0 1 1 0 1 0 1 0 6 A 0.775

0 1 1 0 1 0 1 1 6 B 0.780

0 1 1 0 1 1 0 0 6 C 0.785

0 1 1 0 1 1 0 1 6 D 0.790

0 1 1 0 1 1 1 0 6 E 0.795

0 1 1 0 1 1 1 1 6 F 0.800

0 1 1 1 0 0 0 0 7 0 0.805

0 1 1 1 0 0 0 1 7 1 0.810

0 1 1 1 0 0 1 0 7 2 0.815

0 1 1 1 0 0 1 1 7 3 0.820

0 1 1 1 0 1 0 0 7 4 0.825

0 1 1 1 0 1 0 1 7 5 0.830

0 1 1 1 0 1 1 0 7 6 0.835

0 1 1 1 0 1 1 1 7 7 0.840

0 1 1 1 1 0 0 0 7 8 0.845

0 1 1 1 1 0 0 1 7 9 0.850

0 1 1 1 1 0 1 0 7 A 0.855

0 1 1 1 1 0 1 1 7 B 0.860

0 1 1 1 1 1 0 0 7 C 0.865

0 1 1 1 1 1 0 1 7 D 0.870

0 1 1 1 1 1 1 0 7 E 0.875

0 1 1 1 1 1 1 1 7 F 0.880

1 0 0 0 0 0 0 0 8 0 0.885

1 0 0 0 0 0 0 1 8 1 0.890

1 0 0 0 0 0 1 0 8 2 0.895

1 0 0 0 0 0 1 1 8 3 0.900

1 0 0 0 0 1 0 0 8 4 0.905

1 0 0 0 0 1 0 1 8 5 0.910

1 0 0 0 0 1 1 0 8 6 0.915

1 0 0 0 0 1 1 1 8 7 0.920

1 0 0 0 1 0 0 0 8 8 0.925

1 0 0 0 1 0 0 1 8 9 0.930

1 0 0 0 1 0 1 0 8 A 0.935

1 0 0 0 1 0 1 1 8 B 0.940

1 0 0 0 1 1 0 0 8 C 0.945

1 0 0 0 1 1 0 1 8 D 0.950

To be continued

RT8168B

8DS8168B-00 November 2011www.richtek.com

To be continued

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

1 0 0 0 1 1 1 0 8 E 0.955

1 0 0 0 1 1 1 1 8 F 0.960

1 0 0 1 0 0 0 0 9 0 0.965

1 0 0 1 0 0 0 1 9 1 0.970

1 0 0 1 0 0 1 0 9 2 0.975

1 0 0 1 0 0 1 1 9 3 0.980

1 0 0 1 0 1 0 0 9 4 0.985

1 0 0 1 0 1 0 1 9 5 0.990

1 0 0 1 0 1 1 0 9 6 0.995

1 0 0 1 0 1 1 1 9 7 1.000

1 0 0 1 1 0 0 0 9 8 1.005

1 0 0 1 1 0 0 1 9 9 1.010

1 0 0 1 1 0 1 0 9 A 1.015

1 0 0 1 1 0 1 1 9 B 1.020

1 0 0 1 1 1 0 0 9 C 1.025

1 0 0 1 1 1 0 1 9 D 1.030

1 0 0 1 1 1 1 0 9 E 1.035

1 0 0 1 1 1 1 1 9 F 1.040

1 0 1 0 0 0 0 0 A 0 1.045

1 0 1 0 0 0 0 1 A 1 1.050

1 0 1 0 0 0 1 0 A 2 1.055

1 0 1 0 0 0 1 1 A 3 1.060

1 0 1 0 0 1 0 0 A 4 1.065

1 0 1 0 0 1 0 1 A 5 1.070

1 0 1 0 0 1 1 0 A 6 1.075

1 0 1 0 0 1 1 1 A 7 1.080

1 0 1 0 1 0 0 0 A 8 1.085

1 0 1 0 1 0 0 1 A 9 1.090

1 0 1 0 1 0 1 0 A A 1.095

1 0 1 0 1 0 1 1 A B 1.100

1 0 1 0 1 1 0 0 A C 1.105

1 0 1 0 1 1 0 1 A D 1.110

1 0 1 0 1 1 1 0 A E 1.115

1 0 1 0 1 1 1 1 A F 1.120

1 0 1 1 0 0 0 0 B 0 1.125

1 0 1 1 0 0 0 1 B 1 1.130

RT8168B

DS8168B-00 November 2011 www.richtek.com

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

1 0 1 1 0 0 1 0 B 2 1.135

1 0 1 1 0 0 1 1 B 3 1.140

1 0 1 1 0 1 0 0 B 4 1.145

1 0 1 1 0 1 0 1 B 5 1.150

1 0 1 1 0 1 1 0 B 6 1.155

1 0 1 1 0 1 1 1 B 7 1.160

1 0 1 1 1 0 0 0 B 8 1.165

1 0 1 1 1 0 0 1 B 9 1.170

1 0 1 1 1 0 1 0 B A 1.175

1 0 1 1 1 0 1 1 B B 1.180

1 0 1 1 1 1 0 0 B C 1.185

1 0 1 1 1 1 0 1 B D 1.190

1 0 1 1 1 1 1 0 B E 1.195

1 0 1 1 1 1 1 1 B F 1.200

1 1 0 0 0 0 0 0 C 0 1.205

1 1 0 0 0 0 0 1 C 1 1.210

1 1 0 0 0 0 1 0 C 2 1.215

1 1 0 0 0 0 1 1 C 3 1.220

1 1 0 0 0 1 0 0 C 4 1.225

1 1 0 0 0 1 0 1 C 5 1.230

1 1 0 0 0 1 1 0 C 6 1.235

1 1 0 0 0 1 1 1 C 7 1.240

1 1 0 0 1 0 0 0 C 8 1.245

1 1 0 0 1 0 0 1 C 9 1.250

1 1 0 0 1 0 1 0 C A 1.255

1 1 0 0 1 0 1 1 C B 1.260

1 1 0 0 1 1 0 0 C C 1.265

1 1 0 0 1 1 0 1 C D 1.270

1 1 0 0 1 1 1 0 C E 1.275

1 1 0 0 1 1 1 1 C F 1.280

1 1 0 1 0 0 0 0 D 0 1.285

1 1 0 1 0 0 0 1 D 1 1.290

1 1 0 1 0 0 1 0 D 2 1.295

1 1 0 1 0 0 1 1 D 3 1.300

1 1 0 1 0 1 0 0 D 4 1.305

1 1 0 1 0 1 0 1 D 5 1.310

To be continued

RT8168B

10 DS8168B-00 November 2011www.richtek.com

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

1 1 0 1 0 1 1 0 D 6 1.315

1 1 0 1 0 1 1 1 D 7 1.320

1 1 0 1 1 0 0 0 D 8 1.325

1 1 0 1 1 0 0 1 D 9 1.330

1 1 0 1 1 0 1 0 D A 1.335

1 1 0 1 1 0 1 1 D B 1.340

1 1 0 1 1 1 0 0 D C 1.345

1 1 0 1 1 1 0 1 D D 1.350

1 1 0 1 1 1 1 0 D E 1.355

1 1 0 1 1 1 1 1 D F 1.360

1 1 1 0 0 0 0 0 E 0 1.365

1 1 1 0 0 0 0 1 E 1 1.370

1 1 1 0 0 0 1 0 E 2 1.375

1 1 1 0 0 0 1 1 E 3 1.380

1 1 1 0 0 1 0 0 E 4 1.385

1 1 1 0 0 1 0 1 E 5 1.390

1 1 1 0 0 1 1 0 E 6 1.395

1 1 1 0 0 1 1 1 E 7 1.400

1 1 1 0 1 0 0 0 E 8 1.405

1 1 1 0 1 0 0 1 E 9 1.410

1 1 1 0 1 0 1 0 E A 1.415

1 1 1 0 1 0 1 1 E B 1.420

1 1 1 0 1 1 0 0 E C 1.425

1 1 1 0 1 1 0 1 E D 1.430

1 1 1 0 1 1 1 0 E E 1.435

1 1 1 0 1 1 1 1 E F 1.440

1 1 1 1 0 0 0 0 F 0 1.445

1 1 1 1 0 0 0 1 F 1 1.450

1 1 1 1 0 0 1 0 F 2 1.455

1 1 1 1 0 0 1 1 F 3 1.460

1 1 1 1 0 1 0 0 F 4 1.465

1 1 1 1 0 1 0 1 F 5 1.470

1 1 1 1 0 1 1 0 F 6 1.475

1 1 1 1 0 1 1 1 F 7 1.480

1 1 1 1 1 0 0 0 F 8 1.485

To be continued

RT8168B

DS8168B-00 November 2011 www.richtek.com

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

1 1 1 1 1 0 0 1 F 9 1.490

1 1 1 1 1 0 1 0 F A 1.495

1 1 1 1 1 0 1 1 F B 1.500

1 1 1 1 1 1 0 0 F C 1.505

1 1 1 1 1 1 0 1 F D 1.510

1 1 1 1 1 1 1 0 F E 1.515

1 1 1 1 1 1 1 1 F F 1.520

RT8168B

12 DS8168B-00 November 2011www.richtek.com

Functional Pin Description

Pin No. Pin Name Pin Function

1 BOOT1 CPU VR Bootstrap Power Pin. This pin powers the high side MOSFET drivers.

Connect this pin to the PHASE1 pin with a bootstrap capacitor.

2 TONSET

Single-Phase CPU VR On-Time Setting Pin. Connect this pin to VIN with a

resis tor to s et ripple si ze in PWM m ode .

3 ISEN1P Positive Current Sense Input Pin of CPU VR.

4 IS EN 1N N egati ve C urren t S en se In put P in of C PU VR .

5 C OMP CPU VR Compensation Pin. This pin is the output of the error amplifier.

6 FB CPU VR Feedback Pin. This pin is the inverting input node of the error amplifier.

7 RGND Return Ground for CPU VR. This pin is the inverting input node for differential

remote voltage sensing.

8 GFXPS2

Set Pin for GPU VR Operation Mode. Logic-high on this pin will force the GPU VR

to enter DCM.

9 VCC Controller Power Supply Pin. Connect this pin to GND via a ceramic capacitor

la rger tha n 1 μF.

10 SETINIA ADC Input for Single-Phase GPU VR VBOOT Voltage Setting.

11 SETINI ADC Input for Single-Phase CPU VR VBOOT Voltage Setting.

12 TMPMAX ADC Input for Single-Phase CPU VR Maximum Temperature Setting.

13 ICCMAX ADC Input for Single-Phase CPU VR Maximum Current Setting.

14 ICCMAXA ADC Input for Single-Phase GPU VR Maximum Current Setting.

15 TSEN Thermal Monitor Sense Input Pin for CPU VR.

16 OCSET

Set Pin for Single-Phase CPU VR Over Current Protection Threshold.

C on nec t a resis ti ve v ol t ag e di vi der fr om V CC to g r oun d, a nd c onnec t th e jo int of

the voltage divider to the OCSET pin. The voltage, VOCSET, at this pin sets the

over current threshold, ILIMIT, for CP U VR.

17 TSENA Ther mal Monit or Sens e Input for GPU VR.

18 OCSETA

Set Pin for Single-Phase GPU VR Over Current Protec tion Threshold.

C on nec t a resis ti ve v ol t ag e di vi der fr om V CC to g r oun d, a nd c onnec t th e jo int of

the voltage divider to the OCSE TA pin. The voltage, VOCSETA, at this pin sets the

over current threshold, ILIMIT, for GPU VR.

19 IBIAS In ternal Bias Curr en t Set ting. C on nec t a 53.6k Ω r e si sto r from t h is pin t o G N D to

set the internal bias current.

20 VRHOT Th e rmal Monitor Outpu t Pin (active low).

21 VR_READY CPU VR Voltage Ready Indicator. This pin has an open drain output.

22 VRA_READY GPU VR Voltage Ready Indicator. This pin has an open drain output.

23 ALERT Alert Line of SVID Interface (active low). This pin has an open drain output.

24 VDIO Data Transmission Line of SVID Interface.

25 VCLK C lock Signal Line of S VID Interface.

26 RGNDA Return Ground for Single-Phase GPU VR.

This pin is the inverting input node for differential remote voltage sensing.

27 FBA GPU VR Feedback Pin. This pin is the inverting input node of the error amplifier.

28 COMPA Single-Phase GPU VR Compensation Pin. This pin is the output of the error

amplifier.

29 ISENAN N eg ati ve Curr en t S en se In put Pin of S i ng le-Ph as e G PU V R.

30 ISENAP Positive Current Sense Input Pin of Single-Phase GPU VR.

31 TONSETA

Single-Phase GPU VR On-Time Setting Pin. Connect this pin to VIN with a

resis tor to s et ripp le si ze in PWM m ode.

To be continued

RT8168B

DS8168B-00 November 2011 www.richtek.com

Pin No. Pin Name Pin Function

32 EN Voltage Regulator Enable Signal Input Pin.

33 BOOTA

GPU VR Boo ts trap Po w er P in . Thi s pi n po w ers the h igh s id e M OSFE T driv er s .

Connect this pin to the PHASEA pin with a bootstrap capacitor.

34 UGATEA

U ppe r G ate D riv er of G PU VR . This pi n d r iv es the hi gh si de MO SFE T of GPU

VR.

35 PHASEA

Switc h Nod e of G P U V R. T his pin is t he return n ode of the h igh si de M O SFET

driver for GPU VR. Connect this pin to the joint of the source of high side

MOSFET, drain of the low side M OSFET, and the output inductor.

36 LGATEA

Lower Gate Driver of GPU VR. This pin drives the low side MOSFET of GPU

VR.

37 PVCC

MOSFET Driver Power Supply Pin. Connect this pin to GND via a ceramic

capacitor larger than 1μF.

38 LGATE1

Lower Gate Driver of CPU VR. This pin drives the low side MOSFET of CPU

VR.

39 PHASE1

Switc h N od e o f C PU VR . Th is pin is the ret ur n n od e o f th e h igh si de dri ver f or

CPU VR. Connec t this pin to the joint of the source of high side MOSFET, drain

of the low side MOSFET, and the output inductor.

40 UGATE1

U ppe r G ate D riv er of C PU VR. T his pin d r iv es th e h igh s ide M O SFE T o f CPU

VR.

41 (E xp os ed Pad) G ND Gr ound of Low Sid e M OSFE T D riv er. The ex pos ed pa d m us t b e s old ered to a

large P CB and connected to GND for maximum power dissipation.

RT8168B

14 DS8168B-00 November 2011www.richtek.com

Function Block Diagram

ICCMAX

ICCMAXA

TSEN

FBA

COMPA

ERROR

AMP

TMPMAX

Control & Protection Logic

MUX

ADC

SVID XCVR

VDIO

VCLK

VR_READY

VRA_READY

RGNDA

PWM CMP

From Control Logic

VREFA

VCC

UVLO

PVCC

BOOTA

UGATEA

PHASEA

LGATEA

SETINIA

SETINI

TSENA

TONSETA

TON Time

Generator

Driver Logic

Control

Offset

Cancellation

GFXPS2

VRHOT

ALERT

DAC

OCPOVP/UVP/NVP

ERROR

AMP

RGND

PWM CMP

From Control Logic

Soft-Start & Slew

Rate Control VREF

BOOT1

UGATE1

PHASE1

LGATE1

TONSET

TON Time

Generator

Driver Logic

Control

Offset

Cancellation +

DAC

To Protection Logic

Soft-Start & Slew

Rate Control

10 OCP OVP/UVP/NVP

To Protection Logic

COMP

ISEN1P

ISEN1N

OCSET

ISENAP

ISENAN

OCSETA

IBIAS

RT8168B

DS8168B-00 November 2011 www.richtek.com

Recommended Operating Conditions (Note 4)

zSupply Voltage, VCC ------------------------------------------------------------------------------------- 4.5V to 5.5V

zInput Voltage, VIN ----------------------------------------------------------------------------------------- 5V to 25V

zJunction T emperature Range--------------------------------------------------------------------------- −40°C to 125°C

zAmbient T emperature Range--------------------------------------------------------------------------- −40°C to 85°C

Absolute Maximum Ratings (Note 1)

zPVCC, VCC to GND ------------------------------------------------------------------------------------- −0.3V to 6.5V

zRGNDx to GND ------------------------------------------------------------------------------------------- −0.3V to 0.3V

zTONSETx to GND ---------------------------------------------------------------------------------------- −0.3V to 28V

zOthers------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)

zBOOTx to PHASEx-------------------------------------------------------------------------------------- −0.3V to 6.5V

zPHASEx to GND

DC------------------------------------------------------------------------------------------------------------ −3V to 28V

<20ns ------------------------------------------------------------------------------------------------------- −8V to 32V

zUGATEx to PHASEx

DC------------------------------------------------------------------------------------------------------------ −0.3V to (BOOTx − PHASEx)

<20ns ------------------------------------------------------------------------------------------------------- −5V to 7.5V

zLGA TEx to GND

DC------------------------------------------------------------------------------------------------------------ −0.3V to (PVCC + 0.3V)

<20ns ------------------------------------------------------------------------------------------------------- −2.5V to 7.5V

zPower Dissipation, PD @ TA = 25°C

WQFN−40L 5x5------------------------------------------------------------------------------------------- 2.778W

zPa ckage Thermal Resista nce (Note 2)

WQFN−40L 5x5, θJA ------------------------------------------------------------------------------------- 36°C/W

WQFN−40L 5x5, θJC------------------------------------------------------------------------------------- 6°C/W

zJunction T emperature------------------------------------------------------------------------------------ 150°C

zLead T emperature (Soldering, 10 sec.)-------------------------------------------------------------- 260°C

zStorage T emperature Range --------------------------------------------------------------------------- −65°C to 150°C

zESD Susceptibility (Note 3)

HBM (Human Body Mode) ----------------------------------------------------------------------------- 2kV

MM (Ma chine Mode) ------------------------------------------------------------------------------------- 200V

Electrical Characteristics

(VCC = 5V, TA = 25°C, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

Sup ply Inpu t VCC/VPVCC V

EN = 1.05V, Not Switching 4.5 5 5.5 V

Input Voltage Range VIN Battery Input Voltage 5 -- 25 V

Supply Current

(VCC + PVCC) IVCC + IPVCC V

EN = 1.05V, Not Switching -- 12 20 mA

Supply Current

(TONSETx) ITONSETx V

FB =1 V, VIN = 1 2V, RTON = 100kΩ -- 110 -- μA

To be continued

RT8168B

16 DS8168B-00 November 2011www.richtek.com

To be continued

Parameter Symbol Test Conditions Min Typ Max Unit

Shu tdown Current

(PVCC + VCC) IVCC_SHDN

+ IPVCC_SHDN VEN = 0V -- -- 5 μA

Shu tdown Current

(TONSETx) ITONSETx_SHDN V

EN = 0V -- -- 5 μA

TON Setting

TO NSETx Voltage VTONSETx I

RTON = 80μA, VFBx = 1V 0.95 1.075 1. 2 0V

On-Time tON I

RTON = 80μA, VFBx = 1V 315 350 385 ns

TONS ETx Input

Current Range IRTON V

FBx = 1.1V 25 -- 2 80 μA

Minimum Off-Time T OFF_MIN -- 350 -- ns

GFX VR Force d D EM

GFXPS2x Ena ble

Threshold VGFXPS 4.3 -- -- V

GFXPS2x Disable

Threshold VGFXPS -- -- 0.7 V

Refer ences and System Out put Vo lt age

VIDSVID Se tt in g = 1.000V~ 1. 520V

OFSSVID Setting = 0 V −0.5 0 0.5 %VID

VIDSVID Se tt in g = 0.800V~ 1. 000V

OFSSVID Setting = 0 V −5 0 5

VIDSVID Se tt in g = 0.500V~ 0. 800V

OFSSVID Setting = 0 V −8 0 8

VIDSVID Se tt in g = 0.250V~ 0. 500V

OFSSVID Setting = 0 V −8 0 8

DA C Accuracy

(PS0/PS1) VFBx

VIDSVID Se tt in g = 1.100V

OFSSVID Setting = −0.640V~0.635V −10 0 10

VINI_CORE = 0 V, VINI_GFX = 0V 0 0 .3125 0.5125

VINI_CORE = 0.9V, VINI_GFX = 0.9V 0.7375 0. 9375 1. 13 75

VINI_CORE = 1 V, VINI_GFX = 1V 1. 3625 1.5625 1.7625

SETINIx Voltage VSETINIx

VINI_CORE = 1.1V, VINI_GFX = 1.1V 2.6125 -- 5

IBIA S Pin Voltage VIBIAS R

IBIAS = 5 3.6 kΩ 2.09 2.14 2.19 V

S et VI D Slow 2. 5 3.125 3.75

Dynam ic VI D Slew

Rate SRDVID SetVID Fas t 10 1 2.5 15 mV/μs

Error Amplifier

DC Gain ADC R

L = 4 7 kΩ (Note5) 70 80 -- dB

Gain-Ban dwidth

Product GBW CLOAD = 5pF (Note5) -- 10 -- MHz

Slew Rate SRCOMP CLOAD = 10pF (Gai n = −4,

RLOAD_COMP = 47kΩ, VCOMPx =

0. 5V to 3V) -- 5 -- V/μs

Output Voltage

Range VCOMP R

L = 4 7 kΩ 0.5 -- 3.6 V

MA X Source /S ink

Current ICOMP V

COMP = 2V -- 250 - - μA

Im pedance of FB x RFBx 1 -- -- MΩ

RT8168B

DS8168B-00 November 2011 www.richtek.com

To be continued

Parameter Symbol Test Conditions Min Typ Max Unit

Current Sen se Amplifier

I nput Of f s et Voltage V OFS_CSA −1 -- 1 mV

I mpedance of Neg. I nput R ISENxN 1 -- -- MΩ

Impedance of Pos. Input RISENxP 1 -- -- MΩ

Current Sense

D if ferenti al Input Range VCSDIx VFBx = 1.1V,

VCSDIx = V ISENxP − VISENxN −50 -- 100 mV

Current Sense D C Gain

(Loop) AI V

FBx = 1.1V, −30m V < V CSDIx < 50mV -- 1 0 -- V/V

VISEN Lin ear it y VISEN_ACC V

DAC = 1.1V −30mV < VISEN_IN < 50mV −1 -- 1 %

Gate Driver

U pper Driver S our ce R UGATEx_sr VBOOTx − VPHASEx = 5 V

VBOOTx − VUGATEx = 0.1V -- 1 -- Ω

U pper Driver Sink R UGATEx_sk V

UGATEx = 0.1V - - 1 -- Ω

Lower Dr i v er S our ce R LGATEx_sr PVCC = 5V, PVCC − VLGATEx = 0.1V -- 1 -- Ω

Lower Dr ive r Sink RLGATEx_sk V

LGATEx = 0.1V - - 0.5 -- Ω

Internal Boot Charging

Sw itc h On -Resis ta n ce RBOOTx PVCC to BOOTx -- 30 -- Ω

Zer o Current Det ect ion

Threshold VZCD_TH V

ZCD_TH = GND − VPHASEx -- 10 -- mV

Protection

U nder V ol t age Lock- out

Threshold VUVLO V C C Fal ling edge 4. 04 4. 24 -- V

U nder V ol t age Lock- out

Hysteresis ΔVUVLO -- 100 -- mV

Over Volt age Protection

Threshold VOVP Respect to VOUT_MAXSVID, with 1μs

fi lte r time 100 150 200 mV

U nder V ol t age Pr ot ecti on

Threshold VUVP VUVP = VISENxN − VREFx, 0.8V < VREFx

<1. 52V, wit h 3μs fi lt er t ime −350 −300 −250 mV

Negat i ve Vol tage

P ro tecti on Thres hold VNVP V

NVP = VISENxN − GND −100 −50 -- mV

C ur rent S ense Ga in for

Over Current Protectio n AOC VOCSET = 2. 4V

VISENxP − VISENxN = 5 0mV -- 48 -- V/V

Logi c Inputs

Logic-High VIH Wi th r espect t o 1V, 70% 0. 7 -- --

EN Input

Threshold

Voltage Logic-Low VIL Wi th r espect t o 1V, 30% - - - - 0.3 V

Leakage Current of EN −1 -- 1 μA

VIH W ith res p ect to Intel Spec . 0 .65 - - --

VC LK,VDIO Input

Thr eshold Vol tage VIL W ith re s p ec t to Intel Spec . -- - - 0 .45 V

Leakage Current of

VCL K, VDIO ILEAK_IN −1 -- 1 μA

RT8168B

18 DS8168B-00 November 2011www.richtek.com

Parameter Symbol Test Conditions Min Typ Max Unit

ALERT

ALE RT Low Voltage VALERT IALERT _ SIN K = 4mA -- -- 0.4 V

V R R eady

V Rx_RE AD Y Low Vol tage V VRx_READY I

VRx_ R EADY_ SINK = 4mA -- - - 0. 4 V

VRx_READY Delay tVRx_READY V

ISENxN = VBOOT to VVRx_READY high 70 100 160 μs

T her ma l T hro ttlin g

V RH O T Ou tpu t V ol t age VVRHOT I

VRHOT_SINK = 40mA -- 0.4 -- V

H igh Im pedance Outp ut

AL ERT, VRx_READY,

VRHOT ILEAK_OUT −1 -- 1 μA

Temperature Zone

TSE N Threshold for

Tm p_Zone [7] t ransit ion 100°C -- 1.8725 -- V

TSE N Threshold for

Tm p_Zone [6] t ransit ion 97°C -- 1.8175 -- V

TSE N Threshold for

Tm p_Zone [5] t ransit ion 94°C -- 1.7625 -- V

TSE N Threshold for

Tm p_Zone [4] t ransit ion 91°C -- 1.7075 -- V

TSE N Threshold for

Tm p_Zone [3] t ransit ion

VTSENx

88°C -- 1.6525 -- V

TSE N Threshold for

Tm p_Zone [2] t ransit ion 85°C -- 1.5975 -- V

TSE N Threshold for

Tm p_Zone [1] t ransit ion 82°C -- 1.5425 -- V

TSE N Threshold for

Tm p_Zone [0] t ransit ion

VTSENx

75°C -- 1.4875 -- V

U pdate Peri od tTSEN -- 1600 -- μs

ADC

Latency tLAT -- -- 400 μs

CICCMAX1 V

ICCMAX = 0.637V 29 32 35 decim al

CICCMAX2 V

ICCMAX = 1.2642V 61 64 67 decim al

Di gi tal Code of ICCMAX

CICCMAX3 V

ICCMAX = 2.5186V 125 128 131 decim al

CICCMAXA1 V

ICCMAXA = 0 .1666V 5 8 11 deci mal

CICCMAXA2 V

ICCMAXA = 0.3234V 13 16 19 decimal Di gi tal Code of ICCMAXA

CICCMAXA3 V

ICCMAXA = 0.637V 29 32 35 decimal

CTMPMAX1 V

TMPMAX = 1.6758V 82 85 88 decim al

CTMPMAX2 V

TMPMAX = 1.9698V 97 100 103 decim al D ig it al C ode of TM PMAX

CTMPMAX3 V

TMPMAX = 2.4598V 122 125 128 decim al

RT8168B

DS8168B-00 November 2011 www.richtek.com

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may remain possibility to affect device reliability.

Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of

JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the

package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. Guaranteed by design.

RT8168B

20 DS8168B-00 November 2011www.richtek.com

Typical Operating Characteristics

Boot VID = 1V

Time (100μs/Div)

CORE VR Power On from EN

(2V/Div)

VCORE

(500mV/Div)

VR_READY

(2V/Div)

UGATE

(20V/Div)

Time (100μs/Div)

CORE VR Power Off from EN

Boot VID = 1V

(2V/Div)

VCORE

(500mV/Div)

VR_READY

(2V/Div)

UGATE

(20V/Div)

VID = 1.1V

Time (100μs/Div)

CORE VR OCP

ILOAD

(10A/Div)

VCORE

(1V/Div)

VR_READY

(1V/Div)

UGATE

(20V/Div)

Time (40μs/Div)

CORE VR OVP and NVP

VID = 1.1V

LGATE

(10V/Div)

VCORE

(1V/Div)

VR_READY

(1V/Div)

UGATE

(20V/Div)

0.7V to 1.2V, Slew Rate = Slow, ILOAD = 4A

Time (40μs/Div)

CORE VR Dynamic VID Up

VDIO

(2V/Div)

VCLK

(2V/Div)

VCORE

(500mV/Div)

ALERT

(2V/Div)

Time (40μs/Div)

CORE VR Dy n amic VID Down

1.2V to 0.7V, Slew Rate = Slow, ILOAD = 4A

ALERT

(2V/Div)

VCORE

(500mV/Div)

VDIO

(2V/Div)

VCLK

(2V/Div)

RT8168B

DS8168B-00 November 2011 www.richtek.com

Time (10μs/Div)

CORE VR Dynamic VID Up

0.7V to 1.2V, Slew Rate = Fast, ILOAD = 4A

VDIO

(2V/Div)

VCLK

(2V/Div)

VCORE

(500mV/Div)

ALERT

(2V/Div)

Time (10μs/Div)

CORE VR Dy n amic VID Down

1.2V to 0.7V, Slew Rate = Fast, ILOAD = 4A

VCORE

(500mV/Div)

ALERT

(2V/Div)

VDIO

(2V/Div)

VCLK

(2V/Div)

VID = 1.1V, ILOAD = 1A to 8A, Slew Time = 150ns

Time (100μs/Div)

CORE VR Load Transient

VCORE

(20mV/Div)

ILOAD

(A/Div)

Time (100μs/Div)

CORE VR Load Transient

VID = 1.1V, ILOAD = 8A to 1A, Slew Time = 150ns

VCORE

(20mV/Div)

ILOAD

(A/Div)

VID = 1.1V, PS0 to PS2, ILOAD = 0.2A

Time (100μs/Div)

CORE VR Mode Transition

UGATE

(20V/Div)

VCLK

(1V/Div)

LGATE

(10V/Div)

VCORE

(20mV/Div)

Time (100μs/Div)

CORE VR Mode Transition

VID = 1.1V, PS2 to PS0, ILOAD = 0.2A

UGATE

(20V/Div)

VCORE

(20mV/Div)

VCLK

(1V/Div)

LGATE

(10V/Div)

RT8168B

22 DS8168B-00 November 2011www.richtek.com

CORE VR VREF vs. Temperature

0.990

0.992

0.994

0.996

0.998

1.000

1.002

1.004

1.006

-50 -25 0 25 50 75 100 125

Temperature (°C)

VREF (V)

Time (100μs/Div)

GFX VR OCP

ILOAD

(5A/Div)

VGFX

(1V/Div)

VRA_READY

(1V/Div)

UGATEA

(20V/Div)

Time (40μs/Div)

GFX VR OVP and NVP

VID = 1.1V

LGATEA

(10V/Div)

VGFX

(1V/Div)

VRA_READY

(1V/Div)

UGATEA

(20V/Div)

Time (100μs/Div)

GFX VR Power On from EN

Boot VID = 1V

(2V/Div)

VGFX

(500mV/Div)

VRA_READY

(2V/Div)

UGATEA

(20V/Div)

Time (100μs/Div)

GFX VR Power Off from EN

Boot VID = 1V

UGATEA

(20V/Div)

(2V/Div)

VGFX

(500mV/Div)

VRA_READY

(2V/Div)

TSEN Sweep from 1.7V to 1.9V

Time (10ms/Div)

CORE VR Thermal Monitoring

VRHOT

(500mV/Div)

TSEN

(V/Div)

1.9

1.7

RT8168B

DS8168B-00 November 2011 www.richtek.com

Time (40μs/Div)

GFX VR Dynamic VID

0.7V to 1.2V, Slew Rate = Slow, ILOAD = 1.25A

VDIO

(2V/Div)

VCLK

(2V/Div)

VGFX

(500mV/Div)

ALERT

(2V/Div)

Time (40μs/Div)

GFX VR Dynamic VID

ALERT

(2V/Div)

VGFX

(500mV/Div)

1.2V to 0.7V, Slew Rate = Slow, ILOAD = 1.25A

VDIO

(2V/Div)

VCLK

(2V/Div)

Time (10μs/Div)

GFX VR Dynamic VID

0.7V to 1.2V, Slew Rate = Fast, ILOAD = 1.25A

VDIO

(2V/Div)

VCLK

(2V/Div)

VGFX

(500mV/Div)

ALERT

(2V/Div)

Time (10μs/Div)

GFX VR Dynamic VID

ALERT

(2V/Div) 1.2V to 0.7V, Slew Rate = Fast, ILOAD = 1.25A

VDIO

(2V/Div)

VCLK

(2V/Div)

VGFX

(500mV/Div)

Time (100μs/Div)

GFX VR Load Transient

VID = 1.1V, ILOAD = 1A to 4A, Slew Time = 150ns

VGFX

(20mV/Div)

ILOAD

(A/Div)

Time (100μs/Div)

GFX VR Load Transient

VID = 1.1V, ILOAD = 4A to 1A, Slew Time = 150ns

VGFX

(20mV/Div)

ILOAD

(A/Div)

RT8168B

24 DS8168B-00 November 2011www.richtek.com

GFX VR VREF vs. Temperature

0.988

0.990

0.992

0.994

0.996

0.998

1.000

1.002

1.004

1.006

-50-250 255075100125

Tempera tu re (°C )

VREF (V)

Time (100μs/Div)

GFX VR Mode Transition

VID = 1.1V, PS2 to PS0, ILOAD = 0.1A

UGATEA

(20V/Div)

VGFX

(20mV/Div)

VCLK

(1V/Div)

LGATEA

(10V/Div)

Time (100μs/Div)

GFX VR Mode Transition

VID = 1.1V, PS0 to PS2, ILOAD = 0.1A

UGATEA

(20V/Div)

VCLK

(1V/Div)

LGATEA

(10V/Div)

VGFX

(20mV/Div)

Time (10ms/Div)

GFX VR Thermal Monitoring

TSENA Sweep from 1.7V to 1.9V

1.9

1.7

TSENA

(V/Div)

VRHOT

(500mV/Div)

RT8168B

DS8168B-00 November 2011 www.richtek.com

Application Information

The RT8168B is a VR12/IMVP7 compliant, dual single-

phase synchronous Buck PWM controller for the CPU

CORE V R a nd GFX VR. The gate drivers are embedded

to facilitate PCB design and reduce the total BOM cost. A

serial VID (SVID) interface is built-in in the RT8168B to

communicate with Intel V R12/IMVP7 compliant CPU.

The RT8168B adopts G-NAVPTM (Green Native AVP),

which is Richtek's proprietary topology derived from finite

DC gain compensator, making it an easy setting PWM

controller to meet AVP requirements. The load line can

be ea sily progra mmed by setting the DC gain of the error

amplifier. The RT8168B has fast tra n sient response due

to the G-NAVPTM commanding variable switching

frequency.

G-NAVPTM topology also represents a high efficiency

system with green power concept. With G-NAVPTM

topology , the RT8168B becomes a green power controller

with high efficiency under heavy load, light load, a nd very

light load conditions. The RT8168B supports mode

transition function between CCM and DEM. These different

operating states allow the overall power system to have

low power loss. By utilizing the G-NAVPTM topology, the

operating frequency of RT8168B varies with output voltage,

load and VIN to further enhance the efficiency even in CCM.

The built-in high accuracy DAC converts the SVID code

ranging from 0.25V to 1.52V with 5mV per step. The

differential remote output voltage sense and high accuracy

DAC allow the system to have high output voltage accuracy.

The RT8168B supports VR12/IMVP7 compatible power

management states and VID on-the-fly function. The power

management states include DEM in PS2/PS3 and Forced-

CCM in PS1/PS0. The VID on-the-fly function has three

different slew rates : Fa st, Slow and Decay . The RT8168B

integrates a high accuracy ADC for platform setting

functions, such as no-load offset and over current level.

The controller supports both DCR and sense-resistor

current sensing. The RT8168B provides VR ready output

signals of both CORE VR and GFX VR. It also features

complete fault protection functions including over voltage,

under voltage, negative voltage, over current a nd under

voltage lockout. The RT8168B is available in a WQFN-

48L 6x6 small f oot print package.

De sign Tool

To help users reduce efforts and errors caused by ma nual

calculations, a user-friendly design tool is now available

on request. This design tool calculates all necessary

design parameters by entering user's requirements.

Please conta ct Richtek's representatives for details.

Serial VID (SVID) Interface

SVID is a three-wire serial synchronous interface defined

by Intel. The three wire bus includes VDIO, VCLK and

ALERT signals. The master (Intel's VR12/IMVP7 CPU)

initiates and terminates SVID transa ctions and drives the

V DIO, VCLK, a nd ALERT during a transaction. The slave

(RT8168B) receives the SVID transactions and acts

accordingly.

RT8168B

26 DS8168B-00 November 2011www.richtek.com

Standard Serial VID Command

Code Commands Master Payload

Contents Slave Payload

Contents Description

00h not supported N/A N/A N/A

01h SetVID_Fast VID code N/A Se t new tar get VID code, VR ju mps t o n ew VID

target with controlled default “fast” slew rate

12.5mV/μs.

02h SetVID_Slow VID code N/A Se t new tar get VID code, VR ju mps t o n ew VID

target with controlled default “slow” slew rate

3.125mV/μs.

03h SetVID_Decay VID code N/A

Se t new tar get VID code, VR ju mps t o n ew VID

target, but does not control the slew rate. The

output voltage decays at a rate proportional to

the load current

04h SetPS Byte indicating

power states N/A Set power state

05h SetRegADR

Pointer of registers

in data table N/A Set the pointer of the data register

06h SetReg DAT New data r egister

content N/A Write the contents to the data register

07h GetReg

Pointer of registers

in data table

Specified

Contents

Slave returns the contents of the specified

08h

1Fh not supported N/A N/A N/A

RT8168B

DS8168B-00 November 2011 www.richtek.com

Data and Configuration Register

Index Register Name Description Access Default

00h V endor ID V endor I D, defa ult 1Eh. RO, V endor 1 Eh

01h Pr oduct ID Product ID . RO, V endor 65h

02h Pr oduct Revisi on Product Rev isi on. RO, V endor 01h

05h Protocol ID SVI D Prot ocol ID . RO, Vendor 01h

06h VR_Capability Bi t m apped r egi s t er , iden ti fies the SVID VR c apabil it ies

and whi ch of the opt ional telem etry r egi ster are

supported. RO, V endor 81h

10h S t at us _1 Da ta register contai ning the st at us of V R. R -M, W- PWM 00h

11h Status-2 Da ta r egi s ter contai ning the st at us of t ransmi ss i on. R -M, W- P WM 00h

12h Temperature

Zone Data r egi s ter show ing temper ature zone t hat have been

entered. R-M, W-PWM 00h

15h Output_Current Da ta register show ing dir ect AD C convers ion of av eraged

output cur rent . R-M, W-PWM 00h

1C h St at us_2_l as t read The register cont ai ns a copy of t he st atus_2. R -M, W-PWM 00h

21h ICC_Max Data r egister contai ni ng the m axi mu m ICC o f pl at form

supports.

Bi nary for m at i n Amp, I E 64h = 10 0A. RO, Platform --

22h Temp_Max

Da ta re gist er cont aining the tempe ra ture max t he plat for m

supports.

Bi nary for m at i n °C , I E 64h = 100°C

On ly for CORE VR

RO, Platform --

24h SR-Fast Da ta reg ist er cont aining the capabil ity of fast slew r at e th e

platform can sustains. Binary format in mV/μs, IE 0Ah =

10mV/μs. RO 0Ah

25h SR-Slow Dat a regist er cont aining t he capabil ity of slow slew rate.

Binary format in mV /μs I E 02h = 2. 5m V/μs. RO 02h

30h VOUT_Max The register i s progr am m ed by th e master a nd sets the

maximum VID. RW, Mast er BFh

31h VID Setting Data r egi s ter contai ning currently pro gra mm ed VID . RW, Master 00h

32h Power St at e R egi ster containing the curr ent programm ed power state. RW, Master 00h

33h Of f set Se t of fset in V ID steps. RW, M as t er 00h

34h Mult i VR Conf ig Bit mapped dat a register which conf igures m ul ti ple V Rs

behavior on the same bus. RW, Master 00h

35h Pointer Scratch pad regist er f or tem por ar y storage of the

Set RegA DR poi nter register. RW, Master 30h

Notes :

RO = Read Only

RW = Read/Write

R-M = Read by Master

W-PWM = Write by PWM only

Vendor = hard coded by VR vendor

Platform = programmed by platform

Master = programmed by the master

PWM = programmed by the VR control IC

RT8168B

28 DS8168B-00 November 2011www.richtek.com

Figure 5. ADC Pins Setting

A/D

Converter

ICCMAX

ICCMAXA

TMPMAX

VCC

ICCMAX, ICCMAXA and TMPMAX

The RT8168B provides ICCMAX, ICCMAXA and TMPMAX

pins for platform users to set the maximum level of output

current or VR temperature: ICCMAX for CORE VR

maximum current, ICCMAXA for GFX VR maximum

current, and TMPMAX for CORE VR maximum

temperature.

To set ICCMAX, ICCMAXA and TMPMAX, platform

designers should use resistive voltage dividers on these

three pins. The current of the divider should be several

milli-Amps to avoid noise effect. The three items share

the sa me algorithms : the ADC divides 5V into 255 levels.

Therefore, LSB = 5/255 = 19.6mV, which mea ns 19.6mV

a pplied to ICCMAX pin equals to 1A setting. For exa mple,

if a platform designer wants to set TMPMAX to 120°C, the

voltage applied to TMPMAX should be 120 x 19.6mV =

2.352V. The ADC circuit inside these three pins will

decode the voltage a pplied and store the maximum current/

temperature setting into ICC_MAX and Temp_Max

registers. The ADC monitors a nd decodes the voltage at

these three pins only after EN = high. If EN = low, the

RT8168B will not take any a ction even when the VR output

current or temperature exceeds its maximum setting at

these ADC pins. The maximum level settings at these

ADC pins are different from over current protection or over

temperature protection. That means, these maximum level

setting pins are only for platform users to define their

system operating conditions and these messages will only

be utilized by the CPU.

VINI_CORE and VINI_GFX Setting

The initial start up voltage (VINI_CORE, VINI_GFX) of the

RT8168B can be set by platform users through SETINI

and SETINIA pins. V oltage divider circuit is recommended

to be a pplied to SETINI and SETINIA pins. The VINI_CORE/

VINI_GFX relate to SETINI/SETINIA pin voltage setting as

shown in Figure 6. Recommended voltage setting at SETINI

a nd SETINIA pins are also shown in Figure 6.

Precise Reference Current Generation

The RT8168B includes extensive analog circuits inside

the controller. These analog circuits need very precise

reference voltage/current to drive these a nalog devices.

The RT8168B will auto-generate a 2.14V voltage source

at IBIAS pin, and a 53.6kΩ resistor is required to be

connected between IBIAS and analog ground. Through

this connection, the RT8168B generates a 40μA current

from IBIAS pin to analog ground and this 40μA current will

be mirrored inside the RT8168B for internal use. Other

types of connection or other values of resista nce a pplied

at the IBIAS pin may cause failure of the RT8168B's analog

circuits. Thus a 53.6kΩ resistor is the only recommended

component to be connected to the IBIAS pin. The

resistance accuracy of this resistor is recommended to

be at least 1%.

Figure 4. IBIAS Setting

IBIAS

53.6k

Current

Mirror

2.14V

Power Ready Detection and Power On Reset (POR)

During start-up, the RT8168B detects the voltage on the

voltage input pins : VCC and EN. When VCC > VUVLO,

the RT8168B will recognize the power state of system to

be ready (POR = high) and wait for enable command at

EN pin. After POR = high a nd EN > VENTH, the RT8168B

will enter start-up sequence for both CORE VR a nd GFX

VR. If the voltage on any voltage pin drops below POR

threshold (POR = low), the RT8168B will enter power down

sequence and all the functions will be disabled. SVID will

be invalid within 300μs after chip becomes enabled. All

the protection latches (OVP, OCP, UVP, OTP) will be

cleared only after POR = low. EN = low will not clear

these latches.

Figure 3. Power Ready Detection a nd Power On Reset

(POR)

UVLO

ENTH

POR

Chip EN

VCC

RT8168B

DS8168B-00 November 2011 www.richtek.com

Figure 6. SETINI a nd SETINIA Pin Voltage Setting

Start Up Sequence

The RT8168B utilizes internal soft-start sequence which

strictly follows Intel VR12/IMVP7 start up sequence

specifications. After POR = high and EN = high, a 300μs

delay is needed for the controller to determine whether all

the power inputs are ready for entering start up sequence.

If pin voltage of SETINI/SETINIA is zero, the output voltage

of CORE/GFX VR is programmed to stay at 0V. If pin

voltage of SETINI/SETINIA is not zero, VR output voltage

will ra mp up to initial boot voltage (VINI_CORE, VINI_GFX) after

both POR = high a nd EN = high. After the output voltage

of CORE/GFX V R rea ches target initial boot voltage, the

controller will keep the output voltage at the initial boot

voltage and wait for the next SVID comma nds. After the

RT8168B receives valid VID code (typically SetVID_Slow

command), the output voltage will ramp up/down to the

target voltage with specified slew rate. After the output

voltage reaches the target voltage, the RT8168B will send

out VR_READY signal to indicate the power state of the

RT8168B is ready. The VR_READY circuit is an open-

drain structure so a pull-up resistor is recommended for

connecting to a voltage source.

VINI_CORE

VINI_GFX Recomm ended

SETINI/SETINIA Pin Voltage

1.1V 5

8x VCC≒3.125V or VCC

1V 3

8x VCC≒1.875V

0.9V 3

16 x VCC≒0.9375V

0V 1

16 x VCC≒0.3125V or GND

VCC (5V)

GND

1/8 VCC

1/4 VCC

1/2 VCC

VINI_CORE= 0.9V

VINI_GFX= 0.9V

VINI_CORE = 1.1V

VINI_GFX= 1.1V

VINI_CORE= 1V

VINI_GFX= 1V

VINI_CORE= 0V

VINI_GFX= 0V

Power Down Sequence

Similar to the start up sequence, the RT8168B also utilizes

a soft shutdown mecha nism during turn-off. After POR =

low, the internal reference voltage (positive terminal of

compensation EA) starts ra mping down with 3.125mV/μs

slew rate, and output voltage will follow the reference

voltage to 0V. After output voltage drops below 0.2V, the

RT8168B shuts down a nd all functions are disabled. The

VR_READY will be pulled down immediately after POR =

low.

RT8168B

30 DS8168B-00 November 2011www.richtek.com

Figure 7 (a). Power sequence for RT8168B (VINI_CORE = VINI_GFX = 0V)

Figure 7 (b). Power sequence for RT8168B (VINI_CORE 0, VINI_GFX 0V)

≠ ≠

SVID Valid xx

VCORE

VR_READY 100µs

POR

0.2V

CORE VR

Operation Mode CCM CCM

0.2V

VGFX

SVID defined

CCM SVID defined

GFX VR

Operation Mode

100µs

VRA_READY

CCM

300µs

Off

VCC

EN Chip

(Internal Signal)

Off

VRA_READY

EN Chip

(Internal Signal)

SVID Valid xx

VCORE

VR_READY 100µs

POR

0.2V

CORE VR

Operation Mode CCM CCMOff

0.2V

VGFX

SV ID d efin ed

CCMOff SVID d e fine d

GFX VR

Operation Mode CCM

250µs

Off

VCC

100µs

300µs

VINI_GFX

VINI_CORE

50µs

RT8168B

DS8168B-00 November 2011 www.richtek.com

Since the DCR of inductor is temperature dependent, it

affects the output a ccuracy in high temperature conditions.

Temperature compensation is recommended for the

lossless inductor DCR current sense method. Figure 10

shows a simple but effective way of compensating the

temperature variations of the sense resistor using an NTC

thermistor pla ced in the feedback path.

Figure 10. Loop Setting with Temperature Compensation

VCC_SENSE

+VSS_SENSE

FBx

RGNDx

COMPx

C2 C1

R2 R1b

R1a

NTC

VREFx

Figure 8. Simplified Schematic for Droop a nd Remote

Sense in CCM

Disable GFX VR : Before EN = High

GFX VR enable or disable is determined by the internal

circuitry that monitors the ISENAN voltage during start

up. Before EN = high, GFX VR detects whether the voltage

of ISENAN is higher than “VCC − 1V” to disable GFX

VR. The unused driver pins ca n be connected to GND or

left floating.

GFX VR Forced-DEM Function Enable : After

VRA_Ready = High

The GFX VR's forced-DEM function can be enabled or

disabled with GFXPS2 pin. The RT8168B detects the

voltage of GFXPS2 for forced-DEM function. If the voltage

at GFXPS2 pin is higher than 4.3V, the GFX VR operates

in forced-DEM. If this voltage is lower tha n 0.7V , the GFX

VR f ollows SVID power state command.

Loop Control

Both CORE a nd GFX VR a dopt Richtek's proprietary G-

NAVPTM topology. G-NAVPTM is based on the finite-gain

valley current mode with CCRCOT (Constant Current

Ripple Con stant On Time) topology. The output voltage,

VCORE or VGFX, will decrease with increasing output load

current. The control loop consists of PWM modulator with

power stage, current sense amplifier and error amplifier

as shown in Figure 8.

Similar to the valley current mode control with finite

compensator gain, the high side MOSFET on-time is

determined by the CCRCOT PWM generator . When load

current increa ses, VCS increa ses, the steady state COMP

voltage also increases which makes the output voltage

decrease, thus achieving A VP.

Droop Setting (with Temperature Compensation)

It's very easy to achieve the Active Voltage Positioning

(AVP) by properly setting the error amplifier gain due to

the native droop chara cteristics. The target is to have

VOUT = VREFx − ILOAD x RDROOP (1)

Then solving the switching condition VCOMPx = VCSx in

Figure 8 yields the desired error a mplif ier gain a s

where AI is the internal current sen se amplifier gain and

RSENSE is the current sense resistance. If no external sense

resistor is present, the DCR of the inductor will act as

RSENSE. RDROOP is the resistive slope value of the converter

output a nd is the desired static output i mpedance.

Figure 9. Error Amplifier Gain (AV) Influence on VOUT

Accuracy

AV1

AV2

AV2 > AV1

VOUT

Load Current

I SENSE

VDROOP

AR1 R (2)

VIN

ISENxP

ISENxN

FBx

RGNDx

High Side

MOSFET L

RXCX

R2 CORE/GFX VR

VCC_SENSE

COMPx

VCSx

C2 C1

VREFx

GFX/CORE VR

CCRCOT

PWM Generator

Driver

Logic

Control

CByp

UGATEx

PHASEx

LGATEx

CORE/GFX VR

VSS_SENSE

VOUT

(VCORE/VGFX)

CMP

Low Side

MOSFET

RT8168B

32 DS8168B-00 November 2011www.richtek.com

Loop Compensation

Optimized compensation of the CORE VR allows for best

possible load step response of the regulator's output. A

type-I compensator with one pole and one zero is adequate

for a proper compensation. Figure 10 shows the

compensation circuit. It wa s previously mentioned that to

determine the resistive feedback components of error

amplifier gain, C1 and C2 must be calculated for the

compensation. The target is to achieve constant resistive

output impedance over the widest possible frequency

range.

The pole frequency of the compensator must be set to

compensate the output capacitor ESR zero :

where C is the ca pacitance of the output capa citor and RC

is the ESR of the output capa citor. C2 ca n be calculated

as follows :

The zero of compensator has to be placed at half of the

switching frequency to filter the switching-related noise.

Such that,

TON Setting

High frequency operation optimizes the application by

trading off efficiency due to higher switching losses with

smaller component size. This may be a cceptable in ultra-

portable devices where the load currents are lower and

the controller is powered from a lower voltage supply . Low

frequency operation offers the best overall efficiency at

the expense of component size a nd board space. Figure

11 shows the on-time setting circuit. Connect a resistor

(RTONSETx) between VIN and TONSETx to set the on-ti me

of UGATEx :

SENSE, HOT NTC, HOT NTC, COLD

SENSE, COLD

SENSE, HOT

SENSE, COLD

R1b

R(R1a//R ) (R1a//R )

×−

⎛⎞

−

⎜⎟

⎝⎠

(8)

f2CR

=×π× × (9)

C2 R2

= (10)

(1 1)

()

NTC, 25 C SW

C1 R1b R1a //R f

=+×π×

Usually, R1a is set to equal RNTC (25°C), while R1b is

selected to linearize the NTC's temperature characteristic.

For a given NTC, the design would be to obtain R1b a nd

R2 and then C1 and C2. According to (2), to compensate

the temperature variations of the sense resistor , the error

amplifier gain (AV) should have the same temperature

coefficient with RSENSE. Hence

From (2), we can have Av at any temperature (T) a s

The standard formula for the resistance of NTC thermistor

as a function of temperature is given by :

where RNTC, 25 is the thermistor's nominal resistance at

room temperature, β (beta) is the thermistor's material

constant in Kelvins, and T is the thermistor's actual

temperature in Celsius.

The DCR value at different temperatures can be calculated

using the equation below :

DCRT = DCR25 x [1+0.00393 x (T-25)] (6)

where 0.00393 is the temperature coefficient of copper.

For a given NTC thermistor, solving (4) at room temperature

(25°C) yields

R2 = AV, 25 x (R1b + R1a // RNTC, 25) (7)

where AV, 25°C is the error a mplifier gain at room temperature

obtained from (2). R1b can be obtained by substituting

(7) to (3),

V, HOT SENSE, HOT

V, COLD SENSE, COLD

= (3)

V, T NTC, T

AR1a / /R R1b

=+ (4)

(

)

(

)

{

}

T+273 298

NTC, T NTC, 25

RR e

⎡⎤

β−

⎢⎥

⎣⎦

= (5)

(12)

××

<= −

-12 TONSETx

ONx REFx IN REFx

28 10 R

t (V 1.2V) VV

where tONx is the UGA TEx turn on period, VIN is the input

voltage of converter, and VREFx is the internal reference

voltage.

RT8168B

DS8168B-00 November 2011 www.richtek.com

Figure 11. On-T ime Setting with RC Filter

(13)

≥

×× ×

=−

ONx REFx -12 TONSETx REFx

IN REFx

t (V 1.2V)

23.33 10 R V

(14)

−

−−

=×

−

⎡⎤

+× +−

⎣⎦

⎡⎤

+× −

⎣⎦

S(MAX) ON HS Delay

REFx(MAX) LOAD(MAX) ON_LS FET DROOP

IN(MAX) LOAD(MAX) ON_LS FET ON_HS FET

f(kHz)

VI R DCRR

VI R R

When VREFx is larger than 1.2V, the equivalent switching

frequency may be over the maximum design range, making

it una cceptable. Therefore, the VR implements a pseudo-

constant-frequency technology to avoid this disadvantage

of CCRCOT topology. When VREFx is larger than 1.2V,

the on-time equation will be modified to :

On-time tra nslates roughly to switching frequencies. The

on-times guaranteed in the Electrical Characteristics are

influenced by switching delays in external high side

MOSFET. Also, the dead-time effect increases the effective

on-time, reducing the switching frequency. It occurs only

in CCM during dynamic output voltage transitions when

the inductor current reverses at light or negative load

currents. With reversed inductor current, PHASEx goes

high earlier than normal, extending the on-time by a period

equal to the high side MOSFET rising dead time.

For better efficiency of the given load range, the maximum

switching frequency is suggested to be :

where fS(MAX) is the maximum switching frequency, tHS-

Delay is the turn on delay of high side MOSFET, VREFx(MAX)

is the maximum application DAC voltage of application,

VIN(MAX) is the maximum application input voltage,

ILOAD(MAX) is the maximum loa d of a pplication, RON_LS-FET

is the low side MOSFET RDS(ON), RON_HS-FET is the high

side MOSFET RDS(ON), DCRL is the inductor DCR, and

RDROOP is the load line setting.

GFX/CORE

VR CCRCOT

PWM

Generator

TONSETx RTONSETx R1

VIN

VREFx

On-Time

Differential Remote Sense Setting

The CORE/GFX VR includes differential, remote-sense

inputs to eliminate the effects of voltage drops along the

PC board tra c es, CPU intern al power routes and socket

contacts. The CPU contains on-die sense pins CORE/

GFX VCC_SENSE and VSS_SENSE. Connect RGNDx to CORE/

GFX VSS_SENSE. Connect FBx to CORE/GFX VCC_SENSE

with a resistor to build the negative input path of the error

a mplifier. The precision voltage reference VREFx is referred

to RGND f or accurate remote sen sing.

Current Sense Setting

The current sense topology of the CORE/GFX VR is

continuous inductor current sensing. Therefore, the

controller can be less noise sensitive. Low offset a mplifiers

are used for loop control a nd over current detection. The

internal current sense a mplifier gain (AI) is fixed to be 10.

The ISENxP and ISENxN denote the positive and negative

input of the current sense amplifier .

Users can either use a current sense resistor or the

inductor's DCR for current sensing. Using inductor's DCR

allows higher eff iciency a s shown in Figure 12. To let

then the transient performance will be optimum. For

example, choose L = 0.36μH with 1mΩ DCR and

CX = 100nF, to yields for RX :

LRC

DCR =× (15)

X0.36 H

R3.6k

1m 100nF

==Ω

Ω× (16)

LDCR

RXCX

VOUT

(VCORE/VGFX)

CByp

ISENxP

ISENxN

PHASEx

VCSx

Figure 12. Lossless Inductor Sensing

RT8168B

34 DS8168B-00 November 2011www.richtek.com

Considering the inducta nce tolerance, the resistor RX ha s

to be tuned on board by exa mining the tra nsient voltage.

If the output voltage tra nsient has an initi al dip below the

minimum loa d line requirement with a slow recovery, RX

is too small. V ice versa, if the resistance is too large the

output voltage transient will only have a small initial dip

a nd the recovery will be too fast, causing a ring-ba ck.

Using current-sense resistor in series with the inductor

can have better accuracy , but the efficiency is a trade-off.

Considering the equivalent inductance (LESL) of the current

sense resistor , a RC filter is recommended. The RC filter

calculation method is similar to the above-mentioned

inductor DCR sensing method.

Operation Mode Transition

The RT8168B supports operation mode transition function

in CORE/GFX VR for the SetPS command of Intel's VR12/

IMVP7 CPU. The default operation mode of the RT8168B's

CORE/GFX VR is PS0, which is CCM operation. The other

operation mode is PS2 (DEM operation).

After receiving SetPS comma nd, the CORE/GFX VR will

immediately change to the new operation state. When

VR receives SetPS command of PS2 operation mode,

the V R operates as a DEM controller.

If VR receives dynamic VID cha nge command (SetVID),

VR will automatically enter PS0 operation mode. After

output voltage reaches target voltage, VR will stay at PS0

state and ignore former SetPS command. Only by

re-sending SetPS command after SetVID comma nd will

VR be forced into PS2 operation state again.

Thermal Monitoring and Temperature Reporting

CORE/GFX VR provides thermal monitoring function via

sensing TSEN pin voltage. Through the voltage divider

resistors R1, R2, R3 and RNTC, the voltage of TSEN will

be proportional to VR temperature. When VR temperature

rises, the TSENx voltage also rises. The ADC circuit of

VR monitors the voltage variation at TSENx pin from 1.47V

to 1.89V with 55mV resolution, and this voltage is decoded

into digital format and stored into the Temperature Zone

Figure 13. Thermal Monitoring Circuit

To meet Intel's VR12/IMVP7 specification, platform users

have to set the TSEN voltage to meet the temperature

variation of VR from 75% to 100% VR max temperature.

For exa mple, if the VR max temperature is 100°C, platform

users have to set the TSEN voltage to be 1.4875V when

VR temperature reaches 75°C and 1.8725V when VR

temperature reaches 100°C. Detailed voltage setting

versus temperature variation is shown in Table 2.

Thermometer code is implemented in the Temperature

Zone register.

TSENx

VCC

RNTC

Table 2. Temperature Zone Register

VRHOT SVID

Thermal

Alert

C om par at or Tr ip P oin ts

Temper atures Scaled to maximum =

100%

Vol tage Represents Assert bit

Minimu m L ev el

b7 b6 b5 b4 b3 b2 b1 b0

100% 97% 94% 91% 88% 85% 82% 75%

1.855V 1.8V 1.745

V 1.69

V 1.635

V 1.58

V 1.52

5V 1.47

TS E N Pin Volt age Tem peratur e_Z one

1.855 ≤ VTSEN 1111_1111

1.800 ≤ VTSEN ≤ 1.835 0 1 1 1_11 1 1

1.745 ≤ VTSEN ≤ 1.780 0011_1 1 11

1.690 ≤ VTSEN ≤ 1.725 0001_ 1 1 1 1

1.635 ≤ VTSEN ≤ 1.670 0000_ 1 1 1 1

1.580 ≤ VTSEN ≤ 1.615 00 00_011 1

1.525 ≤ VTSEN ≤ 1.560 0000_ 001 1

1.470 ≤ VTSEN ≤ 1.505 00 00_000 1

VTSEN < 1.470 0000_0000

RT8168B

DS8168B-00 November 2011 www.richtek.com

Figure 15. OCP Setting with Temperature Compensation

OCSETx

VCC

ROC1b

ROC2

ROC1a NTC

Usually, ROC1a is selected to be equal to the thermistor's

nominal resista nce at room temperature. Ideally, VOCSET

is assumed to have the same temperature coefficient as

RSENSE (Inductor DCR) :

OCSET, HOT SENSE, HOT

OCSET, COLD SENSE, COLD

= (19)

(18)

OC1 OC2 OCSET

RR 1

⎛⎞

=× −

⎜⎟

⎝⎠

Figure 14. OCP Setting without Temperature

Compensation

VCC

OCSETx

ROC1

ROC2

The current limit is triggered when inductor current

exceeds the current limit threshold ILIMIT, defined by

VOCSET. The driver will be f orced to turn off UGATE until

the over current condition is cleared. If the over current

condition remains valid for 15 PWM cycles, VR will trigger

OCP latch. Latched OCP forces both UGA TE and LGA TE

to go low. When OCP is triggered in one of VRs, the

other VR will enter into soft shutdown sequence. The OCP

latch mechanism will be masked when VRx_READY =

low , which mea ns that only the current li mit will be a ctive

when VOUT is ramping up to initial voltage (or V REFx).

If inductor DCR is used as the current sense component,

then temperature compensation is recommended for

protection under all conditions. Figure 15 shows a typical

OCP setting with temperature compensation.

Over Current Protection

The CORE/GFX VR compares a programmable current

limit set point to the voltage from the current sense amplifier

output for Over Current Protection (OCP). The voltage

applied to OCSETx pin defines the desired peak current

limit threshold ILIMIT :

VOCSET = 48 x ILIMIT x RSENSE (17)

Connect a resistive voltage divider from VCC to GND, with

the joint of the resistive divider connected to OCSET pin

a s shown in Figure 14. For a given ROC2, then

The RT8168B supports two temperature reporting,

VRHOT(hardware reporting) and ALERT(software

reporting), to fulfill VR12/IMVP7 specification. VRHOT is

an open-drain structure which sends out active-low VRHOT

signals. When TSEN voltage rises above 1.855V (100%

of VR temperature), the VRHOT signal will be set to low.

When TSEN voltage drops below 1.8V (97% of VR

temperature), the VRHOT signal will be reset to high. When

TSEN voltage rises above 1.8V (97% of VR temperature),

The RT8168B will update the bit1 data from 0 to 1 in the

Status_1 register and assert ALERT. When TSEN voltage

drops below 1.745V (94% of VR temperature), VR will

update the bit1 data from 1 to 0 in the Status_1 register

and a ssert ALERT.

The temperature reporting function for the GFX VR can be

disabled by pulling TSENA pin to VCC in case the

temperature reporting function for the GFX VR is not used

or the GFX VR is disabled. When the GFX VR's

temperature reporting function is disabled, the RT8168B

will reject the SVID command of getting the

Temperature_Zone register content of the GFX VR.

However , note that the temperature reporting function for

the CORE V R is always active. CORE VR's temperature

reporting function can not be disabled by pulling TSEN

pin to VCC.

RT8168B

36 DS8168B-00 November 2011www.richtek.com

According to the basic circuit calculation, VOCSET ca n be

obtained at a ny temperature :

OC2

OCSET, T CC OC1a NTC, T OC1b OC2

R//R R R

=× ++

(20)

Re-write (19) from (20), to get VOCSET at room temperature

OC1a NTC, COLD OC1b OC2 SENSE, HOT

OC1a NTC, HOT OC1b OC2 SENSE, COLD

R//R R R R

++=

++ (21)

(22)

OCSET, 25

OC2

CC OC1a NTC, 25 OC1b OC2

V R//R R R

×++

Solving (21) and (22) yields ROC1b and ROC2

(23)

OC2

EQU, HOT EQU, COLD EQU, 25

OCSET, 25

RRR (1)R

V(1 )

α× − + −α ×

×−α

(24)

OC1b

EQU, HOT EQU, COLD

R(1)R2 R R

(1 )

α− × +α× −

−α

where

SENSE, HOT 25 HOT

SENSE, COLD 25 COLD

RDCR [1 0.00393 (T 25)]

R DCR [1 0.00393 (T 25)]

α=

×+ × −

=×+ × −

(25)

REQU, T = ROC1a // RNTC, T (26)

Over Voltage Protection (OVP)

The over voltage protection circuit of CORE/GFX VR

monitors the output voltage via the ISENxN pin. The

supported maximum operating VID of VR (V(MAX)) is stored

in the Vout_Max register. Once VISENxN exceeds “V(MAX)

+ 200mV”, OVP is triggered and latched. VR will try to

turn on low side MOSFETs and turn off high side

MOSFETs to protect CPU. When OVP is triggered by

the one of the VRs, the other VR will enter soft shutdown

sequence. A 10μs delay is used in OVP detection circuit

to prevent false trigger .

(27)

IN OUT

MIN ON

Ripple(MAX)

I−

=×

Negative Voltage Protection (NVP)

During OVP latch state, both CORE/GFX VRs also monitor

ISENxN pin for negative voltage protection. Since the OVP

latch will continuously turn on low side MOSFET of VR,

VR may suffer negative output voltage. Therefore, when

the voltage of ISENxN drops below −0.05V after triggering

OVP, VR will turn of f low side MOSFETs while high side

MOSFETs remain off. The N VP function will be active only

after OVP is triggered.

Under Voltage Protection (UVP)

Both CORE/GFX VR implement Under V oltage Protection

(UVP). If ISENxN is less than VREFx by 300mV + VOFFSET,

VR will trigger UVP latch. The UVP latch will turn off both

high side and low side MOSFET s. When UVP is triggered

by one of the VRs, the other VR will enter into soft

shutdown sequence. The UVP mechanism is masked

when V Rx_READY = low.

Under Voltage Lock Out (UVLO)

During normal operation, if the voltage at the VCC pin

drops below UVLO falling edge threshold, both VR will

trigger UVLO. The UVLO protection forces all high side

MOSFETs and low side MOSFETs off to turn off.

Inductor Selection

The switching frequency and ripple current determine the

inductor value a s f ollows :

where tON is the UGA TE turn on period.

Higher inducta nce induces less ripple current a nd hence

higher efficiency. However, the tradeoff is a slower transient

response of the power stage to load transients. This might

increa se the need for more output ca pacitors, thus driving

up the cost. Find a low-loss inductor having the lowest

possible DC resistance that fits in the allotted dimensions.

The core must be large enough not to be saturated at the

pea k inductor current.

RT8168B

DS8168B-00 November 2011 www.richtek.com

Output Capacitor Selection

Output capacitors are used to obtain high bandwidth for

the output voltage beyond the bandwidth of the converter

itself. Usually, the CPU manufacturer recommends a

capacitor configuration. Two different kinds of output

capacitors can be found, bulk capa citors closely located

to the inductors and ceramic output capacitors in close

proximity to the load. Latter ones are for mid-frequency

decoupling with very small ESR and ESL values while the

bulk ca p acitors have to provide enough stored energy to

overcome the low-frequency bandwidth ga p between the

regulator and the CPU.

Layout Consideration

Careful PC board layout is critical to achieving low

switching losses and clean, stable operation. The

switching power stage requires particular attention. If

possible, mount all of the power components on the top

side of the board with their ground terminals flushed

against one another . Follow these guidelines for optimum

PC board layout :

`Keep the high current paths short, especially at the

ground terminals.

`Keep the power traces and load connections short. This

is essenti al for high efficiency.

`When trade-offs in trace lengths must be made, it's

preferable to allow the inductor charging path to be made

longer than the discharging path.

`Place the current sense component close to the

controller. ISENxP and ISENxN connections for current

limit a nd voltage positioning must be made using Kelvin

sense connections to guarantee the current sense

a ccuracy . The PCB tra ce from the sense nodes should

be parallel to the controller .

`Route high-speed switching nodes away from sensitive

analog areas (COMPx, FBx, ISENxP, ISENxN, etc...)

`Special attention should be paid in placing the DCR

current sensing components. The DCR current sensing

capacitor and resistors must be placed close to the

controller.

`The capacitor connected to the ISEN1N/ISENAN for noise

decoupling is optional a nd it should also be placed close

to the ISEN1N/ISENAN pin.

`The NTC thermistor should be placed physically close

to the inductor for better DCR thermal compensation.

RT8168B

38 DS8168B-00 November 2011www.richtek.com

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit

design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be

guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

Richtek Technology Corporation

Headquarter

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789 Fax: (8863)5526611

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Taipei Office (Marketing)

5F, No. 95, Minchiuan Road, Hsintien City

Taipei County, Taiwan, R.O.C.

Tel: (8862)86672399 Fax: (8862)86672377

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Outline Dimension

Dimensions In Millimete rs Dimensions In Inches

Symbol Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.150 0.250 0.006 0.010

D 4.950 5.050 0.195 0.199

D2 3.250 3.500 0.128 0.138

E 4.950 5.050 0.195 0.199

E2 3.250 3.500 0.128 0.138

e 0.400 0.016

L 0.350 0.450

0.014 0.018

W-Type 40L QFN 5x5 Package

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

DETAIL A

Pin #1 ID a nd T ie Bar Mark Option s

A1 A3

SEE DETAIL A