Programmable Delay Units ; . ECL Interfaced series: PDU-108H 3 BIT Features: @ Low propagation delay Mi Digitally programmable in 8 delay steps. M@ Delay increments of la ns thru 50 ns. [0 MAX. M@ Fits standard 16 pins DIP socket. M@ Output ECL interfaced. x Specifications: Max y # Logic 1 input voltage: .980 V. TY i rT 160 030 @ Logic 1 input current: 10 ma. t t FE TYP. ! w Logic 0 input voltage: 1.65 V. 10-4 ' off oreve w Logic 0 input current: 20 ma. @ Logic 1 output voltage: - .96 V. m= Logic 0 output voltage: 1.65 V. = Operating temperature: 0 to 70C. yo Do t Spo : # Storage temperature: - 55 to + 125. q 12 tf 6 FB F t = Power dissipation: 290 mw typ. (no load). on +~ 4 p- 300 410 MAX = Temperature coefficient: 100 PPM/C. ie 38 0 8 1 | m Delay variation: Monotonic in one direction. | = = Total delay tolerance: + 5% or 1 ns whichever is greater. to a0 | = Inherent delay (Too): 2.8 ns typ. + or case stand-offs ms Propagation delay: Address to output (Tsua): = 3.6 ns typ. : r ADORESS Enable to output (Tsue): = 1.7 ns typ. : ' yg: 9 7] 107.9 Test Conditions: ---t-4xebt 8 1 @ Input pulse-width: Yee 9 | 150% of total delay. Wo 8 NETWonK p18 our = Input pulse rise-time: =6 ns. gr o_1.18! Le . I Input pulse voltage: - 1.5 V. e @ Vee supply voltage: - 5 V. Lee ee ee je @ Vee supply current: 56 ma typ. AL > 302 = Operating temperature: 25C. (me clade anion TRUTH TABLE Enable | Address (Bit No.) Delay Min. Delay Total Detay* (Es) 3. 2 | Out Part No."* | increment (ns) | Change (ns) 0 0 0 0 T 1 = High 0 0 0 1 Tt 0 = Low PDU-108H-.5 S23 $5 0 0 1 0 To 6 = Dont care PDU-108H-1 1 + 4 1, = Reframe o ume | Pee | 0 0 1 1 T -108H- + 0 1 S 0 n inherent delay PDU-108H-5 5 + 6 35 0 1 T, to T, = Muttipiler of PDU-108H-10 19 +1 70 0 1 1 0 Ts incremental delay. PDU-108H-20 20 +45 140 0 1 1 1 T; PDU-108H-40 40 =2 280 1 9 9 9 0 PDU-108H-50 50 + 25 350 *This delay value does not inctude the T. delay. **Other delay increments available on request. 3 Mt. Prospect Avenue, Clifton. New Jersey 07013 m@ (201) 773-2299 m FAX (201) 773-9672 48