1
Motorola TMOS Power MOSFET Transistor Device Data
!
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS power FET is designed to withstand high
energy in the avalanche and commutation modes. This new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications such as power supplies, PWM motor controls and
other inductive loads, the avalanche energy capability specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.
•Avalanche Energy Specified at Elevated Temperature
•Low Stored Gate Charge for Efficient Switching
•Internal Source–to–Drain Diode Designed to Replace External Zener
Transient Suppressor – Absorbs High Energy in the Avalanche Mode
•Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
•Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
•Available in Insertion Mount, Add –1 or 1 to Part Number
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain–to–Source V oltage VDSS 100 Vdc
Drain–to–Gate V oltage (RGS = 1.0 MΩ) VDGR 100 Vdc
Gate–to–Source Voltage — Continuous
Gate–to–Source V oltage — Single Pulse (tp ≤ 50 µS) VGS
VGSM ±20
±25 Vdc
Vdc
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µS)
ID
ID
IDM
14
10
49
Adc
Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C when mounted with the minimum recommended pad size
PD72
0.58
1.75
Watts
W/°C
Watts
Operating and Storage Temperature Range TJ, Tstg –55 to 150 °C
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (TJ < 150°C)
Single Pulse Drain–to–Source Avalanche Energy — STARTING TJ = 25°C
(VDD = 75 Vdc, VGS = 10 Vdc, PEAK IL = 14 Apk, L = 1.0 mH, RG = 25 Ω)EAS 98 mJ
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
RθJC
RθJA
RθJA
1.73
100
71.4
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL260 °C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
SEMICONDUCTOR TECHNICAL DATA Order this document
by MTD14N10E/D
Motorola, Inc. 1997
TMOS POWER FET
14 AMPERES
100 VOLTS
RDS(on) = 0.11
W
Motorola Preferred Device
D
S
G
CASE 369A–13, Style 2
DPAK
MTD14N10E
2 Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage Cpk ≥ 1.5(3)
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS 100
——
112 —
—
Vdc
V/°C
Zero Gate Voltage Drain Current
(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS —
——
—10
100
µAdc
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS — — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage Cpk ≥ 2.0(3)
(VDS = VGS, ID = 0.25 mAdc)
Threshold Temperature Coefficient (Negative)
VGS(th) 2.0
—2.9
6.2 4.0
—
Vdc
mV/°C
Static Drain–to–Source On–Resistance Cpk ≥ 2.0(3)
(VGS = 10 Vdc, ID = 8.0 Adc) RDS(on) —0.098 0.11 Ohms
Drain–to–Source On–V oltage
(VGS = 10 Vdc, ID = 14 Adc)
(VGS = 10 Vdc, ID = 8.0 Adc, TJ = 125°C)
VDS(on) —
——
—1.85
1.62
Vdc
Forward T ransconductance (VDS = 15 Vdc, ID = 8.0 Adc) gFS 4.0 7.4 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(V 25 Vdc V 0 Vdc
Ciss —700 980 pF
Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz
)
Coss —200 280
T ransfer Capacitance
f
=
1
.
0
MHz)
Crss —65 130
SWITCHING CHARACTERISTICS (2)
T urn–On Delay Time
(V 50 Vd I 14 Ad
td(on) —9.0 20 ns
Rise T ime (VDS = 50 Vdc, ID = 14 Adc,
VGS =10Vdc
tr— 58 120
T urn–Off Delay Time
V
GS =
10
Vd
c,
RG = 9.1 Ω)td(off) —26 50
Fall T ime
G)
tf— 33 70
Gate Charge
(V 80 Vd I 14 Ad
QT— 26 40 nC
(VDS = 80 Vdc, ID = 14 Adc, Q1— 5.0 —
(DS ,D,
VGS = 10 Vdc) Q2—13 —
Q3—11 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (IS = 14 Adc, VGS = 0 Vdc)
(IS = 14 Adc, VGS = 0 Vdc, TJ = 125°C)
VSD —
—0.92
0.80 1.2
—
Vdc
Reverse Recovery Time
(I 14 Ad
trr — 103 — nS
(IS = 14 Adc, ta— 78 —
(S,
dIS/dt = 100 A/µs) tb— 25 —
Reverse Recovery Stored Charge QRR —0.46 — µC
(1) Pulse Test: Pulse Width ≤300 µS, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values. Cpk
+Ť
Max limit – Typ
3
sigma
Ť
MTD14N10E
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
RDS(on), DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
RDS(on), DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on), DRAIN–TO–SOURCE RESISTANCE (OHMS)
0246810
0
15
25
30
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0 5 10 20
0.00
0.02
0.06
0.10
0.14
0 5 20 30
0.06
0.08
0.10
0.12
0.14
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
–50
0
0.4
1.2
2.0
20 40 60 80 90 100
1
10
100
1000
TJ, JUNCTION TEMPERATURE (
°
C)
Figure 5. On–Resistance Variation with
Temperature
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
IDSS, LEAKAGE (nA)
–25 0 25 50 75 100 125 150
TJ = 25
°
CVDS
≥
10 V TJ = –55
°
C
25
°
C100
°
C
TJ = 100
°
C
25
°
C
–55
°
C
TJ = 25
°
C
VGS = 10 V
10
20
13579
5
9 V
5 V
6 V
7 V
8 V
VGS = 10 V
0
15
25
30
10
20
5
23456789
0.12
0.08
0.04
15 25 30
0.13
0.11
0.09
0.07
10 15 25
0.8
1.6
30 50 70
VGS = 10 V
15 V
VGS = 10 V
ID = 8 A
0.2
0.6
1.4
1.0
1.8
100
VGS = 0 V TJ = 125
°
C
100
°
C
0.16
0.18
0.20
2.5 3.5 4.5 5.5 6.5 7.5 8.5
2.5 7.5 12.5 22.517.5 27.5 2.5 7.5 22.512.5 17.5 27.5
110
MTD14N10E
4 Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
10 0 10152025
GATE–TO–SOURCE OR DRAIN–T O–SOURCE VOLT AGE (VOLTS)
C, CAPACITANCE (pF)
Figure 7. Capacitance Variation
1400
1000
600
200
0
VGS VDS
TJ = 25
°
C
VDS = 0 V VGS = 0 V
1200
800
400
55
C
iss
Coss
Ciss
Crss
Crss
1600
1800
2000
2200
MTD14N10E
5
Motorola TMOS Power MOSFET Transistor Device Data
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
0.6 0.7 0.8 0.9
0
4
10
12
VSD, SOURCE–TO–DRAIN VOLT AGE (VOLTS)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
IS, SOURCE CURRENT (AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE (OHMS)
1 10 100
1000
10
t, TIME (ns)
tr
tf
td(off)
td(on)
VGS = 0 V
TJ = 25
°
C
Figure 10. Diode Forward Voltage versus Current
80
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
72
64
56
48
40
32
0
9
7
4
0
QG, TOTAL GA TE CHARGE (nC)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOL TS)
10
8
2
5101520
T
J
= 25
°
C
ID = 14 A
VDS
VGS
25 0
Q1 Q2
QT
Q3
100
2
6
0.65 0.75 0.85 0.95
TJ = 25
°
C
ID = 14 A
VDD = 50 V
VGS = 10 V
6
5
3
1
24
16
81
8
14
2.5 7.5 12.5 17.5 22.5 27.5
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power aver-
aged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
MTD14N10E
6 Motorola TMOS Power MOSFET Transistor Device Data
SAFE OPERATING AREA
TJ, STAR TING JUNCTION TEMPERATURE (
°
C)
E
AS, SINGLE PULSE DRAIN–T O–SOURCE
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
0.1 1.0 100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
0.1
10
AV ALANCHE ENERGY (mJ)
ID, DRAIN CURRENT (AMPS)
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT 0
25 50 75 100 125
40
20
ID = 14 A
100
1.0
10 150
t, TIME (s)
Figure 13. Thermal Response
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESIST ANCE
R
θ
JC(t) = r(t) R
θ
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) R
θ
JC(t)
P(pk)
t1t2
DUTY CYCLE, D = t1/t2
Figure 14. Diode Reverse Recovery Waveform
di/dt
trr
ta
tp
IS
0.25 IS
TIME
IS
tb
VGS = 20 V
SINGLE PULSE
TC = 25
°
C
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
D = 0.5
90
80
60
100
0.1
1.0
0.01
100
µ
s
1ms
10 ms dc
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00
1000
10
µ
s
30
10
70
50
110
MTD14N10E
7
Motorola TMOS Power MOSFET Transistor Device Data
PACKAGE DIMENSIONS
CASE 369A–13
ISSUE Y
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
D
A
K
B
R
V
S
FL
G
2 PL
M
0.13 (0.005) T
E
C
U
J
H
–T–
SEATING
PLANE
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.235 0.250 5.97 6.35
B0.250 0.265 6.35 6.73
C0.086 0.094 2.19 2.38
D0.027 0.035 0.69 0.88
E0.033 0.040 0.84 1.01
F0.037 0.047 0.94 1.19
G0.180 BSC 4.58 BSC
H0.034 0.040 0.87 1.01
J0.018 0.023 0.46 0.58
K0.102 0.114 2.60 2.89
L0.090 BSC 2.29 BSC
R0.175 0.215 4.45 5.46
S0.020 0.050 0.51 1.27
U0.020 ––– 0.51 –––
V0.030 0.050 0.77 1.27
Z0.138 ––– 3.51 –––
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
123
4
MTD14N10E
8 Motorola TMOS Power MOSFET Transistor Device Data
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Af firmative Action Employer.
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MTD14N10E/D
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