1
Synchronous Step-Down MOSFET Drivers
ZL1505
The ZL1505 is an integrated high-speed, high-current
N-channel MOSFET driver for synchronous step-down DC/DC
conversion applications. When used with Zilker Labs Digital-
DC™ PWM controllers, the ZL1505 enables dynamically
adaptive dead-time control that optimizes efficiency under all
operating conditions. A dual input PWM configuration enables
this efficiency optimization while minimizing complexity within
the driver.
Operating from a 4.5V to 7.5V input, the ZL1505 combines a
5A, 0.5W low-side driver and a 3A, 0.8W high-side driver to
support high step-down buck applications. A unique adjustable
gate drive current scheme allows the user to adjust the drive
current on both drivers to optimize performance for a wide
rage of input/output voltages, load currents, power MOSFETs
and switching frequencies up to 1.4MHz. An integrated 30V
bootstrap Schottky diode is used to charge the external
bootstrap capacitor. An internal watchdog circuit prevents
excessive shoot-through currents and protects the external
MOSFET switches.
The ZL1505 is specified over a wide -40°C to +125°C junction
temperature range and is available in an exposed pad DFN-10
package.
Features
• High-speed, high-current drivers for synchronous N-channel
MOSFETs
• Adaptive dead-time control optimizes efficiency when used
with Digital-DC controllers
• Integrated 30V bootstrap Schottky diode
• Capable of driving 40A per phase
• Supports switching frequency up to 1.4MHz
- >4A source, >5A sink low-side driver
- >3A source/sink high-side driver
- <10ns rise/fall times, low propagation delay
• Adjustable gate drive strength optimizes efficiency for
different VIN, VOUT, IOUT, FSW and MOSFET combinations
• Internal non-overlap watchdog prevents shoot-through
currents
Applications*(see page 12)
• High efficiency, high-current DC/DC buck converters with
digital control and PMBus™
• Multi-phase digital DC/DC converters with phase
adding/dropping
•Power train modules
• Synchronous rectification for secondary side isolated power
converters
Related Literature*(see page 12)
•ZL2004 Adaptive Digital DC/DC Controller with Current
Sharing
FIGURE 1. ZL1505 BLOCK DIAGRAM
VDD BST
GH
SW
ZL1505
GL
LEVEL
SHIFT
SHOOT-
THROUGH
PROTECTION
PWMH
PWML
GND
VDD
LSEL
HSEL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2009-2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
February 25, 2011
FN6845.3
ZL1505
2FN6845.3
February 25, 2011
Typical Application Circuit
The following application circuit represents the typical implementation of the ZL1505 (Notes 1, 2).
NOTES:
1. For VDD of 4.5V to 7.5V, the maximum VIN of the ZL1505 is 22.5V to 25.5V. ZL1505 input supply voltage range (VIN) is specified in Figure 2.
2. VIN for this application circuit is limited by the ZL2004 VIN of 4.5V to 14V.
FIGURE 2. POWER TRAIN MODULE USING ZL2004 PWM CONTROLLER
VOUT
VIN
4.5-14V
VBIAS
4.5-7.5V
ZL2004
GND
GND
PWML
PWMH
PWML
PWMH
CS-CS+
TEMP-
TEMP+
ISENB
ISENA
VSEN+
VSEN-
XTEMP
SGND
VIN
PWMH
PWML
VDD
BST
GND
GH
GL
SW
ZL1505
VINVDD
Power Train
Module
HSEL
LSEL
VMON
ZL1505
3FN6845.3
February 25, 2011
Pin Configuration
ZL1505
(10 LD DFN)
TOP VIEW
2
3
4
1
5
9
8
7
10
6
HSEL
GH
SW
PWMH
PWML
BST
VDD
GL
GND
LSEL
*CONNECT TO GND
EPAD*
Pin Descriptions
PIN NUMBER PIN NAME TYPE (Note 3) DESCRIPTION
1 HSEL I High-side gate drive current selector. Connect to BST for maximum gate drive current;
connect to SW for 50% of maximum gate drive current.
2 GH O Output of high-side gate driver. Connect to the gate of high-side FET.
3 SW I/O Phase node. Return path for high-side driver. Connect to source of high-side FET and drain
of low-side FET.
4 PWMH I High-side PWM control input.
5 PWML I Low-side PWM control input.
6 LSEL I Low-side gate drive current selector. Connect to VDD for maximum gate drive current;
connect to GND for 50% of maximum gate drive current.
7 GND PWR Ground. All signals return to this pin.
8 GL O Output of low-side gate driver. Connect to the gate of low-side FET.
9 VDD PWR Gate drive bias supply. Connect a high-quality bypass capacitor from this pin to GND.
10 BST PWR Bootstrap supply. Connect external capacitor to SW node.
EPAD GND PWR Ground.
NOTE:
3. I = Input, O = Output, PWR = Power OR Ground.
Ordering Information
PART NUMBER
(Notes 4, 7)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
Tape and Reel
(Pb-free)
PKG.
DWG. #
ZL1505ALNNT (Note 5) 1505 -40 to +125 10 Ld 3x3 DFN L10.3x3D
ZL1505ALNNT1 (Note 5) 1505 -40 to +125 10 Ld 3x3 DFN L10.3x3D
ZL1505ALNNT6 (Note 5) 1505 -40 to +125 10 Ld 3x3 DFN L10.3x3D
ZL1505ALNFT (Note 6) 1505 -40 to +125 10 Ld 3x3 DFN L10.3x3D
ZL1505ALNFT1 (Note 6) 1505 -40 to +125 10 Ld 3x3 DFN L10.3x3D
ZL1505ALNFT6 (Note 6) 1505 -40 to +125 10 Ld 3x3 DFN L10.3x3D
NOTES:
4. Please refer to Tech Brief TB347 for details on reel specifications.
5. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
6. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
7. For Moisture Sensitivity Level (MSL), please see device information page for ZL1505. For more information on MSL please see Tech Brief TB363.
ZL1505
4FN6845.3
February 25, 2011
Absolute Maximum Ratings Thermal Information
Voltage Measured with Respect to GND
DC Supply Voltage for VDD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 8V
High-Side Supply Voltage for BST Pin. . . . . . . . . . . . . . . . . . . . . -0.3V to 30V
High-Side Drive Voltage for
GH Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VSW - 0.3V) to (VBST + 0.3V)
Low-Side Drive Voltage for
GL Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (VDD + 0.3V)
Boost to Switch Differential (VBST - VSW) for
BST, SW Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 8V
Switch Voltage for SW Pin
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to 30V
<100ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 5V) to 30V
Logic I/O Voltage for PWMH, PWML, LSEL Pins . . . . . . . . . . . . . -0.3V to 6V
HSEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VSW - 0.3V) to (VBST + 0.3V)
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
GL Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
Latch Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tested to JESD78
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)
10 Ld DFN (Notes 8, 9) . . . . . . . . . . . . . . . . 50 7
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Gate Drive Bias Supply Voltage Range
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 7.5V
Input Supply Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . 3V to 30V - VDD
Operating Junction Temperature Range, TJ . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
8. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
9. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications VDD = 6.5V, TJ = -40°C to +125°C unless otherwise noted. Typical values are at TA= +25°C. Boldface limits
apply over the operating temperature range, -40°C to +125°C.
PARAMETER CONDITIONS
MIN
(Note 10) TYP
MAX
(Note 10) UNIT
BIAS CURRENT CHARACTERISTICS
IDD supply current Not switching – 110 180 µA
PWM INPUT CHARACTERISTICS
PWM Input Bias Current VPWM = 5 V – 5 – µA
VPWM = 0 V – – 1 µA
PWM Input Logic Low, VIL PWMH or PWML VDD = 6.5V – – 1.7 V
VDD = 5.0V – – 1.4 V
PWM Input Logic High, VIH PWMH or PWML VDD = 6.5V 3.4 –– V
VDD = 5.0V 2.7 –– V
Hysteresis PWMH or PWML VDD = 6.5V - 1.1 - V
VDD = 5.0V - 0.8 - V
Minimum PWMH On-time to Produce GH Pulse,
tPWMH,ON (Note 11)
CGH = 0 – 12 - ns
Minimum GH On-time Pulse, tGH,ON (Note 12) CGH = 0 – 14 - ns
CGH = 3 nF, VHSEL = VBST -20- ns
Minimum PWMH Off-time to Produce Valid GH
Pulse, tPWMH,OFF
CGH = 0 – 17 - ns
BOOTSTRAP DIODE CHARACTERISTICS
Forward Voltage (VF) Forward bias current 100 mA – 0.8 – V
ZL1505
5FN6845.3
February 25, 2011
THERMAL PROTECTION
Thermal Trip Point – 150 – °C
Thermal Reset Point –134– °C
UPPER GATE DRIVER CHARACTERISTICS
Driver Voltage (VBST – VSW)–6– V
High-side Driver Peak Gate Drive Current (Pull-up) (VGH – VSW) = 2.5V HSEL connected to
BST
2.0 3.2 – A
HSEL connected to
SW
1.0 1.7 - A
High-side Driver Peak Gate Drive Current
(Pull-down)
(VGH – VSW) = 2.5V HSEL connected to
BST
2.0 3.2 – A
HSEL connected to
SW
1.0 1.6 - A
High-side Driver Pull-up Resistance (VBST – VGH) = 50mV HSEL connected to
BST
–0.70.9 Ω
HSEL connected to
SW
-0.91.2 Ω
High-side Driver Pull-down Resistance (VGH – VSW) = 50mV HSEL connected to
BST
–0.81.1 Ω
HSEL connected to
SW
–1.11.5 Ω
LOWER GATE DRIVER CHARACTERISTICS
Driver voltage (VDD)-6.5- V
Low-side Driver Peak Gate Drive Current (Pull-
up)
(VGL - VGNG) = 2.5V LSEL connected to
VDD
3.0 4.5 – A
LSEL connected to
GND
1.5 2.4 - A
Low-side Driver Peak Gate Drive Current (Pull-
down)
(VGL – VGND) = 2.5V LSEL connected to
VDD
3.5 5.4 – A
LSEL connected to
GND
1.8 2.8 - A
Low-side Driver Pull-up Resistance (VDD - VGL) = 50mV LSEL connected to
VDD
–0.70.9 Ω
LSEL connected to
GND
-1.01.3 Ω
Low-side Driver Pull-down Resistance (VGL – GND) = 50mV LSEL connected to
VDD
–0.50.7 Ω
LSEL connected to
GND
-0.71.0 Ω
SWITCHING CHARACTERISTICS
GH rise time, tRH CGH = 3nF HSEL connected to
BST
–5.38.5 ns
HSEL connected to
SW
- 10.5 16.5 ns
Electrical Specifications VDD = 6.5V, TJ = -40°C to +125°C unless otherwise noted. Typical values are at TA= +25°C. Boldface limits
apply over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER CONDITIONS
MIN
(Note 10) TYP
MAX
(Note 10) UNIT
ZL1505
6FN6845.3
February 25, 2011
GH fall time, tFH CGH = 3nF HSEL connected to
BST
-4.87.5 ns
HSEL connected to
SW
-9.515 ns
GL rise time, tRL CGL = 3nF LSEL connected to
VDD
–4.06.0 ns
LSEL connected to
GND
-7.812 ns
GL fall time, tFL CGL = 3nF LSEL connected to
VDD
-3.04.5 ns
LSEL connected to
GND
-5.58.5 ns
GH turn-on propagation delay, tDHR HSEL connected to BST – 30.0 – ns
HSEL connected to SW - 31.5 - ns
GH turn-off propagation delay, tDHF HSEL connected to BST – 37.5 – ns
HSEL connected to SW - 39.0 - ns
GL turn-on propagation delay, tDLR LSEL connected to VDD – 26.5 – ns
LSEL connected to GND - 28.0 - ns
GL turn-off propagation delay, tDLF LSEL connected to VDD – 30.0 – ns
LSEL connected to GND - 31.5 - ns
NOTES:
10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
11. The minimum PWMH on-time pulse (tPWMH,ON) is specified from VPWM = 2.5V on the rise edge to VPWM = 2.5V on the falling edge.
12. The minimum GH on-time pulse (tGH,ON) is specified at VGH = 2.5V.
Electrical Specifications VDD = 6.5V, TJ = -40°C to +125°C unless otherwise noted. Typical values are at TA= +25°C. Boldface limits
apply over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER CONDITIONS
MIN
(Note 10) TYP
MAX
(Note 10) UNIT
FIGURE 3. TIMING DIAGRAM
tPWMH,ON
10%
2.5V 2.5V
PWM
GH
90% 90%
10%
tRH tFH
tDLR
tDLF
2.5V 2.5V
tGH,ON
ZL1505
7FN6845.3
February 25, 2011
Typical Performance Curves Performance curves with temperature are measured at ambient temperatures (TA) of
+85°C, +25°C, and -25°C.
FIGURE 4. IVDD vs VDD WITH TEMPERATURE (NO SWITCHING) FIGURE 5. THERMAL PROTECTION THRESHOLDS
FIGURE 6. MINIMUM GH ON-TIME, tGH,ON (TA = +25°C) FIGURE 7. tGH,ON WITH TEMPERATURE (CGH = 0) (see Figure 3
for tGH,ON timing)
FIGURE 8. MINIMUM PWMH ON-TIME, tPWMH,ON (CGH = 0) FIGURE 9. MINIMUM PWMH OFF-TIME, tPWMH,OFF (CGH = 0)
130
100
110
120
80
90
70
4.5 5.5 6.5 7.5
VDD (V)
IVDD (µA)
5.0 6.0 7.0
+25°C
+85°C
-25°C
155
140
145
150
125
135
120
4.5 7.5
VDD (V)
T (C)
130
7.06.56.05.55.0
TRISING
TFALLING
22
16
18
20
10
14
8
4.5 7.5
VDD (V)
ON-TIME (ns)
12
7.06.56.05.55.0
CGH = 3nF, HSEL = SW
CGH = 3nF, HSEL = BST
CGH = 0
ON-TIME (ns)
VDD (V)
4.5 7.57.06.56.05.55.0
16
13
14
15
10
12
8
11
9
+25°C
+85°C
-25°C
16
10
12
14
4
8
2
6
ON-TIME (ns)
VDD (V)
4.5 7.57.06.56.05.55.0
+25°C
-25°C
VDD (V)
16
10
12
14
4
8
2
6
+85°C
4.5 7.57.06.56.05.55.0
VDD (V)
30
22
26
14
18
10
OFF-TIME (ns)
-25°C
+25°C
+85°C
ZL1505
8FN6845.3
February 25, 2011
FIGURE 10. LOW-SIDE DRIVER PULL-UP CURRENT
(VGL = 2.5V, TA = +25°C)
FIGURE 11. LS PULL-UP CURRENT WITH TEMPERATURE
(VGL = 2.5V, LSEL = VDD)
FIGURE 12. LOW-SIDE DRIVER PULL-DOWN CURRENT
(VGL = 2.5V, TA = +25°C)
FIGURE 13. LS PULL-DOWN CURRENT WITH TEMPERATURE
(VGL = 2.5V, LSEL = VDD)
FIGURE 14. LOW-SIDE DRIVER RISE TIME, tRL (CGL = 3nF,
TA = +25°C)
FIGURE 15. tRL WITH TEMPERATURE (CGL = 3nF, LSEL = VDD)
Typical Performance Curves Performance curves with temperature are measured at ambient temperatures (TA) of
+85°C, +25°C, and -25°C. (Continued)
IGL (A)
4.5 7.57.06.56.05.55.0
VDD (V)
6.6
3.6
4.6
5.6
0.6
2.6
1.6
LSEL = GND
LSEL = VDD
4.5 7.57.06.56.05.55.0
VDD (V)
IGL (A)
6.6
3.6
4.6
5.6
2.6
1.6
+25°C
-25°C
+85°C
IGL (A)
4.5 7.57.06.56.05.55.0
VDD (V)
8
5
6
7
2
4
3LSEL = GND
1
LSEL = VDD
4.5 7.57.06.56.05.55.0
VDD (V)
IGL (A)
8
5
6
7
4
3
+25°C
-25°C
+85°C
4.5 7.57.06.56.05.55.0
VDD (V)
12
9
10
11
3
8
7
LSEL = GND
LSEL = VDD
6
5
4
tRISE (ns)
tRISE (ns)
4.5 7.57.06.56.05.55.0
VDD (V)
6.5
5.0
5.5
6.0
3.5
4.5
3.0
4.0
+25°C
-25°C
+85°C
ZL1505
9FN6845.3
February 25, 2011
FIGURE 16. LOW-SIDE DRIVER FALL TIME, tFL (CGL = 3nF,
TA = +25°C)
FIGURE 17. tFL WITH TEMPERATURE (CGL = 3nF, LSEL = VDD)
FIGURE 18. HIGH-SIDE DRIVER PULL-UP CURRENT
(VGH - VSW = 2.5V, TA = +25°C)
FIGURE 19. HS PULL-UP CURRENT WITH TEMPERATURE
(VGH - VSW = 2.5V, HSEL = BST)
FIGURE 20. HIGH-SIDE DRIVER PULL-DOWN CURRENT
(VGH - VSW = 2.5V, TA= +25°C)
FIGURE 21. HS PULL-DOWN CURRENT WITH TEMPERATURE
(VGH - VSW = 2.5V, HSEL = BST)
Typical Performance Curves Performance curves with temperature are measured at ambient temperatures (TA) of
+85°C, +25°C, and -25°C. (Continued)
4.5 7.57.06.56.05.55.0
VDD (V)
7
4
5
6
2
3
LSEL = GND
LSEL = VDD
tFALL (ns)
4.5 7.57.06.56.05.55.0
VDD (V)
4.5
3.0
3.5
4.0
2.0
2.5
tFALL (ns)
+25°C
-25°C
+85°C
4.5 7.57.06.56.05.55.0
VDD (V)
5
2
3
4
0
1
HSEL = SW
HSEL = BST
IGH (A)
IGH (A)
VDD (V)
4.5 7.57.06.56.05.55.0
5.0
3.5
4.0
4.5
2.0
3.0
1.0
2.5
1.5
-25°C
+25°C
+85°C
4.5 7.57.06.56.05.55.0
VDD (V)
5
2
3
4
0
1
HSEL = SW
HSEL = BST
IGH (A)
VDD (V)
4.5 7.57.06.56.05.55.0
5.0
3.5
4.0
4.5
2.0
3.0
2.5
1.5
IGH (A)
-25°C
+25°C
+85°C
ZL1505
10 FN6845.3
February 25, 2011
ZL1505 Overview
Theory of Operation
The ZL1505 is a synchronous N-channel MOSFET driver that is
intended for use with Zilker Labs Digital-DC PWM controllers to
enable a high-efficiency DC/DC conversion scheme. The
patented Digital-DC control scheme utilizes a closed-loop
algorithm to optimize the dead-time applied between the gate
drive signals for the high-side and low-side MOSFETs. By
monitoring the duty cycle of the resulting DC/DC converter
circuit, this dynamic routine continuously varies the MOSFET
dead times to optimize conversion efficiency in response to
varying circuit conditions. The ZL1505’s dual PWM input
configuration enables this optimization scheme to be applied
while minimizing the complexity within the driver device. Please
refer to the ZL2004 data sheet for details on the dynamic
dead-time optimization routine.
The ZL1505 integrates two powerful gate drivers that have been
optimized for step-down DC/DC conversion circuit configurations
whose output current can exceed 40A per phase. The ZL1505
also integrates a 30V bootstrap Schottky diode to minimize the
external components and provide a high drive voltage to the
high-side driver device.
Variable Gate Drive Current
The ZL1505 incorporates an innovative variable drive current
scheme that enables the user to optimize the gate drive current
levels to the requirements of the external MOSFETs used over a
wide range of operating frequencies. Each of the gate drivers
incorporates a logic input (HSEL and LSEL) that allows the user to
select the gate drive strength to 50% or 100% of the total rated
drive current.
With the HSEL pin connected to the BST pin, the high-side driver
can deliver the full rated gate drive current; with the HSEL pin
connected to the SW pin, the output current will be limited to
50% of the full rated output capability. With the LSEL pin
connected to VDD, the low-side driver can deliver the full rated
gate drive current; with the LSEL pin connected to GND, the
FIGURE 22. HIGH-SIDE DRIVER RISE TIME, tRH (CGH = 3nF,
TA = +25°C)
FIGURE 23. tRH WITH TEMPERATURE (CGH = 3nF, HSEL = BST)
FIGURE 24. HIGH-SIDE DRIVER FALL TIME, tFH (CGH = 3nF,
TA = +25°C)
FIGURE 25. tFH WITH TEMPERATURE (CGH = 3nF, HSEL = BST)
Typical Performance Curves Performance curves with temperature are measured at ambient temperatures (TA) of
+85°C, +25°C, and -25°C. (Continued)
VDD (V)
4.5 7.57.06.56.05.55.0
17.5
11.5
13.5
15.5
5.5
9.5
7.5
3.5
tRISE (ns)
HSEL = SW
HSEL = BST
4.5 7.57.06.56.05.55.0
VDD (V)
8.5
5.5
6.5
7.5
3.5
4.5
tRISE (ns)
-25°C
+25°C
+85°C
4.5 7.57.06.56.05.55.0
VDD (V)
11.5
5.5
7.5
9.5
3.5
tFALL (ns)
HSEL = SW
HSEL = BST
4.5 7.57.06.56.05.55.0
VDD (V)
7.5
4.5
5.5
6.5
3.5
tFALL (ns)
-25°C
+25°C
+85°C
ZL1505
11 FN6845.3
February 25, 2011
output current will be limited to 50% of the full rated output
capability. Using HSEL and LSEL, the ZL1505 can be used across
a wide range of applications using only a simple PCB layout
change.
Also, the VDD pin is the gate drive bias supply for the external
MOSFETs. VDD can be used to vary the gate drive strength as
shown for the low-side driver in Figures 9 through 12 and for the
high-side driver in Figures 17 through 20.
Overlap Protection Circuit
The ZL1505 includes an internal watchdog circuit that prevents
excessive shoot-through current from occurring in the unlikely
event that the PWM converter places both switches in the ON
position. If the overlap time between the PWMH and PWML
pulses exceeds 30ns, the PWMH signal will be forced to the LOW
state until the overlap condition ceases, allowing normal
switching operation to continue.
Start-up Requirements
During power-up, the ZL1505 maintains both GH and GL outputs
in the LOW state while the VIN voltage is ramping up. Once the
VDD supply is within specification, the GH and GL pins may be
operated using the PWMH and PWML logic inputs respectively.
In the case where the PWM controller is powered from a supply
other than the ZL1505’s VDD supply, and the PWM controller is
powered up first, the PWM controller gate outputs should be kept
in low or in high-impedance state until the VDD supply is within
specification. Additionally, if the ZL1505 begins its power-down
sequence prior to the PWM controller then the PWM controller
gate outputs should be set in low or in high-impedance state
before the VDD voltage supply drops below its specified range.
Thermal Protection
When the junction temperature exceeds +150°C the high-side
driver output GH is forced to logic low state. The driver output is
allowed to switch logic states again once the junction
temperature drops below +134°C.
ZL1505
12
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6845.3
February 25, 2011
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Products
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE REVISION CHANGE
2/15/11 FN6845.3 Added ZL1505ALNFT, ZL1505ALNFT1 and ZL1505ALNFT6 to “Ordering Information” on page 3. Added applicable lead finish
note (note 6).
2/9/11 Pg. 4: under “Absolute Maximum Ratings,” changed maximum voltage from 8V to 6V for the following pins:
From: “Logic I/O Voltage for PWMH, PWML, LSEL Pins . . . -0.3V to 8V”
To: “Logic I/O Voltage for PWMH, PWML, LSEL Pins . . . -0.3V to 6V”
10/19/10 FN6845.2 “PWM Input Logic Low, VIL” on page 4, changed Max spec from 2.2V to 1.7V for “VDD = 6.5V”. Removed Min/Typ specs of 1.7/2
“PWM Input Logic Low, VIL” on page 4, changed Max spec from 1.9V to 1.4V for “VDD = 5.0V”. Removed Min/Typ specs of
1.5/1.7
“PWM Input Logic High, VIH” on page 4, changed Min spec from 2.8V to 3.4V for “VDD = 6.5V”. Removed Typ/Max specs of
3.1/3.4
“PWM Input Logic High, VIH” on page 4, changed Min spec from 2.2V to 2.7V for “VDD = 5.0V”. Removed Typ/Max specs of
2.5/2.7
7/9/10 On page 4, Electrical Specifications Table, the parameter “Minimum GH On-time Pulse, tGH,ON (Note 12)”, removed 14 and 20
from Max column. In TYP column, changed 10 to 14 and 14 to 20.
On page 4, Electrical Specifications Table, the parameter “Minimum PWMH On-time to Produce GH Pulse, tPWMH,ON (Note
11)”, removed 12 from Max column. In TYP column, changed 8.5 to 12.
On page 4, Electrical Specifications Table, the parameter “Minimum PWMH Off-time to Produce Valid GH Pulse, tPWMH,OFF”,
removed 17 from Max column. In TYP column, changed 13 to 17.
Replaced POD drawing with updated revisions and changes were as follows:
Converted to new standards by adding land pattern and moving dimensions from table onto drawing
2/14/09 FN6845.1 Assigned file number FN6845 to datasheet as this will be the first release with an Intersil file number. Replaced header and
footer with Intersil header and footer. Updated disclaimer information to read “Intersil and it’s subsidiaries including Zilker Labs,
Inc.” No changes to datasheet content
12/4/09 FN6845.0 Converted to new Intersil template. Changed in Abs Max Ratings “Low-Side Drive Voltage for GL pin” from “(GND - 0.3) to (VIN +
0.3)” to “(GND - 0.3) to (VDD + 0.3)”. Removed Bullet "Adjustable gate drive voltage: 4.5V to 7.5V" and "Exposed pad 3mmx3mm
DFN-10 Package" from Features. Intersil Standards applied are: Added Related Information, Updated ordering information with
Notes that includes MSL. Updated Abs Max Ratings with notes, added ESD Ratings and Latchup, added Boldface text in
Electrical Spec Table. Added POD
ZL1505
13 FN6845.3
February 25, 2011
Package Outline Drawing
L10.3x3D
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.015mm and 0.30mm from the terminal tip.
Dimension applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
10X 0 . 40
INDEX AREA
C
(10 X 0.60)
(2.80)
( 8X 0 .50 )
( 10X 0.25 )
(1.60)
0 . 05 MAX.
C
0 . 00 MIN.
0 . 2 REF
SEATING PLANE
C
5
0.08
(4X)
( 2.30 )
3.00
0.15 BC0.10 M A
1.00 MAX
2.30
10
SEE DETAIL "X"
0.10 C
10 X 0.25
4
5M0.05 C
1.60
INDEX AREA
B
3.00 A
PIN 1
6
PIN 1
6
1
2.0 REF
8X 0.50 BSC
5
Angular: ±2.50°
Compliant to JEDEC MO-229-WEED-3 except exposed pad length 7.
(2.30mm).
