Micropower Single-Supply
Rail-to-Rail Input/Output Op Amps
OP191/OP291/OP491
Rev. E
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FEATURES
Single-supply operation: 2.7 V to 12 V
Wide input voltage range
Rail-to-rail output swing
Low supply current: 300 μA/amp
Wide bandwidth: 3 MHz
Slew rate: 0.5 V/μs
Low offset voltage: 700 μV
No phase reversal
APPLICATIONS
Industrial process control
Battery-powered instrumentation
Power supply control and protection
Telecommunications
Remote sensors
Low voltage strain gage amplifiers
DAC output amplifiers
PIN CONFIGURATIONS
NC = NO CONNECT
OP191
NC
1
–
INA
2
+
INA
3
–V
4
NC
+V
OUTA
NC
8
7
6
5
00294-001
OP291
OUTA
1
–INA
2
+INA
3
–V
4
+V
OUTB
–INB
+INB
8
7
6
5
0
0294-002
Figure 1. 8-Lead Narrow-Body SOIC Figure 2. 8-Lead Narrow-Body SOIC
OP491
OUTA
1
–INA
2
+INA
3
+V
4
OUTD
–IND
+IND
–V
14
13
12
11
+INB
5
–INB
6
OUTB
7
+INC
–INC
OUTC
10
9
8
00294-003
OP491
OUTA
1
–INA
2
+INA
3
+V
4
+INB
5
OUTD
–IND
+IND
–V
+INC
14
13
12
11
10
–INB
6
O
UTB
7
–INC
OUTC
9
8
00294-004
+
-
+
-
+
-
+
-
Figure 3. 14-Lead Narrow-Body SOIC Figure 4. 14-Lead PDIP
OP491
OUTA
1
–INA
2
+INA
3
+V
4
OUTD
–IND
+IND
–V
14
13
12
11
+INB
5
–INB
6
OUTB
7
+INC
–INC
OUTC
10
9
8
00294-005
Figure 5. 14-Lead TSSOP
GENERAL DESCRIPTION
The OP191, OP291, and OP491 are single, dual, and quad
micropower, single-supply, 3 MHz bandwidth amplifiers
featuring rail-to-rail inputs and outputs. All are guaranteed to
operate from a +3 V single supply as well as ±5 V dual supplies.
Fabricated on Analog Devices CBCMOS process, the OPx91
family has a unique input stage that allows the input voltage to
safely extend 10 V beyond either supply without any phase
inversion or latch-up. The output voltage swings to within
millivolts of the supplies and continues to sink or source
current all the way to the supplies.
Applications for these amplifiers include portable tele-
communications equipment, power supply control and
protection, and interface for transducers with wide output
ranges. Sensors requiring a rail-to-rail input amplifier include
Hall effect, piezo electric, and resistive transducers.
The ability to swing rail-to-rail at both the input and output
enables designers to build multistage filters in single-supply
systems and to maintain high signal-to-noise ratios.
The OP191/OP291/OP491 are specified over the extended
industrial –40°C to +125°C temperature range. The OP191
single and OP291 dual amplifiers are available in 8-lead plastic
SOIC surface-mount packages. The OP491 quad is available in a
14-lead PDIP, a narrow 14-lead SOIC package, and a 14-lead
TSSOP.
OP191/OP291/OP491
Rev. E | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Specifications ............................................................... 3
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 17
Input Overvoltage Protection ................................................... 18
Output Voltage Phase Reversal ................................................. 18
Overdrive Recovery ................................................................... 18
Applications Information .............................................................. 19
Single 3 V Supply, Instrumentation Amplifier ....................... 19
Single-Supply RTD Amplifier ................................................... 19
A 2.5 V Reference from a 3 V Supply ...................................... 20
5 V Only, 12-Bit DAC Swings Rail-to-Rail ............................. 20
A High-Side Current Monitor .................................................. 20
A 3 V, Cold Junction Compensated Thermocouple Amplifier
....................................................................................................... 21
Single-Supply, Direct Access Arrangement for Modems ...... 21
3 V, 50 Hz/60 Hz Active Notch Filter with False Ground ..... 22
Single-Supply, Half-Wave, and Full-Wave Rectifiers ............. 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 24
REVISION HISTORY
4/10—Rev. D to Rev. E
Changes to Input Voltage Parameter, Table 4 ............................... 7
4/06—Rev. C to Rev. D
Changes to Noise Performance, Voltage Density, Table 1 ........... 3
Changes to Noise Performance, Voltage Density, Table 2 ........... 4
Changes to Noise Performance, Voltage Density, Table 3 ........... 5
Changes to Figure 23 and Figure 24 ............................................. 10
Changes to Figure 42 ...................................................................... 13
Changes to Figure 43 ...................................................................... 14
Changes to Figure 57 ...................................................................... 16
Added Figure 58 .............................................................................. 16
Changed Reference from Figure 47 to Figure 12 ........................ 17
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 24
3/04—Rev. B to Rev. C.
Changes to OP291 SOIC Pin Configuration ................................. 1
11/03—Rev. A to Rev. B.
Edits to General Description ........................................................... 1
Edits to Pin Configuration ............................................................... 1
Changes to Ordering Guide ............................................................. 5
Updated Outline Dimensions ....................................................... 19
12/02—Rev. 0 to Rev. A.
Edits to General Description ........................................................... 1
Edits to Pin Configuration ............................................................... 1
Changes to Ordering Guide ............................................................. 5
Edits to Dice Characteristics ............................................................ 5
OP191/OP291/OP491
Rev. E | Page 3 of 24
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
@ VS = 3.0 V, VCM = 0.1 V, VO = 1.4 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage
OP191G VOS 80 500 μV
−40°C ≤ TA ≤ +125°C 1 mV
OP291G/OP491G VOS 80 700 μV
−40°C ≤ TA ≤ +125°C 1.25 mV
Input Bias Current IB 30 65 nA
−40°C ≤ TA ≤ +125°C 95 nA
Input Offset Current IOS 0.1 11 nA
−40°C ≤ TA ≤ +125°C 22 nA
Input Voltage Range 0 3 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.9 V 70 90 dB
−40°C ≤ TA ≤ +125°C 65 87 dB
Large Signal Voltage Gain AVO RL = 10 kΩ, VO = 0.3 V to 2.7 V 25 70 V/mV
−40°C ≤ TA ≤ +125°C 50 V/mV
Offset Voltage Drift ∆VOS/∆T 1.1 μV/°C
Bias Current Drift ∆IB/∆T 100 pA/°C
Offset Current Drift ∆IOS/∆T 20 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 100 kΩ to GND 2.95 2.99 V
−40°C to +125°C 2.90 2.98 V
R
L = 2 kΩ to GND 2.8 2.9 V
−40°C to +125°C 2.70 2.80 V
Output Voltage Low VOL RL = 100 kΩ to V+ 4.5 10 mV
−40°C to +125°C 35 mV
R
L = 2 kΩ to V+ 40 75 mV
−40°C to +125°C 130 mV
Short-Circuit Limit ISC Sink/source ±8.75 ±13.50 mA
−40°C to +125°C ±6.0 ±10.5 mA
Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 200 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V 80 110 dB
−40°C ≤ TA ≤ +125°C 75 110 dB
Supply Current/Amplifier ISY VO = 0 V 200 350 μA
−40°C ≤ TA ≤ +125°C 330 480 μA
DYNAMIC PERFORMANCE
Slew Rate +SR RL = 10 kΩ 0.4 V/μs
Slew Rate –SR RL = 10 kΩ 0.4 V/μs
Full-Power Bandwidth BWP 1% distortion 1.2 kHz
Settling Time tS To 0.01% 22 μs
Gain Bandwidth Product GBP 3 MHz
Phase Margin θO 45 Degrees
Channel Separation CS f = 1 kHz, RL = 10 kΩ 145 dB
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 2 μV p-p
Voltage Noise Density en f = 1 kHz 30 nV/√Hz
Current Noise Density in 0.8 pA/√Hz
OP191/OP291/OP491
Rev. E | Page 4 of 24
@ VS = 5.0 V, VCM = 0.1 V, VO = 1.4 V, TA = 25°C, unless otherwise noted. +5 V specifications are guaranteed by +3 V and ±5 V testing.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage
OP191 VOS 80 500 μV
−40°C ≤ TA ≤ +125°C 1.0 mV
OP291/OP491 VOS 80 700 μV
−40°C ≤ TA ≤ +125°C 1.25 mV
Input Bias Current IB 30 65 nA
−40°C ≤ TA ≤ +125°C 95 nA
Input Offset Current IOS 0.1 11 nA
−40°C ≤ TA ≤ +125°C 22 nA
Input Voltage Range 0 5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 4.9 V 70 93 dB
–40°C ≤ TA ≤ +125°C 65 90 dB
Large Signal Voltage Gain AVO RL = 10 kΩ, VO = 0.3 V to 4.7 V 25 70 V/mV
−40°C ≤ TA ≤ +125°C 50 V/mV
Offset Voltage Drift ∆VOS/∆T −40°C ≤ TA ≤ +125°C 1.1 μV/°C
Bias Current Drift ∆IB/∆T 100 pA/°C
Offset Current Drift ∆IOS/∆T 20 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 100 kΩ to GND 4.95 4.99 V
−40°C to +125°C 4.90 4.98 V
R
L = 2 kΩ to GND 4.8 4.85 V
−40°C to +125°C 4.65 4.75 V
Output Voltage Low VOL RL = 100 kΩ to V+ 4.5 10 mV
−40°C to +125°C 35 mV
R
L = 2 kΩ to V+ 40 75 mV
−40°C to +125°C 155 mV
Short-Circuit Limit ISC Sink/source ±8.75 ±13.5 mA
−40°C to +125°C ±6.0 ±10.5 mA
Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 200 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V 80 110 dB
−40°C ≤ TA ≤ +125°C 75 110 dB
Supply Current/Amplifier ISY VO = 0 V 220 400 μA
−40°C ≤ TA ≤ +125°C 350 500 μA
DYNAMIC PERFORMANCE
Slew Rate +SR RL = 10 kΩ 0.4 V/μs
Slew Rate –SR RL = 10 kΩ 0.4 V/μs
Full-Power Bandwidth BWP 1% distortion 1.2 kHz
Settling Time tS To 0.01% 22 μs
Gain Bandwidth Product GBP 3 MHz
Phase Margin θO 45 Degrees
Channel Separation CS f = 1 kHz, RL = 10 kΩ 145 dB
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 2 μV p-p
Voltage Noise Density en f = 1 kHz 42 nV/√Hz
Current Noise Density in 0.8 pA/√Hz
OP191/OP291/OP491
Rev. E | Page 5 of 24
@ VO = ±5.0 V, –4.9 V ≤ VCM ≤ +4.9 V, TA = +25°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage
OP191 VOS 80 500 μV
−40°C ≤ TA ≤ +125°C 1 mV
OP291/OP491 VOS 80 700 μV
−40°C ≤ TA ≤ +125°C 1.25 mV
Input Bias Current IB 30 65 nA
−40°C ≤ TA ≤ +125°C 95 nA
Input Offset Current IOS 0.1 11 nA
−40°C ≤ TA ≤ +125°C 22 nA
Input Voltage Range −5 +5 V
Common-Mode Rejection Ratio CMRR VCM = ±5 V 75 100 dB
−40°C ≤ TA ≤ +125°C 67 97 dB
Large Signal Voltage Gain AVO RL = +10 kΩ, VO = ±4.7 V 25 70
−40°C ≤ TA ≤ +125°C 50 V/mV
Offset Voltage Drift ∆VOS/∆T 1.1 μV/°C
Bias Current Drift ∆IB/∆T 100 pA/°C
Offset Current Drift ∆IOS/∆T 20 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage Swing VO RL = 100 kΩ to GND ±4.93 ±4.99 V
−40°C to +125°C ±4.90 ±4.98 V
R
L = 2 kΩ to GND ±4.80 ±4.95 V
–40°C ≤ TA ≤ +125°C ±4.65 ±4.75 V
Short-Circuit Limit ISC Sink/source ±8.75 ±16.00 mA
−40°C to +125°C ±6 ±13 mA
Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 200 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±5 V 80 110 dB
−40°C ≤ TA ≤ +125°C 75 100 dB
Supply Current/Amplifier ISY VO = 0 V 260 420 μA
−40°C ≤ TA ≤ +125°C 390 550 μA
DYNAMIC PERFORMANCE
Slew Rate ±SR RL = 10 kΩ 0.5 V/μs
Full-Power Bandwidth BWP 1% distortion 1.2 kHz
Settling Time tS To 0.01% 22 μs
Gain Bandwidth Product GBP 3 MHz
Phase Margin θO 45 Degrees
Channel Separation CS f = 1 kHz 145 dB
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 2 μV p-p
Voltage Noise Density en f = 1 kHz 42 nV/√Hz
Current Noise Density in 0.8 pA/√Hz
OP191/OP291/OP491
Rev. E | Page 6 of 24
10
100
0%
5V
200s
5V
INPUT
OUTPUT
V
s
=±5V
R
L
=2k
A
V
=+1
V
IN
=20Vp-p
90
00294-006
Figure 6. Input and Output with Inputs Overdriven by 5 V
OP191/OP291/OP491
Rev. E | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 16 V
Input Voltage GND to (VS + 10 V)
Differential Input Voltage 7 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range
N, R, RU Packages −65°C to +150°C
Operating Temperature Range
OP191G/OP291G/OP491G −40°C to +125°C
Junction Temperature Range
N, R, RU Packages −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
THERMAL RESISTANCE
θJA is specified for the worst-case conditions; that is, θJA is
specified for device in socket for PDIP packages; θJA is specified
for device soldered in circuit board for TSSOP and SOIC
packages.
Table 5. Thermal Resistance
Package Type θJA θJC Unit
8-Lead SOIC (R) 158 43 °C/W
14-Lead PDIP (N) 76 33 °C/W
14-Lead SOIC (R) 120 36 °C/W
14-Lead TSSOP (RU) 180 35 °C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Absolute maximum ratings apply to both DICE and packaged
parts, unless otherwise noted.
OP191/OP291/OP491
Rev. E | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
180
0
0.22
40
20
–0.18
60
80
100
120
140
160
0.140.06–0.02–0.10
INPUT OFFSET VOLTAGE (mV)
UNITS
V
S
= 3V
T
A
= 25°C
BASED ON
1200 OP AMPS
00294-012
Figure 7. OP291 Input Offset Voltage Distribution, VS = 3 V
00294-013
UNITS
120
0
7
60
20
1
40
0
100
80
6432
INPUT OFFSET VOLTAGE (µV/°C)
5
V
S
= 3V
–40°C < T
A
< +125°C
BASED ON 600 OP AMPS
Figure 8. OP291 Input Offset Voltage Drift Distribution, VS = 3 V
00294-014
INPUT OFFSET VOLTAGE (mV)
12525–40 85
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
V
S
= 3V
V
CM
= 3V
TEMPERATURE (°C)
V
CM
= 0.1V
V
CM
= 0V
V
CM
= 2.9V
Figure 9. Input Offset Voltage vs. Temperature, VS = 3 V
00294-015
INPUT BIAS CURRENT (nA)
40
30
20
10
0
–10
–20
–30
–40
–50
–60
12525 85
TEMPERATURE (°C)
–40
V
S
= 3V
V
CM
= 3V
V
CM
= 2.9V
V
CM
= 0.1V
V
CM
= 0V
Figure 10. Input Bias Current vs. Temperature, VS = 3 V
00294-016
INPUT OFFSET CURRENT (nA)
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
12525 85
TEMPERATURE (°C)
–40
V
CM
= 0.1V
V
CM
= 2.9V
V
CM
= 3V
V
CM
= 0V
V
S
= 3V
Figure 11. Input Offset Current vs. Temperature, VS = 3 V
00294-017
INPUT COMMON-MODE VOLTAGE (V)
INPUT BIAS CURRENT (nA)
36
–36
3.0
–18
–30
0.3
–24
0
0
–12
–6
6
12
18
30
24
2.72.42.11.81.51.20.90.6
VS = 3V
Figure 12. Input Bias Current vs. Input Common-Mode Voltage, VS = 3 V
OP191/OP291/OP491
Rev. E | Page 9 of 24
00294-018
TEMPERATURE (°C)
OUTPUT VOLTAGE SWING (V)
3.00
2.75
125
2.90
2.80
25
2.85
–40
2.95
85
VS = 3V
+VO @ RL = 100k
+VO @ RL = 2k
Figure 13. Output Voltage Swing vs. Temperature, VS = 3 V
160
100
60
–40
1k
80
100
120
140
–20
0
20
40 90
–90
–45
0
45
FREQUENCY (Hz)
10M1M100k10k
VS=3V
TA= 25°C
00294-019 OPEN PHASE SHIFT (Degrees)
OPEN-LOOP GAIN (dB)
Figure 14. Open-Loop Gain and Phase vs. Frequency, VS = 3 V
00294-020
TEMPERATURE (°C)
OPEN-LOOP GAIN (V/mV)
1200
1000
800
600
400
200
012525–40 85
R
L
= 100k,
V
CM
= 2.9V
V
S
= 3V, V
O
= 0.3V/2.7V
R
L
= 100k,
V
CM
= 0.1V
Figure 15. Open-Loop Gain vs. Temperature, VS = 3 V
00294-021
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
50
0
–50
10
20
30
40
–40
–30
–20
–10
10 100 1k 10k 100k 1M 10M
VS = 3V
TA = 25°C
Figure 16. Closed-Loop Gain vs. Frequency, VS = 3 V
00294-022
FREQUENCY (Hz)
CMRR (dB)
160
60
–40
80
100
120
140
–20
0
20
40
CMRR
VS = 3V
TA = 25°C
100 1k 10M1M100k10k
Figure 17. CMRR vs. Frequency, VS = 3 V
00294-023
TEMPERATURE (°C)
CMRR (dB)
90
84
125
87
85
25
86
–40
89
88
85
V
S
= 3V
Figure 18. CMRR vs. Temperature, VS = 3 V
OP191/OP291/OP491
Rev. E | Page 10 of 24
00294-024
FREQUENCY (Hz)
PSRR (dB)
160
60
–40
80
100
120
140
–20
0
20
40
±PSRR
V
S
= 3V
T
A
= 25°C
+PSRR
–PSRR
100 1k 10M1M100k10k
Figure 19. PSRR vs. Frequency, VS = 3 V
00294-025
TEMPERATURE (°C)
PSRR (dB)
113
107
125
110
108
25
109
–40
112
111
85
V
S
= 3V
Figure 20. PSRR vs. Temperature, VS = 3 V
00294-026
TEMPERATURE (°C)
SLEW RATE (V/µs)
1.6
0
125
0.4
0.2
25–40
0.8
0.6
1.0
1.2
1.4
85
V
S
= 3V
+SR
–SR
Figure 21. Slew Rate vs. Temperature, VS = 3 V
00294-027
TEMPERATURE (°C)
SUPPLY CURRENT/AMPLIFIER (mA)
0.35
0.05
125
0.20
0.10
25
0.15
–40
0.30
0.25
85
V
S
= 3V
Figure 22. Supply Current vs. Temperature, VS = +3 V, +5 V, ±5 V
00294-028
FREQUENCY (Hz)
MAXIMUM OUTPUT SWING (V)
3.0
0
1M
1.0
0.5
100 1k 10k 100k
2.0
1.5
2.5
V
IN
= 2.8V p-p
V
S
= 3V
A
V
= +1
R
L
= 100k
Figure 23. Maximum Output Swing vs. Frequency, VS = 3 V
00294-029
FREQUENCY (Hz)
VOLTAGE NOISE DENSITY (nV/ Hz)
1k
10
10 100 1k 10k
100
Figure 24. Voltage Noise Density, VS = 5 V or ±5 V
OP191/OP291/OP491
Rev. E | Page 11 of 24
00294-030
INPUT OFFSET VOLTAGE (mV)
UNITS
70
0
0.50
30
10
20
–0.50
60
40
50
0.300.10–0.10–0.30
V
S
= 5V
T
A
= 25°C
BASED ON 600
OP AMPS
Figure 25. OP291 Input Offset Voltage Distribution, VS = 5 V
00294-031
UNITS
120
0
7
60
20
1
40
0
100
80
6432
INPUT OFFSET VOLTAGE (µV/°C)
5
V
S
= 5V
–40°C < T
A
< +125°C
BASED ON 600 OP AMPS
Figure 26. OP291 Input Offset Voltage Drift Distribution, VS = 5 V
00294-032
TEMPERATURE (°C)
V
OS
(mV)
0.15
–0.10
125
0.05
–0.05
25
0
–40
0.10
85
V
S
= 5V
V
CM
= 0V
V
CM
= 5V
Figure 27. Input Offset Voltage vs. Temperature, VS = 5 V
00294-033
I
B
(nA)
40
30
20
10
0
–10
–20
–30
–40
12525 85
TEMPERATURE (°C)
–40
V
S
= 5V
V
CM
= 5V
V
CM
= 0V
+I
B
–I
B
–I
B
+I
B
Figure 28. Input Bias Current vs. Temperature, VS = 5 V
00294-034
INPUT OFFSET CURRENT (nA)
1.4
1.6
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
12525 85
TEMPERATURE (°C)
–40
V
S
=5V
V
CM
=0V
V
CM
=5V
Figure 29. Input Offset Current vs. Temperature, VS = 5 V
00294-035
COMMON-MODE INPUT VOLTAGE (V)
INPUT BIAS CURRENT (nA)
36
–36
5
–18
–30
–24
0
0
–12
–6
6
12
18
30
24
4321
V
S
= 5V
Figure 30. Input Bias Current vs. Common-Mode Input Voltage, VS = 5 V
OP191/OP291/OP491
Rev. E | Page 12 of 24
00294-036
TEMPERATURE (°C)
OUTPUT VOLTAGE SWING (V)
5.00
4.70
125
4.85
4.75
25
4.80
–40
4.95
4.90
85
R
L
= 100k
R
L
= 2k
V
S
= 5V
Figure 31. Output Voltage Swing vs. Temperature, VS = 5 V
160
100
60
–40
1k
80
100
120
140
–20
0
20
40
FREQUENCY (Hz)
10M1M100k10k
VS=5V
TA= 25°C
00294-037
90
–90
–45
0
45
OPEN PHASE SHIFT (Degrees)
OPEN-LOOP GAIN (dB)
Figure 32. Open-Loop Gain and Phase vs. Frequency, VS = 5 V
00294-038
TEMPERATURE (°C)
OPEN-LOOP GAIN (V/mV)
140
0
125
60
20
25
40
–40
120
80
100
85
V
S
= 5V
R
L
= 100k, V
CM
= 5V
R
L
= 2k, V
CM
= 5V
R
L
= 2k, V
CM
= 0V
R
L
= 100k, V
CM
= 0V
Figure 33. Open-Loop Gain vs. Temperature, VS = 5 V
00294-039
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
50
0
–50
10
20
30
40
–40
–30
–20
–10
10 100 1k 10k 100k 1M 10M
V
S
= 5V
T
A
= 25°C
Figure 34. Closed-Loop Gain vs. Frequency, VS = 5 V
00294-040
FREQUENCY (Hz)
CMRR (dB)
160
60
–40
80
100
120
140
–20
0
20
40
CMRR
V
S
=5V
T
A
=25°C
100 1k 10M1M100k10k
Figure 35. CMRR vs. Frequency, VS = 5V
00294-041
TEMPERATURE (°C)
CMRR (dB)
96
86
89
87
25
88
–40
92
90
91
93
94
95
85 125
V
S
= 5V
Figure 36. CMRR vs. Temperature, VS = 5 V
OP191/OP291/OP491
Rev. E | Page 13 of 24
00294-042
FREQUENCY (Hz)
PSRR (dB)
160
60
–40
80
100
120
140
–20
0
20
40
±PSRR
V
S
= 5V
T
A
= 25°C
+PSRR
–PSRR
100 1k 10M1M100k10k
Figure 37. PSRR vs. Frequency, VS = 5 V
00294-043
TEMPERATURE (°C)
SR (V/µs)
0.6
0
125
0.3
0.1
25
0.2
–40
0.5
0.4
85
V
S
=5V
+SR –SR
Figure 38. OP291 Slew Rate vs. Temperature, VS = 5 V
00294-044
TEMPERATURE (°C)
SR (V/µs)
0.50
0
125
0.15
0.05
25
0.10
–40
0.30
0.20
0.25
0.35
0.40
0.45
85
+SR
–SR
V
S
= 5V
Figure 39. OP491 Slew Rate vs. Temperature, VS = 5 V
00294-045
TEMPERATURE (°C)
SHORT-CIRCUIT CURRENT (mA)
20
4
125
8
6
25–40
12
10
14
16
18
85
–I
SC
, V
S
= +3V
+I
SC
, V
S
= ±5V
–I
SC
, V
S
= ±5V
+I
SC
, V
S
= +3V
Figure 40. Short-Circuit Current vs. Temperature, VS = +3 V, +5 V, ±5 V
00294-046
FREQUENCY (Hz)
VOLTAGE (V)
80
0
2500
20
10
0
40
30
50
60
70
200015001000500
A
10k
10k1k
V
IN
= 10V p-p @ 1kHz
B
V
O
V
S
= ±5V
Figure 41. Channel Separation, VS = ±5 V
00294-047
FREQUENCY (Hz)
MAXIMUM OUTPUT SWING (V)
5.0
0
1.5
0.5
1.0
3.0
2.0
2.5
3.5
4.0
4.5
V
IN
= 4.8V p-p
V
S
= 5V
A
V
= +1
R
L
= 100k
1M100 1k 10k 100k
Figure 42. Maximum Output Swing vs. Frequency, VS = 5 V
OP191/OP291/OP491
Rev. E | Page 14 of 24
00294-048
FREQUENCY (Hz)
MAXIMUM OUTPUT SWING (V)
10
0
2
6
4
8
0
1M100 1k 10k 100k
V
IN
= 9.8V p-p
V
S
= ±5V
A
V
= +1
R
L
= 100k
Figure 43. Maximum Output Swing vs. Frequency, VS = ±5 V
00294-049
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (mV)
0.15
–0.10
125
0.05
–0.05
25
0
–40
0.10
85
V
S
=±5V
V
CM
=+5V
V
CM
= –5V
Figure 44. Input Offset Voltage vs. Temperature, VS = ±5 V
00294-050
I
B
(nA)
50
40
30
20
10
0
–10
–20
–30
–40
–50
12525 85
TEMPERATURE (°C)
–40
+I
B
–I
B
–I
B
V
S
= ±5V
V
CM
= +5V
V
CM
= –5V
+I
B
Figure 45. Input Bias Current vs. Temperature, VS = ±5 V
00294-051
INPUT OFFSET CURRENT (nA)
1.4
1.6
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
12525 85
TEMPERATURE (°C)
–40
V
S
=±5V
V
CM
= –5V
V
CM
=+5V
Figure 46. Input Offset Current vs. Temperature, VS = ±5 V
00294-052
COMMON-MODE INPUT VOLTAGE (V)
INPUT BIAS CURRENT (nA)
36
–36
5–4
–24
–5
0
–12
12
24
43210–1–2–3
V
S
= ±5V
Figure 47. Input Bias Current vs. Common-Mode Voltage, VS = ±5 V
00294-053
TEMPERATURE (°C)
OUTPUT VOLTAGE SWING (V)
5.00
–5.00
125
–4.85
–4.95
25
–4.90
–40
0
–4.80
–4.75
4.75
4.80
4.85
4.95
4.90
85
V
S
= ±5V
R
L
= 2k
R
L
= 2k
R
L
= 2k
R
L
= 2k
Figure 48. Output Voltage Swing vs. Temperature, VS = ±5 V
OP191/OP291/OP491
Rev. E | Page 15 of 24
00294-054
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
70
20
–30
30
40
50
60
–20
–10
0
10
90
45
0
270
225
180
135
PHASE SHIFT (Degrees)
1k 10M1M100k10k
V
S
= ±5V
T
A
= 25°C
Figure 49. Open-Loop Gain and Phase vs. Frequency, VS = ±5 V
00294-055
TEMPERATURE (°C)
OPEN-LOOP GAIN (V/mV)
200
0
125
65
25
25
40
–40
120
80
100
140
160
180
85
V
S
= ±5V
R
L
= 2k
R
L
= 2k
Figure 50. Open-Loop Gain vs. Temperature, VS = ±5 V
00294-056
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
50
0
–50
10
20
30
40
–40
–30
–20
–10
10 100 1k 10k 100k 1M 10M
V
S
= ±5V
T
A
= 25°C
Figure 51. Closed-Loop Gain vs. Frequency, VS = ±5 V
00294-057
FREQUENCY (Hz)
CMRR (dB)
160
60
–40
80
100
120
140
–20
0
20
40
CMRR
V
S
= ±5V
T
A
= 25°C
100 1k 10k 100k 1M 10M
Figure 52. CMRR vs. Frequency, VS = ±5 V
00294-058
TEMPERATURE (°C)
CMRR (dB)
102
92
125
95
93
25
94
–40
98
96
97
99
100
101
85
V
S
= ±5V
Figure 53. CMRR vs. Temperature, VS =± 5 V
00294-059
FREQUENCY (Hz)
PSRR (dB)
160
60
–40
80
100
120
140
–20
0
20
40
±PSRR
V
S
= ±5V
T
A
= 25°C
100 1k 10k 100k 1M 10M
+PSRR
–PSRR
Figure 54. PSRR vs. Frequency, VS = ±5 V
OP191/OP291/OP491
Rev. E | Page 16 of 24
00294-060
TEMPERATURE (°C)
PSRR (dB)
115
90
125
105
95
25
100
–40
110
85
OP491
OP291
V
S
= ±5V
Figure 55. OP291/OP491 PSRR vs. Temperature, VS = ±5 V
00294-061
TEMPERATURE (°C)
SR (V/µs)
12525–40 85
V
S
=±5V
0.7
0
0.6
0.5
0.4
0.3
0.2
0.1
+SR
–SR
Figure 56. Slew Rate vs. Temperature, VS = ±5 V
00294-062
FREQUENCY (Hz)
OUTPUT IMPEDANCE ()
1k
0.1
1
10
100
1k 10k 100k 1M 2M
V
S
= 3V
A
V
= +100
A
V
= +10
A
V
= +1
Figure 57. Output Impedance vs. Frequency
00294-078
FREQUENCY (Hz)
VOLTAGE NOISE DENSITY (nV/ Hz)
1k
10
10 100 1k 10k
100
Figure 58. Voltage Noise Density, VS = 3 V
00294-063
100mV500mV
1.00V
2.00µs
INPUT
OUTPUT
VS=3V
RL= 200k
10
0%
90
100
Figure 59. Large Signal Transient Response, VS = 3 V
0
0294-064
100mV1.00V
2.00V
INPUT
O
UTPUT
2.00µs
V
S
=±5V
R
L
= 200k
A
V
=+1V/V
10
100
0%
90
Figure 60. Large Signal Transient Response, VS = ±5 V
OP191/OP291/OP491
Rev. E | Page 17 of 24
THEORY OF OPERATION
The OP191/OP291/OP491 are single-supply, micropower
amplifiers featuring rail-to-rail inputs and outputs. To achieve
wide input and output ranges, these amplifiers employ unique
input and output stages. In Figure 61 , the input stage comprises
two differential pairs, a PNP pair and an NPN pair. These two
stages do not work in parallel. Instead, only one stage is on for
any given input signal level. The PNP stage (Transistor Q1 and
Transistor Q2) is required to ensure that the amplifier remains
in the linear region when the input voltage approaches and
reaches the negative rail. On the other hand, the NPN stage
(Transistor Q5 and Transistor Q6) is needed for input voltages
up to and including the positive rail.
For the majority of the input common-mode range, the PNP
stage is active, as is shown in Figure 12. Notice that the bias
current switches direction at approximately 1.2 V to 1.3 V
below the positive rail. At voltages below this, the bias current
flows out of the OP291, indicating a PNP input stage. Above
this voltage, however, the bias current enters the device,
revealing the NPN stage. The actual mechanism within the
amplifier for switching between the input stages comprises
Transistor Q3, Transistor Q4, and Transistor Q7. As the input
common-mode voltage increases, the emitters of Q1 and Q2
follow that voltage plus a diode drop. Eventually, the emitters
of Q1 and Q2 are high enough to turn on Q3, which diverts the
8 µA of tail current away from the PNP input stage, turning it
off. Instead, the current is mirrored through Q4 and Q7 to
activate the NPN input stage.
Notice that the input stage includes 5 kΩ series resistors and
differential diodes, a common practice in bipolar amplifiers to
protect the input transistors from large differential voltages.
These diodes turn on whenever the differential voltage exceeds
approximately 0.6 V. In this condition, current flows between
the input pins, limited only by the two 5 kΩ resistors. This
characteristic is important in circuits where the amplifier may
be operated open-loop, such as a comparator. Evaluate each
circuit carefully to make sure that the increase in current does
not affect the performance.
The output stage in OP191 devices uses a PNP and an NPN
transistor, as do most output stages; however, Q32 and Q33, the
output transistors, are actually connected with their collectors
to the output pin to achieve the rail-to-rail output swing. As the
output voltage approaches either the positive or negative rail,
these transistors begin to saturate. Thus, the final limit on
output voltage is the saturation voltage of these transistors,
which is about 50 mV. The output stage does have inherent gain
arising from the collectors and any external load impedance.
Because of this, the open-loop gain of the amplifier is
dependent on the load resistance.
Q1
8µA
5k
Q3 5k
–IN
Q5 Q6
Q11
Q10Q8
Q7
Q4
Q13 Q15
Q14Q12
Q9
Q16 Q17
Q18 Q19
Q20
Q21
Q24
Q23
Q22
Q27
Q26
Q30
Q31
Q28
Q25 Q29
Q32
V
OUT
Q33
10pF
+IN Q2
0
0294-065
Figure 61. Simplified Schematic
OP191/OP291/OP491
Rev. E | Page 18 of 24
INPUT OVERVOLTAGE PROTECTION
As with any semiconductor device, whenever the condition
exists for the input to exceed either supply voltage, check the
input overvoltage characteristic. When an overvoltage occurs,
the amplifier could be damaged depending on the voltage level
and the magnitude of the fault current. Figure 62 shows the
characteristics for the OP191 family. This graph was generated
with the power supplies at ground and a curve tracer connected
to the input. When the input voltage exceeds either supply by
more than 0.6 V, internal PN junctions energize, allowing
current to flow from the input to the supplies. As described, the
OP291/OP491 do have 5 kΩ resistors in series with each input
to help limit the current. Calculating the slope of the current vs.
voltage in the graph confirms the 5 kΩ resistor.
+2mA
+1mA
–1mA
–2mA
–5V +10V–10V +5V
V
IN
I
IN
00294-066
Figure 62. Input Overvoltage Characteristics
This input current is not inherently damaging to the device as
long as it is limited to 5 mA or less. For an input of 10 V over
the supply, the current is limited to 1.8 mA. If the voltage is
large enough to cause more than 5 mA of current to flow, then
an external series resistor should be added. The size of this
resistor is calculated by dividing the maximum overvoltage by
5 mA and subtracting the internal 5 kΩ resistor. For example, if
the input voltage could reach 100 V, the external resistor should
be (100 V/5 mA) − 5 k = 15 kΩ. This resistance should be
placed in series with either or both inputs if they are subjected
to the overvoltages.
OUTPUT VOLTAGE PHASE REVERSAL
Some operational amplifiers designed for single-supply
operation exhibit an output voltage phase reversal when their
inputs are driven beyond their useful common-mode range.
Typically, for single-supply bipolar op amps, the negative supply
determines the lower limit of their common-mode range.
With these devices, external clamping diodes with the anode
connected to ground and the cathode to the inputs prevent
input signal excursions from exceeding the device’s negative
supply (that is, GND), preventing a condition that could cause
the output voltage to change phase. JFET input amplifiers can
also exhibit phase reversal, and, if so, a series input resistor is
usually required to prevent it.
The OP191 is free from reasonable input voltage range
restrictions due to its novel input structure. In fact, the input
signal can exceed the supply voltage by a significant amount
without causing damage to the device. As shown in Figure 64,
the OP191 family can safely handle a 20 V p-p input signal on
±5 V supplies without exhibiting any sign of output voltage
phase reversal or other anomalous behavior. Thus, no external
clamping diodes are required.
OVERDRIVE RECOVERY
The overdrive recovery time of an operational amplifier is the
time required for the output voltage to recover to its linear
region from a saturated condition. This recovery time is
important in applications where the amplifier must recover
quickly after a large transient event, such as a comparator. The
circuit shown in Figure 63 was used to evaluate the OPx91
overdrive recovery time. The OPx91 takes approximately 8 µs to
recover from positive saturation and approximately 6.5 µs to
recover from negative saturation.
+
–
1/2
OP291
3
2
1
R1
9k
R2
10k
R3
10k
V
IN
10V STEP
V
S
= ±5V
V
OUT
00294-068
Figure 63. Overdrive Recovery Time Test Circuit
10
90
100
0%
TIME (200µs/DIV)
V
IN
(2.5V/DIV)
10
90
100
0%
TIME (200µs/DIV)
V
OUT
(2V/DIV)
20mV 20mV
5µs5µs
+5V
–5V
V
IN
20V p-p
V
OUT
8
1
3
24
1/2
OP291
+
–
00294-067
Figure 64. Output Voltage Phase Reversal Behavior
OP191/OP291/OP491
Rev. E | Page 19 of 24
APPLICATIONS INFORMATION
SINGLE 3 V SUPPLY, INSTRUMENTATION
AMPLIFIER
The OP291 low supply current and low voltage operation
make it ideal for battery-powered applications, such as the
instrumentation amplifier shown in Figure 65. The circuit uses
the classic two op amp instrumentation amplifier topology, with
four resistors to set the gain. The equation is simply that of a
noninverting amplifier, as shown in Figure 65. The two resistors
labeled R1 should be closely matched both to each other and to
the two resistors labeled R2 to ensure good common-mode
rejection performance. Resistor networks ensure the closest
matching as well as matched drifts for good temperature
stability. Capacitor C1 is included to limit the bandwidth and,
therefore, the noise in sensitive applications. The value of this
capacitor should be adjusted depending on the desired closed-
loop bandwidth of the instrumentation amplifier. The RC
combination creates a pole at a frequency equal to 1/(2π ×
R1C1). If AC-CMRR is critical, then a matched capacitor to C1
should be included across the second resistor labeled R1.
1/2
OP291
1/2
OP291
R1 R2 R2 R1
3
V
C1
100pF
V
IN
V
OUT
V
OUT
= (1 + ) = V
IN
R1
R2
–
00294-069
3
2
1
8
5
64
7
+
Figure 65. Single 3 V Supply Instrumentation Amplifier
Because the OP291 accepts rail-to-rail inputs, the input
common-mode range includes both ground and the positive
supply of 3 V. Furthermore, the rail-to-rail output range ensures
the widest signal range possible and maximizes the dynamic
range of the system. Also, with its low supply current of
300 µA/device, this circuit consumes a quiescent current of
only 600 µA yet still exhibits a gain bandwidth of 3 MHz.
A question may arise about other instrumentation amplifier
topologies for single-supply applications. For example, a
variation on this topology adds a fifth resistor between the two
inverting inputs of the op amps for gain setting. While that
topology works well in dual-supply applications, it is inherently
inappropriate for single-supply circuits. The same could be said
for the traditional three op amp instrumentation amplifier. In
both cases, the circuits simply cannot work in single-supply
situations unless a false ground between the supplies is created.
SINGLE-SUPPLY RTD AMPLIFIER
The circuit in Figure 66 uses three op amps of the OP491 to
develop a bridge configuration for an RTD amplifier that
operates from a single 5 V supply. The circuit takes advantage of
the OP491 wide output swing range to generate a high bridge
excitation voltage of 3.9 V. In fact, because of the rail-to-rail
output swing, this circuit works with supplies as low as 4.0 V.
Amplifier A1 servos the bridge to create a constant excitation
current in conjunction with the AD589, a 1.235 V precision
reference. The op amp maintains the reference voltage across
the parallel combination of the 6.19 kΩ and 2.55 MΩ resistors,
which generate a 200 µA current source. This current splits
evenly and flows through both halves of the bridge. Thus,
100 µA flows through the RTD to generate an output voltage
based on its resistance. A 3-wire RTD is used to balance the line
resistance in both 100 Ω legs of the bridge to improve accuracy.
1/4
OP491
V
OUT
365365
1/4
OP491
100k
0.01pF
A3
5V
GAIN = 274
100k
1/4
OP491
37.4k
5V
AD589
2.55M
6.19k
200
10 TURNS
26.7k26.7k
A2
A1
100
100
RTD
ALL RESISTORS 1% OR BETTER
00294-070
Figure 66. Single-Supply RTD Amplifier
Amplifier A2 and Amplifier A3 are configured in the two op
amp instrumentation amplifier topology described in the Single
3 V Supply, Instrumentation Amplifier section. The resistors are
chosen to produce a gain of 274, such that each 1°C increase in
temperature results in a 10 mV change in the output voltage, for
ease of measurement. A 0.01 µF capacitor is included in parallel
with the 100 kΩ resistor on Amplifier A3 to filter out any
unwanted noise from this high gain circuit. This particular RC
combination creates a pole at 1.6 kHz.
OP191/OP291/OP491
Rev. E | Page 20 of 24
A 2.5 V REFERENCE FROM A 3 V SUPPLY
In many single-supply applications, the need for a 2.5 V
reference often arises. Many commercially available monolithic
2.5 V references require a minimum operating supply voltage of
4 V. The problem is exacerbated when the minimum operating
system supply voltage is 3 V. The circuit illustrated in Figure 67
is an example of a 2.5 V reference that operates from a single
3 V supply. The circuit takes advantage of the OP291 rail-to-rail
input and output voltage ranges to amplify an AD589 1.235 V
output to 2.5 V. The OP291 low TCVOS of 1 µV/°C helps
maintain an output voltage temperature coefficient of less than
200 ppm/°C. The circuit overall temperature coefficient is
dominated by the temperature coefficient of R2 and R3. Lower
temperature coefficient resistors are recommended. The entire
circuit draws less than 420 µA from a 3 V supply at 25°C.
RESISTORS = 1%, 100ppm/°C
POTENTIOMETER = 10 TURN, 100ppm/°C
R3
100k
1/2
OP291
R2
100k
3V
R1
5k
2.5VREF
R1
17.4k
A
D589
3V
3
2
1
8
4
00294-071
Figure 67. A 2.5 V Reference that Operates on a Single 3 V Supply
5 V ONLY, 12-BIT DAC SWINGS RAIL-TO-RAIL
The OPx91 family is ideal for use with a CMOS DAC to
generate a digitally controlled voltage with a wide output range.
Figure 68 shows the DAC8043 used in conjunction with the
AD589 to generate a voltage output from 0 V to 1.23 V. The
DAC is operated in voltage switching mode, where the reference
is connected to the current output, IOUT, and the output voltage
is taken from the VREF pin. This topology is inherently
noninverting as opposed to the classic current output mode,
which is inverting and, therefore, unsuitable for single supply.
5V
R1
17.8k
A
D589
R2
R3 R4
232
1%
32.4k
1%
100k
1%
V
OUT
= –––– (5V)
D
4096
GND CLK SR1
4765
DIGITAL
CONTROL
LD
V
REF
R
FB
V
DD
I
OUT
2
3
8
1.23V
5
V
DAC8043
1/2
OP291
3
2
1
8
4
1
00294-072
Figure 68. 5 V Only, 12-Bit DAC Swings Rail-to-Rail
The OP291 serves two functions. First, it is required to buffer
the high output impedance of the DAC VREF pin, which is on the
order of 10 kΩ. The op amp provides a low impedance output
to drive any following circuitry. Second, the op amp amplifies
the output signal to provide a rail-to-rail output swing. In this
particular case, the gain is set to 4.1 to generate a 5.0 V output
when the DAC is at full scale. If other output voltage ranges are
needed, such as 0 V to 4.095 V, the gain can easily be adjusted
by altering the value of the resistors.
A HIGH-SIDE CURRENT MONITOR
In the design of power supply control circuits, a great deal of
design effort is focused on ensuring a pass transistor’s long-
term reliability over a wide range of load current conditions.
As a result, monitoring and limiting device power dissipation
is of prime importance in these designs. The circuit illustrated
in Figure 69 is an example of a 5 V, single-supply, high-side
current monitor that can be incorporated into the design of a
voltage regulator with fold-back current limiting or a high
current power supply with crowbar protection. This design uses
an OP291 rail-to-rail input voltage range to sense the voltage
drop across a 0.1 Ω current shunt. A p-channel MOSFET used
as the feedback element in the circuit converts the op amp
differential input voltage into a current. This current is then
applied to R2 to generate a voltage that is a linear representation
of the load current. The transfer equation for the current
monitor is given by
L
SENSE I
R
R
ROutputMonitor ×
⎟
⎠
⎞
⎜
⎝
⎛
×= 1
2
For the element values shown, the monitor output transfer
characteristic is 2.5 V/A.
5V
R
SENSE
0.1
5V 5V
I
L
SG
M1
3N163
D
R2
2.49k
MONITOR
OUTPUT
R1
100
1/2
OP291
3
2
1
8
4
00294-073
Figure 69. A High-Side Load Current Monitor
OP191/OP291/OP491
Rev. E | Page 21 of 24
A 3 V, COLD JUNCTION COMPENSATED
THERMOCOUPLE AMPLIFIER
The OP291 low supply operation makes it ideal for 3 V battery-
powered applications such as the thermocouple amplifier
shown in Figure 70. The K-type thermocouple terminates in an
isothermal block where the junction ambient temperature is
continuously monitored using a simple 1N914 diode. The diode
corrects the thermal EMF generated in the junctions by feeding
a small voltage, scaled by the 1.5 MΩ and 475 Ω resistors, to the
op amp.
To calibrate this circuit, immerse the thermocouple measuring
junction in a 0°C ice bath and adjust the 500 Ω potentiometer
to 0 V out. Next, immerse the thermocouple in a 250°C
temperature bath or oven and adjust the scale adjust
potentiometer for an output voltage of 2.50 V. Within this
temperature range, the K-type thermocouple is accurate to
within ±3°C without linearization.
8
1
4
3
2
OP291
500
10 TURN
ZERO
ADJUST
24.3k
1%
7.15k
1%
24.9k
1%
2.1k
1%
475
1%
1.5M
1%
1N914
AL
CR
ISOTHERMAL
BLOCK
ALUMEL
CHROMEL
COLD
JUNCTIONS
K-TYPE
THERMOCOUPLE
40.7V/°C
10k3.0V
AD589
1.33M20k
SCALE
ADJUST
VOUT
0V = 0°C
3V = 300°C
1.235
V
11.2mV
4.99k
1%
00294-074
1/2
Figure 70. A 3 V, Cold Junction Compensated Thermocouple Amplifier
SINGLE-SUPPLY, DIRECT ACCESS ARRANGEMENT
FOR MODEMS
An important building block in modems is the telephone line
interface. In the circuit shown in Figure 71, a direct access
arrangement is used to transmit and receive data from the
telephone line. Amplifier A1 is the receiving amplifier;
Amplifier A2 and Amplifier A3 are the transmitters. The fourth
amplifier, A4, generates a pseudo ground halfway between the
supply voltage and ground. This pseudo ground is needed for
the ac-coupled bipolar input signals.
The transmit signal, TXA, is inverted by A2 and then reinverted
by A3 to provide a differential drive to the transformer, where
each amplifier supplies half the drive signal. This is needed
because of the smaller swings associated with a single supply as
opposed to a dual supply. Amplifier A1 provides some gain for
the received signal, and it also removes the transmit signal
present at the transformer from the received signal. To do this,
the drive signal from A2 is also fed to the noninverting input of
A1 to cancel the transmit signal from the transformer.
RXA 1/4
OP491
37.4k
A1
3.3k
0.0047F
A2
20k,1%
475,1%
0.033F
37.4k,1%
390p
F
750pF
0.1F
0.1F
A3
T1
1:1
5.1V TO 6.2V
ZENER 5
A4
100k
100k
3V OR 5V
10F0.1F
20k,1%
20k,1%
20k,1%
TXA
20k,1%
13
12
14
8
10
9
1/4
OP491
7
6
5
1/4
OP491
3
1
2
1/4
OP491
4
11
0
0294-075
Figure 71. Single-Supply, Direct Access Arrangement for Modems
The OP491 bandwidth of 3 MHz and rail-to-rail output swings
ensure that it can provide the largest possible drive to the
transformer at the frequency of transmission.
OP191/OP291/OP491
Rev. E | Page 22 of 24
3 V, 50 HZ/60 HZ ACTIVE NOTCH FILTER WITH
FALSE GROUND
The filter section uses a pair of OP491s in a twin-T
configuration whose frequency selectivity is very sensitive
to the relative matching of the capacitors and resistors in
the twin-T section. Mylar is the material of choice for the
capacitors, and the relative matching of the capacitors and
resistors determines the pass band symmetry of the filter. Using
1% resistors and 5% capacitors produces satisfactory results.
To process ac signals in a single-supply system, it is often best
to use a false ground biasing scheme. Figure 72 illustrates a
circuit that uses this approach. In this circuit, a false-ground
circuit biases an active notch filter used to reject 50 Hz/60 Hz
power line interference in portable patient monitoring
equipment. Notch filters are quite commonly used to reject
power line frequency interference that often obscures low
frequency physiological signals, such as heart rates, blood
pressure readings, EEGs, and EKGs. This notch filter effectively
squelches 60 Hz pickup at a filter Q of 0.75. Substituting
3.16 kΩ resistors for the 2.67 kΩ resistors in the twin-T section
(R1 through R5) configures the active filter to reject 50 Hz
interference.
SINGLE-SUPPLY, HALF-WAVE, AND FULL-WAVE
RECTIFIERS
An OPx91 device configured as a voltage follower operating on
a single supply can be used as a simple half-wave rectifier in low
frequency (<2 kHz) applications. A full-wave rectifier can be
configured with a pair of OP291s, as illustrated in Figure 73.
The circuit works in the following way. When the input signal is
above 0 V, the output of Amplifier A1 follows the input signal.
Because the noninverting input of Amplifier A2 is connected to
the output of A1, op amp loop control forces the inverting input
of the A2 to the same potential. The result is that both terminals
of R1 are equipotential; that is, no current flows. Because there
is no current flow in R1, the same condition exists for R2; thus,
the output of the circuit tracks the input signal. When the input
signal is below 0 V, the output voltage of A1 is forced to 0 V.
This condition now forces A2 to operate as an inverting voltage
follower because the noninverting terminal of A2 is also at 0 V.
The output voltage at VOUTA is then a full-wave rectified version
of the input signal. If needed, a buffered, half-wave rectified
version of the input signal is available at VOUTB.
R11
100k
V
OU
T
R1
2.67k
R3
2.67k
A1
1/4
OP491
3V
V
IN
R6
100k
0.01F
C5
A3
R12
499
C6
1.5V
1F
3V
R9
1M
R10
1M
C4
1F
C2
R4
2.67k
A2
R5
1.33k
(2.67k ÷ 2) R7
1k
R8
1k
C1
1F1F
R2
2.67k
1
2
4
3
11
1/4
OP491 7
6
5
9
1/4
OP491
10
8
00294-076
C3
2F
(1F × 2)
10
(1V/DIV)
(0.5V/DIV)
(0.5V/DIV)
TIME (200s/DIV)
R1
100k
A1
5V
V
IN
2V p-
p
<2kHz
R2
100k
1/2
OP291
A2
V
OUT
A
V
OUT
B
FULL-WAVE
RECTIFIED
OUTPUT
HALF-WAVE
RECTIFIED
OUTPUT
6
7
5
1/2
OP291
2
1
3
4
8
1V 500mV
V
OUT
A
V
IN
V
OUT
B
90
100
0%
00294-077
500mV 200s
Figure 72. A 3 V Single-Supply, 50 Hz/60 Hz Active Notch Filter
with False Ground
Amplifier A3 is the heart of the false ground bias circuit.
It buffers the voltage developed by R9 and R10 and is the
reference for the active notch filter. Because the OP491
exhibits a rail-to-rail input common-mode range, R9 and R10
are chosen to split the 3 V supply symmetrically. An in-the-loop
compensation scheme used around the OP491 allows the op
amp to drive C6, a 1 µF capacitor, without oscillation. C6
maintains a low impedance ac ground over the operating
frequency range of the filter.
Figure 73. Single-Supply, Half-Wave, and Full-Wave Rectifiers
Using an OP291
OP191/OP291/OP491
Rev. E | Page 23 of 24
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 74. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8) [S-Suffix]
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
45°
Figure 75. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-14) [S-Suffix]
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BSC
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 76. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
OP191/OP291/OP491
Rev. E | Page 24 of 24
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
14
17
8
0.100 (2.54)
BSC
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 77. 14-Lead Plastic Dual In-Line Package [PDIP]
(N-14)
Dimensions shown s and (millimeters)
ORDERING GUIDE
Temperature Range Package Description Package Option
[P-Suffix]
in inche
Model1
OP191GS −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix]
OP191GS-REEL −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix]
OP191GS-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix]
OP191GSZ
−40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix]
OP191GSZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix]
OP191GSZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix]
OP291GS −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix]
OP291GS-REEL −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix]
OP291GS-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix]
OP291GSZ −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix]
OP291GSZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix]
OP291GSZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix]
OP491GP −40°C to +125°C 14-Lead PDIP N-14 [P-Suffix]
OP491GPZ −40°C to +125°C 14-Lead PDIP N-14 [P-Suffix]
OP491GRU-REEL −40°C to +125°C 14-Lead TSSOP RU-14
OP491GRUZ-REEL −40°C to +125°C 14-Lead TSSOP RU-14
OP491GS −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix]
OP491GS-REEL −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix]
OP491GS-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix]
OP491GSZ −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix]
OP491GSZ-REEL −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix]
OP491GSZ-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix]
1 Z = RoHS Compliant Part.
©1994–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00294-0-4/10(E)
