MC33269DR2012G - ON SEMICONDUCTOR

July, 2016 − Rev. 11

1Publication Order Number:

MC10E195/D

MC10E195, MC100E195

5 V ECL Programmable

Delay Chip

Description

The MC10E/100E195 is a programmable delay chip (PDC)

designed primarily for clock de-skewing and timing adjustment. It

provides variable delay of a differential ECL input transition.

The delay section consists of a chain of gates organized as shown in

the logic symbol. The first two delay elements feature gates that have

been modified to have delays 1.25 and 1.5 times the basic gate delay of

approximately 80 ps. These two elements provide the E195 with a

digitally-selectable resolution of approximately 20 ps. The required

device delay is selected by the seven address inputs D[0:6], which are

latched on chip by a high signal on the latch enable (LEN) control.

Because the delay programmability of the E195 is achieved by

purely differential ECL gate delays the device will operate at

frequencies of > 1.0 GHz while maintaining over 600 mV of output

swing.

The E195 thus offers very fine resolution, at very high frequencies,

that is selectable entirely from a digital input allowing for very

accurate system clock timing.

An eighth latched input, D7, is provided for cascading multiple

PDC’s for increased programmable range. The cascade logic allows

full control of multiple PDC’s, at the expense of only a single added

line to the data bus for each additional PDC, without the need for any

external gating.

The VBB pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB

and VCC via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, VBB should be left open.

The 100 Series contains temperature compensation.

Features

•2.0 ns Worst Case Delay Range

•≈20 ps/Delay Step Resolution

•> 1.0 GHz Bandwidth

•On Chip Cascade Circuitry

•PECL Mode Operating Range: VCC = 4.2 V to 5.7 V

with VEE = 0 V

•NECL Mode Operating Range: VCC = 0 V

with VEE = −4.2 V to −5.7 V

•Internal Input 50 kW Pulldown Resistors

•ESD Protection:

♦> 2 kV Human Body Model

♦> 200 V Machine Model

•Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

•Moisture Sensitivity: Level 3 (Pb-Free)

(For Additional Information, see Application Note AND8003/D)

MARKING DIAGRAM*

xxx = 10 or 100

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb-Free Package

PLCC−28

FN SUFFIX

CASE 776−02

MCxxxE195FNG

AWLYYWW

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*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

•Flammability Rating: UL 94 V−0 @ 0.125 in

Oxygen Index: 28 to 34

•Transistor Count = 368 Devices

•These Devices are Pb-Free, Halogen Free

and are RoHS Compliant

See detailed ordering and shipping information on page 9

of this data sheet.

MC10E195, MC100E195

www.onsemi.com

D2 D3 D4 D5 D6 D7 NC

NC NC EN

SET MIN

SET MAX

CASCADE

VCC

VCCO

LEN

25 24 23 22 21 20 19

56 7891011

Figure 1. Pinout: 28-Lead PLCC

(Top View)

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

Warning: All VCC, VCCO, and VEE pins must be externally

connected to Power Supply to guarantee proper operation.

*All VCC and VCCO pins are tied together on the die.

MC10E195

MC100E195

Table 1. PIN DESCRIPTION

PIN FUNCTION

IN/IN

D[0:7]

Q/Q

LEN

SET MIN

SET MAX

CASCADE, CASCADE

VBB

VCC, VCCO

VEE

ECL Signal Input

ECL Input Enable

ECL MUX Select Inputs

ECL Signal Output

ECL Latch Enable

ECL Min Delay Set

ECL Max Delay Set

ECL Cascade Signal

Reference Voltage Output

Positive Supply

Negative Supply

No Connect

Table 2. TRUTH TABLE

EN. LQ = IN

EN H Q Logic Low

LEN L Pass Through D[0:10]

LEN H Latch D[0:10]

SETMIN L Normal Mode

SETMIN H Min Delay Path

SETMAX L Normal Mode

SETMAX H Max Delay Path

Figure 2. Logic Diagram − Simplified

VBB

LEN

SET MIN

SET MAX

111

CASCADE

7 BIT LATCH

LEN Q

LATCH

4 GATES 8 GATES 16 GATES

* 1.25 * 1.5

D0 D1 D2 D3 D4 D5 D6 D7

* delays are 25% or 50% longer than

* standard (standard ≈ 80 ps)

VEE

MC10E195, MC100E195

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Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC PECL Mode Power Supply VEE = 0 V 8 V

VEE NECL Mode Power Supply VCC = 0 V −8 V

VIPECL Mode Input Voltage

NECL Mode Input Voltage

VEE = 0 V

VCC = 0 V

VI ≤ VCC

VI ≥ VEE

−6

Iout Output Current Continuous

Surge

100

IBB VBB Sink/Source ± 0.5 mA

TAOperating Temperature Range 0 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm

500 lfpm

PLCC−28

63.5

43.5

°C/W

qJC Thermal Resistance (Junction-to-Case) Standard Board PLCC−28 22 to 26 °C/W

VEE PECL Operating Range

NECL Operating Range

4.2 to 5.7

−5.7 to −4.2

Tsol Wave Solder (Pb-Free) 265 °C

MC10E195, MC100E195

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Table 4. 10E SERIES PECL DC CHARACTERISTICS (VCCx = 5.0 V; VEE = 0.0 V (Note 1))

Symbol Characteristic

0°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 130 156 130 156 130 156 mA

VOH Output HIGH Voltage (Note 2) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mV

VOL Output LOW Voltage (Note 2) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mV

VIH Input HIGH Voltage (Single-Ended) 3830 3995 4160 3870 4030 4190 3940 4110 4280 mV

VIL Input LOW Voltage (Single-Ended) 3050 3285 3520 3050 3285 3520 3050 3302 3555 mV

VBB Output Voltage Reference 3.62 3.74 3.65 3.75 3.69 3.81 V

VIHCMR Input HIGH Voltage Common Mode Range

(Differential Configuration) (Note 3)

2.2 4.6 2.2 4.6 2.2 4.6 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.3 0.5 0.25 0.3 0.2 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.

2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.

3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.

Table 5. 10E SERIES NECL DC CHARACTERISTICS (VCCx = 0.0 V; VEE = −5.0 V (Note 1))

Symbol Characteristic

0°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 130 156 130 156 130 156 mA

VOH Output HIGH Voltage (Note 2) −1020 −930 −840 −980 −895 −810 −910 −815 −720 mV

VOL Output LOW Voltage (Note 2) −1950 −1790 −1630 −1950 −1790 −1630 −1950 −1773 −1595 mV

VIH Input HIGH Voltage (Single−Ended) −1170 −1005 −840 −1130 −970 −810 −1060 −890 −720 mV

VIL Input LOW Voltage (Single−Ended) −1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445 mV

VBB Output Voltage Reference −1.38 −1.27 −1.35 −1.25 −1.31 −1.19 V

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration) (Note 3)

−2.8 −0.4 −2.8 −0.4 −2.8 −0.4 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.3 0.5 0.065 0.3 0.2 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.

2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.

3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.

MC10E195, MC100E195

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Table 6. 100E SERIES PECL DC CHARACTERISTICS (VCCx = 5.0 V; VEE = 0.0 V (Note 1))

Symbol Characteristic

0°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 130 156 130 156 150 179 mA

VOH Output HIGH Voltage (Note 2) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mV

VOL Output LOW Voltage (Note 2) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mV

VIH Input HIGH Voltage (Single−Ended) 3835 3975 4120 3835 3975 4120 3835 3975 4120 mV

VIL Input LOW Voltage (Single−Ended) 3190 3355 3525 3190 3355 3525 3190 3355 3525 mV

VBB Output Voltage Reference 3.62 3.74 3.62 3.74 3.62 3.74 V

VIHCMR Input HIGH Voltage Common Mode Range

(Differential Configuration) (Note 3)

2.2 4.6 2.2 4.6 2.2 4.6 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.3 0.5 0.25 0.5 0.2 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.

2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.

3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.

Table 7. 100E SERIES NECL DC CHARACTERISTICS (VCCx = 0.0 V; VEE = −5.0 V (Note 1))

Symbol Characteristic

0°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 130 156 130 156 150 179 mA

VOH Output HIGH Voltage (Note 2) −1025 −950 −880 −1025 −950 −880 −1025 −950 −880 mV

VOL Output LOW Voltage (Note 2) −1810 −1705 −1620 −1810 −1745 −1620 −1810 −1740 −1620 mV

VIH Input HIGH Voltage (Single-Ended) −1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880 mV

VIL Input LOW Voltage (Single-Ended) −1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475 mV

VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V

VIHCMR Input HIGH Voltage Common Mode Range

(Differential Configuration) (Note 3)

−2.8 −0.4 −2.8 −0.4 −2.8 −0.4 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.3 0.5 0.25 0.5 0.2 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.

2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.

3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.

MC10E195, MC100E195

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Table 8. AC CHARACTERISTICS (VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 1))

Symbol Characteristic

0°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

fMAX Maximum Toggle Frequency > 1.0 GHz

tPLH

tPHL

Propagation Delay

IN to Q; Tap = 0

IN to Q; Tap = 127

EN to Q; Tap = 0

D7 to CASCADE

1210

3200

1250

300

1360

3570

1450

450

1510

3970

1650

700

1240

3270

1275

300

1390

3630

1475

450

1540

4030

1675

700

1440

3885

1350

300

1590

4270

1650

450

1765

4710

1950

700

tRANGE Programmable Range

tPD (max)−tPD (min) 2000 2175 2050 2240 2375 2580

DtStep Delay (Note 2)

D0 High

D1 High

D2 High

D3 High

D4 High

D5 High

D6 High

115

250

505

1000

136

272

544

1088

105

180

325

620

1190

115

250

515

1030

17.5

140

280

560

1120

105

180

325

620

1220

140

305

620

1240

168

336

672

1344

120

205

380

740

1450

Lin Linearity (Note 3) D1 D0 D1 D0 D1 D0

tSKEW Duty Cycle Skew

tPHL−tPLH (Note 4) ±30 ±30 ±30

tJITTER Random Clock Jitter (RMS) < 5 < 5 < 5 ps

tsSetup Time

D to LEN

D to IN (Note 5)

EN to IN (Note 6)

200

800

200

0 200

800

200

0 200

800

200

thHold Time

LEN to D

IN to EN (Note 7)

500

250 500

250

tRRelease Time

EN to IN (Note 8)

SET MAX to LEN

SET MIN to LEN

300

800

300

800

300

800

tjit Jitter < 5 < 5 < 5 ps

Output Rise/Fall Time

20−80% (Q)

20−80% (CASCADE)

125

300

225

450

325

650

125

300

225

450

325

650

125

300

225

450

325

650

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

1. 10 Series: VEE can vary −0.46 V / +0.06 V.

100 Series: VEE can vary −0.46 V / +0.8 V.

2. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations

of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.

3. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for

increasing binary counts on the control inputs Dn). Typically the device will be monotonic to the D0 input, however under worst case conditions

and process variation, delays could decrease slightly with increasing binary counts when the D0 input is the LSB. With the D1 input as the

Least Significant Bit (LSB), the device is guaranteed to be monotonic over all specified environmental conditions and process variation.

4. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.

5. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.

6. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than

±75 mV to that IN/IN transition.

7. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response

greater than ±75 mV to that IN/IN transition.

8. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets

the specified IN to Q propagation delay and transition times.

MC10E195, MC100E195

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VCCO

ADDRESS BUS (A0-A6)

INPUT

LEN

VEE

VBB

SET MIN

SET MAX

CASCADE

VCC

VCCO

LEN

VEE

VBB

SET MIN

SET MAX

CASCADE

VCC

VCCO

OUTPUT

E195

Chip #1

E195

Chip #2

Figure 3. Cascading Interconnect Architecture

Cascading Multiple E195’s

To increase the programmable range of the E195 internal

cascade circuitry has been included. This circuitry allows for

the cascading of multiple E195’s without the need for any

external gating. Furthermore this capability requires only

one more address line per added E195. Obviously cascading

multiple PDC’s will result in a larger programmable range

however this increase is at the expense of a longer minimum

delay.

Figure 3 illustrates the interconnect scheme for cascading

two E195’s. As can be seen, this scheme can easily be

expanded for larger E195 chains. The D7 input of the E195

is the cascade control pin. With the interconnect scheme of

Figure 3 when D7 is asserted it signals the need for a larger

programmable range than is achievable with a single device.

An expansion of the latch section of the block diagram is

pictured below. Use of this diagram will simplify the

explanation of how the cascade circuitry works. When D7

of chip #1 above is low the cascade output will also be low

while the cascade bar output will be a logical high. In this

condition the SET MIN pin of chip #2 will be asserted and

thus all of the latches of chip #2 will be reset and the device

will be set at its minimum delay. Since the RESET and SET

inputs of the latches are overriding any changes on the

A0−A6 address bus will not affect the operation of chip #2.

Chip #1 on the other hand will have both SET MIN and

SET MAX de-asserted so that its delay will be controlled

entirely by the address bus A0−A6. If the delay needed is

greater than can be achieved with 31.75 gate delays

(1111111 on the A0−A6 address bus) D7 will be asserted to

signal the need to cascade the delay to the next E195 device.

When D7 is asserted the SET MIN pin of chip #2 will be

de-asserted and the delay will be controlled by the A0−A6

address bus. Chip #1 on the other hand will have its SET

MAX pin asserted resulting in the device delay to be

independent of the A0−A6 address bus.

When the SET MAX pin of chip #1 is asserted the D0 and

D1 latches will be reset while the rest of the latches will be

set. In addition, to maintain monotonicity an additional gate

delay is selected in the cascade circuitry. As a result when D7

of chip #1 is asserted the delay increases from 31.75 gates

to 32 gates. A 32 gate delay is the maximum delay setting for

the E195.

To expand this cascading scheme to more devices one

simply needs to connect the D7 input and CASCADE

outputs of the current most significant E195 to the new most

significant E195 in the same manner as pictured in Figure 3.

The only addition to the logic is the increase of one line to

the address bus for cascade control of the second PDC.

SET MIN

ET MAX

TO SELECT MULTIPLEXERS

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

D0 Q0

LEN

Reset Reset

D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7

LEN LEN LEN LEN LEN LEN LEN

CASCADE

Figure 4. Expansion of the Latch Section of the E195 Block Diagram

Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset

MC10E195, MC100E195

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−5.5

−4.7

−15

−4.5−4.9−5.1 −4.3

VEE, (V)

DELAY VARIATION (ps)

−5

−10

−5.3 0

1600

1575

1550

1525

1375

503020 60

1500

1475

1450

1425

1400

1350

1325

1300

70 80 90 100

Temperature (°C)

Figure 5. Change in Delay vs. Change in

Supply Voltage

Figure 6. Delay vs. Temperature (Fixed Path)

PROPAGATION DELAY (ps)

4400

4300

4200

4100

3500

503020 60

4000

3900

3800

3700

3600

3400

70 80 90 100

Figure 7. Delay vs. Temperature (Max. Delay).

Temperature (°C)

064

2000

32 96

3600

2800

1200

128

Figure 8. 100E195 Temperature Effects on

Delay.

Tap Delay

PROPAGATION DELAY (ps)

85°C

0°C

040

503020 60

70 80 90 100

Figure 9. Delay vs. Temperature (Per Gate).

Temperature (°C)

04020 60

3900

3400

2900

2400

1900

1400 80 120100

Figure 10. E195 Delay Linearity.

Tap Selection

PROPAGATION DELAY (ps)

DELAY (ps)

Note:

All Taps Selected

SET = H, Temp. = 0°C

MC10E195, MC100E195

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Figure 11. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices)

Driver

Device

Receiver

Device

Q D

Zo = 50 W

50 W50 W

VTT

VTT = VCC − 2.0 V

ORDERING INFORMATION

Device Package Shipping†

MC10E195FNR2G PLCC−28

(Pb-Free)

500 / Tape & Reel

MC100E195FNG PLCC−28

(Pb-Free)

37 Units / Rail

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Resource Reference of Application Notes

AN1405/D −ECL Clock Distribution Techniques

AN1406/D −Designing with PECL (ECL at +5.0 V)

AN1503/D −ECLinPSt I/O SPiCE Modeling Kit

AN1504/D −Metastability and the ECLinPS Family

AN1568/D −Interfacing Between LVDS and ECL

AN1672/D −The ECL Translator Guide

AND8001/D −Odd Number Counters Design

AND8002/D −Marking and Date Codes

AND8020/D −Termination of ECL Logic Devices

AND8066/D −Interfacing with ECLinPS

AND8090/D −AC Characteristics of ECL Devices

MC10E195, MC100E195

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PACKAGE DIMENSIONS

28 LEAD PLLC

FN SUFFIX

CASE 776−02

ISSUE F

−N−

−M−

−L−

Y BRK

28 1

VIEW S

L-M

0.010 (0.250) N S

L-M

0.007 (0.180) N S

0.004 (0.100)

SEATING

PLANE

L-M

0.007 (0.180) N S

−T−

L-M

0.010 (0.250) N S

L-M

0.007 (0.180) N S

L-M

0.007 (0.180) N S

G1X

VIEW D−D

L-M

0.007 (0.180) N S

VIEW S

L-M

0.007 (0.180) N S

NOTES:

1. DATUMS -L-, -M-, AND -N- DETERMINED

WHERE TOP OF LEAD SHOULDER EXITS

PLASTIC BODY AT MOLD PARTING LINE.

2. DIMENSION G1, TRUE POSITION TO BE

MEASURED AT DATUM -T-, SEATING PLANE.

3. DIMENSIONS R AND U DO NOT INCLUDE

MOLD FLASH. ALLOWABLE MOLD FLASH IS

0.010 (0.250) PER SIDE.

4. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

5. CONTROLLING DIMENSION: INCH.

6. THE PACKAGE TOP MAY BE SMALLER THAN

THE PACKAGE BOTTOM BY UP TO 0.012

(0.300). DIMENSIONS R AND U ARE

DETERMINED AT THE OUTERMOST

EXTREMES OF THE PLASTIC BODY

EXCLUSIVE OF MOLD FLASH, TIE BAR

BURRS, GATE BURRS AND INTERLEAD

FLASH, BUT INCLUDING ANY MISMATCH

BETWEEN THE TOP AND BOTTOM OF THE

PLASTIC BODY.

7. DIMENSION H DOES NOT INCLUDE DAMBAR

PROTRUSION OR INTRUSION. THE DAMBAR

PROTRUSION(S) SHALL NOT CAUSE THE H

DIMENSION TO BE GREATER THAN 0.037

(0.940). THE DAMBAR INTRUSION(S) SHALL

NOT CAUSE THE H DIMENSION TO BE

SMALLER THAN 0.025 (0.635).

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.485 0.495 12.32 12.57

B0.485 0.495 12.32 12.57

C0.165 0.180 4.20 4.57

E0.090 0.110 2.29 2.79

F0.013 0.021 0.33 0.53

G0.050 BSC 1.27 BSC

H0.026 0.032 0.66 0.81

J0.020 --- 0.51 ---

K0.025 --- 0.64 ---

R0.450 0.456 11.43 11.58

U0.450 0.456 11.43 11.58

V0.042 0.048 1.07 1.21

W0.042 0.048 1.07 1.21

X0.042 0.056 1.07 1.42

Y--- 0.020 --- 0.50

Z2 10 2 10

G1 0.410 0.430 10.42 10.92

K1 0.040 --- 1.02 ---

__ __

MC10E195, MC100E195

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