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DEVICE INFORMATIONFEATURES
LNAO
GND
VDDA
LOP
GND
LON
GND
GND
LNAI
VDDLO
RFAGC
VDD2
IFOP
GND
IFON
MXRI
VDDIF
RFATTN
IFB
GND
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DESCRIPTION
TRF1216
SLWS172A – APRIL 2005 – REVISED DECEMBER 2005
3.5-GHz, HIGH DYNAMIC RANGE, LOW-NOISE DOWN-CONVERTER
•Performs First Down-Conversion in 3.5-GHzRadios (3300–3800 MHz)•Integrated LNA/Mixer/IF Amp/LO Buffer•Provision for External ImageReject/Band-Pass Filter•Low Noise-Figure/High Linearity•Digital 10-dB Attenuator for High-LevelSignals
•Frequency Range: 3.3–3.8 GHz•28 dB of Gain with 20 dB of Gain Control(10-dB Fixed)•2.5-dB Noise Figure, Typical•LO Drive Level = 0 dBm, Typical
The TRF1216 is the first of two integrated circuits used in the receiver section of Texas Instruments’ 3.5-GHzradio chipset. The TRF1216 down-converts the 3.5-GHz input frequency to an intermediate frequency in therange of 400 MHz to 500 MHz. The device provides a differential output that passes through a SAW filter beforeconnecting to a second down converter. For the best performance, Texas Instruments TRF1212 should be usedto perform both the second down conversion and also provide the local oscillator for the TRF1216.
The TRF1216 includes a LNA with switchable attenuation, a balanced mixer, a variable gain IF amplifier and adifferential LO Buffer for improved performance. In order to provide exceptional image rejection and extra jammerimmunity, the TRF1216 offers a signal path to an off-chip filter. Specifications are provided assuming an in-band2-dB insertion loss filter. To maximize input dynamic range, a 10-dB switchable attenuator is provided in the RFpath as well as 10 dB of analog IF gain control. After the image reject filter, an on-chip Balun converts the signalfrom single ended to differential in order to provide better noise immunity at the mixer.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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BLOCK DIAGRAM
LNAI
Mixer
Dual Stage-LNA
LO Buffer
VGA
LOP
VDD1
RFAGC
LON
BALUN
LNAO MXRI
IFOP
IFON
RFATTN VDDLO
IFB
VDDIFVDD2
GND
B0084-01
TRF1216
SLWS172A – APRIL 2005 – REVISED DECEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the deviceplaced in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
The detailed block diagram and the pin-out of the ASIC are shown in Figure 1 and Table 1.
Figure 1. Detailed Block Diagram of TRF1216
TERMINAL FUNCTIONS
TERMINAL
I/O TYPE DESCRIPTIONNO. NAME
1 LNAO O Analog LNA Output, 50 Ω, ac-coupled2 VDD1 I Power LNA1 DC Bias (+5 V nominal)3, 4, 6, 9,
GND – – Ground16, 195 LNAI I Analog RF input – Needs dc block and input matching for optimum noise figure7 LOP I Analog LO input positive, ac coupled8 LON I Analog LO input negative, ac coupled10 VDDLO I Power LO DC Bias (+5 V nominal)Not connected for normal operation. IF Bias Adjustment. Do not ground this pin or connect to any11 IFB – –
other pin.12 VDDIF I Power IF Bias Network dc Bias (+5 V nominal)13 IFON O Analog IF output and bias (see the application schematic for connections).14 IFOP O Analog IF output and bias (see the application schematic for connections).Input voltage for analog gain control V
RFAGC
= 0 V to 1.5 V Max gain at V
RFAGC
= 0 V Min gain at15 RFAGC I Analog
V
RFAGC
= 1.5 VTTL control for switched attenuator TTL low – Attenuator switched in TTL high – Attenuator17 RFATTN I Digital
switched out18 MXRI I Analog Mixer Input 50 Ω20 VDD2 – Power LNA2 dc bias (+5 V nominal)Back GND – – Back of package has metal base that must be grounded for thermal and RF performance.
2
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ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
TRF1216
SLWS172A – APRIL 2005 – REVISED DECEMBER 2005
VALUES UNIT
V
DD
DC supply voltage, VDD 0 to 5.5 VP
IN
RF input power 10 dBmT
J
Junction temperature 200 °CP
D
Power dissipation 1100 mWV
D
Digital input voltage –0.3 to 5.5 VV
A
Analog input voltage –0.3 to 5 Vθ
JC
Thermal resistance junction-to-case
(1)
9.1 °C/WT
stg
Storage temperature –40 to 105 °CT
op
Operating temperature –40 to 85 °CLead temperature (40 Sec Max) 260 °C
(1) Thermal resistance is junction to ambient assuming thermal pad with nine thermal vias under package metal base. See therecommended PCB layout.
The characteristics listed in the following tables are at V
CC
= 5 V, T
A
= 25 °C unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC CHARACTERISTICS
V
DD
Supply voltage 5 5.5 VI
DD
Total supply current 175 200 mAI
LNA1
LNA1 supply current Pin 2 (VDD1) 35 mAI
LNA2
LNA2 supply current Pin 20 (VDD2) 35 mAI
IF
IF AMP supply current Pin 12 (VDDIF) plus IF drain bias on pins 13 55 mAand 14 (IFOP, IFON)I
LO
LO supply current Pin 10 (VDDLO) 50 mAV
AGC
Gain control voltage 0 2 VI
AGC
Gain control current 0 100 µAV
IH
Input high voltage 2.5 5 VV
IL
Input low voltage 0 0.8 VI
IH
Input high current 300 µAI
IL
Input low current –50 µA
3
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DOWNCONVERTER CHARACTERISTICS
TRF1216
SLWS172A – APRIL 2005 – REVISED DECEMBER 2005
Unless otherwise stated V
DD
= 5 V, FRF = 3500 MHz, T
A
= 25 °C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
F
RF
RF input frequency 3300 3800 MHzF
LO
LO input frequency 2800 3400 MHzF
IF
IF output frequency 400 480 500 MHzG Maximum gain V
AGC
= 0 V, RFATTN disabled, Measured into 100- Ω27 30 33 dBdifferential load∆
AGC
Analog gain control range V
AGC
from 0 to 1.5 V, Any RFATTN setting. Measured 7 10 dBinto 100- Ωdifferential load∆
ATTN
Switched attenuator range RFATTN from high-to-low, any VAGC setting. 8.5 10 11.5 dBMeasured into 100- Ωdifferential loadG
HG
Gain flatness full band Any 200-MHz band 1 2 dBG
NB
Gain flatness / 6 MHz Any 6-MHz band 0.4 dBV
AGC
= 0 V, RFATTN disabled 2.5V
AGC
= 0 V, RFATTN enabled 4.8NF Noise figure
(1)
dBV
AGC
= 1.5 V, RFATTN disabled 3.2V
AGC
= 1.5 V, RFATTN enabled 6.8V
AGC
= 0 V, RFATTN disabled –17V
AGC
= 0 V, RFATTN enabled –6IP-1dB Input power at 1-dB compression dBmV
AGC
= 1.5 V, RFATTN disabled –10V
AGC
= 1.5 V, RFATTN enabled –4V
AGC
= 0 V, RFATTN disabled –7V
AGC
= 0 V, RFATTN enabled -1IIP3 Input 3rd order intercept point dBmV
AGC
= 1.5 V, RFATTN disabled –5V
AGC
= 1.5 V, RFATTN enabled 5P
LO
LO input power Referenced to 100- Ωdifferential 0 dBmLO to MXRI leakage LO input = 3 dBm, V
AGC
= 0 V –35 –45 dBLO to IF leakage LO input = 3 dBm, V
AGC
= 0 V –40 –50 dBLNAO to RXI isolation F
RF
F = 3300 to 3800 MHz, RFATTN = TTL High 40 dB
(1) Assured by lab characterization/design and not subject to production test.
4
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TYPICAL CHARACTERISTICS
f − Frequency − MHz
0
5
10
15
20
25
30
35
40
3300 3350 3400 3450 3500 3550 3600 3650 3700 3750 3800
Gain − dB
VAGC = 0 V
G001
Gain With Attenuator Disabled
Gain With Attenuator Enabled
−40°C
25°C
85°C
f − Frequency − MHz
0
5
10
15
20
25
30
3300 3350 3400 3450 3500 3550 3600 3650 3700 3750 3800
Gain − dB
VAGC = 1.5 V
G002
Gain With Attenuator Enabled
−40°C
25°C
85°C
Gain With Attenuator Disabled
TRF1216
SLWS172A – APRIL 2005 – REVISED DECEMBER 2005
Measurements resulting in the following graphs were taken on the evaluation board of the ASIC (see Figure 9 ).
Figure 2. Gain vs Frequency for VAGC = 0 V
Figure 3. Gain vs Frequency for VAGC = 1.5 V
5
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VAGC − Analog Gain Control V oltage − V
0
5
10
15
20
25
30
0.00 0.25 0.50 0.75 1.00 1.25 1.50
Gain − dB
G003
Attenuator Disabled
3550 MHz
3800 MHz
Attenuator Enabled
3300 MHz
TA = 25°C
f − Frequency − MHz
−25
−20
−15
−10
−5
0
5
3300 3350 3400 3450 3500 3550 3600 3650 3700 3750 3800
Input P1dB − dBm
TA = 25°C
G004
Attenuator Disabled, VAGC = 1.5 V
Attenuator Enabled, VAGC = 1.5 V
Attenuator Disabled, VAGC = 0 V
Attenuator Enabled, VAGC = 0 V
TRF1216
SLWS172A – APRIL 2005 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS (continued)
Figure 4. Gain vs VAGC for Different Frequencies, (T
A
= 25 °C)
Figure 5. Input P1dB vs Frequency, (T
A
= 25 °C)
6
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f − Frequency − MHz
−15
−10
−5
0
5
10
3300 3350 3400 3450 3500 3550 3600 3650 3700 3750 3800
Input IP3 − dBm
TA = 25°C
G005
Attenuator Disabled, VAGC = 1.5 V
Attenuator Enabled, VAGC = 1.5 V
Attenuator Disabled, VAGC = 0 V
Attenuator Enabled, VAGC = 0 V
0
5
10
15
20
25
30
3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9
Frequency [GHz]
Gain [dB]
1
2
3
4
5
6
7
NF [dB]
−40C
85C25C
−40C
85C
25C
TRF1216
SLWS172A – APRIL 2005 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS (continued)
Figure 6. Input IP3 vs Frequency, (T
A
= 25 °C)
Figure 7. LNA Noise Figure vs Frequency With VAGC = 0 V
7
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APPLICATION INFORMATION
Dia. 15 Mil
1 oz. Copper + ½ oz. Copper Plated
Upper and Lower Surfaces
Layer 2: 1 oz. Copper
Layer 3: 1 oz. Copper
½oz. Copper Plated
DuPont CB 100
Conductive ViaPlug
8 Mil
Prepreg
35 Mil
Layer 4
Layer 1
M0020-02
10 Mil Core FR4
10 Mil Core FR4
TRF1216
SLWS172A – APRIL 2005 – REVISED DECEMBER 2005
A typical application schematic is shown in Figure 9 .
The PCB material recommendations are shown in Table 1 and Figure 8 .
Table 1. PCB Recommendations
Board Material FR4Board Material Core Thickness 10 milCopper Thickness (starting) 1 ozPrepreg Thickness 8 milRecommended Number of Layers 4Via Plating Thickness 1/2 ozFinal Plate White immersion tinFinal Board Thickness 33–37 mil
NOTE: Top and bottom surface finish: copper flash with 50–70 µin white tin immersion.
Figure 8. PCB Construction and Via Cross Section
8
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TRF1216
SLWS172A – APRIL 2005 – REVISED DECEMBER 2005
A. Place 100-pF capacitors close to package pins.B. Place 22-nH inductors close to package pins.
Figure 9. Recommended Application Schematic
9
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M0022-02
0.25 TYP
Notes: 9 Via Holes, Each 0.38 mm.
Solder Mask. No Solder Mask Under Chip, On Lead Pads or On Ground Connections.
Dimensions in mm
DIA 0.38 TYP
PIN 1
0.50 TYP
1.00 TYP
0.60 TYP
1.00 TYP
0.20 TYP
2.80
2.80
2.00
2.00
TRF1216
SLWS172A – APRIL 2005 – REVISED DECEMBER 2005
Figure 10. Recommended Pad Layout
10
PACKAGE OPTION ADDENDUM
www.ti.com 21-Jul-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TRF1216IRGPR ACTIVE QFN RGP 20 3000 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
TRF1216IRGPRG3 ACTIVE QFN RGP 20 3000 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
TRF1216IRGPT ACTIVE QFN RGP 20 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
TRF1216IRGPTG3 ACTIVE QFN RGP 20 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TRF1216IRGPR QFN RGP 20 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2
TRF1216IRGPT QFN RGP 20 250 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TRF1216IRGPR QFN RGP 20 3000 338.1 338.1 20.6
TRF1216IRGPT QFN RGP 20 250 338.1 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jul-2012
Pack Materials-Page 2
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