256K (32K x 8) St atic RAM
CY62256
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05248 Rev. *F Revised August 3, 2006
Features
•High speed
—55 ns
• Temperature Range s
— Commercial: 0°C to 70°C
— Industrial: –40 °C to 85°C
— Automotive: –40°C to 125°C
• Voltage range
— 4.5V – 5.5V
• Low active power and stan dby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/po we r
• A vaila ble in a Pb-free an d non Pb-fr ee st an dard 28 -pin
narrow SOIC, 28-pin TSOP-1, 28-pin Reverse TSOP-1
and 28-pin DIP packages
Functional Description[1]
The CY62256 is a high-performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and Tri-state drivers. This device has an
automatic power-down feature, reducing the power
consumption by 99.9% when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/outpu t pin s
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW ,
while WE remains inac tive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
A9
A8
A7
A6
A5
A4
A3
A2
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUTBUFFER
POWER
DOWN
WE
OE
I/O0
CE
I/O1
I/O2
I/O3
I/O7
I/O6
I/O5
I/O4
A10
A13
A11
A12
A
A14
A1
0
Logic Block Diagram
32K × 8
ARRAY
CY62256
Document #: 38-05248 Rev. *F Page 2 of 14
Pin Configurations
Product Portfolio
Product
VCC Range (V) Speed
(ns)
Power Dissipation
Operating, ICC
(mA) Standby, ISB2
(µA)
Min. Typ.[2] Max. Typ.[2] Max. Typ.[2] Max.
CY62256L Com’l/Ind’l 4.5 5.0 5.5 55/70 25 50 2 50
CY62256LL Commercial 70 25 50 0.1 5
CY62256LL Industrial 55/70 25 50 0.1 10
CY62256LL Automotive 55 25 50 0.1 15
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
Top View
Narrow SOIC
12
13
25
28
27
26
GND
A6
A7
A8
A9
A10
A11
A12
A13
WE
VCC
A4
A3
A2
A1
I/O7
I/O6
I/O5
I/O4
A14
A5
I/O0
I/O1
I/O2
CE
OE
A0
I/O3
22
23
24
25
26
27
28
1
2
510
11
15
14
13
12
16
19
18
17
3
4
20
21
7
68
9
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
0
CE
I/O
7
I/O
6
I/O
5
GND
I/O
2
I/O
1
I/O
4
I/O
0
A
14
A
10
A
11
A
13
A
12
I/O
3
TSOP I
Top View
(not to scale)
Reverse Pinout
22
23
24
25
26
27
28
1
2
510
11
15
14
13
12
16
19
18
17
3
4
20
21
7
68
9
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
0
CE
I/O
7
I/O
6
I/O
5
GND
I/O
2
I/O
1
I/O
4
I/O
0
A
14
A
10
A
11
A
13
A
12
I/O
3
TSOP I
Top View
(not to scale)
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
Top View
DIP
12
13
25
28
27
26
GND
A6
A7
A8
A9
A10
A11
A12
A13
WE
VCC
A4
A3
A2
A1
I/O7
I/O6
I/O5
I/O4
A14
A5
I/O0
I/O1
I/O2
CE
OE
A0
I/O3
Pin Definitions
Pin Number Type Description
1–10, 21, 23–26 Input A0–A14. Address Inputs
11–13, 15– 19, Input/Output I/O0–/O7. Data lines. Used as input or output lines depend ing on operation
27 Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted
20 Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip
22 Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pi ns
behave as outputs. When deasserted HIGH, I/O pins are Tri-st ated, and act as input
data pins
14 Ground GND. Ground for the device
28 Power Supply VCC. Power supply for the device
Note:
2. T ypical specifications are the mean value s measured over a large sample size across normal prod uction process variations and are taken at nominal conditions
(TA = 25°C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
CY62256
Document #: 38-05248 Rev. *F Page 3 of 14
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .............................. ...–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)............ .............. ... ... ..............–0.5V to +7V
DC Voltage Applied to Outputs
in High-Z S tate[3]....................................–0.5V to VCC + 0.5V
DC Input Voltage[3] ......... .............. .........–0.5V to V CC + 0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current............... ... ... ............................... > 200 mA
Operating Range
Range Ambient Temperature (TA)[4] VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
Automotive –40°C to +125°C 5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
CY62256−55 CY62256−70
UnitMin. Typ.[2] Max. Min. Typ.[2] Max.
VOH Output HIGH Voltage VCC = Min., I OH = −1.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., I OL = 2.1 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC
+0.5V 2.2 VCC
+0.5V V
VIL Input LOW Voltage –0.5 0.8 –0.5 0 .8 V
IIX Input Leakage Current GND < VI < VCC –0.5 +0.5 –0.5 +0.5 µA
IOZ Output Leakage Current GND < VO < V CC, Output Disabled –0.5 +0.5 –0.5 +0.5 µA
ICC VCC Operating Supply
Current VCC = 5.5V,
IOUT = 0 mA,
f = fMax = 1/tRC
L25502550mA
LL 25 50 25 50
ISB1 Automatic CE
Power-down Current—
TTL Inputs
VCC = 5.5V, CE > VIH,
VIN > VIH or VIN < VIL,
f = fMax
L 0.4 0.6 0.4 0.6 mA
LL 0.3 0.5 0.3 0.5
ISB2 Automatic CE
Power-down Current—
CMOS Inputs
VCC = 5.5V,
CE > VCC − 0.3V
VIN > VCC − 0.3V, or
VIN < 0.3V, f = 0
L250250µA
LL - Com’l 0.1 5 0.1 5
LL - Ind’l 0.1 10 0.1 10
LL - Auto 0.1 15
Capacitance[5]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz, VCC = VCC(typ.) 6pF
COUT Output Capacitance 8 pF
Thermal Resistance[5]
Parameter Description Test Con dition s DIP SOIC TSOP RTSOP Unit
ΘJA Thermal Resistance
(Junction to Ambient) Still Air , soldered on a 4.25 x 1.125 inch,
2-layer printed circuit board 75.61 76.56 93.89 93.89 °C/W
ΘJC Thermal Resistance
(Junction to Case) 43.12 36.07 24.64 24.64 °C/W
Notes:
3. VIL (min.) = −2.0V for pulse durations of less than 20 ns.
4. TA is the “Instant-On” case tempe rature.
5. Tested initially and afte r any design or process changes that may affect these parameters.
CY62256
Document #: 38-05248 Rev. *F Page 4 of 14
AC Test Loads and Waveforms
Data Retention Characteristics
Parameter Description Conditions[6] Min. Typ.[2] Max. Unit
VDR VCC for Data Retention 2.0 V
ICCDR Data Retention Current L VCC = 2.0V, CE > VCC − 0.3V,
VIN > VCC − 0.3V, or VIN < 0.3V 250µA
LL - Com’l 0.1 5 µA
LL - Ind’l 0.1 10 µA
LL - Auto 0.1 10 µA
tCDR[5] Chip Deselect to Data Retention Time 0 ns
tR[5] Operation Recovery T ime tRC ns
Data Retention Waveform
Note:
6. No input may exceed VCC + 0.5V.
3.0V
5V
OUTPUT
R1 1800Ω
R2
990Ω
100 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
<5ns <5ns
5V
OUTPUT
R1 1800Ω
R2
990Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT 1.77V
Equivalent to: THE VENIN EQUIVALENT
ALL INPUT PULSES
639Ω
VCC(min)
VCC(min)
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
VCC
CY62256
Document #: 38-05248 Rev. *F Page 5 of 14
Switching Characteristics Over the Operating Range[7]
Parameter Description
CY62256−55 CY62256−70
UnitMin. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 55 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 5 5 ns
tACE CE LOW to Data Valid 55 70 ns
tDOE OE LOW to Data Valid 25 35 ns
tLZOE OE LOW to Low-Z[8] 55ns
tHZOE OE HIGH to High-Z[8, 9] 20 25 ns
tLZCE CE LOW to Low-Z[8] 55ns
tHZCE CE HIGH to High-Z[8, 9] 20 25 ns
tPU CE LOW to Power-up 0 0 ns
tPD CE HIGH to Power-down 55 70 ns
Write Cycle[10, 11]
tWC Write Cycle Time 55 70 ns
tSCE CE LOW to Write End 45 60 ns
tAW Address Set-up to Write End 45 60 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-up to Write Start 0 0 ns
tPWE WE Pulse Width 40 50 ns
tSD Data Set-up to Write End 25 30 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High-Z[8, 9] 20 25 ns
tLZWE WE HIGH to Low-Z[8] 55ns
Notes:
7. Test conditions assume signal transition time of 5 ns or l ess, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100 pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10.The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can
terminate a Write by going HIGH. The data input set-up and hold timing shoul d be referenced to the rising edge of the signal that terminates the Write.
11.The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
CY62256
Document #: 38-05248 Rev. *F Page 6 of 14
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[12, 13]
Read Cycle No. 2 (OE Controlled)[13, 14]
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
Notes:
12.Device is continuously selected. OE, CE = VIL.
13.WE is HIGH for Read cycle.
14.Address valid prior to or coincident with CE transition LOW.
15.Data I/O is high impedance if OE = VIH.
16.If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17.During this period, the I/Os are in output state and input signals should not be applied.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
IMPEDANCE
ICC
ISB
HIGH
DATA OUT
OE
CE
VCC
SUPPLY
CURRENT
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATAINVALID
NOTE 17
DATA I/O
ADDRESS
CE
WE
OE
CY62256
Document #: 38-05248 Rev. *F Page 7 of 14
Write Cycle No. 2 (CE Controlled)[10, 15, 16]
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]
Switching Waveforms (continued)
tWC
tAW
tSA tHA
tHD
tSD
tSCE
DATAINVALID
WE
DATA I/O
ADDRESS
CE
tHD
tSD
tLZWE
tSA
tHA
tAW
tWC
tHZWE
DATAINVALID
NOTE 17
DATA I/O
ADDRESS
WE
CE
CY62256
Document #: 38-05248 Rev. *F Page 8 of 14
Typical DC and AC Characteristics
1.2
1.4
1.0
0.6
0.4
0.2
4.0 4.5 5.0 5.5 6.0
1.6
1.4
1.2
1.0
0.8
−55 25 125
−55 25 125
1.2
1.0
0.8
NORMALIZED tAA
120
100
80
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SOURCE CURRENT (mA)
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.0
0.8
1.4
1.1
1.0
0.9
4.0 4.5 5.0 5.5 6.0
NORMALIZED tAA
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SINK CURRENT (mA)
0
80
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
0.6
0.4
0.2
0.0
NORMALIZED ICC
NORMALIZED ICC, ISB
ICC
ICC
VCC = 5.0V VCC = 5.0V
TA= 25°C
VCC = 5.0V
TA= 25°C
ISB
TA= 25°C
0.6
0.8
0
1.3
1.2
VIN = 5.0V
TA= 25°C
1.4
VCC = 5.0V
VIN = 5.0V
−55 25 105
2.5
2.0
1.5
CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
1.0
0.5
0.0
–0.5
ISB
3.0
STANDBY
VCC = 5.0V
VIN = 5.0V
ISB2 µA
CY62256
Document #: 38-05248 Rev. *F Page 9 of 14
Truth Table
CE WE OE Inputs/Outputs Mode Power
H X X High-Z Deselect/Power-down Standby (ISB)
L H L Data Out Read Active (ICC)
L L X Data In Write Active (ICC)
L H H High-Z O utput Disabled Active (ICC)
Typical DC and AC Characteristics (continued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0 1.0 2.0 3.0 4.0
NORMALIZED IPO
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE 30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELTA t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING 1.25
1.00
0.75
10 20 30 40
NORMALIZED ICC
CYCLE FREQUENCY (MHz)
0.0 5.0 0.0 1000 0.50
VCC = 4.5V
TA= 25°C
VCC =5.0V
TA= 2 5°C
VIN = 0.5V
NORMALIZED ICC vs. CYCLE TIME
CY62256
Document #: 38-05248 Rev. *F Page 10 of 14
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
55 CY62256LL−55SNI 51-85092 28-pin (300-mil Narrow Body) SNC Industrial
CY62256LL−55SNXI 28-pin (300-mil Narrow Body) SNC (Pb-free)
CY62256LL−55ZXI 51-85071 28-pin TSOP I (Pb-free)
CY62256LL−55SNE 51-85092 28-pin (300-mil Narrow Body) SNC Automotive
CY62256LL−55SNXE 28-pin (300-mil Narrow Body) SNC (Pb-free)
CY62256LL−55ZE 51-85071 28-pin TSOP I
CY62256LL−55ZXE 28-pin TSOP I (Pb-free)
CY62256LL−55ZRXE 51-85074 28-pin Reverse TSOP I (Pb-free)
70 CY62256LL−70PC 51-85017 28-pin (600-Mil) Molded DIP Commercial
CY62256LL−70PXC 28-pin (600-Mil) Molded DIP (Pb-free)
CY62256L−70SNC 51-85092 28-pin (300-mil Narrow Body) SNC
CY62256L−70SNXC 28-pin (300-mil Narrow Body) SNC (Pb-free)
CY62256LL−70SNC 28-pin (300-mil Narrow Body) SNC
CY62256LL−70SNXC 28-pin (300-mil Narrow Body) SNC (Pb-free)
CY62256LL−70ZC 51-85071 28-pin TSOP I
CY62256LL−70ZXC 28-pin TSOP I (Pb-free)
CY62256L–70SNI 51-85092 28-pin (300-mil Narrow Body) SNC Industrial
CY62256L–70SNXI 28-pin (300-mil Narrow Body) SNC (Pb-free)
CY62256LL−70SNI 28-pin (300-mil Narrow Body) SNC
CY62256LL−70SNXI 28-pin (300-mil Narrow Body) SNC (Pb-free)
CY62256LL−70ZXI 51-85071 28-pin TSOP I (Pb-free)
CY62256LL−70ZRI 51-85074 28-pin Reverse TSOP I
CY62256LL−70ZRXI 28-pin Reverse TSOP I (Pb-free)
Please contact your local Cypress sales representative for availability of these parts
CY62256
Document #: 38-05248 Rev. *F Page 11 of 14
Package Diagrams
DIMENSIONS IN INCHES MIN.
MAX.
SEATING PLANE
0.090
0.110
0.055
0.065
0.140
0.195
0.015
0.060
0.014
0.022
0.155
0.200
1.380
1.480
0.115
0.160
0.530
0.550
0.070
0.090
114
15 28
REFERENCE JEDEC Ms-020
0.600
0.625
0.610
0.700
0.009
0.012
3° MIN.
28-pin (600-mil) Molded DIP (51-85017)
51-85017-*B
28-pin (300-mil) SNC (Narrow Body) (51-85092)
51-85092-*B
CY62256
Document #: 38-05248 Rev. *F Page 12 of 14
Package Diagrams (continued)
28-pin Thin Small Outline Package Type 1 (8 x 13.4 mm) (51-85071)
51-85071-*G
CY62256
Document #: 38-05248 Rev. *F Page 13 of 14
© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is subject to change wi t hou t n oti ce. C ypr ess S em ic onductor Corporation assumes no resp onsibility f or the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furtherm ore, Cypress doe s not authorize i ts
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All product and company names mentioned in this document are the trademarks of their respective holders.
Package Diagrams (continued)
51-85074-*F
28-pin Reverse Thin Small Outline Package Type 1 (8x13.4 mm) (51-85074)
CY62256
Document #: 38-05248 Rev. *F Page 14 of 14
Document History Page
Document Title: CY62256, 256K (32K x 8) Static RAM
Document Number: 38-05248
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 113454 03/06/02 MGN Change from Spec number: 38-00455 to 38-05248
Remove obsolete parts from ordering info, standardize format
*A 115227 05/23/02 GBI Changed SN Package Diagram
*B 116506 09/04/02 GBI Added footnote 1
Corrected package description in Ordering Information table
*C 238448 See ECN AJU Added Automotive product information
*D 344595 See ECN SYT Added Pb-free packages on page# 10
*E 395936 See ECN SYT Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First St reet” to “198 Champion Court”
Added CY62256L–70SNXI package in the Ordering Information on Page # 10
*F 493277 See ECN VKN Updated Ordering Information table
