140 54112/74112 Dual J-K Negative-Triggered Flip-Flop with Preset and Clear Schottky TTL High-Speed TTL Low-Power Schottky TTL Standard TTL Low-Power TTL Package Package Package Package Package Device Type Device Type Device Type Device Type Device Type C}P|MICF C|PiM|CF C}P|MICF C {P| MiICF Ci|P|M|CF Tl SN54S 112 Jo Q SN5AL S112 JO) Wo A SNPS 112 GING SN74LStl2 2 O[ND FM54S112/FM 98112|DG) FHSALS112,/FMaLsii2 [ 0@ FO FAIRCHILD FG14S112-FO9S112 [Dt FO rerasiiz7reasi2 |r! p@ FO MOTORLA SNT4LSH2 PO} OM74S112 NO OMS4LS U2 oO NSC. DM74L S112 PHILIPS NTAS 112 a N74LS 112 S545 112 F OBO oO SIGNETICS Foisia Bw N74L S112 AD SIEMENS FUJITSU 7S Ma HITACHI HD74S 112 OPO HO?74L S112 PQ MITSUBISH] [oes75 Pa MT4L S112 Po NEC uPB2SI12 Da TAL S112 co TOSHIBA . erish . . : Electrical Characteristics SNS4LS112/SN74LS112 Pin Assignment (Top View) absolute maximum ratings over operating free-air temperature range Supply voltage. Yoo 7v | Operating free-air [snstis | -ssc to 1st 1 2 Input voltage 7V | temperature range t SN74LS oc to 70C Voc CLA CLR 20K 2K 2 2PR 20 Storage temperature range 65C to 150 @D 16p 415 tah fray tio recommend operating conditions SNS4LS112 SN74US 112 unit aR 7 MIN NOM MAX MIN NOM MAX Supply voltage. Vcc 45 5 35 | a75 5 525 |v i ol pn Wighleval output current ton 400 ~ 400 | ma Pa CUR Lowlevel output. lo 4 8 mA 1 Gack high 20 20 1 2 3 4 5 6 7 8 Pu width, ns Waa width. ty Gant of preset iow 25 25 TCK 1K Ww TPR (10 16 2 GND Tegra) eat mn 24 "S112 "LSI12 Function Table (See Note 2) Setup time. tsetup. as . Lowseve! data 204 204 Hold time, trod ols ols Lid INPUTS OUTPUTS . Oparating trea temperotore, Tq =35 vs | 0 7 |e PRESET CLEAR CLOCK J K | Q_ @ | _ H>high level (steady state). 7 - L H x x x H L L =low jevel (steady state). electrical characteristics over recommended operating X irrevant. free-air temperature range H t x x x |] tc oH J =transition trom high to fow level. PARAMETER + TEST CONDITIONSt [MIN TYP$ MAX | UNIT L u xX xX pHs He Vind High-level input voltage 2 v H H t L Q9 A Vit Low-level input voltage a3) Vv H H 1 HL H L vi Input clamp voltage Voc=MIN, fie 18mA 1.5 Vv H H 4 L H L H Vv High-level Series 54LS Voc=MIN, ViIH= 2V, 2.5 3.4 vO" H H 4 H H | TOGGLE OF output voltage [Series 74S | Vic =0.8V. tons -40CnA | 2.7 3.4 H H H x x [a Voc=MIN. Vin=2V, Vou Low-level output voltage we 0.av. | ee amd 05) Vv mae ou 5 Functional Block Diagrams Input current at OL K poo Clear 0.3 | t v MAX. Vi 7V mA ! maximum input Preset cc A I 03 . voltage Clock 04 a i 9 J.K,of 0 20 = High-level | 60 ti tairieve Clear Voo=MAX, Vj=2.7V uA wa input current Preset 60 clean PRESET Clock 80 i 71 J.K.or 0 0.4 Low-level Clear 0.8 Voo= MAX. Vi=0.5V A te input current Preset ce ' aa) Seon S112 DUAL J-K WITH CLEAR ANO PRESET Clock 0.8 los Short-crcuit output current Voc= MAX 20 100] mA 1 it loc Supply curren Voc= MAX, See Note 1 4 6] mA (average per flip-flop) o4 a imax maximum clock frequency Voo= 5V. 30 a5 MHz vests e 1PLA Ta =25C, 1 aD] ons t orkan from clear. Preset OL <I50F 2 | 4 * 1 = ISpF. teHL or cloek to Q or 0 AL = 2k 15 20| ns { crock "LS112 DUAL J-K WITH CLEAR AND PRESET NOTE: 2 QO=the level of Q before the indicated input conditions were established. TOGGLE: Each output changes to the cmplement of its previous level on each active transition NOTE 1 ipulse! of the clock With atl outputs open. icc 1s measured with the Q and Q outputs high in turn At the time of * This configuration is nonstable, that is, it with not persist when preset and clear inputs return measurement. the clock nput 1% grounded to their inactive (high) state 4 For conditions shown as MIN or MAX,use the appropriate vaue specified under recommended operating conditions Ail typical values are at Voc= 5. Ta=25C @Not more than one output should be shorted at a time, and duration of short-circuit should nat exceed one second. Opagation delay time, low-to-high-level output opagation delay time, high: to-lowtevel output $. The arrow indicates that the falling edge of the clock pulse is used for retesce.