80486DX2RP RADIATION HARDENED 32-BIT MICROPROCESSOR SEi 80486DX2RP FEATURES: * 32-Bit Microprocessor * Total Dose Hardness: typical 100 Krad (Si); dependent upon orbit * Single Event Effect - SELTH = 59.6 MeV/mg/cm2 - SEUTH = 5 MeV/mg/cm2 * Package: - 208 Pin RAD-PAK(R) Quad Flat Pack * 8-Kilobyte On-Chip Cache with Consistency Support * External Cache Controller * Integrated Floating-Point Unit * Single Cycle Execution * 32-Bit RISC Integer Core * Instruction Pipelining * On-Chip Management Unit * Write Buffers * Bus Backoff * Instruction Restart * On Chip Floating Point Unit DESCRIPTION: Space Electronics' 80486DX2RP (RP for RAD-PAK(R)) high-performance 32-bit microprocessor features a typical 100krad (Si) total dose tolerance. The 80486DX2RP processor integrates an 8K unified cache and floating-point (FPU) hardware-onchip. The on-chip memory management unit is completely compatible with the 80386 processor. The on-chip cache memory allows frequently used data and code to be stored on-chip, reducing accesses to the external bus. Its speed-multiplying technology, allowing the processor to operate at frequencies higher than the external memory bus. The clock multiplier on the 80486DX2RP improves execution performance without increasing board design complexity. It enhances all operations operating out of the cache and/or not blocked by external bus accesses. The burst bus feature enables fast cache fills. The patented radiationhardened RAD-Pak(R) technology incorporates radiation shielding in the microcircuit package. It provides a 100 Krad or better (Si) total dose survivability, based on a GEO-type orbit. Actual TID tolerance is dependent upon orbit and mission duration. Capable of surviving in-space environment, the 80486DX2RP is ideal for satellite, spacecraft, and space probe missions. It is available in Class S packaging and screening. 1 0311.98Rev1 Specification and design are subject to change without notice. --4.3-- (c)1998 Space Electronics Inc. All rights reserved 80486DX2RP 32-BIT MICROPROCESSOR RADIATION HARDENED 80486DX2RP ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Respect to Ground DC Voltage on Other Pins with Respect to Ground Operating Temperature Range Storage Temperature Range SYMBOL VCC MIN -0.5 -0.5 MAX +6.5 VCC + 0.5 TOPR TSTG -55 -65 +125 +150 UNIT V V O O C C 80486DX2RP OPERATING CONDITIONS PARAMETER Digital Supply Voltage Temperature Range SYMBOL VCC TA MIN 4.5 -55 MAX 5.5 +125 UNIT V O C 80486DX2RP DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION (VCC=5V 10%, TA = -55 to +125C, unless otherwise specified) PARAMETER Input Leakage Current Output Leakage Current UP# Active Supply Current Input Leakage Current Input Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage ICC Active (Power Supply) TEST CONDITION Inputs without Pull-ups or pull-downs 0V < VIN < VCC 3/ 1/ 5/ 2/ Address, Data, BEn 4.0mA Definition, Control 5.0mA Address, Data, BEn -1.0mA Definition, Control -0.9mA fOP = 50MHz fOP = 66MHz fOP = 50MHz fOP = 66MHz fOP = 50MHz fOP = 66MHz fOP = 0MHz @ 1MHz 4/ @ 1MHz 4/ @ 1MHz 4/ SYMBOL ILI MIN -15 MAX +15 UNIT mA ILO ICCU IIH -15 +15 50 200 300 -400 0.8 VCC + 0.3 0.45 mA mA mA IIL VIL VIH VOL -0.3 2.0 VOH 2.4 V 950 6/ 1200 906 ICC Active (Thermal Supply) 1145 4/ 7/ 8/ ICC Stop Grant 70 9/ 90 ICC Stop Clock 10/ 2 CLK2 Capacitance CCLK 6 Input Capacitance CIN 10 Output or I/O Capacitance COUT 10 Note: 1/ This parameter is for inputs with pull-downs and VIH = 2.4V. 2/ This parameter is for inputs with pull-ups and VIL = 0.45V. 3/ When the processor is in Stop Grant state, the I CCU of the host processor is less than 2 mA. 4/ Not 100% tested. 5/ This parameter is for inputs with pull-downs and VIH = 2.4V. (SRESET pin only). mA mA mA mA pF pF pF 2 0311.98Rev1 Specification and design are subject to change without notice. mA V V V --4.3-- (c)1998 Space Electronics Inc. All rights reserved 80486DX2RP RADIATION HARDENED 32-BIT MICROPROCESSOR 6/ This parameter is for proper power supply selection. It is measured using the worst case instruction mix at VCC = 5.25V. 7/ The maximum current column is for thermal design power dissipation. It is measured using the worst case instruction mix at VCC = 5V. 8/ The typical current column is the typical operating current in a system. This value is measured in a system using a typical device at VCC = 5V, running Microsoft Windows 3.1 at an idle condition. This typical value is dependent upon the specific system configuration. 9/ The ICC Stop Grant specification refers to the ICC value once the processor enters the Stop Grant or Auto HALT Power Down state. 10/ The ICC Stop Clock specification refers to the ICC value once the processor enters the Stop Clock state. The VIH and VIL levels must be equal to VCC and 0V, respectively, in order to meet the ICC Stop Clock specifications. 80486DX2RP AC ELECTRICAL CHARACTERISTICS (VCC=5V 10%, TA = -55 to +125 C, unless otherwise specified) PARAMETER TEST CONDITION SYMBOL MIN MAX Operating Frequency 1/ 80486DX2RP-50 50 80486DX2RP-66 66 CLK Frequency 80486DX2RP-50 8 25 80486DX2RP-66 8 33 CLK Period t1 80486DX2RP-50 40 125 80486DX2RP-66 30 125 CLK Period Stability t1a 80486DX2RP-50 +250 +250 80486DX2RP-66 CLK High Time at 2V t2 80486DX2RP-50 14 80486DX2RP-66 11 CLK2 Low Time at 0.8V t3 80486DX2RP-50 14 80486DX2RP-66 11 CLK Fall Time 2V to 0.8V t4 80486DX2RP-50 4 80486DX2RP-66 3 CLK2 Rise Time 0.8V to 2V t5 80486DX2RP-50 4 80486DX2RP-66 3 A2 - A31, PWT, PCD, t6 BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, SMIACT#, FERR# Valid Delay 80486DX2RP-50 3 19 80486DX2RP-66 3 14 A2 - A31, PWT, PCD, t7 BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, Float Delay 2/ 80486DX2RP-50 28 80486DX2RP-66 20 MHz MHz ns ps ns ns ns ns ns 3 0311.98Rev1 Specification and design are subject to change without notice. UNIT --4.3-- (c)1998 Space Electronics Inc. All rights reserved 80486DX2RP RADIATION HARDENED 32-BIT MICROPROCESSOR 80486DX2RP AC ELECTRICAL CHARACTERISTICS (continue) (VCC=5V 10%, VPP = VSS, TA = -55 to +125C, unless otherwise specified) PARAMETER TEST CONDITION SYMBOL MIN MAX PCHK# Valid Delay t8 80486DX2RP-50 3 24 80486DX2RP-66 3 14 BLAST#, PLOCK# Valid Delay t8a 80486DX2RP-50 3 24 80486DX2RP-66 3 14 BLAST#, PLOCK# Float Delay t9 2/ 80486DX2RP-50 28 80486DX2RP-66 20 D0-D31, DP0-DP3 Write Data t10 Valid Delay 3 20 80486DX2RP-50 80486DX2RP-66 3 14 D0-D31, DP0-DP31 Write t11 Data Float Delay 2/ 80486DX2RP-50 28 80486DX2RP-66 20 EADS# Setup Time t12 80486DX2RP-50 8 80486DX2RP-66 5 EADS# Hold Time t13 80486DX2RP-50 3 80486DX2RP-66 3 KEN#, BS16#, BS#, Setup t14 Time 8 80486DX2RP-50 80486DX2RP-66 5 KEN#, BS16#, BS# Hold Time t15 80486DX2RP-50 80486DX2RP-66 3 3 RDY#, BRDY# Setup Time t16 80486DX2RP-50 8 80486DX2RP-66 5 RDY#, BRDY# Hold Time t17 80486DX2RP-50 3 80486DX2RP-66 3 HOLD, AHOLD Setup Time t18 80486DX2RP-50 8 80486DX2RP-66 6 BOFF# Setup Time t18a 80486DX2RP-50 8 80486DX2RP-66 7 ns ns ns ns ns ns ns ns ns ns ns ns ns 4 0311.98Rev1 Specification and design are subject to change without notice. UNIT --4.3-- (c)1998 Space Electronics Inc. All rights reserved 80486DX2RP RADIATION HARDENED 32-BIT MICROPROCESSOR 80486DX2RP AC ELECTRICAL CHARACTERISTICS (continue) (VCC=5V 10%, VPP = VSS, TA = -55 to +125C, unless otherwise specified) PARAMETER TEST CONDITION SYMBOL MIN MAX HOLD, AHOLD, BOFF# Hold t19 Time 80486DX2RP-50 3 80486DX2RP-66 3 FLUSH#, A20M#, NMI, INTR, t20 SMI#, STPCLK#, SRESET, RESET, IGNNE# Setup Time 80486DX2RP-50 8 80486DX2RP-66 5 FLUSH#, A20M#, NMI, INTR, t21 SMI#, STPCLK#, SRESET, RESET, IGNNE# Hold Time 80486DX2RP-50 3 80486DX2RP-66 3 D0-D31, DP0-DP3, A4-A31 t22 Read Setup Time 80486DX2RP-50 5 80486DX2RP-66 5 D0-D31, DP0-DP3, A4-A31 t23 Read Hold Time 3 80486DX2RP-50 80486DX2RP-66 3 Note: 1/ 0-MHz operation is guaranteed when the STPCLK# and Stop Grant bus cycle protocol is used. 2/ Not 100% tested, guaranteed by design characterization. 80486DX2RP AC SPECIFICATIONS FOR THE TEST ACCESS PORT VCC=5V 10%, VPP = VSS, TA = -55 to +125C, unless otherwise specified) PARAMETER TEST CONDITION SYMBOL MIN MAX TCK Frequency 1/ t24 8 TCK Period t25 125 TCK High Time at 2.0V t26 40 TCK Low Time at 0.8V t27 40 TCK Rise Time 2/ t28 8 TCK Fall Time 2/ t29 8 TDI, TMS Setup Time 3/ t30 8 TDI, TMS Hold Time 3/ t31 10 TDO Valid Delay 3/ t32 3 30 TDO Float Delay 3/ t33 36 All Outputs (Non-Test) Valid t34 3 30 Delay 3/ All Outputs (Non-Test) Float t35 36 Delay 3/ All Inputs (Non-Test) Setup t36 8 Time 3/ All Inputs (Non-Test) Hold t37 10 Setup 3/ ns ns ns ns ns UNIT MHz ns ns ns ns ns ns ns ns ns ns ns ns ns 5 0311.98Rev1 Specification and design are subject to change without notice. UNIT --4.3-- (c)1998 Space Electronics Inc. All rights reserved 80486DX2RP 32-BIT MICROPROCESSOR RADIATION HARDENED Note: 1/ TCK period < CLK period. 2/ Rise/Fall times are measured between 0.8V and 2.0V. Rise/Fall times can be relaxed by 1 ns per 10-ns increase in TCK period. 3/ Parameters t30 - t36 are measured from TCK. 80486DX2RP PINOUT DESCRIPTION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 SYMBOL Vss Vcc Vcc PCHK# BRDY# BOFF# BS16# BS8# Vcc Vss NC RDY# KEN# Vcc Vss HOLD AHOLD TCK Vcc Vcc Vss Vcc Vcc CLK Vcc HLDA W/R# Vss Vcc BREQ BE0# BE1# BE2# BE3# Vcc PIN 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 SYMBOL Vss M/IO# Vcc D/C# PWT PCD Vcc Vss Vcc Vcc EADS# A20M# RESET FLUSH# INTR NMI Vss Vss Vcc Vss Vcc Vss SRESET SMIACT# Vcc Vss Vcc NC NC SMI# FERR# NC TDO Vcc NC PIN 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 SYMBOL NC IGNNE# STPCLK# D31 D30 Vss Vcc D29 D28 Vcc Vss Vcc D27 D26 D25 Vcc D24 Vss Vcc DP3 D23 D22 D21 Vss Vcc NC Vss Vcc D20 D19 D18 Vcc D17 Vss Vss SYMBOL Vcc Vss D16 DP2 Vss Vcc D15 D14 Vcc Vss D13 D12 D11 D10 Vss Vcc Vss D9 D8 DP1 D7 NC Vcc D6 D5 Vcc Vss Vcc Vcc Vss Vcc Vcc Vss Vcc D4 PIN 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 SYMBOL D3 D2 D1 D0 DP0 Vss A31 A30 A29 Vcc A28 A27 A26 A25 Vcc Vss Vss A24 A23 A22 A21 Vcc Vcc A20 A19 A18 TMS TDI Vcc Vss A17 Vcc A16 A15 Vss PIN 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 SYMBOL Vcc A14 A13 Vcc A12 Vss A11 Vcc Vss Vcc A10 A9 Vcc Vss A8 Vcc A7 A6 UP# A5 A4 A3 Vcc Vss Vcc Vss A2 ADS# BLAST# Vcc PLOCK# LOCK# Vss 6 0311.98Rev1 Specification and design are subject to change without notice. PIN 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 --4.3-- (c)1998 Space Electronics Inc. All rights reserved 80486DX2RP RADIATION HARDENED 32-BIT MICROPROCESSOR Figure 1. 80486DX2RP CLK Waveforms Figure 2. 80486DX2RP Input Setup and Hold Timing Figure 3. 80486DX2RP Input Setup and Hold Timing 7 0311.98Rev1 Specification and design are subject to change without notice. --4.3-- (c)1998 Space Electronics Inc. All rights reserved 80486DX2RP RADIATION HARDENED 32-BIT MICROPROCESSOR Figure 4. 80486DX2RP PCHK# Valid Delay Timing Figure 5. 80486DX2RP Output Valid Delay Timing 8 0311.98Rev1 Specification and design are subject to change without notice. --4.3-- (c)1998 Space Electronics Inc. All rights reserved 80486DX2RP RADIATION HARDENED 32-BIT MICROPROCESSOR Figure 6. 80486DX2RP Maximum Float Delay Timing Figure 7. 80486DX2RP Test Signal Timing 9 0311.98Rev1 Specification and design are subject to change without notice. --4.3-- (c)1998 Space Electronics Inc. All rights reserved 80486DX2RP 32-BIT MICROPROCESSOR RADIATION HARDENED A2 Pin 1 Pin 52 208 Pin QFP RAD-PAK(R) Top View Symbol A A1 b c D D1 S1 e L L1 A1 N Dimension (inches) Minimum Maximum .110 .150 .026 .007 .013 .004 .009 1.133 1.515 1.275 BSC .013 .025 BSC 2.500 2.540 2.485 2.505 .075 .125 208 Note: This package has to be mounted cavity down to match the pinout. 10 0311.98Rev1 Specification and design are subject to change without notice. --4.3-- (c)1998 Space Electronics Inc. All rights reserved