LT3033
1
Rev. A
For more information www.analog.com
TYPICAL APPLICATION
FEATURES DESCRIPTION
3A, 0.95V to 10V, Very Low Dropout Linear
Regulator with Programmable Current Limit
The LT
®
3033 is a very low dropout voltage (VLDO™) linear
regulator that operates from a single input supply down to
0.95V. The device supplies 3A output current with 95mV
typical dropout voltage. The LT3033 is ideal for low input
voltage to low output voltage applications, providing
comparable electrical efficiency to a switching regulator.
The LT3033 optimizes stability and transient response
with low ESR ceramic output capacitors as small as 10μF.
Other features include programmable current limit, an
output current monitor and a power good flag to indicate
output voltage regulation. In shutdown, quiescent cur-
rent typically drops to 22μA. Internal protection circuitry
includes reverse-battery protection, current limiting with
foldback, thermal limiting with hysteresis and reverse-
current protection.
The LT3033 is available as an adjustable device with an
output voltage down to the 200mV reference. The device
is available in a thermally enhanced, low profile 3mm ×
4mm × 0.75mm QFN package.
1.2V to 0.9V, 3A VLDO Regulator
Minimum Input Voltage vs
Temperature
All registered trademarks and trademarks are the property of their respective owners.
n Single Supply VIN Range: 0.95V to 10V
n Dropout Voltage: 95mV Typical
n Output Current: 3A
n Adjustable Output Voltage: 200mV to 9.7V
n Single Capacitor Soft-Starts Reference and Lowers
Output Noise
n Stable with Low ESR, Ceramic Output Capacitors
n 0.075% Typical Load Regulation from 1mA to 3A
n Quiescent Current: 1.9mA Typical
n Quiescent Current in Shutdown: 22μA Typical
n Power Good (PWRGD) Flag (Status Valid in Shutdown)
n Current Limit Protection with Foldback
n Programmable Current Limit
n Output Current Monitor: IOUT/2650
n Thermal Limiting with Hysteresis
n Reverse Battery, Reverse Output, and Reverse
Current Protection
n 20-Lead 3mm × 4mm QFN Package
APPLICATIONS
n High Efficiency Linear Regulators
n Battery-Powered Systems
n Logic Supplies
n Post Regulator for Switching Supplies
n Wireless Modems
n FPGA Core Supplies
10µF
100k
10nF
3033 TA01a
10µF
442Ω
500mV AT
IOUT = 3A
10nF
IN
SHDN
PWRGD
V
IN
1.2V
REF/BYP
GND
IMON
ILIM
ADJ
OUT
LT3033
VOUT
0.9V
3A
13.7k
1%
3.92k
1%
I
L
= 3A
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
MINIMUM INPUT VOLTAGE (V)
3033 TA01b
Document Feedback
LT3033
2
Rev. A
For more information www.analog.com
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
(Note 1)
20 19 18 17
7 8
TOP VIEW
UDC PACKAGE
20-LEAD (3mm × 4mm) QFN, IN/OUT EXPOSED PADS
TJMAX = 125°C, θJA = 38°C/W, θJC = 3.4°C/W
9 10
6
5
4
3
2
1
11
12
13
14
15
16
IN
IN
OUT
OUT
GND
GND
IN
IN
OUT
OUT
SHDN
PWRGD
OUT
23
OUT
OUT
OUT
OUT
ILIM
IMON
REF/BYP
ADJ
OUT
24
IN
21
IN
22
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3033EUDC#PBF LT3033EUDC#TRPBF LGVQ 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C
LT3033IUDC#PBF LT3033IUDC#TRPBF LGVQ 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
IN Pin Voltage .........................................................±10V
OUT Pin Voltage ......................................................±10V
Input-to-Output Differential Voltage ........................ ±10V
ADJ Pin Voltage ......................................................±10V
REF/BYP Pin Voltage ....................................... 1V, –0.3V
SHDN Pin Voltage ...................................................±10V
PWRGD Pin Voltage ...................................... 10V, –0.3V
ILIM Pin Voltage ...................................................... ±7V
IMON Pin Voltage ....................................................±10V
Output Short-Circuit Duration ..........................Indefinite
Operating Junction Temperature (Notes 2, 3)
E-/I-grades .........................................–40°C to 125°C
Storage Temperature Range
QFN Package ...................................... –65°C to 150°C
ORDER INFORMATION
LT3033
3
Rev. A
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Input Voltage (Notes 4, 6) ILOAD = 3A, TA > 0°C
ILOAD = 3A, TA ≤ 0°C
0.95
0.95
1.05
1.14
V
V
ADJ Pin Voltage (Notes 5, 6, 7) VIN = 1.5V, ILOAD = 1mA
1.14V < VIN < 10V, 1mA < ILOAD < 3A
l
197
194
200
200
203
206
mV
mV
Line Regulation (Note 13) VIN = 1.14V to 10V, ILOAD = 1mA l0.1 1.25 mV
Load Regulation (Note 13) VIN = 1.14V, ILOAD = 1mA to 3A
l
0.15 1
2
mV
mV
Dropout Voltage
VIN = VOUT(NOMINAL)
(Notes 8, 9)
ILOAD = 100mA
ILOAD = 100mA
l
45 70
165
mV
mV
ILOAD = 500mA
ILOAD = 500mA
l
55 85
175
mV
mV
ILOAD = 1.5A
ILOAD = 1.5A
l
70 105
195
mV
mV
ILOAD = 3A
ILOAD = 3A
l
95 135
240
mV
mV
GND Pin Current
VIN = VOUT(NOMINAL) + 0.4V
(Notes 9, 10)
ILOAD = 0mA
ILOAD = 1mA
ILOAD = 100mA
ILOAD = 500mA
ILOAD = 1.5A
ILOAD = 3A
l
l
l
l
l
l
1.9
2
3.2
6
13
27
3.5
3.8
7
14
36
60
mA
mA
mA
mA
mA
mA
Output Voltage Noise COUT = 10μF, ILOAD = 3A, BW = 10Hz to 100kHz,
CREF/BYP = 10nF, VOUT = 1.2V, CFF = 10nF
60 µVRMS
ADJ Pin Bias Current (Notes 9, 11) VADJ = 0.2V, VIN = 1.5V 5 40 nA
Shutdown Threshold VOUT = Off to On
VOUT = On to Off
l
l
0.25
0.65
0.63
0.95 V
V
SHDN Pin Current (Note 12) VSHDN = 0V, VIN = 10V
VSHDN = 10V, VIN = 10V
l
l
5.8
±1
15
µA
µA
Quiescent Current in Shutdown VIN = 6V, VSHDN = 0V 22 37 µA
PWRGD Trip Point % of Nominal Output Voltage, Output Rising l88 92 95 %
PWRGD Trip Point Hysteresis % of Nominal Output Voltage, Output Falling 1.9 %
PWRGD Output Low Voltage IPWRGD = 100μA l40 150 mV
PWRGD Leakage Current VSHDN = 0V, VPWRGD = 10V l1 µA
Ripple Rejection (Note 13) VIN – VOUT = 1V, VRIPPLE = 0.5VP-P,
fRIPPLE = 120Hz, ILOAD = 3A
60 dB
VIN – VOUT = 1V, VRIPPLE = 50mVRMS,
fRIPPLE = 10kHz, ILOAD = 3A
60 dB
VIN – VOUT = 1V, VRIPPLE = 50mVRMS,
fRIPPLE = 1MHz, ILOAD = 3A
52 dB
Internal Current Limit (Note 9) VIN = 4V, VOUT = 0V
VIN = 1.14V, ∆VOUT = –0.1V
l
l
3.6
3.1
4.5 5.4 A
A
Programmable Current Limit (Note 9) VIN = 1.5V, RILIM = 332, VOUT = 0V
VIN = 1.5V, RILIM = 162, VOUT = 0V
l
l
1.32
2.64
1.5
3
1.68
3.36
A
A
Input Reverse Leakage Current (Note 14) VIN = –10V, VOUT = 0V 5 µA
Reverse Output Current (Notes 15, 16) VOUT = 1.2V, VIN = 0V 0.1 15 µA
Current Monitor Ratio (Note 17)
Ratio = IOUT/IMON
ILOAD = 0.1A, 0.5A, 1.5A, 3A TA > 0°C
VIN = 1.5V, VOUT = 1.2V TA ≤ 0°C
2517.5
2491
2650
2650
2782.5
2809
A/A
A/A
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
LT3033
4
Rev. A
For more information www.analog.com
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3033 is tested and specified under pulse load conditions
such that TJ ≈ TA. The LT3033E is 100% tested at TA = 25°C and
performance is guaranteed from 0°C to 125°C. Performance of the
LT3033E over the full –40°C and 125°C operating junction temperature
range is assured by design, characterization and correlation with statistical
process controls. The LT3033I is guaranteed over the full –40°C to 125°C
operating junction temperature range. High junction temperatures degrade
operating lifetimes. Operating lifetime is derated at junction temperatures
greater than 125°C.
Note 3: The LT3033 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature exceeds the maximum operating junction temperature when
overtemperature protection is active. Continuous operation above the
specified maximum operating junction temperature may impair device
reliability.
Note 4: Minimum input voltage is the voltage required by the LT3033 to
regulate the output voltage and supply the rated 3A output current. This
specification is tested at VOUT = 0.2V. For higher output voltages, the
minimum input voltage required for regulation equals the regulated output
voltage VOUT plus the dropout voltage or 1.14V, whichever is greater.
Note 5: Maximum junction temperature limits operating conditions. The
regulated output voltage specification does not apply for all possible
combinations of input voltage and output current. Limit the output current
range if operating at maximum input voltage. Limit the input-to-output
voltage differential range if operating at maximum output current.
ELECTRICAL CHARACTERISTICS
Note 6: The LT3033 typically supplies 3A output current with a 0.95V input
supply. The guaranteed minimum input voltage for 3A output current is
1.14V, especially if cold temperature operation is required.
Note 7: The LT3033 is tested and specified for these conditions with ADJ
tied to OUT.
Note 8: Dropout voltage is the minimum input to output voltage differential
needed to maintain regulation at a specified output current. In dropout the
output voltage equals: (VIN – VDROPOUT).
Note 9: The LT3033 is tested and specified for these conditions with
an external resistor divider (3.92k and 19.6k) setting VOUT to 1.2V. The
external resistor divider adds 50μA of load current.
Note 10: GND pin current is tested with VIN = VOUT(NOMINAL) + 0.4V and a
current source load. GND pin current increases in dropout. See GND pin
current curves in the Typical Performance Characteristics section.
Note 11: Adjust pin bias current flows into the ADJ pin.
Note 12: Shutdown pin current flows into the SHDN pin.
Note 13: The LT3033 is tested and specified for this condition with an
external resistor divider (3.92k and 11.8k) setting VOUT to 0.8V. The
external resistor divider adds 50μA of load current. The specification refers
to the change in the 0.2V reference voltage, not the 0.8V output voltage.
Note 14: Input reverse leakage current flows out of the IN pin.
Note 15: Reverse output current is tested with IN grounded and OUT
forced to the rated output voltage. This current flows into the OUT pin and
out of the GND pin.
Note 16: Reverse current is higher for the case of (rated_output) < VOUT
< VIN, because the no-load recovery circuitry is active in this region and is
trying to restore the output voltage to its nominal value.
Note 17: For detailed information on how to calculate the output current
from the IMON pin, please see the Applications Information section. If the
current monitor function is not needed, the IMON pin must be tied to GND.
LT3033
5
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Input Voltage ADJ Pin Voltage ADJ Pin Bias Current
Quiescent Current Quiescent Current Quiescent Current in Shutdown
Dropout Voltage Guaranteed Dropout Voltage Dropout Voltage
TA = 25°C, unless otherwise noted.
V
OUT
= 1.2V
T
J
= –55°C
T
J
= –40°C
T
J
= 25°C
T
J
= 125°C
T
J
= 150°C
OUTPUT CURRENT (A)
0
0.5
1
1.5
2
2.5
3
0
30
60
90
120
150
180
210
240
270
300
DROPOUT VOLTAGE (mV)
3033 G01
= TEST POINTS
T
J
= 150°C
T
J
= 25°C
OUTPUT CURRENT (A)
0
0.5
1
1.5
2
2.5
3
0
30
60
90
120
150
180
210
240
270
300
GUARANTEED DROPOUT VOLTAGE (mV)
3033 G02
V
OUT
= 1.2V
I
L
= 3A
I
L
= 1.5A
I
L
= 0.5A
I
L
= 0.1A
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
30
60
90
120
150
180
210
240
270
300
DROPOUT VOLTAGE (mV)
3033 G03
I
L
= 3A
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
MINIMUM INPUT VOLTAGE (V)
3033 G04
I
L
= 1mA
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
194
195
196
197
198
199
200
201
202
203
204
205
206
ADJ PIN VOLTAGE (mV)
3033 G05
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
–40
–30
–20
–10
0
10
20
30
40
ADJ PIN BIAS CURRENT (nA)
3033 G06
V
IN
= 1.6V
V
SHDN
= V
IN
V
OUT
= 1.2V
I
L
= 0
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
0.35
0.70
1.05
1.40
1.75
2.10
2.45
2.80
3.15
3.50
QUIESCENT CURRENT (mA)
3033 G07
V
SHDN
= V
IN
V
OUT
= 1.2V
I
L
= 0
T
J
=25°C
INPUT VOLTAGE (V)
0
1
2
3
4
5
6
7
8
9
10
0
0.35
0.70
1.05
1.40
1.75
2.10
2.45
2.80
3.15
3.50
QUIESCENT CURRENT (mA)
3033 G08
V
IN
= 1.6V
V
SHDN
= 0V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
10
20
30
40
50
60
70
80
90
100
QUIESCENT CURRENT (µA)
3033 G09
LT3033
6
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
GND Pin Current SHDN Pin Threshold SHDN Pin Input Current
SHDN Pin Input Current PWRGD Trip Point PWRGD Output Low Voltage
Quiescent Current in Shutdown GND Pin Current GND Pin Current
TA = 25°C, unless otherwise noted.
V
SHDN
= 0V
T
J
= 25°C
INPUT VOLTAGE (V)
0
1
2
3
4
5
6
7
8
9
10
0
10
20
30
40
50
60
70
80
90
100
QUIESCENT CURRENT (µA)
3033 G10
V
OUT
= 1.2V
I
L
= 1mA
I
L
= 100mA
I
L
= 500mA
I
L
= 1.5A
I
L
= 3A
INPUT VOLTAGE (V)
0
1
2
3
4
5
6
7
8
0
9
18
27
36
45
54
63
72
GND PIN CURRENT (mA)
3033 G11
V
IN
= 1.6V
V
OUT
= 1.2V
OUTPUT CURRENT (A)
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
0
4
8
12
16
20
24
28
32
36
40
GND PIN CURRENT (mA)
3033 G12
V
IN
= 1.6V
V
OUT
= 1.2V
I
L
= 1mA
I
L
= 100mA
I
L
= 500mA
I
L
= 1.5A
I
L
= 3A
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
9
18
27
36
45
54
63
72
GND PIN CURRENT (mA)
3033 G13
I
L
= 1mA
OFF TO ON
ON TO OFF
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
SHDN
PIN THRESHOLD (V)
3033 G14
V
IN
= 10V
SHDN
PIN VOLTAGE (V)
0
1
2
3
4
5
6
7
8
9
10
0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
13.5
15.0
SHDN
PIN INPUT CURRENT (µA)
3033 G15
V
IN
= 10V
V
SHDN
= 10V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
13.5
15.0
SHDN
PIN INPUT CURRENT (µA)
3033 G16
I
PWRGD
= 100µA
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
15
30
45
60
75
90
105
120
135
150
PWRGD OUTPUT LOW VOLTAGE (mV)
3033 G18
OUTPUT RISING
OUTPUT FALLING
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
88
89
90
91
92
93
94
95
PWRGD TRIP POINT (% OF OUTPUT VOLTAGE)
3033 G17
LT3033
7
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Programmable Current Limit IOUT/IMON Current Ratio, IOUT = 3A IOUT/IMON Current Ratio, IOUT = 3A
IOUT/IMON Current Ratio Input Reverse Leakage Current Reverse Output Current
PWRGD Pin Leakage Current Internal Current Limit Internal Current Limit
TA = 25°C, unless otherwise noted.
V
PWRGD
= 10V
V
SHDN
= 0V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
PWRGD PIN LEAKAGE CURRENT (µA)
3033 G19
V
OUT
= 0V
T
J
= –55°C
T
J
= –40°C
T
J
= 25°C
T
J
= 125°C
T
J
= 150°C
INPUT VOLTAGE (V)
0
1
2
3
4
5
6
7
8
CURRENT LIMIT (A)
3033 G20
2
3
4
5
6
7
8
9
10
0
1
V
OUT
= 0V
V
IN
= 10V
V
IN
= 4V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
CURRENT LIMIT (A)
3033 G21
V
OUT
= 0V
V
IN
= 1.5V
R
ILIM
= 332Ω
R
ILIM
= 162Ω
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
CURRENT LIMIT (A)
3033 G22
V
OUT
= 1.2V
V
IN
= 1.8V
T
J
= –55°C
T
J
= –40°C
T
J
= 25°C
T
J
= 125°C
T
J
= 150°C
V
IMON
(V)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
2491.0
2517.5
2544.0
2570.5
2597.0
2623.5
2650.0
2676.5
2703.0
2729.5
2756.0
2782.5
2809.0
I
OUT
/I
MON
CURRENT RATIO (A/A)
3033 G24
V
IN
= –10V
V
OUT
= 0V
V
SHDN
= 10V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
INPUT CURRENT (µA)
3033 G26
V
IN
= 0V
V
OUT
= 1.2V
I
OUT
FLOWS INTO OUT PIN
I
IN
FLOWS OUT OF IN PIN
I
OUT
I
IN
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
REVERSE OUTPUT CURRENT (mA)
3033 G27
V
OUT
= 1.2V
V
IN
= 1.5V
V
IMON
= 0.6V
T
J
= –55°C
T
J
= –40°C
T
J
= 25°C
T
J
= 125°C
T
J
= 150°C
OUTPUT CURRENT (A)
0
0.5
1
1.5
2
2.5
3
2491.0
2517.5
2544.0
2570.5
2597.0
2623.5
2650.0
2676.5
2703.0
2729.5
2756.0
2782.5
2809.0
I
OUT
/I
MON
CURRENT RATIO (A/A)
3033 G25
V
OUT
= 1.2V
V
IN
= 1.5V
T
J
= –55°C
T
J
= –40°C
T
J
= 25°C
T
J
= 125°C
T
J
= 150°C
V
IMON
(V)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
2491.0
2517.5
2544.0
2570.5
2597.0
2623.5
2650.0
2676.5
2703.0
2729.5
2756.0
2782.5
2809.0
I
OUT
/I
MON
CURRENT RATIO (A/A)
3033 G23
LT3033
8
Rev. A
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TYPICAL PERFORMANCE CHARACTERISTICS
Input Ripple Rejection Input Ripple Rejection Input Ripple Rejection
Input Ripple Rejection Line Regulation Load Regulation
No-Load Recovery Threshold No-Load Recovery Threshold Input Ripple Rejection
TA = 25°C, unless otherwise noted.
T
J
= 25°C
OUTPUT OVERSHOOT (%)
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
OUTPUT SINK CURRENT (mA)
3033 G28
I
OUT(SINK)
= 5mA
I
OUT(SINK)
= 1mA
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
2
4
6
8
10
12
14
16
OUTPUT OVERSHOOT (%)
3033 G29
I
LOAD
= 3A
C
REF/BYP
= 10nF
C
FF
= 10nF
V
OUT
= 1.2V
V
IN
= 1.5V+50mV
RMS
RIPPLE
C
OUT
= 10µF
C
OUT
= 47µF
C
OUT
= 22µF
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0
10
20
30
40
50
60
70
80
90
100
RIPPLE REJECTION (dB)
3033 G30
I
LOAD
= 3A
C
OUT
= 10µF
V
OUT
= 1.2V
C
REF/BYP
= 10nF; C
FF
=10nF
C
REF/BYP
= 10nF; C
FF
= 0
C
REF/BYP
= 0; C
FF
= 0
C
REF/BYP
= 0; C
FF
= 10nF
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0
10
20
30
40
50
60
70
80
90
100
RIPPLE REJECTION (dB)
3033 G31
V
IN
= 1.5V+50mV
RMS
RIPPLE
C
OUT
= 10µF
C
REF/BYP
= 10nF
C
FF
= 10nF
V
OUT
= 1.2V
V
IN
= 1.5V+50mV
RMS
RIPPLE
I
LOAD
= 3A
I
LOAD
= 1.5A
I
LOAD
= 0.5A
I
LOAD
= 0.1A
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0
10
20
30
40
50
60
70
80
90
100
RIPPLE REJECTION (dB)
3033 G32
I
LOAD
= 3A
C
OUT
= 47µF
C
REF/BYP
= 10nF
C
FF
= 10nF
V
OUT
= 1.2V
10kHz
100kHz
500kHz
1MHz
2MHz
INPUT/OUTPUT DIFFERENTIAL (V)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0
10
20
30
40
50
60
70
80
90
100
RIPPLE REJECTION (dB)
3033 G33
I
LOAD
= 3A
C
REF/BYP
= C
FF
= 10nF
C
OUT
= 10µF
V
OUT
= 1.2V
V
IN
= 1.5V+50mV
RMS
RIPPLE
f = 120Hz
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
10
20
30
40
50
60
70
80
90
100
RIPPLE REJECTION (dB)
3033 G34
∆V
IN
= 1.14V TO 10V
V
OUT
= 0.2V
I
L
= 1mA
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
–1.0
–0.8
–0.6
–0.4
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
LINE REGULATION (mV)
3033 G35
V
IN
= 1.14V
V
OUT
= 0.8V
∆I
L
= 1mA TO 3A
LOAD REGULATION NUMBER REFERS
TO CHANGE IN THE 200mV REFERENCE
VOLTAGE
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
–2.0
–1.6
–1.2
–0.8
–0.4
0.0
0.4
0.8
1.2
1.6
2.0
LOAD REGULATION (mV)
3033 G36
LT3033
9
Rev. A
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TYPICAL PERFORMANCE CHARACTERISTICS
RMS Output Noise
CREF/BYP = 10nF, CFF = 0
RMS Output Noise vs
Feedforward Capacitor (CFF)
RMS Output Noise vs
Bypass Capacitor (CREF/BYP)
SHDN Transient Response
CREF/BYP = 0
SHDN Transient Response
CREF/BYP = 10nF
Output Noise Spectral Density
CREF/BYP = 0, CFF = 0
Output Noise Spectral Density
CREF/BYP = 10nF
RMS Output Noise
VOUT = 0.2V, CFF = 0
TA = 25°C, unless otherwise noted.
C
OUT
= 10µF
I
L
= 3A
V
OUT
= 5V
V
OUT
= 3.3V
V
OUT
= 2.5V
V
OUT
= 1.8V
V
OUT
= 1.5V
V
OUT
= 1.2V
V
OUT
= 0.9V
V
OUT
= 0.2V
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
0.001
0.01
0.1
1
10
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
3033 G37
V
OUT
= 1.2V
C
OUT
= 10µF
I
L
= 3A
C
FF
= 0pF
C
FF
= 100pF
C
FF
= 1nF
C
FF
= 10nF
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
0.001
0.01
0.1
1
10
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
3033 G38
f = 10Hz TO 100kHz
C
OUT
= 10µF
C
REF/BYP
= 0pF
C
REF/BYP
= 100pF
C
REF/BYP
= 10nF
OUTPUT CURRENT (mA)
0.01
0.1
1
10
100
1k
10k
0
10
20
30
40
50
60
70
80
90
100
OUTPUT NOISE (µV
RMS
)
3033 G39
V
IN
= 1.5V
V
OUT
= 1.2V
R
L
= 0.4Ω
C
OUT
= 10µF
2ms/DIV
V
SHDN
1V/DIV
V
OUT
500mV/DIV
3033 G43
f = 10Hz TO 100kHz
C
OUT
= 10µF
OUTPUT CURRENT (mA)
0.01
0.1
1
10
100
1k
10k
0
60
120
180
240
300
360
420
480
OUTPUT NOISE (µV
RMS
)
3033 G40
V
OUT
= 5V
V
OUT
= 3.3V
V
OUT
= 2.5V
V
OUT
= 1.8V
V
OUT
= 1.5V
V
OUT
= 1.2V
V
OUT
= 0.9V
V
OUT
= 0.2V
f = 10Hz TO 100kHz
C
REF/BYP
= 10nF
C
OUT
= 10µF
I
L
= 3A
V
OUT
= 5V
V
OUT
= 3.3V
V
OUT
= 2.5V
V
OUT
= 1.8V
V
OUT
= 1.5V
V
OUT
= 1.2V
V
OUT
= 0.9V
V
OUT
= 0.2V
FEEDFORWARD CAPACITOR, C
FF
(pF)
10
100
1k
10k
0
30
60
90
120
150
180
210
240
270
300
330
360
OUTPUT NOISE (µV
RMS
)
3033 G41
f = 10Hz TO 100kHz
V
OUT
= 1.2V
C
OUT
= 10µF
I
L
= 3A
C
FF
= 10nF
C
FF
= 0
BYPASS CAPACITOR, C
REF/BYP
(nF)
0.01
0.1
1
10
100
1k
0
20
40
60
80
100
120
140
160
180
200
OUTPUT NOISE (µV
RMS
)
3033 G42
V
IN
= 1.5V
V
OUT
= 1.2V
R
L
= 0.4Ω
C
OUT
= 10µF
2ms/DIV
V
SHDN
1V/DIV
V
OUT
500mV/DIV
3033 G44
LT3033
10
Rev. A
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TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Transient Response
CFF = 0
Start-Up Time
Transient Response
CFF = 10nF
V
IN
= 1.5V
V
OUT
= 1.2V
I
OUT
= 30mA to 3A
C
OUT
= 47µF
t
RISE
= t
FALL
= 100ns
100µs/DIV
I
OUT
2A/DIV
V
OUT
100mV/DIV
3033 G46
V
IN
= 1.5V
V
OUT
= 1.2V
I
OUT
= 30mA to 3A
C
OUT
= 47µF
t
RISE
= t
FALL
= 100ns
50µs/DIV
I
OUT
2A/DIV
V
OUT
100mV/DIV
3033 G47
V
OUT
= 1.2V
C
OUT
= 10µF
I
L
= 1mA
C
FF
= 0
C
FF
= 10nF
BYPASS CAPACITOR, C
REF/BYP
(nF)
0.01
0.1
1
10
100
1k
0.01
0.1
1
10
100
1k
START-UP TIME (ms)
3033 G45
LT3033
11
Rev. A
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PIN FUNCTIONS
IN (Pins 1, 2, 15, 16, Exposed Pad Pins 21, 22): Input.
These pins supply power to the device. The LT3033 requires
a bypass capacitor at IN if located more than six inches from
the main input filter capacitor. Include a bypass capacitor
in battery-powered circuits as a battery’s output imped-
ance rises with frequency. A minimum bypass capacitor
of 10μF suffices. The LT3033 withstands reverse voltages
on the IN pin with respect to ground and the OUT pin. In
the case of a reversed input, which occurs if a battery is
plugged in backwards, the LT3033 behaves as if a diode
is in series with its input. No reverse current flows into
the LT3033 and no reverse voltage appears at the load.
The device protects itself and the load.
OUT (Pins 3, 4, 13, 14, 17, 18, 19, 20, Exposed Pad
Pins 23, 24): Output. These pins supply power to the
load. Use a minimum output capacitor of 10μF to prevent
oscillations. Large load transient applications require larger
output capacitors to limit peak voltage transients. See the
Applications Information section for more information on
output capacitance and reverse-output characteristics.
GND (Pins 5, 6): Ground. Connect the bottom of the external
resistor divider, directly to GND for optimum regulation.
ILIM (Pin 7): Current Limit Programming Pin. This pin is
the collector of a current mirror PNP that is 1/2650th the
size of the output power PNP. This pin is also the input to
the current limit amplifier. Current limit threshold is set by
connecting a resistor between the ILIM pin and GND. For
detailed information on how to set the ILIM pin resistor
value, please see the Applications Information section. If
not used, tie ILIM to ground.
IMON (Pin 8): Output Current Monitor. This pin is the
collector of a PNP current mirror that outputs 1/2650th of
the power PNP current. For detailed information on how
to calculate the output current from the IMON pin, please
see the Applications Information section. If the IMON pin
is not used, tie IMON to GND.
REF/BYP (Pin 9): Reference/Bypass. Connecting a single
capacitor from this pin to GND bypasses the LT3033’s
reference noise and soft-starts the reference. A 10nF by-
pass capacitor typically reduces output voltage noise to
60μVRMS in a 10Hz to 100kHz bandwidth. Soft-start time
is directly proportional to the REF/BYP capacitor value.
If the LT3033 is placed in shutdown, REF/BYP is actively
pulled low by an internal device to reset soft-start. If low
noise or soft-start performance is not required, this pin
must be left floating (unconnected). Do not drive this pin
with any active circuitry.
ADJ (Pin 10): Adjust. This pin is the error amplifier invert-
ing terminal. Its 5nA typical input bias current flows into
the pin (see curve of ADJ Pin Bias Current vs Temperature
in the Typical Performance Characteristics). The ADJ pin
reference voltage is 200mV (referred to GND).
PWRGD (Pin 11): Power Good. The PWRGD flag is an
open-collector flag to indicate that the output voltage
has increased above 92% of the nominal output voltage.
There is no internal pull-up on this pin; a pull-up resistor
must be used. The PWRGD pin actively pulls low if the
output is less than 90.1% of the nominal output voltage.
The maximum pull-down current of the PWRGD pin in
the low state is 100μA. The PWRGD flag status is valid
in shutdown.
SHDN (Pin 12): Shutdown. Pulling the SHDN pin low
puts the LT3033 into a low power state and turns the
output off. Drive the SHDN pin with either logic or an
open-collector/drain device with a pull-up resistor. The
resistor supplies the pull-up current to the open collector/
drain logic, normally several microamperes, and the SHDN
pin current, typically 5.8μA. If unused, connect the SHDN
pin to VIN. The LT3033 does not function if the SHDN pin
is not connected.
LT3033
12
Rev. A
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BLOCK DIAGRAM
1
Q1
1/2650
Q2
1/2650
Q3
D2
Q4
R3
D1
10k
Q5
Q6
R2
R1
IN
IMON
SHUTDOWN
GND
ILIM
ADJ
PWRGD
SHDN
BIAS CURRENT
AND
REFERENCE
GENERATOR
200mV
210mV
CURRENT
GAIN
THERMAL
SHUTDOWN
184mV
REF/BYP
IDEAL
DIODE
ERROR
AMPLIFIER
CURRENT
LIMIT
AMPLIFIER
NO-LOAD
RECOVERY
PWRGD
COMPARATOR
11
NOTE:
R1 AND R2 ARE EXTERNAL
12
10
9
8
7
5, 6
1, 2, 15, 16, 21, 22
3, 4, 13, 14,
17, 18, 19,
20, 23, 24
OUT
–
+
–
+
–
+
–
+
LT3033
13
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
The LT3033 very low dropout linear regulator is capable of
0.95V input supply operation. It supplies 3A output current
and dropout voltage is typically 95mV. Quiescent current
is typically 1.9mA and drops to 22μA in shutdown. The
LT3033 incorporates several protection features, making
it ideal for use in battery-powered systems. The device
protects itself against reverse-input and reverse-output
voltages. If the output is held up by a backup battery
when the input is pulled to ground in a battery backup
application, the LT3033 behaves as if a diode is in series
with its output, preventing reverse current flow. In dual
supply applications where the regulator load is returned to
a negative supply, pulling the output below ground by as
much as 10V does not affect start-up or normal operation.
Adjustable Operation
The LT3033’s output voltage range
is 0.2V to 9.7V. Figure 1. Adjustable Operation
shows that the external resistor ratio sets output
voltage. The device regulates the output to maintain
ADJ at 200mV referred to ground. If R1's current is
at least 50µA, the ADJ pin bias current can be ne-
glected and R2's current is equal to R1's current. Use
Figure 1’s formula to calculate output voltage. In shutdown,
the output is off and the divider current is zero. Curves of
ADJ Pin Voltage vs Temperature and ADJ Pin Bias Cur-
rent vs Temperature appear in the Typical Performance
Characteristics section.
Figure 1. Adjustable Operation
Specifications for output voltages greater than 200mV
are proportional to the ratio of desired output voltage to
200mV (VOUT/200mV). For example, load regulation for
an output current change of 1mA to 3A is typically 150μV
at VADJ = 200mV. At VOUT = 1.5V, load regulation is:
1.5V/200mV • 150μV = 1.125mV
Table 1 shows 1% resistor divider values for some common
output voltages with a resistor divider current equaling or
about 50μA.
Table 1
VOUT (V) R1 (kΩ) R2 (kΩ)
0.9 3.92 13.7
1.0 3.92 15.8
1.2 3.92 19.6
1.5 3.92 25.5
1.8 3.92 31.6
2.5 3.92 45.3
3.3 3.92 60.4
5 3.92 95.3
Bypass Capacitance, Output Voltage Noise and
Transient Response
The LT3033 regulator provides low output voltage noise
over the 10Hz to 100kHz bandwidth while operating at
full load with the addition of a reference bypass capacitor
(CREF/BYP) from the REF/BYP pin to GND. A good quality,
low leakage capacitor is recommended. This capacitor
bypasses the internal reference of the regulator, provid-
ing a low frequency noise pole. With the use of 10nF for
CREF/BYP, the output voltage noise decreases to as low as
160μVRMS when the output voltage is set for 1.2V. For
higher output voltages (generated by using a feedback
resistor divider), the output voltage noise gains up ac-
cordingly when using CREF/BYP by itself.
To lower the output voltage noise for higher output volt-
ages, include a feedforward capacitor (CFF) from VOUT
to the ADJ pin. A good quality, low leakage capacitor is
recommended. This capacitor bypasses the error amplifier
of the regulator, providing a low frequency noise pole. With
the use of 10nF for both CFF and CREF/BYP, output voltage
R2
R1
IN
SHDN
V
IN
GND
ADJ
OUT
LT3033
V
OUT
V
OUT
: 200mV • (1 + R2/R1) + (I
ADJ
• R2)
V
ADJ
: 200mV
I
ADJ
: 5nA AT 25°C
OUTPUT RANGE: 0.2V TO 9.7V
+
LT3033
14
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
noise decreases to 60μVRMS when the output voltage is
set to 1.2V by a 50μA feedback resistor divider. If the cur-
rent in the feedback resistor divider is doubled, CFF must
also be doubled to achieve equivalent noise performance.
Higher values of output voltage noise are often measured
if care is not exercised with regard to circuit layout and
testing. Crosstalk from nearby traces induces unwanted
noise onto the LT3033’s output. Power supply ripple rejec-
tion must also be considered. The LT3033 regulator does
not have unlimited power supply rejection and will pass
a small portion of the input noise through to the output.
Using a feedforward capacitor (CFF) from VOUT to the ADJ
pin has the added benefit of improving transient response
for output voltages greater than 0.2V. With no feedforward
capacitor, the settling time will increase as the output volt-
age is raised above 0.2V (see Transient Response in the
Typical Performance Characteristics section).
During start-up, the internal reference soft-starts if a refer-
ence bypass capacitor is present. Regulator start-up time
is directly proportional to the size of the bypass capaci-
tor, slowing to 0.5ms with a 10nF bypass capacitor (See
Start-Up Time in the Typical Performance Characteristics
section). The reference bypass capacitor is actively pulled
low during shutdown to reset the internal reference.
Start-up time is also affected by the use of a feedforward
capacitor. Start-up time is directly proportional to the size
of the feedforward capacitor and output voltage, and is
inversely proportional to the feedback resistor divider cur-
rent, slowing to 0.4ms with a 10nF feedforward capacitor
and a 10μF output capacitor for an output voltage set to
1.2V by a 50μA feedback resistor divider.
Input Capacitance and Stability
The LT3033 design is stable with a minimum of 10μF
capacitor placed at the IN pin. Very low ESR ceramic
capacitors may be used. However, in cases where long
wires connect the power supply to the LT3033’s input and
ground, use of low value input capacitors combined with
an output load current of greater than 20mA may result
in instability. The resonant LC tank circuit formed by the
wire inductance and the input capacitor is the cause and
not a result of LT3033 instability.
The self-inductance, or isolated inductance, of a wire
is directly proportional to its length. However, the wire
diameter has less influence on its self-inductance. For
example, the self-inductance of a 2-AWG isolated wire
with a diameter of 0.26" is about half the inductance of a
30-AWG wire with a diameter of 0.01". One foot of 30-AWG
wire has 465nH of self-inductance.
Several methods exist to reduce a wire’s self-inductance.
One method divides the current flowing towards the
LT3033 between two parallel conductors. In this case,
placing the wires further apart reduces the inductance;
up to a 50% reduction when placed only a few inches
apart. Splitting the wires connects two equal inductors
in parallel. However, when placed in close proximity to
each other, mutual inductance adds to the overall self-
inductance of the wires. The most effective technique to
reducing overall inductance is to place the forward and
return current conductors (the input wire and the ground
wire) in close proximity. Tw o 30-AWG wires separated by
0.02" reduce the overall self-inductance to about one-fifth
of a single wire.
If a battery, mounted in close proximity, powers the LT3033,
a 10μF input capacitor suffices for stability. However, if a
distantly located supply powers the LT3033, use a larger
value input capacitor. Use a rough guideline of 1μF (in
addition to the 10μF minimum) per eight inches of wire
length. The minimum input capacitance needed to stabi-
lize the application also varies with power supply output
impedance variations. Placing additional capacitance on
the LT3033’s output also helps. However, this requires
an order of magnitude more capacitance in comparison
with additional LT3033 input bypassing. Series resistance
between the supply and the LT3033 input also helps stabi-
lize the application; as little as 0.1Ω to 0.5Ω suffices. This
impedance dampens the LC tank circuit at the expense of
dropout voltage. A better alternative is to use higher ESR
tantalum or electrolytic capacitors at the LT3033 input in
place of ceramic capacitors.
LT3033
15
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Output Capacitance and Transient Response
The LT3033’s design is stable with a wide range of output
capacitors, but is optimized for low ESR ceramic capaci-
tors. The output capacitor’s ESR affects stability, most
notably with small value capacitors. Use a minimum output
capacitor of 10μF with an ESR of less than 0.1Ω to prevent
oscillations. The LT3033 is a low voltage device and output
load transient response is a function of output capacitance.
Larger values of output capacitance decrease the peak
deviations and provide improved transient response for
large load current changes. Ceramic capacitors require extra
consideration. Manufacturers make ceramic capacitors
with a variety of dielectrics; each with a different behavior
across temperature and applied voltage. The most com-
mon dielectrics are Z5U, Y5V, X5R and X7R. Z5U and Y5V
dielectrics provide high C-V products in a small package
at low cost, but exhibit strong voltage and temperature
coefficients. X5R and X7R dielectrics yield highly stable
characteristics and are more suitable for use as the output
capacitor at fractionally increased cost. X7R works over a
larger temperature range and exhibits better temperature
stability whereas X5R is less expensive and is available in
higher values. Care still must be exercised when using X5R
and X7R capacitors. The X5R and X7R codes only specify
operating temperature range and maximum capacitance
change over temperature. Capacitance change due to DC
bias with X5R and X7R capacitors is better than Y5V and
Z5U capacitors, but can still be significant enough to drop
capacitor values below appropriate levels. Capacitor DC
bias characteristics tend to improve as component case
size increases, but expected capacitance at operating volt-
age should be verified. Figure 2 and Figure 3 show volt-
age coefficient and temperature coefficient comparisons
between Y5V and X5R material.
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or mi-
crophone works. For a ceramic capacitor, the stress
can be induced by vibrations in the system or thermal
transients. The resulting voltages produced can cause ap-
preciable amounts of noise. A ceramic capacitor produced
Figure 4’s trace in response to light tapping from a pencil.
Similar vibration induced behavior can masquerade as
increased output voltage noise.
Figure 2. Ceramic Capacitor DC Bias Characteristics
Figure 3. Ceramic Capacitor Temperature Characteristics
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
3033 F02
20
0
–20
–40
–60
–80
–100 04810
2 6 12 14
X5R
Y5V
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
TEMPERATURE (°C)
–50
40
20
0
–20
–40
–60
–80
–100 25 75
3033 F03
–25 0 50 100
125
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
1mV/DIV
1ms/DIV
3033 F04
VOUT = 1.3V
COUT = 10µF
ILOAD = 0
Figure 4. Noise Resulting from Tapping on a Ceramic Capacitor
LT3033
16
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
No-Load/Light-Load Recovery
A possible transient load step that occurs is where the
output current changes from its maximum level to zero
current or a very small load current. The output voltage
responds by overshooting until the regulator lowers the
amount of current it delivers to the new level. The regulator
loop response time and the amount of output capacitance
control the amount of overshoot. Once the regulator has
decreased its output current, the current provided by the
resistor divider (which sets VOUT) is the only current re-
maining to discharge the output capacitor from the level
to which it overshot. The amount of time it takes for the
output voltage to recover easily extends to milliseconds
with minimum divider current and many microfarads of
output capacitance.
To eliminate this problem, the LT3033 incorporates a
no-load or light load recovery circuit. This circuit is a
voltage-controlled current sink that significantly improves
the light load transient response time by discharging the
output capacitor quickly and then turning off. The current
sink turns on when the output voltage exceeds 5.3% of
the nominal output voltage. The current sink level is then
proportional to the overdrive above the threshold up to a
maximum of about 27mA. Consult the curve in the Typical
Performance Characteristics for the No-Load Recovery
Threshold.
If external circuitry forces the output above the no-load
recovery circuit’s threshold, the current sink turns on in
an attempt to restore the output voltage to nominal. The
current sink remains on until the external circuitry releases
the output. However, if the external circuitry pulls the
output voltage above the input voltage or the input falls
below the output, the LT3033 turns the current sink off and
shuts down the bias current/reference generator circuitry.
PWRGD Flag
The PWRGD flag indicates that the ADJ pin voltage is
within 8% of the regulated voltage. The PWRGD pin is an
open-collector output, capable of sinking 100μA of current
when the ADJ pin voltage is below 90.1% of the regulated
voltage. There is no internal pull-up on the PWRGD pin;
an external pull-up resistor must be used. As the ADJ
pin voltage rises above 92% of its regulated voltage, the
PWRGD pin switches to a high impedance state and the
external pull-up resistor pulls the PWRGD pin voltage up.
During normal operation, an internal glitch filter prevents
the PWRGD pin from switching to a low voltage state if
the ADJ pin voltage falls below the regulated voltage by
more than 10% in a short transient (<40μs typical) event.
The use of a feedforward capacitor, CFF, can result in
the ADJ pin being pulled artificially high during start-up
transients, which causes the PWRGD flag to assert early.
To avoid this problem, ensure that the REF/BYP capaci-
tor is significantly larger than the feedforward capacitor,
causing REF/BYP time constant to dominate over the time
constant of the resistor divider network.
IMON Pin Operation (Current Monitor)
The IMON pin is the collector of a PNP which mirrors
the LT3033 output PNP at a ratio of 1:2650 (see Block
Diagram). Additional circuitry compensates for early
voltage variation by regulating the collector of the IMON
mirror PNP at the output voltage. This circuitry is active
for VIMON ≤ (VOUT – 400mV). Use the IMON pin where the
early voltage compensation circuit is active and calculate
the output current from the simple equation:
IOUT = 2650 • (VIMON/RIMON)
The IMON mirror ratio is affected by power dissipation in
the LT3033; the IMON pin current increases at a rate of
approximately two percent per watt of power dissipation
in the device.
ILIM Pin Operation
The ILIM pin is the collector of a PNP which mirrors the
LT3033 output PNP at a ratio of 1:2650 (see Block Dia-
gram). The ILIM pin is also the input to the current limit
amplifier. If the output load increases to the point where
it causes the ILIM pin voltage to reach 0.198V, the cur-
rent limit amplifier takes control of the output regulation
so that the ILIM pin regulates at 0.198V, regardless of
the output voltage. The current limit threshold (ILIMIT) is
set by connecting a resistor (RILIM) from ILIM to GND:
RILIM = 2650 • (0.198V/ILIMIT) – 14Ω
In cases where the IN to OUT differential voltage exceeds
5V, fold-back current limit lowers the internal current limit
LT3033
17
Rev. A
For more information www.analog.com
level, possibly causing it to override the external program-
mable current limit. See the Internal Current Limit vs VIN
graph in the Typical Performance Characteristics section.
If the external programmable current limit is not needed,
tie the ILIM pin to GND. The external programmable cur-
rent limit is affected by power dissipation in the LT3033; it
decreases at a rate of approximately four percent per watt.
Paralleling Devices
Paralleling multiple LT3033s together produces higher
output current. Tie the individual OUT pins together and tie
the individual IN pins together. IMON pins combined with
an external NPN or NMOS current mirror create a simple
amplifier. This amplifier injects current into or out of the
feedback divider of the slave LT3033 to force the IMON
currents from each LT3033 to be equal. Figure 5 shows
an implementation with inexpensive 2N3904 NPN devices.
100Ω resistors provide 113mV emitter degeneration at
full load to guarantee good current mirror matching. The
feedback resistors of the slave LT3033 are split into sec-
tions to ensure adequate headroom for the slave 2N3904.
A 10nF, 5.1k capacitor and resistor combination added to
the IMON pin of the slave device frequency compensates
the feedback loop.
This circuit architecture is scalable to as many LT3033s
as are needed simply by extending the current mirror and
adding slave LT3033 devices. In addition to higher output
currents, this architecture also benefits heat spreading by
spreading the devices on the printed circuit board.
Thermal Considerations
The LT3033’s maximum rated junction temperature of
125°C limits its power handling capability. Tw o components
comprise the power dissipation of the device:
1. Output current multiplied by the input-to-output voltage
differential:
(ILOAD) • (VIN – VOUT) and
Figure 5. Paralleling Devices
APPLICATIONS INFORMATION
3033 F05
IN
REF/BYP
200mV
OUT
IMON
ADJ
2650x 1x
LT3033 (MASTER)
10nF
VOUT
1.5V
6A
+
–
–
+
25.5k
1%
3.92k
1%
22µF
INVIN
1.8V
200mV
OUT
IMON
ADJ
2650x 1x
LT3033 (SLAVE)
10nF
10µF
+
–
–
+
18.7k
1%
3.92k
1%
3.92k
1% 100Ω
5.1k
10nF
100Ω
2N3904
REF/BYP
LT3033
18
Rev. A
For more information www.analog.com
2. GND pin current multiplied by the input voltage:
(IGND) • (VIN)
GND pin current is found by examining the GND pin current
curves in the Typical Performance Characteristics. Power
dissipation equals the sum of the two components listed.
The LT3033’s internal thermal limiting (with hysteresis)
protects the device during overload conditions. For nor-
mal continuous conditions, do not exceed the maximum
junction temperature rating of 125°C (E- and I-grades).
Carefully consider all sources of thermal resistance from
junction to ambient including other heat sources mounted
in proximity to the LT3033.
The underside of the LT3033 UDC package has exposed
metal from the lead frame to the die attachment. Heat
transfers directly from the die junction to the printed circuit
board metal, allowing maximum junction temperature
control. The multiple IN and OUT pins of the LT3033
also assist in spreading heat to the PCB. Copper board
stiffeners and plated throughholes can also be used to
spread the heat generated by power devices. Table 2 lists
thermal resistance as a function of copper area in a fixed
board size. All measurements are taken in still air on a
4-layer FR-4 board with 1oz solid internal planes, and
2oz external trace planes with a total board thickness of
1.6mm. For more information on thermal resistance and
high thermal conductivity test boards, refer to JEDEC
standard JESD51, notably JESD51-12 and JESD51-7.
Achieving low thermal resistance necessitates attention
to detail and careful PCB layout.
Table 2. Measured Thermal Resistance for UDC Package
COPPER AREA BOARD AREA THERMAL
RESISTANCE
(JUNCTION-TO-
AMBIENT)
TOPSIDE* BACKSIDE
2500mm22500mm22500mm238°C/W
1000mm22500mm22500mm240°C/W
225mm22500mm22500mm241°C/W
100mm22500mm22500mm245°C/W
*Device is mounted on topside
PCB Layout Considerations
Given the probable high power consumption in the LT3033,
care must be taken in the layout of the PCB to achieve good
thermal performance. Figure 6 shows a recommended
layout that improves thermal resistance. The vias next to
the input and output exposed pads as shown in Figure
6 help improve the thermal resistance with 30°C/W as
measured on the demo board of the LT3033. Refer to the
LT3033’s DC2362A demo board manual for further details.
Calculating Junction Temperature
Example: Given an output voltage of 1.5V, an input voltage
range of 1.8V to 1.9V, an output load current range of 1mA
to 3A and a maximum ambient temperature of 70°C, what
is the maximum junction temperature for an application
using the UDC package?
The power dissipated by the device equals:
ILOAD(MAX) • (VIN(MAX) – VOUT) + IGND • (VIN(MAX))
where:
ILOAD(MAX) = 3A
VIN(MAX) = 1.9V
IGND at (ILOAD = 3A, VIN = 1.9V) = 27mA
so:
P = 3A • (1.9V – 1.5V) + 27mA • (1.9V) = 1.25W
The thermal resistance is about 40°C/W depending on
the copper area. So the junction temperature rise above
ambient is approximately equal to:
1.25W • (40°C/W) = 50°C
The maximum junction temperature equals the maximum
junction temperature rise above ambient plus the maximum
ambient temperature or:
TJMAX = 70°C + 50°C = 120°C
APPLICATIONS INFORMATION
LT3033
20
Rev. A
For more information www.analog.com
Protection Features
The LT3033 incorporates several protection features that
make it ideal for use in battery-powered circuits. In ad-
dition to the normal protection features associated with
monolithic regulators, such as current limiting and thermal
limiting, the device also protects against reverse-input
voltages, reverse-output voltages and reverse output to-
input voltages.
Current limit protection and thermal overload protection
protect the device against current overload conditions at
its output. For normal operation, do not exceed 125°C (E-
and I-grades) junction temperature. The typical thermal
shutdown temperature is 175°C and the thermal shutdown
circuit incorporates about 6°C of hysteresis.
The IN pins withstand reverse voltages of 10V. The LT3033
limits current flow to less than 10μA and no negative volt-
age appears at OUT. The device protects both itself and the
load against batteries that are plugged in backwards. The
LT3033 incurs no damage if OUT is pulled below ground.
If IN is left open circuited or grounded, OUT can be pulled
below ground by 10V. No current flows from the pass
transistor connected to OUT. However, current flows in
(but is limited by) the resistor divider that sets the output
voltage. Current flows from the bottom resistor in the
divider and from the ADJ pin’s internal clamp through the
top resistor in the divider to the external circuitry pulling
OUT below ground. If IN is powered by a voltage source,
OUT sources current equal to its current limit capability
and the LT3033 protects itself by thermal limiting. In this
case, grounding SHDN turns off the LT3033 and stops
OUT from sourcing current.
The LT3033 incurs no damage if the ADJ pin is pulled
above or below ground by 10V. If IN is left open-circuited
or grounded and ADJ is pulled above ground, ADJ acts
like a 10k resistor in series with two diodes. ADJ acts like
a 10k resistor if pulled below ground. If IN is powered by
a voltage source and ADJ is pulled below its reference
voltage, the LT3033 attempts to source its current limit
capability at OUT. The output voltage increases to VIN –
VDROPOUT with VDROPOUT set by whatever load current the
LT3033 supports. This condition can potentially damage
external circuitry powered by the LT3033 if the output
voltage increases to an unregulated high voltage. If IN
is powered by a voltage source and ADJ is pulled above
its reference voltage, two situations can occur. If ADJ is
pulled slightly above its reference voltage, the LT3033
turns off the pass transistor, no output current is sourced
and the output voltage decreases to either the voltage at
ADJ or less. If ADJ is pulled above its no-load recovery
threshold, the no-load recovery circuitry turns on and at-
tempts to sink current. OUT is actively pulled low and the
output voltage clamps at a Schottky diode above ground.
Please note that the behavior described above applies to
the LT3033 only. If a resistor divider is connected under
the same conditions, there will be additional R current.
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled to
ground, pulled to some intermediate voltage or is left open
circuit. In the case where the input is grounded, there is
less than 5μA of reverse output current. If the LT3033 IN
pin is forced below the OUT pin or the OUT pin is pulled
above the IN pin, input current drops to less than 30μA
typically. This occurs if the LT3033 input is connected to
a discharged (low voltage) battery and either a backup
battery or a second regulator circuit holds up the output.
The state of the SHDN pin has no effect on the reverse
output current if OUT is pulled above IN.
APPLICATIONS INFORMATION
LT3033
21
Rev. A
For more information www.analog.com
Overload Recovery
Like many IC power regulators, the LT3033 has safe
operating area (SOA) protection. The safe area protec-
tion decreases current limit as input-to-output voltage
increases and keeps the power transistor inside a safe
operating region for all values of input-to-output voltage.
The protective design provides some output current at
all values of input-to-output voltage up to the specified
maximum operational input voltage of 10V.
When power is first applied, as input voltage rises, the
output follows the input, allowing the regulator to start-
up into heavy loads. During start-up, as the input voltage
is rising, the input-to-output voltage differential is small,
allowing the regulator to supply large output currents.
With a high input voltage, an event can occur wherein
removal of an output short will not allow the output to
recover. The event occurs with a heavy output load when
the input voltage is high and the output voltage is low.
Common situations occur immediately after the removal
of a short-circuit or if the shutdown pin is pulled high after
the input voltage has already been turned on. The load line
intersects the output current curve at two points creating
two stable output operating points for the regulator. With
this double intersection, the input power supply may need
to be cycled down to zero and brought up again to make
the output recover.
APPLICATIONS INFORMATION
LT3033
22
Rev. A
For more information www.analog.com
PACKAGE DESCRIPTION
3.00 ±0.10
4.00 ±0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 5)
0.35 ±0.10
0.50
BSC
PIN 1 ID
0.40±0.10
1.100
BSC
0.019
BSC
0.61
TYP
0.25
±0.05
1
6
11
16
17 20
710
BOTTOM VIEW—EXPOSED PAD
2.50 REF
0.75 ±0.05
R = 0.110
TYP
0.200 REF
0.00 – 0.05
(UDC20) QFN 0618 REV B
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1536 Rev B)
Exposed Pad Variation AB
1.225
BSC
1.225 BSC
0.41 ±0.10
1.50 REF
0.25 ±0.10
1.100
BSC
0.61
±0.05
0.61
±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
2.50 REF
3.10 ±0.05
4.50 ±0.05
1.50 REF
2.10 ±0.05
3.50 ±0.05
PACKAGE OUTLINE
0.50 BSC
0.41
±0.05
0.25 ±0.05
1.225
BSC
0.019
BSC
0.61
TYP
LT3033
23
Rev. A
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 02/19 Edited Part Marking in the Order Information Section. Changed from 3033 to LGVQ. 2
LT3033
24
Rev. A
For more information www.analog.com
D16954-0-02/19(A)
www.analog.com
ANALOG DEVICES, INC. 2018-2019
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Cable Drop Compensation
3033 TA02
IN
REF/BYP
200mV OUT
IMON
ADJ
2650x1x
LT3033
10nF +
–
–
+
RCABLE • 2650
RCABLE/2
RCABLE/2
95.3k – RCABLE • 2650
1k 1k 3.92k
100nF
10nF
10µF
2N3904
VIN
7V
10µF 10µF
+
–
5V, COMPENSATED
FOR DROP ALONG
RCABLE/2 RESISTORS
