Product Folder Order Now Technical Documents Support & Community Tools & Software LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 LMC6484 CMOS, Quad, Rail-to-Rail Input and Output, Operational Amplifier 1 Features 3 Description * The LMC6484 device provides a common-mode range that extends to both supply rails. This rail-to-rail performance combined with excellent accuracy, due to a high CMRR, makes this device unique among rail-to-rail input amplifiers. 1 * * * * * * Rail-to-rail input common-mode voltage range (specified over temperature) Rail-to-rail output swing (within 20 mV of supply rail, 100-k load) Specified 3-V, 5-V and 15-V performance Excellent CMRR and PSRR: 82 dB Ultra-low input current: 20 fA High voltage gain (RL = 500 k): 130 dB Specified for 2-k and 600- loads 2 Applications * * * * * * * * * * * Data acquisition (DAQ) Currency counter Oscilloscope (DSO) Intra-DC interconnect (METRO) Macro remote radio unit (RRU) Multiparameter patient monitor Merchant telecom rectifiers Train control and management Process analytics (pH, gas, concentration, force, and humidity) Three phase UPS Improved replacement for TLC274, TLC279 The LMC6484 is an excellent choice for systems, such as data acquisition, that require a large input signal range. The device is also an excellent upgrade for circuits using limited common-mode range amplifiers, such as the TLC274 and TLC279. Maximum dynamic signal range is maintained in low voltage and single-supply systems by the rail-to-rail output swing of the LMC6484. The rail-to-rail output swing of the LMC6484 is specified for loads down to 600 . Specified low voltage characteristics and low power dissipation make the LMC6484 an excellent choice for battery-operated systems. See the LMC6482 for a dual CMOS operational amplifier with these same features. Device Information(1) PART NUMBER LMC6484 PACKAGE BODY SIZE (NOM) SOIC (14) 8.65 mm x 3.91 mm PDIP (14) 19.177 mm x 6.35 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Single-Ended Unity Gain Buffer 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 1 1 1 2 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 DC Electrical Characteristics for LMC6484AI ........... 5 DC Electrical Characteristics for LMC6484I.............. 7 DC Electrical Characteristics for LMC6484M............ 9 DC Electrical Characteristics for LMC6484AI ......... 11 DC Electrical Characteristics for LMC6484I............ 11 DC Electrical Characteristics for LMC6484M........ 12 AC Electrical Characteristics for LMC6484A ........ 13 AC Electrical Characteristics for LMC6484I.......... 13 AC Electrical Characteristics for LMC6484M........ 14 AC Electrical Characteristics: V+ = 3 V, V- = 0 V . 14 Typical Characteristics .......................................... 15 7 Detailed Description ............................................ 23 7.1 7.2 7.3 7.4 8 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 23 23 23 24 Application and Implementation ........................ 25 8.1 Application Information............................................ 25 8.2 Typical Application ................................................. 25 8.3 System Examples ................................................... 31 9 Power Supply Recommendations...................... 36 10 Layout................................................................... 36 10.1 Layout Guidelines ................................................. 36 10.2 Layout Example .................................................... 37 11 Device and Documentation Support ................. 38 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Documentation Support ........................................ Support Resources ............................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 38 38 38 38 38 38 12 Mechanical, Packaging, and Orderable Information ........................................................... 38 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (September 2015) to Revision D Page * Deleted old note 3 from DC Electrical Characteristics for LMC6484AI table ......................................................................... 5 * Deleted old note 3 from DC Electrical Characteristics for LMC6484I table ........................................................................... 7 * Deleted old note 3 from DC Electrical Characteristics for LMC6484M table ........................................................................ 9 Changes from Revision B (August 2000) to Revision C * 2 Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1 Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 5 Pin Configuration and Functions D or NFF Packages 14-Pin SOIC or PDIP Top View Pin Functions PIN NO. NAME TYPE DESCRIPTION 1 OUTPUT1 O Output for Amplifier 1 2 INVERTING INPUT1 I Inverting input for Amplifier 1 3 NONINVERTING INPUT1 I Noninverting input for Amplifier 1 4 V+ P Positive voltage supply pin 5 NONINTERTING INPUT2 I Noninverting input for Amplifier 2 6 INVERTING INPUT2 I Inverting input for Amplifier 2 7 OUTPUT2 O Output for Amplifier 2 8 OUTPUT3 O Output for Amplifier 3 9 INVERTING INPUT3 I Inverting input for Amplifier 3 10 NONINVERTING INPUT3 I Noninverting input for Amplifier 3 11 V- P Negative supply voltage pin 12 NONINVERTING INPUT4 I Noninverting input for Amplifier 4 13 INVERTING INPUT4 I Inverting input for Amplifier 4 14 OUTPUT4 O Output for Amplifier 5 Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 3 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings See (1) (2) MIN Differential input voltage (V-) - 0.3 Voltage at input/output pin + MAX (V+) + 0.3 - 16 V Current at input pin (3) 5 mA 30 mA 40 mA 150 C 150 C Current at power supply pin TJ Junction temperature (6) Tstg Storage temperature, Tstg (2) (3) (4) (5) (6) V Supply voltage (V - V ) Current at output pin (4) (5) (1) UNIT Supply Voltage -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications. Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings. Applies to both single supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150C. Output currents in excess of 30 mA over long term may adversely affect reliability. Do not short circuit output to V+, when V+ is greater than 13 V or reliability will be adversely affected. The maximum power dissipation is a function of TJ(max), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) - TA)/RJA. All numbers apply for packages soldered directly into a PC board. 6.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2) VALUE UNIT 2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Human body model, 1.5-k resistor in series with 100 pF. All pins rated per method 3015.6 of MIL-STD-883. This is a class 2 device rating. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) V+ MIN MAX Supply voltage TJ Junction temperature UNIT 3 15.5 V LMC6484AM -55 125 C LMC6484AI, LMC6484I -40 85 C 6.4 Thermal Information LMC6484 THERMAL METRIC RJA (1) 4 (1) Junction-to-ambient thermal resistance D (SOIC) NFF (PDIP) 14 PINS 14 PINS 110 70 UNIT C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 6.5 DC Electrical Characteristics for LMC6484AI unless otherwise specified, all limits specified for TJ = 25C, V+ = 5 V, V- = 0 V, VCM = VO = V+/2, and RL > 1 M PARAMETER VOS Input offset voltage TCVOS Input offset voltage average drift IB Input current IOS Input offset current CIN Common-mode input capacitance RIN Input resistance TEST CONDITIONS TYP (2) MAX (1) 0.11 0.75 At the temperature extremes pA 2 3 pF >10 Positive power supply rejection ratio 5 V V+ 15 V V- = 0 V VO = 2.5 V -PSRR Negative power supply rejection ratio -5 V V- -15 V V+ = 0 V VO = -2.5 V 70 At the temperature extremes dB 82 dB 67 70 At the temperature extremes 82 67 70 At the temperature extremes dB 67 70 At the temperature extremes V+ = 5 V and 15 V For CMRR 50 dB 82 dB 67 At the temperature extremes Sourcing Sinking At the temperature extremes Sourcing At the temperature extremes Sinking At the temperature extremes RL = 2 k (3) V 666 V/mV 75 V/mV 20 80 RL = 600 (3) V+ + 0.3 84 35 Large signal voltage gain V V+ 140 At the temperature extremes -0.25 0 V+ + 0.25 At the temperature extremes Tera 82 V- - 0.3 (1) (2) (3) pA 4 At the temperature extremes +PSRR AV V/C 0.01 0 V VCM 5 V V+ = 5 V VCM mV 0.02 At the temperature extremes Common-mode rejection ratio Input commonmode voltage range UNIT 1.35 1 0 V VCM 15 V V+ = 15 V CMRR MIN (1) 300 V/mV 48 20 35 V/mV 13 All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric normal. V+ = 15 V, VCM = 7.5 V and RL connected to 7.5 V. For sourcing tests, 7.5 V VO 11.5 V. For sinking tests, 3.5 V VO 7.5 V. Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 5 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com DC Electrical Characteristics for LMC6484AI (continued) unless otherwise specified, all limits specified for TJ = 25C, V+ = 5 V, V- = 0 V, VCM = VO = V+/2, and RL > 1 M PARAMETER TEST CONDITIONS + V =5V RL = 2 k to V+/2 At the temperature extremes MIN (1) TYP (2) 4.8 4.9 0.1 VO At the temperature extremes V 4.24 0.3 V+ = 15 V RL = 2 k to V+/2 V 14.2 0.16 + V = 15 V RL = 600 to V+/2 V 13 0.5 ISC Output short circuit current V+ = 5 V Sinking, VO = 5 V At the temperature extremes ISC IS (4) 6 Output short circuit current V+ = 15 V Supply current Sinking, VO = 12 V (4) At the temperature extremes 15 mA 30 mA 22 30 At the temperature extremes mA 9.5 28 Sourcing, VO = 0 V 30 mA 24 2 All four amplifiers V+ = +5 V, VO = V+/2 At the temperature extremes All four amplifiers V+ = +15 V, VO = V+/2 At the temperature extremes V 20 12 11 At the temperature extremes 1 1.3 16 V 14.1 At the temperature extremes Sourcing, VO = 0 V 0.32 0.45 13.4 V 14.7 At the temperature extremes At the temperature extremes 0.5 0.65 14.4 At the temperature extremes V 4.7 At the temperature extremes Output swing 0.18 0.24 4.5 UNIT V 4.7 At the temperature extremes V+ = 5 V RL = 600 to V+/2 MAX (1) 2.8 3.6 2.6 mA 3 3.8 mA When V+ is greater than 13 V, do not short circuit output to V+ or reliability will be adversely affected. Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 6.6 DC Electrical Characteristics for LMC6484I unless otherwise specified, all limits specified for TJ = 25C, V+ = 5 V, V- = 0 V, VCM = VO = V+/2, and RL > 1 M PARAMETER VOS Input offset voltage TCVOS Input offset voltage average drift IB Input current IOS Input offset current CIN Common-mode input capacitance RIN Input resistance CMRR Common-mode rejection ratio MIN (1) TEST CONDITIONS TYP (2) 0.11 At the temperature extremes mV V/C 0.02 At the temperature extremes pA 4 0.01 At the temperature extremes pA 2 3 pF >10 65 0 V VCM 15 V V+ = 15 V At the temperature extremes 65 0 V VCM 5 V V+ = 5 V At the temperature extremes 82 -PSRR -5 V V- -15 V Negative power supply rejection ratio V+ = 0 V, VO = -2.5 V At the temperature extremes 65 82 65 82 RL = 2 k (3) Large signal voltage gain At the temperature extremes RL = 600 At the temperature extremes Sinking At the temperature extremes (3) V+ + 0.3 V 666 72 75 20 50 Sourcing V V 35 Sinking -0.25 + 120 At the temperature extremes dB 0 V+ + 0.25 Sourcing dB 62 At the temperature extremes At the temperature extremes dB 82 V- - 0.3 Input common-mode V = 5 V and 15 V voltage range For CMRR 50 dB dB 60 62 + Tera 62 At the temperature extremes (1) (2) (3) 3 1 5 V V+ 15 V Positive power supply rejection ratio V- = 0 V, VO = 2.5 V AV UNIT 3.7 +PSRR VCM MAX (1) 300 V/mV 30 15 35 10 All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric normal. V+ = 15 V, VCM = 7.5 V and RL connected to 7.5 V. For sourcing tests, 7.5 V VO 11.5 V. For sinking tests, 3.5 V VO 7.5 V. Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 7 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com DC Electrical Characteristics for LMC6484I (continued) unless otherwise specified, all limits specified for TJ = 25C, V+ = 5 V, V- = 0 V, VCM = VO = V+/2, and RL > 1 M PARAMETER TEST CONDITIONS V+ = 5 V RL = 2 k to V+/2 At the temperature extremes MIN (1) TYP (2) 4.8 4.9 0.1 VO 4.7 0.3 V = 15 V RL = 2 k to V+/2 At the temperature extremes 14.7 0.16 V = 15 V RL = 600 to V+/2 At the temperature extremes 14.1 0.5 ISC ISC IS (4) 8 Output short circuit current V+ = 15 V Supply current Sourcing, VO = 0 V Sinking, VO = 5 V Sourcing, VO = 0 V Sinking, VO = 12 V (4) All four amplifiers V+ = +5 V VO = V+/2 All four amplifiers V+ = +15 V VO = V+/2 At the temperature extremes 12 At the temperature extremes 9.5 11 28 At the temperature extremes 20 15 mA 30 mA 30 mA 24 2 At the temperature extremes 2.8 3.6 2.6 At the temperature extremes V mA 22 30 At the temperature extremes 1 1.3 16 V V 13 At the temperature extremes Output short circuit current V+ = 5 V 0.32 0.45 13.4 V V 14.2 At the temperature extremes + 0.5 0.65 14.4 + V V 4.24 At the temperature extremes Output swing 0.18 0.24 4.5 At the temperature extremes UNIT V 4.7 At the temperature extremes V+ = 5 V RL = 600 to V+/2 MAX (1) mA 3 3.8 mA When V+ is greater than 13 V, do not short circuit output to V+ or reliability will be adversely affected. Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 6.7 DC Electrical Characteristics for LMC6484M unless otherwise specified, all limits specified for TJ = 25C, V+ = 5 V, V- = 0 V, VCM = VO = V+/2, and RL > 1 M PARAMETER VOS Input offset voltage TCVOS Input offset voltage average drift IB Input current IOS Input offset current CIN Common-mode input capacitance RIN Input resistance CMRR Common-mode rejection ratio TEST CONDITIONS MIN (1) TYP (2) 0.11 At the temperature extremes mV V/C 0.02 At the temperature extremes pA 100 0.01 At the temperature extremes pA 50 3 pF >10 0 V VCM 15 V V+ = 15 V 0 V VCM 5 V V+ = 5 V 65 At the temperature extremes 65 5 V V+ 15 V Positive power supply rejection ratio V- = 0 V, VO = 2.5 V At the temperature extremes 65 -5 V V- -15 V Negative power + supply rejection ratio V = 0 V VO = -2.5 V 65 -PSRR At the temperature extremes 82 Input common-mode V = 5 V and 15 V voltage range For CMRR 50 dB 82 82 dB RL = 2 k Sinking At the temperature extremes (3) At the temperature extremes Sinking At the temperature extremes RL = 600 (3) V+ + 0.3 V 666 72 75 20 50 Sourcing V V+ 35 Large signal voltage gain -0.25 0 120 Sourcing dB 60 V+ + 0.25 At the temperature extremes dB 60 At the temperature extremes At the temperature extremes dB 8 V- - 0.3 + Tera 60 +PSRR (1) (2) (3) 3 1 60 AV UNIT 3.8 At the temperature extremes VCM MAX (1) 300 V/mV 30 15 35 10 All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric normal. V+ = 15 V, VCM = 7.5 V and RL connected to 7.5 V. For sourcing tests, 7.5 V VO 11.5 V. For sinking tests, 3.5 V VO 7.5 V. Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 9 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com DC Electrical Characteristics for LMC6484M (continued) unless otherwise specified, all limits specified for TJ = 25C, V+ = 5 V, V- = 0 V, VCM = VO = V+/2, and RL > 1 M PARAMETER TEST CONDITIONS V+ = 5 V RL = 2 k to V+/2 At the temperature extremes MIN (1) TYP (2) 4.8 4.9 0.1 VO 4.7 0.3 V = 15 V RL = 2 k to V+/2 At the temperature extremes 14.7 0.16 V = 15 V RL = 600 to V+/2 At the temperature extremes 14.1 0.5 ISC ISC IS (4) 10 Output short circuit current V+ = 15 V Supply current Sourcing, VO = 0 V Sinking, VO = 5 V Sourcing, VO = 0 V Sinking, VO = 12 V (4) All four amplifiers V+ = +5 V VO = V+/2 All four amplifiers V+ = +15 V, VO = V+/2 At the temperature extremes At the temperature extremes 15 mA 30 mA 20 30 30 mA 22 2 At the temperature extremes 2.8 3.8 2.6 At the temperature extremes V mA 8 28 At the temperature extremes 20 10 11 At the temperature extremes 1 1.3 16 V V 13 At the temperature extremes Output short circuit current V+ = 5 V 0.32 0.45 13.4 V V 14.2 At the temperature extremes + 0.5 0.65 14.4 + V V 4.24 At the temperature extremes Output swing 0.18 0.24 4.5 At the temperature extremes UNIT V 4.7 At the temperature extremes V+ = 5 V RL = 600 to V+/2 MAX (1) mA 3 4 mA When V+ is greater than 13 V, do not short circuit output to V+ or reliability will be adversely affected. Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 6.8 DC Electrical Characteristics for LMC6484AI unless otherwise specified, all limits specified for TJ = 25C, V+ = 3 V, V- = 0 V, VCM = VO = V+/2, and RL > 1 M PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) 0.9 VOS Input offset voltage TCVOS Input offset voltage average drift IB Input bias current IOS Input offset current CMRR Common-mode rejection ratio 0 V VCM 3 V 64 PSRR Power supply rejection ratio 3 V V+ 15 V, V- = 0 V 68 2 At the temperature extremes 2.7 2 Input common-mode voltage range For CMRR 50 dB V/C pA 0.01 pA 74 dB 80 dB V - 0.25 V+ Output swing RL = 600 to V+/2 IS (1) (2) Supply current All four amplifiers 0 V V+ + 0.25 V 2.8 V 0.2 V RL = 2 k to V+/2 VO mV 0.02 - VCM UNIT 2.5 2.7 V 0.37 0.6 1.65 2.5 At the temperature extremes 3 V mA All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric normal. 6.9 DC Electrical Characteristics for LMC6484I unless otherwise specified, all limits specified for TJ = 25C, V+ = 3 V, V- = 0 V, VCM = VO = V+/2, and RL > 1 M PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) 0.9 3 VOS Input offset voltage TCVOS Input offset voltage average drift IB Input bias current IOS Input offset current CMRR Common-mode rejection ratio 0 V VCM 3 V 60 PSRR Power supply rejection ratio 3 V V+ 15 V, V- = 0 V 60 80 VCM Input common-mode voltage range At the temperature extremes 3.7 2 + V RL = 2 k to V+/2 VO Output swing 2.5 RL = 600 to V+/2 IS (1) (2) Supply current All four amplifiers At the temperature extremes mV V/C 0.02 pA 0.01 pA 74 dB V- - 0.25 For CMRR 50 dB UNIT dB 0 + V V + 0.25 V 2.8 V 0.2 V 2.7 V 0.37 0.6 1.65 2.5 3 V mA All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric normal. Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 11 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com 6.10 DC Electrical Characteristics for LMC6484M unless otherwise specified, all limits specified for TJ = 25C, V+ = 3 V, V- = 0 V, VCM = VO = V+/2, and RL > 1 M PARAMETER TEST CONDITIONS MIN (1) TYP (2) 0.9 MAX (1) 3 UNIT VOS Input offset voltage TCVOS Input offset voltage average drift IB Input bias current 0.02 pA IOS Input offset current 0.01 pA CMRR Common-mode rejection ratio 74 dB PSRR Power supply rejection ratio VCM Input common-mode voltage range At the temperature extremes 3.8 2 0 V VCM 3 V 60 - + 3 V V 15 V, V = 0 V 60 For CMRR 50 dB V+ RL = 2 k to V+/2 VO Output swing 2.5 RL = 600 to V+/2 IS (1) (2) 12 Supply current All four amplifiers At the temperature extremes V/C 80 V- - 0.25 mV dB 0 V V+ + 0.25 V 2.8 V 0.2 V 2.7 V 0.37 0.6 1.65 2.5 3.2 V mA All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric normal. Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 6.11 AC Electrical Characteristics for LMC6484A unless otherwise specified, all limits specified for TJ = 25C, V+ = 5 V, V- = 0 V, VCM = VO = V+ / 2, and RL > 1 M PARAMETER SR Slew rate (3) GBW Gain-bandwidth product m Gm TEST CONDITIONS At the temperature extremes MIN (1) TYP (2) 1 1.3 V+ = 15 V 1.5 MHz Phase margin 50 Deg Gain margin 15 dB 150 dB 37 nVHz 0.03 pAHz en Input-referred voltage noise f = 1 kHz, VCM = 1 V in Input-referred current noise f = 1 kHz THD Total harmonic distortion f = 1 kHz, AV = -2, RL = 10 k, VO = 4.1 VPP 0.01% f = 10 kHz, AV = -2, RL = 10 k, VO = 8.5 VPP, V+ = 10 V 0.01% (4) UNIT V/s 0.7 Amplifier-to-amplifier isolation (4) (1) (2) (3) MAX (1) All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric normal. V+ = 15 V. Connected as voltage follower with 10-V step input. Number specified is the slower of either the positive or negative slew rates. Input referred, V+ = 15 V and RL = 100 k connected to 7.5 V. Each amplifier excited in turn with 1 kHz to produce VO = 12 VPP. 6.12 AC Electrical Characteristics for LMC6484I unless otherwise specified, all limits specified for TJ = 25C, V+ = 5 V, V- = 0 V, VCM = VO = V+/2, and RL > 1M PARAMETER TEST CONDITIONS MIN (1) TYP (2) 0.9 1.3 MAX (1) UNIT SR Slew rate (3) GBW Gain-bandwidth product 1.5 MHz m Phase margin 50 Deg Gm Gain margin 15 dB 150 dB 37 nVHz 0.03 pAHz At the temperature extremes V+ = 15 V Amplifier-to-amplifier isolation (4) en Input-referred voltage noise f = 1 kHz, VCM = 1 V in Input-referred current noise f = 1 kHz THD Total harmonic distortion f = 1 kHz, AV = -2, RL = 10 k, VO = 4.1 VPP 0.01% f = 10 kHz, AV = -2, RL = 10 k, VO = 8.5 VPP, V+ = 10 V 0.01% (1) (2) (3) (4) V/s 0.63 All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric normal. V+ = 15 V. Connected as Voltage Follower with 10-V step input. Number specified is the slower of either the positive or negative slew rates. Input referred, V+ = 15 V and RL = 100 k connected to 7.5 V. Each amp excited in turn with 1 kHz to produce VO = 12 VPP. Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 13 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com 6.13 AC Electrical Characteristics for LMC6484M unless otherwise specified, all limits specified for TJ = 25C, V+ = 5 V, V- = 0 V, VCM = VO = V+/2, and RL > 1M PARAMETER SR Slew rate (3) GBW Gain-bandwidth product m Phase margin Gm Gain margin TEST CONDITIONS MIN (1) TYP (2) 0.9 1.3 At the temperature extremes 0.54 V+ = 15 V Amplifier-to-amplifier isolation (4) en Input-referred voltage noise f = 1 kHz, VCM = 1 V in Input-referred current noise f = 1 kHz THD (1) (2) (3) (4) Total harmonic distortion MAX (1) UNIT V/s 1.5 MHz 50 Deg 15 dB 150 dB 37 nVHz 0.03 pAHz f = 1 kHz, AV = -2, RL = 10 k, VO = 4.1 VPP 0.01% f = 10 kHz, AV = -2, RL = 10 k, VO = 8.5 VPP, V+ = 10 V 0.01% All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric normal. V+ = 15 V. Connected as Voltage Follower with 10-V step input. Number specified is the slower of either the positive or negative slew rates. Input referred, V+ = 15 V and RL = 100 k connected to 7.5 V. Each amplifier excited in turn with 1 kHz to produce VO = 12 VPP. 6.14 AC Electrical Characteristics: V+ = 3 V, V- = 0 V unless otherwise specified, V+ = 3 V, V- = 0 V, VCM = VO = V+/2, and RL > 1M PARAMETER SR Slew rate (3) GBW Gain-bandwidth product THD (1) (2) (3) 14 Total harmonic distortion TEST CONDITIONS f = 10 kHz, AV = -2, RL = 10 k, VO = 2 VPP LMC6484AI, LMC6484I, LMC6484M MIN (1) TYP (2) MAX (1) UNIT 0.9 V/s 1 MHz 0.01% All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric normal. Connected as voltage follower with 2-V step input. Number specified is the slower of either the positive or negative slew rates. Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 6.15 Typical Characteristics at VS = 15 V, single supply, and TA = 25C (unless otherwise specified) Figure 1. Supply Current vs Supply Voltage Figure 2. Input Current vs Temperature Figure 3. Sourcing Current vs Output Voltage Figure 4. Sourcing Current vs Output Voltage Figure 5. Sourcing Current vs Output Voltage Figure 6. Sinking Current vs Output Voltage Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 15 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com Typical Characteristics (continued) at VS = 15 V, single supply, and TA = 25C (unless otherwise specified) Figure 7. Sinking Current vs Output Voltage Figure 8. Sinking Current vs Output Voltage . 16 Figure 9. Output Voltage Swing vs Supply Voltage Figure 10. Input Voltage Noise vs Frequency Figure 11. Input Voltage Noise vs Input Voltage Figure 12. Input Voltage Noise vs Input Voltage Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 Typical Characteristics (continued) at VS = 15 V, single supply, and TA = 25C (unless otherwise specified) Figure 13. Input Voltage Noise vs Input Voltage Figure 14. Crosstalk Rejection vs Frequency Figure 15. Crosstalk Rejection vs Frequency Figure 16. Positive PSRR vs Frequency Figure 17. Negative PSRR vs Frequency Figure 18. CMRR vs Frequency Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 17 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com Typical Characteristics (continued) at VS = 15 V, single supply, and TA = 25C (unless otherwise specified) 18 Figure 19. CMRR vs Input Voltage Figure 20. CMRR vs Input Voltage Figure 21. CMRR vs Input Voltage Figure 22. VOS vs CMR Figure 23. VOS vs CMR Figure 24. Input Voltage vs Output Voltage Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 Typical Characteristics (continued) at VS = 15 V, single supply, and TA = 25C (unless otherwise specified) Figure 25. Input Voltage vs Output Voltage Figure 26. Open Loop Frequency Response Figure 27. Noninverting Large Signal Pulse Response Figure 28. Noninverting Large Signal Pulse Response Figure 29. Noninverting Large Signal Pulse Response Figure 30. Noninverting Small Signal Pulse Response Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 19 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com Typical Characteristics (continued) at VS = 15 V, single supply, and TA = 25C (unless otherwise specified) 20 Figure 31. Noninverting Small Signal Pulse Response Figure 32. Noninverting Small Signal Pulse Response Figure 33. Inverting Large Signal Pulse Response Figure 34. Inverting Large Signal Pulse Response Figure 35. Inverting Large Signal Pulse Response Figure 36. Inverting Small Signal Pulse Response Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 Typical Characteristics (continued) at VS = 15 V, single supply, and TA = 25C (unless otherwise specified) Figure 37. Inverting Small Signal Pulse Response Figure 38. Inverting Small Signal Pulse Response Figure 39. Stability vs Capacitive Load Figure 40. Stability vs Capacitive Load Figure 41. Stability vs Capacitive Load Figure 42. Stability vs Capacitive Load Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 21 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com Typical Characteristics (continued) at VS = 15 V, single supply, and TA = 25C (unless otherwise specified) Figure 43. Stability vs Capacitive Load 22 Submit Documentation Feedback Figure 44. Stability vs Capacitive Load Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 7 Detailed Description 7.1 Overview The LMC6484 is a quad operational amplifier that offers a low-cost, low-power amplifier for applications requiring multiple operational amplifier stages and rail-to-rail operation. This device supports a wide supply range (3 V to 15 V) and excellent amplifier-to-amplifier isolation (150 dB typical). This device is an excellent choice for batterypowered signal acquisition systems requiring highly integrated solutions to achieve efficient layout. 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Amplifier Topology The LMC6484 incorporates specially designed, wide-compliance range current mirrors, and the body effect to extend input common-mode range to each supply rail. Complementary, paralleled, differential input stages, like the type used in other CMOS and bipolar rail-to-rail input amplifiers, are not used because of their inherent accuracy problems due to CMRR, crossover distortion, and open-loop gain variation. The input stage design of the LMC6484 is complemented by an output stage capable of rail-to-rail output swing even when driving a large load. Rail-to-rail output swing is obtained by taking the output directly from the internal integrator instead of an output buffer stage. 7.3.2 Input Common-Mode Voltage Range Unlike Bi-FET amplifier designs, the LMC6484 does not exhibit phase inversion when an input voltage exceeds the negative supply voltage. Figure 46 shows an input voltage exceeding both supplies with no resulting phase inversion on the output. Figure 45. An Input Voltage Signal Exceeds the LMC6484 Power Supply Voltages With No Output Phase Inversion Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 23 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com Feature Description (continued) The absolute maximum input voltage is 300 mV beyond either supply rail at room temperature. Voltages greatly exceeding this absolute maximum rating, as in Figure 46, can cause excessive current to flow in or out of the input pins possibly affecting reliability. Figure 46. A 7.5V Input Signal Greatly Exceeds the 3-V Supply in Figure 47 Causing No Phase Inversion due to RI Applications that exceed this rating must externally limit the maximum input current to 5 mA with an input resistor, as shown in Figure 47. Figure 47. RI Input Current Protection for Voltages Exceeding the Supply Voltage 7.3.3 Rail-to-Rail Output The approximated output resistance of the LMC6484 is 180- sourcing and 130- sinking at VS = 3 V, and 110 sourcing and 83- sinking at VS = 5 V. Using the calculated output resistance, the maximum output voltage swing can be estimated as a function of load. 7.4 Device Functional Modes The LMC6482 may be used in applications where each amplifier channel is used independently, or in applications with cascaded channels. See the Typical Application section for more information. 24 Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Upgrading Applications The LMC6484 quad-channel devices and LMC6482 dual-channel devices have industry standard pinouts to retrofit existing applications. System performance can be greatly increased by the features of the LMC6484. The key benefit of designing in the LMC6484 is increased linear signal range. Most operational amplifiers have limited input common-mode ranges. Signals that exceed this range generate a nonlinear output response that persists long after the input signal returns to the common-mode range. Linear signal range is vital in applications such as filters, where signal peaking can exceed input common-mode ranges, and result in output phase inversion or severe distortion. 8.1.2 Spice Macromodel A * * * * * * spice macromodel is available for the LMC6484. This model includes accurate simulation of the following: Input common-mode voltage range Frequency and transient response GBW dependence on loading conditions Quiescent and dynamic supply current Output swing dependence on loading conditions Many more characteristics, as listed on the macromodel disk. Contact your local Texas Instruments sales office to obtain an operational amplifier spice model library disk. 8.2 Typical Application RF CF RO VOUT VIN + CL Figure 48. Unity Gain Buffer for High-Capacitive Loads Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 25 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com Typical Application (continued) 8.2.1 Design Requirements * For best performance, make sure that the input voltage swing is between V+ and V-. * Make sure that the input does not exceed the common-mode input range. * To reduce the risk of de-stabilizing the output, use resistive isolation on the output when driving capacitive loads (see the Capacitive Load Compensation section). * When large feedback resistors are used, compensate for parasitic capacitance on the input as needed (see the Compensating for Input Capacitance section). 8.2.2 Detailed Design Procedure 8.2.2.1 Capacitive Load Compensation The LMC6484 typically directly drives a 100-pF load with VS = 15 V at unity gain without oscillating. The unity gain follower is the most sensitive configuration. Direct capacitive loading reduces the phase margin of operational amplifiers. The combination of the output impedance of the operational amplifier and the capacitive load induces phase lag that results in either an under-damped pulse response or oscillation. Capacitive load compensation can be accomplished using resistive isolation, as shown in Figure 49. This simple technique is useful for isolating the capacitive input of multiplexers and analog-to-digital converters (ADCs). Figure 49. Resistive Isolation of a 330-pF Capacitive Load Figure 50. Pulse Response of the LMC6484 Circuit in Figure 49 26 Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 Typical Application (continued) Improved frequency response is achieved by indirectly driving capacitive loads as shown in Figure 51. Figure 51. LMC6484 Noninverting Amplifier Compensated to Handle a 330-pF Capacitive Load R1 and C1 serve to counteract the loss of phase margin by feeding forward the high-frequency component of the output signal back to the inverting input of the amplifier; thereby, preserving phase margin in the overall feedback loop. The values of R1 and C1 are experimentally determined for the desired pulse response. The resulting pulse response is seen in Figure 52. Figure 52. Pulse Response of LMC6484 Circuit in Figure 51 Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 27 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com Typical Application (continued) 8.2.2.2 Compensating for Input Capacitance Large values of feedback resistance are often used with amplifiers that have ultra-low input current, such as the LMC6484. Large feedback resistors can react with small values of input capacitance due to transducers, photodiodes, and circuit-board parasitics to reduce phase margins. Figure 53. Canceling the Effect of Input Capacitance To compensate for the effect of input capacitance, add a feedback capacitor. The feedback capacitor (as in Figure 53), Cf, is first estimated by Equation 1: 1 1 2pR1 CIN 2pR2 Cf or R1 CIN R2 Cf (1) This equation typically provides significant overcompensation. Printed circuit board (PCB) stray capacitance may be larger or smaller than that of a breadboard, so the actual optimum value for Cf may be different. The values of Cf should be checked on the actual circuit. See the LMC660 Quad CMOS Amplifier data sheet for a more detailed discussion. 8.2.2.3 Offset Voltage Adjustment Offset voltage adjustment circuits are illustrated in Figure 54 and Figure 55. Large-value resistances and potentiometers are used to reduce power consumption while providing typically 2.5 mV of adjustment range, referred to the input, for both configurations with VS = 5 V. Figure 54. Inverting Configuration Offset Voltage Adjustment 28 Figure 55. Noninverting Configuration Offset Voltage Adjustment Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 Typical Application (continued) 8.2.3 Application Curves Figure 56. Open Loop Frequency Response Figure 57. Open Loop Frequency Response vs Temperature Figure 58. Maximum Output Swing vs Frequency Figure 59. Gain and Phase vs Capacitive Load Figure 60. Gain and Phase vs Capacitive Load Figure 61. Open Loop Output Impedance vs Frequency Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 29 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com Typical Application (continued) Figure 62. Open Loop Output Impedance vs Frequency 30 Submit Documentation Feedback Figure 63. Slew Rate vs Supply Voltage Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 8.3 System Examples The circuit in Figure 64 uses a single supply to half-wave rectify a sinusoid centered about ground. RI limits current into the amplifier caused by the input voltage exceeding the supply voltage. Figure 65 shows the halfwave rectifier waveform. Full-wave rectification is provided by the circuit in Figure 66. Figure 64. Half-Wave Rectifier With Input Current Protection (RI) Figure 65. Half-Wave Rectifier Waveform Figure 66. Full Wave Rectifier With Input Current Protection (RI) Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 31 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com System Examples (continued) Figure 67. Full Wave Rectifier Waveform Figure 68. Large Compliance Range Current Source Figure 69. Positive Supply Current Sense 32 Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 System Examples (continued) In Figure 70, dielectric absorption and leakage is minimized by using a polystyrene or polyethylene hold capacitor. The droop rate is primarily determined by the value of CH and the diode leakage current. The ultra-low input current of the LMC6484 has a negligible effect on droop. Figure 70. Low Voltage Peak Detector With Rail-to-Rail Peak Capture Range Figure 71. Rail-to-Rail Sample and Hold The high CMRR (85 dB) of the LMC6484 allows excellent accuracy throughout the rail-to-rail dynamic capture range of the circuit. The low-pass filter circuit in Figure 72 can be used as an antialiasing filter with the same voltage supply as the ADC. Filter designs can also take advantage of the LMC6484 ultra-low input current. The ultra-low input current yields negligible offset error even when large value resistors are used, which allows the use of smaller-valued capacitors that take up less board space and cost less. 1 R1 = R2, C1 = C2; f = 1 C2 R2 2 C1 R1 ; DF = 2 pR1C1 Figure 72. Rail-to-Rail, Single-Supply, Low-Pass Filter Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 33 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com System Examples (continued) 8.3.1 Data Acquisition Systems Low-power, single-supply, data acquisition system solutions are provided by buffering the ADC12038 with the LMC6484, as shown in Figure 73. Capable of using the full supply range, the LMC6484 does not require input signals to be scaled down to meet limited common-mode voltage ranges. The LMC6484 CMRR of 82 dB maintains integral linearity of a 12-bit data acquisition system to 0.325 LSB. Other rail-to-rail input amplifiers with only 50 dB of CMRR degrade the accuracy of the data acquisition system to only 8 bits. Figure 73. Operating From the Same Supply Voltage, the LMC6484 Buffers the ADC12038 Maintaining Excellent Accuracy 34 Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 System Examples (continued) 8.3.2 Instrumentation Circuits The LMC6484 has the high input impedance, large common-mode range, and high CMRR required for designing instrumentation circuits. Instrumentation circuits designed with the LMC6484 can reject a larger range of common-mode signals than most instrumentation amps. Thus, instrumentation circuits designed with the LMC6484 are an excellent choice for noisy or industrial environments. Other applications that benefit from these features include analytic medical instruments, magnetic field detectors, gas detectors, and silicon-based transducers. A small-valued potentiometer is used in series with Rg to set the differential gain of the three-op-amp instrumentation circuit in Figure 74. This combination is used instead of one large valued potentiometer to increase gain trim accuracy and reduce error due to vibration. Figure 74. Low-Power, Three-Op-Amp Instrumentation Amplifier A two-op-amp instrumentation amplifier designed for a gain of 100 is shown in Figure 75. Low sensitivity trimming is made for offset voltage, CMRR, and gain. Low cost and low power consumption are the main advantages of this two-op-amp circuit. Higher frequency and larger common-mode range applications are best facilitated by a three-op-amp instrumentation amplifier. Figure 75. Low-Power Two-Op-Amp Instrumentation Amplifier Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 35 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com 9 Power Supply Recommendations The LMC6482 can be operated over a supply range of 3 V to 15 V. To achieve noise immunity as appropriate to the application, make sure to use good PCB layout practices for power supply rails and planes, as well as using bypass capacitors connected between the power supply pins and ground. 10 Layout 10.1 Layout Guidelines 10.1.1 Printed-Circuit-Board Layout for High-Impedance Work Any circuit that must operate with less than 1000 pA of leakage current requires special layout of the PCB. To take advantage of the ultra-low input current of the LMC6484 (typically, less than 20 fA), make sure to have an excellent layout. Fortunately, the techniques for obtaining low leakages are quite simple. First, do not ignore the surface leakage of the PCB, even though this leakage may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6484 inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, an so on, connected to the operational amplifier inputs, as in Figure 78. To have a significant effect, place guard rings in both the top and bottom of the PCB. This PC foil must then be connected to a voltage that is at the same voltage as the amplifier inputs, because no leakage current can flow between two points at the same potential. For example, a PCB trace-to-pad resistance of 1012 , which is normally considered a very large resistance, could leak 5 pA if the trace were a 5-V bus adjacent to the pad of the input. This leakage would cause a 250 times degradation from the actual performance of the LMC6484. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011 would cause only 0.05 pA of leakage current. Figure 76 shows the typical connections of guard rings for standard operational amplifier configurations. Figure 76. Typical Connections of Guard Rings Be aware that when it is inappropriate to lay out a PCB for the sake of just a few circuits, another technique even better than a guard ring on a PCB: do not insert the input pin of the amplifier into the PCB at all, but bend the input pin up in the air and use only air as an insulator. Air is an excellent insulator. In this case, you may have to forego some of the advantages of PCB construction, but the advantages are sometimes well worth the effort of using point-to-point, up-in-the-air wiring, as shown in Figure 77. NOTE: Input pins are lifted out of PCB and soldered directly to components. All other pins connected to PCB. Figure 77. Air Wiring 36 Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 LMC6484 www.ti.com SNOS675D - AUGUST 2000 - REVISED JUNE 2020 10.2 Layout Example Figure 78. Example of Guard Ring in a PCB Layout Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 37 LMC6484 SNOS675D - AUGUST 2000 - REVISED JUNE 2020 www.ti.com 11 Device and Documentation Support 11.1 Device Support For the LMC6584 PSpice model, see SNOM165. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation, see the following: * LMC6482 CMOS Dual Rail-To-Rail Input and Output Operational Amplifier data sheet * LMC660 CMOS Quad Operational Amplifier data sheet) . 11.3 Support Resources TI E2ETM support forums are an engineer's go-to source for fast, verified answers and design help -- straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 38 Submit Documentation Feedback Copyright (c) 2000-2020, Texas Instruments Incorporated Product Folder Links: LMC6484 PACKAGE OPTION ADDENDUM www.ti.com 1-May-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMC6484AIM NRND SOIC D 14 55 TBD Call TI Call TI -40 to 85 LMC6484 AIM LMC6484AIM/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMC6484 AIM LMC6484AIMX NRND SOIC D 14 2500 TBD Call TI Call TI -40 to 85 LMC6484 AIM LMC6484AIMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMC6484 AIM LMC6484AIN/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS & no Sb/Br) SN Level-1-NA-UNLIM -40 to 85 LMC6484AIN LMC6484IM NRND SOIC D 14 55 TBD Call TI Call TI -40 to 85 LMC6484IM LMC6484IM/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMC6484IM LMC6484IMX NRND SOIC D 14 2500 TBD Call TI Call TI -40 to 85 LMC6484IM LMC6484IMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMC6484IM LMC6484IN/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS & no Sb/Br) SN Level-1-NA-UNLIM -40 to 85 LMC6484IN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 1-May-2020 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 1-May-2020 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMC6484AIMX SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LMC6484AIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LMC6484IMX SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LMC6484IMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 1-May-2020 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6484AIMX SOIC D 14 2500 367.0 367.0 35.0 LMC6484AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LMC6484IMX SOIC D 14 2500 367.0 367.0 35.0 LMC6484IMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NFF0014A N0014A N14A (Rev G) www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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