382 9300 4-Bit Parallel-Access Shift Register Schottky TTL High-Speed TTL Low-Power Schottky TTL Standard TTL Low-Power TTL | Package Package . Package . Package . _Package | i Device Type Device Type Device Type Device Type +{ Device Type Fc [Pim cri yPe TTP IM Ice c[P|[M cr c|}P|M |cr C|P|M|CF $N39300 J) tf TA. 5N29300 Dana FM93S00 Da) F M93H00 Du FO FM9300 Di Fs FM93L 00 Diy | Fil FAIRCHILD |= 53500 Dy FC 93H00 Da F.9300 Dupre} Ff FS 93.00 Dupree MC9300 La _ . MOTOROLA M8300 LP OMs9300 Jue Wel . NSC. 08300 Jujnl [wa PHILIPS F JJ321/9300 ft $9300 _ | tt SIGNETICS N9300 Fan SIEMENS FUJITSU HITACHI MITSUBISHI NEC ! TOSHIBA | Electrical Characteristics SN39300/SN29300* Pin Assignment (Top View) absolute maximum ratings over operating free-air temperature range a OUTPUTS Supply voltage. Voc 7V_| Operating free-air [SN39300 -S5C to 125C , SHIFT Input voltage 5.5V_| temperature range _[ $N29300 oc to 75C Voc Oa 98 A 9H OD cLosk Load Storage temperature range 65C to 150C recommended operating conditions SN39300_ [ SN29300 UNIT MIN NOM MAX | MIN NOM MAX Supply voltage, Voc 4.5 .5| 4.79 5.25] Vv High-level output current, Io 800 800| uA Low-level output current. Io, 16 '6[ mA T Clock frequency. tciock Q 30 c 30. | MHz : \ = oo Width of clock input pulse, tw(clook) 16 16 ns 4 6 8 Width of cleat input_puise, tw (clear) 12 lz ns CLEAR J K A 8 c D GND aa i Shift/load 2s a SERIAL INPUTS PARALLEL INPUTS Setup ume, tsetup Serial and parallel data IS (5 ns . . Clear inactive-state 28 28 Positive logic : Shift /load refease time, treigase 10 to} ns Serial_and parallel data hold time, thoig Q G ns Function Table Operating free-air temperature, Ts 55 12s G 7] C 9300 (See Note 2) - a ti electrical characteristics over recommended operating [_ INPUTS OUTPUTS free-air temperature range SHIFT / SERIAL | PARALLEL = PARAMETER * TEST CONDITIONS MIN TYP MAX | UNIT CLEAR CLOCK = Qa On Ac AD AD 7 LOAD J KiA Bc oD Vin High-level input voltage 2 Vv Vie Low-level input voltage as} v L x x xX XIX X X X L L L L H vt Input clamp voltage Voc =MIN, y= (2mA us] ov H L t X xX la beddia b c d qd Voc =MIN, Vin=2V, . Q Vou Aigh-level output voltage ce Iq 2.4 v 4 H L XX |X X X X |Oao 9B0 QCo Qo bq Vi_ =0.8V, IoH = 800uA H H tT LH IX X X X /Qag Ova On OCn QCn Voc=MIN, = 2V, t > VoL Low-level output voltage ce Vinw2 oal v H H LoL yx X X X7 L Qan OBn OCn OCn ViL =0.8V, lot =l6mA H H 1 H oH }X X X Xj H OQAn QBn QCn cn , Input current at_maximurn Voe=MAX, v)=5.8V tl oma H H tT H LIX X X X 1Op~n Qan QBn ABn On (nput_ voltage ) ve = H=high level (steady state ' High-level input current Voo =MAX, Vy =2.4v 40 A iH rs evel npe Ge I # L=low level (steady state) We Owrlevel input current Vy=0.4V 16] mA X =irrelevant (any input, including twansitions) fos Short-circuit output current 18 57| mA T=transition from low to high level loc Suppty current See Note 1 39 63; mA tmax Maximum clock frequency Ta=25C, 30 39 MHz IPH | from clear to Q outputs AL =4002 19 30 ns tPLH | from clock 6 (4 22| 8 teHL | from clock 7 7 26] ns NOTES: |. With all outputs open, shift/load grounaed, and 4.5 V apphed to the J,K,and data inputs, (CC 1S measured by applying 4 mumentary ground, follawed by 4.5 V. clear, and then applying a momentary ground, followea by 4.5 V, 10 clock 2. a,b,c,d=the level of steady-state input at A,B,C. or D. respectively QA0. QB0. Oco. ADg= the level of On, Og. Qc, or Qp. respectively, before the indicated steady-state input conditions were established. QAn. [Bn In =the level of Aa. Og. or Qo. respectively, before the most recent t transition of the clock *For new designs, SNS54195/SN74195 are recommended. t For conditions shown as MIN cr MAX,use the a All typical values are at Voo=5V, Ta =25'C. Not more than one output should be shorted at a time * IPL H* propagation delay time, tow-to-high-level output PHL = Propagation delay time, high-to-low-level output propriate value specified under recommended operating conditions for the applicable device type.