AM27C020-90DCB - Advanced Micro Devices

FINAL

Publication# 11507 Rev: JAmendment/0

Issue Date: January 1999

Am27C020

2 Megabit (256 K x 8-Bit) CMOS EPROM

DISTINCTIVE CHARACTERISTICS

■Fast access time

— Speed options as fast as 55 ns

■Low power consum pti on

— 100 µA maximum CMOS standby current

■JEDEC-approved pinout

— Plug in upgrade of 1 Mbit EPROM

— Easy upgrade from 28-pin JEDEC EPROMs

■Single +5 V power supply

■±10% power supply tolerance standard

■100% Flashrite™ programming

— Typical programming time of 32 seconds

■Latch-up protected to 100 mA from –1 V to

VCC + 1 V

■High noise immu nity

■Compact 32-pin DIP, PDIP, and PLCC packages

GENERAL DESCRIPTION

The Am27C020 is a 2 Megabit, ultraviolet erasable pro-

grammable read-only memory. It is organized as 256

Kwords by 8 bits per word, operates from a sing le +5 V

supply, has a static standby mode, and features fast

single address location programming. Products are

available in windowed ceramic DIP pac kages, as well

as plastic one time programmable (OTP) PDIP and

PLCC packages.

Data can be typically accessed in less than 55 ns, al-

lowing high-performance microprocessors to operate

without any WAIT states. The device offers separate

Output Enable (OE#) and Chip Enable (CE#) controls,

thus eliminating bus contention in a multiple bus micro-

proc esso r sys te m.

AMD’s CMOS process technology provides high

speed, low power, and high noise immunity. Typical

power consumption is only 100 mW in active mode,

and 100 µW in standby mode.

All signals are TTL levels, including programming sig-

nals. Bit locations may be programmed singly, in

blocks, or at random. The device supports AMD’s

Flashrite programming algorithm (100 µs pulses), re-

sulting in a typical programming time of 32 seconds.

BLOCK DIAGRAM

11507J-1

A0–A17

Address

Inputs

PGM#

CE#

OE#

VCC

VSS

VPP

Data Outputs

DQ0–DQ7

Output

Buffers

Gating

2,097,152

Bit Cell

Matrix

Decoder

Output Enable

Chip Enable

and

Prog Logic

2 Am27C020

PRODUCT SELECTOR GUIDE

CONNECTION DIAGRAMS

Top View

DIP PLCC

Notes:

1. JEDEC nomenclature is in parenthesis.

2. The 32-pin DIP to 32-pin PLCC configuration varies from the JEDEC 28-pin DIP to 32-pin PLCC configuration.

PIN DESIGNATIONS

A0–A17 = Address Inputs

CE# (E#) = Chip Enable Input

DQ0–DQ7 = Data Input/Outputs

OE# (G#) = Output Enable Input

PGM# (P#) = Program Enable Input

VCC =V

CC Supply Voltage

VPP = Program Voltage Input

VSS = Ground

LOGIC SYMBOL

Family Part Number Am27C020

Speed Options VCC = 5.0 V ± 5% -55 -75 -255

VCC = 5.0 V ± 10% 55 -70 -90 -120 -150 -200

Max Access Time (ns) 55 70 90 120 150 200 250

CE# (E#) Access (ns) 55 70 90 120 150 200 250

OE# (G#) Access (ns) 35 40 40 50 65 75 100

A16

DQ0

A15

A12

DQ1

DQ2

VSS

A11

OE# (G#)

A10

CE# (E#)

DQ7

VCC

PGM# (P#)

DQ6

A17

A14

A13

DQ5

DQ4

DQ3

VPP

11507J-2

DQ6

VPP

DQ5

DQ4

DQ3

13130234

13 17 18 19 2016

DQ0

A14

A13

A11

OE# (G#)

A10

CE# (E#)

DQ7

A12

A15

A16

VCC

PGM# (P#)

A17

DQ1

DQ2

VSS

11507J-3

DQ0–DQ7

A0–A17

CE# (E#)

OE# (G#)

11507J-4

PGM# (P#)

Am27C020 3

ORDERING INFORMATION

UV EPROM Products

AMD standard products are available in several packages and operating ranges. The order number (V alid Combination) is formed

by a combination of the following:

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION

Am27C020

2 Megabit (256 K x 8-Bit) CMOS UV EPROM

AM27C020 -55 D C

OPTIONAL PROCESSING

Blank = Standard Pro ces sin g

B = Burn-In

VOLTAGE TOLERANCE

5=V

CC ± 5%, 55 ns only

See Product Selector Guide and Valid Combinations

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I=Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAG E TY PE

D = 32-Pin Ceramic DIP (CDV032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

Valid Combinations

AM27C020-55

VCC = 5.0 V ± 5% DC5, DC5B, DI5, DI5B

AM27C020-55

VCC = 5.0 V ± 10% DC, DCB, DI, DIB

AM27C020-70

AM27C020-90

AM27C020-120

DC, DCB, DI, DIB, DE, DEBAM27C020-150

AM27C020-200

AM27C020-255

VCC = 5.0 V ± 5% DC, DCB, DI, DIB

4 Am27C020

ORDERING INFORMATION

OTP EPROM Products

AMD standard products are available in several packages and operating ranges. The order number (V alid Combination) is formed

by a combination of the following:

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

DEVICE NUM BE R/ DES CR IP TIO N

Am27C020

2 Megabit (256 K x 8-Bit) CMOS OTP EPROM

AM27C020 -55 J C

OPTIONAL PROCESSING

Blank = Standard Processing

VOLTAGE TOLERANCE

5=V

CC ± 5%, 55 ns only

See Product Selector Guide and Valid Combinations

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I=Industrial (–40°C to +85°C)

PACKAGE TYPE

P = 32-Pin Plastic DIP (PD 032)

J = 32-Pin Plastic Leaded Chip Carrier (PL 032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

Valid Combinations

AM27C020-55

VCC = 5.0 V ± 5% PC5, PI5, JC5, JI5

AM27C020-55

VCC = 5.0 V ± 10%

JC, PC, JI, PI

AM27C020-70

AM27C020-90

AM27C020-120

AM27C020-150

AM27C020-200

AM27C020-255

VCC = 5.0 V ± 5%

Am27C020 5

FUNCTIONAL DESCRIPTION

Device Erasure

In order to clear all locations of their programmed con-

tents, the device must be exposed to an ultra violet light

source. A dosage of 15 W seconds/cm2 is required to

completely erase the device. This dosage can be ob-

tained by exposure to an ultraviolet lamp—wavelength

of 2537 Å—with intensity of 12,000 µW/cm 2 for 15 to 20

minutes. The device should be directly under and

about one inch from th e source, and all filters should be

removed from the UV light source prior to erasure.

Note that all UV erasable devices will erase with light

sources having wavelengths shorter than 4000 Å, s uch

as fluorescent light and sunlight. Although the erasure

process happens over a much longer time period, ex-

posure to any light source should be prevented for

maximum system reliability. Simply cover the package

window with an opaque label or substance.

Device Programming

Upon delivery, or after each erasure, the device has

all of its bi ts in the “ONE”, or HI GH state. “ZEROs” are

loaded into the device through the programming pro-

cedure.

The device enters the programming mode when 12.75

V ± 0.25 V is applied to the VPP pin, and CE# and

PGM# are at VIL and OE# is at VIH.

For programming, the data to be programmed is ap-

plied 8 bits in parallel to the data pins.

The flowchart in the Programming section of the

EPROM Products Data Book (Section 5, Figure 5-1)

shows AMD’s Flashrite algorithm. The Flashrite algo-

rithm reduces programming time by using a 100 µs pro-

gramming pulse and by giving each address only as

many pulses to reliably program the data. After each

pulse is applied to a giv en address, the data in that ad-

dress is verified. If the data does not verify, additional

pulses are given until it verifies or the maximum pulses

allowed is reached. This process is repeated while se-

quencing thro ugh eac h address o f the device . This part

of the algorithm is done at VCC = 6.25 V to assure that

each EPROM bit is programmed to a sufficiently high

threshold voltage. After the final address is completed,

the entire EPROM memory is verified at VCC = VPP =

5.25 V.

Please refer t o Section 5 of the EPROM Products Data

Book for addit ional programming information and s pec-

ifications.

Program Inhibit

Programming different data to multiple devices in par-

allel is easily accomplished. Except for CE#, all like in-

puts of the devices may be common. A TTL low-level

program pulse applied to one device’s CE# input with

VPP = 12.75 V ± 0.25 V and PGM# LOW, and OE#

HIGH will program that particular device. A high-level

CE# input inhibits the other devices from being pro-

grammed.

Program Verify

A verification should be perfor med on the programmed

bits to det ermine that th ey were correct ly programmed.

The verify should be performed with OE# and CE#, at

VIL, PGM# at V IH, and VPP between 12. 5 V and 13.0 V.

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification through identifier codes on DQ0–

DQ7. This mode is primarily intended for programming

equipment to automatically match a device to be pro-

grammed with its corresponding programming algo-

rithm. This mode is functional in the 25°C ± 5°C

ambient temperature range that is required when pro-

gramming the device.

To activate this mode, the programming equipment

must fo rce VH on address line A9. Two identifier bytes

may then be sequenced from the device outputs by

toggling address line A0 from V IL to VIH (that is, c hang-

ing the address from 00h to 01h). All other address

lines must be held at VIL during the autoselect mode.

Byte 0 (A0 = VIL) represents the manufacturer code,

and Byte 1 (A0 = VIH), the device identifier code. Both

codes have odd parity, with DQ7 as the parity bit.

Read Mode

To obtain data at the device outputs, Chip Enable

(CE#) and Output Enable (OE#) must be driven low.

CE# controls the power to the device and is typically

used to select the device. OE# enables the device to

output data, independent of device selection. Ad-

dresses must be stable for at least tACC–tOE. Refer to

the Switching Waveforms section for the timing dia-

gram.

Standby Mode

The device enters the CMOS sta ndby mode when CE#

is at VCC ± 0.3 V. Maximum VCC current is reduced to

100 µA. The device enters the TTL-standby mode

when CE# is at VIH. Maximum VCC current is reduced

to 1.0 mA. When in either standby mode, the device

places its outputs in a high-impedance state, indepen-

dent of the OE# input.

Output OR-Tieing

To accommodate multiple memory connections, a

two-line control function provid es:

■Low memory power dissipation, and

■Assurance th at output bus contention will not oc cur.

6 Am27C020

CE# should be decoded and used as the primary de-

vice-selecting funct ion, wh ile OE# be made a common

connection to all device s in the array and connect ed to

the READ line from the system control bus. This as-

sures that all deselected memory devices are in their

low-power standby mode and that the output pins are

only active when data is desired from a particular mem-

ory device.

System Applications

During the switch between active and standby condi-

tions, transient current peaks are produced on the ris-

ing and falling edges of Chip Enable. The magnitude of

these transient current peaks is dependent on the out-

put capacitance loading of the device. At a minimum, a

0.1 µF ceramic capacitor (high frequency, low inherent

inductance) should be used on each device between

VCC and VSS to minimize transient effects. In addition,

to overcome the voltage drop caused by the inductive

effects of the printed circuit board traces on EPROM ar-

rays, a 4.7 µF bulk electrolytic capacitor should be

used between VCC and VSS for each eight devices. The

location of the capacitor should be close to where the

power supply is connected to the array.

MODE SELECT TABLE

Notes:

1. VH = 12.0 V

0.5 V.

2. X = Either VIH or VIL.

3. A1–A8 and A10–17 = VIL

4. See DC Programming Characteristics for VPP volta ge dur ing pro gra mm ing .

Mode CE# OE# PGM# A0 A9 VPP Outputs

Read VIL VIL XX XXD

OUT

Output Disable X VIH X X X X High Z

Standby (TTL) VIH X X X X X High Z

Standby (CMOS) VCC ± 0.3 V X X X X X High Z

Program VIL VIH VIL XXV

PP DIN

Program Verify VIL VIL VIH XXV

PP DOUT

Program Inhibit VIH XXX XV

PP High Z

Autoselect

(Note 3) Manufacturer Code VIL VIL XV

IL VHX01h

Device Code VIL VIL XV

IH VHX97h

Am27C020 7

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

OTP Products . . . . . . . . . . . . . . . . . –65°C to +125°C

All Other Products . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temper ature

with Power Applied . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to VSS

All pins except A9, VPP, VCC . . –0.6 V to VCC + 0.6 V

A9 and VPP (Note 2) . . . . . . . . . . . . .–0.6 V to 13.5 V

VCC (Note 1). . . . . . . . . . . . . . . . . . . . .–0.6 V to 7.0 V

Notes:

1. Minimum DC volt age on input or I/O pin s –0.5 V. During

voltage tr ansitions, the input may ov ershoot V SS to –2.0

V for periods of up to 20 ns. Maximum DC voltage on

input and I/O pins is V

+ 5 V . During voltage transitions,

input and I/O pins may overshoot to V

+ 2.0 V for peri-

ods up to 20 ns.

2. Minimum DC input voltage on A9 is –0.5 V . During voltage

transitions , A9 and VPP may overshoo t VSS

to –2.0 V for

periods of up to 20 ns. A9 and VPP must not exceed +13.5

V at any time.

Stresse s above those liste d under “Absolut e Maximum Rat-

ings” may cause p erman ent dam age to th e device . This is a

stress rati ng on ly; fu nct iona l ope rat ion of the de vic e at the se

or any other conditions above those indicated in the opera-

tional sections of this specification is not implied. Exposure of

the device to absolute maximum ratings for extended periods

may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA) . . . . . . . .–55°C to +125°C

Supply Read Voltages

VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V

VCC for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

8 Am27C020

DC CHARACTERISTICS over operating range (unless otherwise specified)

Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied.

Notes:

1. VCC must be applied simultaneously or before VPP

, and removed simultaneously or after VPP..

2. ICC1 is tested with OE# = VIH to simulate open outputs.

3. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.

Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.

Figure 1. Typical Supply Current vs. Frequency

VCC = 5.5 V, T = 25°CFigure 2. Typical Supply Current vs. Te mperature

VCC = 5.5 V, f = 10 MHz

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

VOH Output HIGH Voltage IOH = –400 µA 2.4 V

VOL Output LOW Voltage IOL = 2.1 mA 0.45 V

VIH Input HIGH Voltage 2.0 VCC + 0.5 V

VIL Input LOW Voltage –0.5 +0.8 V

ILI Input Load Current VIN = 0 V to VCC 1.0

ILO Output Leakage Current VOUT = 0 V to VCC 5.0 µA

ICC1 VCC Active Current (Note 2) CE# = VIL, f = 10 MHz,

IOUT = 0 mA C/I Devices 30 mA

E Devices 60

ICC2 VCC TTL Standby Current CE# = VIH 1.0 mA

ICC3 VCC CMOS Standby Current CE# = VCC ± 0.3 V 100 µA

IPP1 VPP Supply Current (Read) CE# = OE# = VIL, VPP = VCC 100 µA

11507J-5

12345678910

Frequency in MHz

Supply Current

in mA

11507J-6

–75 –50 –55 0 25 50 75 100 125 150

Temperature in °C

Supply Current

in mA

Am27C020 9

TEST CONDITIONS

Table 1. Test Specifications

SWITCHING TEST WAVEFORM

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

CL6.2 kΩ

5.0 V

Device

Under

Test

11507J-7

Figure 3. Test Setup

Note:

Diodes are IN3064 or equivalents.

Test Condition -55 All Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig cap aci tan ce) 30 100 pF

Input Rise and Fall Times ≤ 20 ns

Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement

reference levels 1.5 0.8, 2.0 V

Output timing measurement

reference levels 1.5 0.8, 2.0 V

2.4 V

0.45 V Input Output

Te st Points

2.0 V 2.0 V

0.8 V

11507J-8

3 V

0 V Input Output

1.5 V 1.5 V

Te st Points

Note: For CL = 100 pF.Note: For CL = 30 pF.

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changi ng from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

10 Am27C020

AC CHARACTERISTICS

Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or VCC applied.

Notes:

1. VCC must be applied simultaneously or before VPP

, and removed simultaneously or after VPP.

2. This parameter is sampled and not 100% tested.

3. Switching characteristics are over operating range, unless otherwise specified.

4. See Figure 3 and Table 1 for test specifications.

SWITCHING WAVEFORMS

Notes:

1. OE# may be delayed up to tACC – tOE after the falling edge of the addresses without impact on tACC.

2. tDF is specified from OE# or CE#, whichever occurs first.

PACKAGE CAPACITANCE

Notes:

1. This parameter is only sampled and not 100% tested.

2. TA = +25

C, f = 1 MHz.

Parameter Symbols

Description Test Setup

Am27C020

UnitJEDEC Standard -55 -75

-70 -90 -120 -150 -200 -255

tAVQV tACC Address to Output Delay CE#,

OE# = VIL Max 55 70 90 120 150 200 250 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 150 200 250 ns

tGLQV tOE Output Enable to Output Delay CE# = VIL Max 40 40 40 50 65 75 100 ns

tEHQZ

tGHQZ

tDF

(Note 2)

Chip Enable High or Output

Enable High to Output High Z,

Whichever Occurs First Max 25 25 25 30 30 40 60 ns

tAXQX tOH

Output Hold Time from

Addresses, CE# or OE#,

Whichever Occurs First Min0000000ns

Addresses

CE#

OE#

Output 11507J-9

Addresses Valid

High Z High Z

tCE

Valid Ou tpu t

2.4

0.45

2.0

0.8 2.0

0.8

tACC

(Note 1)

tOE tDF (Note 2)

tOH

Parameter Symbol Parameter

Description Test Conditions

CDV032 PD 032 PL 032

UnitTyp Max Typ Max Typ Max

CIN Input Capacitance VIN = 0 10121012 8 10pF

OUT Output Capacitance VOUT = 0 12151215 9 12pF

Am27C020 11

PHYSICAL DIMENSIONS*

CDV032—32-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)

* For reference only. BSC is an ANSI standard for Basic Space Centering.

PD 032—32-Pin Plastic Dual In-Line Package (measured in inches)

TOP VIEW

SIDE VIEW END VIEW

INDEX AND

TERMINAL NO. 1

I.D. AREA

.565

.605

1.635

1.680

.005 MIN .045

.065 .014

.026 .100 BSC

.015

.060

.160

.220

.125

.200

BASE PLANE

SEATING PLANE

.300 BSC .600

BSC .008

.018

94°

105°

.700

MAX

16-000038H-3

CDV032

DF11

3-30-95 ae

DATUM D

CENTER PLANE

DATUM D

CENTER PLANE

UV Lens

Pin 1 I.D.

1.640

1.680

.530

.580

.005 MIN

.045

.065

.090

.110

.140

.225

.120

.160 .014

.022

SEATING PLANE

.015

.060

16-038-SB_AG

PD 032

DG75

2-28-95 ae

32 17

16 .630

.700

0˚

10˚

.600

.625

.008

.015

12 Am27C020

PHYSICAL DIMENSIONS

PL 032—32-Pin Plastic Leaded Chip Carrier (measured in inches)

REVISION SUMMARY FOR AM27C010

Revision I

Global

Changed formatting to match current data sh eets.

Revision J

Ordering Infor mation–O T P EPRO M P roducts

Corrected -75 speed option to -70.

Trademarks

AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.

Flashrite is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

.050 REF.

.026

.032 TOP VIEW

Pin 1 I.D.

.485

.495

.447

.453

.585

.595

.547

.553

16-038FPO-5

PL 032

DA79

6-28-94 ae

SIDE VIEW

SEATING

PLANE

.125

.140

.009

.015

.080

.095

.042

.056

.013

.021

.400

REF. .490

.530