Semiconductor Group 1 1998-10-01
• 2 097 152 words by 8-bit organization
• 0 to 70 °C operating temperature
• Fast Page Mode operation
• Performance:
• Power dissipation:
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh
and test mode
• All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible
• 2048 refresh cycles / 32 ms (2k-refresh)
• Plastic Package: P-SOJ-28-3 400 mil
-50 -60
tRAC RAS access time 50 60 ns
tCAC CAS access time 13 15 ns
tAA Access time from address 25 30 ns
tRC Read/Write cycle time 84 104 ns
tPC Fast page mode cycle time 35 40 ns
HYB5117800 HYB3117800
-50 -60 -50 -60
Power Supply 5 ± 10% 3.3 ± 0.3 V
Active 440 385 288 252 mW
TTL Standby 11 7.2 mW
CMOS Standby 5.5 3.6 mW
2M ×8 - Bit Dynamic RAM
2k Refresh
(Fast Page Mode)
Advanced Information
HYB 5117800/BSJ-50/-60
HYB 3117800BSJ-50/-60
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 2 1998-10-01
The HYB 5(3)117800 are 16 MBit dynamic RAMs based on the die revisions “G” & “F” and
organized as 2 097 152 words by 8-bits. The HYB 5(3)117800 utilizes a submicron CMOS silicon
gate process technology, as well as advanced circuit techniques to provide wide operating margins,
both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)117800 to
be packaged in a standard SOJ-28 plastic package. Package with 400 mil width are available.
These packages provide high system bit densities and are compatible with commonly used
automatic testing and insertion equipment.
Ordering Information
Type Ordering Code Package Descriptions
HYB 5117800BSJ-50 Q67100-Q1092 P-SOJ-28-3 400 mil 5 V 50 ns FPM-DRAM
HYB 5117800BSJ-60 Q67100-Q1093 P-SOJ-28-3 400 mil 5 V 60 ns FPM-DRAM
HYB 3117800BSJ-50 on request P-SOJ-28-3 400 mil 3.3 V 50 ns FPM-DRAM
HYB 3117800BSJ-60 on request P-SOJ-28-3 400 mil 3.3 V 60 ns FPM-DRAM
Pin Names and Configuration
A0 - A10 Row Address Inputs
A0 - A9 Column Address Inputs
RAS Row Address Strobe
OE Output Enable
I/O1 - I/O8 Data Input/Output
CAS Column Address Strobe
WE Read/Write Input
VCC Power Supply
+ 5 V for HYB 5117800
+ 3.3 V for HYB 3117800
VSS Ground (0 V)
N.C. Not Connected
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
A5
OE
I/O5
CAS
A0
A1
A2
I/O3
I/O4
WE
RAS
N.C.
A10
SS
V
CC
V
A9
I/O8
I/O7
SS
V
I/O1
I/O2
V
CC
A3
A6
A7
28
27
26
A8
I/O6
SPP02803
A4
P-SOJ-28 400 mil
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 3 1998-10-01
Block Diagram
SPB03456
&
No.2 Clock
Generator
Address
Column
Buffers (10)
Controller
Refresh
Refresh
Counter (11)
Buffers (11)
Row
Address
Generator
No.1 Clock
11
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
11 Row
Decoder
RAS
2048 x 1024 x 8
Memory Array
2048
1024
x 8
Sense Amplifier
I/O Gating
10 Column
Decoder
Buffer
Data IN Data OUT
Buffer
I/O1
88
OE
Voltage Down
V
CC
V
CC
11
4
A9
(internal)
Generator
CAS
WE
A10
I/O2 I/O8
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 4 1998-10-01
Absolute Maximum Ratings
Operating temperature range ........................................................................................... 0 to 70 °C
Storage temperature range........................................................................................ – 55 to 150 °C
Input/output voltage (5 V versions)................................................... – 0.5 to min (VCC + 0.5, 7.0) V
Input/output voltage (3.3 V versions)................................................ – 0.5 to min (VCC + 0.5, 4.6) V
Power supply voltage (5 V versions) ....................................................................... – 1.0 V to 7.0 V
Power supply voltage (3.3 V versions) .................................................................... – 1.0 V to 4.6 V
Power dissipation (5 V versions) .............................................................................................1.0 W
Power dissipation (3.3 V versions) ..........................................................................................0.5 W
Data out current (short circuit) ................................................................................................50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns
Parameter Symbol Limit Values Unit Test
Condition
min. max.
5 V Versions
Power supply voltage VCC 4.5 5.5 V
Input high voltage VIH 2.4 VCC + 0.5 V 1
Input low voltage VIL – 0.5 0.8 V 1
Output high voltage (IOUT = – 5 mA) VOH 2.4 – V 1
Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V 1
3.3 V Versions
Power supply voltage VCC 3.0 3.6 V
Input high voltage VIH 2.0 VCC + 0.5 V 1
Input low voltage VIL – 0.5 0.8 V 1
TTL Output high voltage (IOUT = – 2 mA) VOH 2.4 – V 1
TTL Output low voltage (IOUT = 2 mA) VOL – 0.4 V 1
CMOS Output high voltage (IOUT = – 100 µA) VOH VCC – 0.2 – V
CMOS Output low voltage (IOUT = 100 µA) VOL – 0.2 V
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 5 1998-10-01
DC Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns
Parameter Symbol Limit Values Unit Test
Condition
min. max.
Common Parameters
Input leakage current
(0 V ≤VIH ≤VCC + 0.3 V, all other pins = 0 V) II(L) – 10 10 µA1
Output leakage current
(DO is disabled, 0 V ≤VOUT ≤VCC + 0.3 V) IO(L) – 10 10 µA1
Average VCC supply current -50 ns version
-60 ns version
(RAS, CAS, address cycling: tRC = tRC MIN.)
ICC1 –
–80
70 mA
mA
2, 3, 4
2, 3, 4
Standby VCC supply current (RAS = CAS = VIH)ICC2 –2mA–
Average VCC supply current, during RAS-only
refresh cycles -50 ns version
-60 ns version
(RAS cycling, CAS = VIH,tRC = tRC MIN.)
ICC3 –
–80
70 mA
mA
2, 4
2, 4
Average VCC supply current,
during fast page mode -50 ns version
-60 ns version
(RAS = VIL,CAS, address cycling: tPC = tPC MIN.)
ICC4 –
–25
20 mA
mA
2, 3,) 4
2, 3, 4
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V) ICC5 –1mA
1
Average VCC supply current, during CAS-
before-RAS refresh mode -50 ns version
-60 ns version
(RAS, CAS cycling: tRC = tRC MIN.)
ICC6 –
–80
70 mA
mA
2, 4
2,) 4
Capacitance
TA = 0 to 70 °C,VCC = 5 V ± 10 %, f = 1 MHz
Parameter Symbol Limit Values Unit
min. max.
Input capacitance (A0 to A10) CI1 –5pF
Input capacitance (RAS, CAS, WE, OE) CI2 –7pF
I/O capacitance (I/O1 to I/O8) CIO –7pF
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 6 1998-10-01
AC Characteristics 5, 6
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 5 ns
Parameter Symbol Limit Values Unit Note
-50 -60
min. max. min. max.
Common Parameters
Random read or write cycle time tRC 90 – 110 – ns
RAS precharge time tRP 30 – 40 – ns
RAS pulse width tRAS 50 10k 60 10k ns
CAS pulse width tCAS 13 10k 15 10k ns
Row address setup time tASR 0–0–ns
Row address hold time tRAH 8 – 10 – ns
Column address setup time tASC 0–0–ns
Column address hold time tCAH 10 – 15 – ns
RAS to CAS delay time tRCD 18 37 20 45
RAS to column address delay time tRAD 13 25 15 30 ns
RAS hold time tRSH 13 15 – ns
CAS hold time tCSH 50 60 – ns
CAS to RAS precharge time tCRP 5–5–ns
Transition time (rise and fall) tT3 50 3 50 ns 7
Refresh period tREF – 32 – 32 ms
Read Cycle
Access time from RAS tRAC – 50 – 60 ns 8, 9
Access time from CAS tCAC – 13 – 15 ns 8, 9
Access time from column address tAA – 25 – 30 ns 8, 10
OE access time tOEA – 13 – 15 ns
Column address to RAS lead time tRAL 25 – 30 – ns
Read command setup time tRCS 0–0–ns
Read command hold time tRCH 0–0–ns
11
Read command hold time referenced to
RAS tRRH 0–0–ns
11
CAS to output in low-Z tCLZ 0–0–ns
8
Output buffer turn-off delay tOFF 0 13 0 15 ns 12
Output buffer turn-off delay from OE tOEZ 0 13 0 15 ns 12
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 7 1998-10-01
Data to OE low delay tDZO 0–0–ns
13
CAS high to data delay tCDD 13 – 15 – ns 14
OE high to data delay tODD 13 – 15 – ns 14
Write Cycle
Write command hold time tWCH 8 – 10 – ns
Write command pulse width tWP 8 – 10 – ns
Write command setup time tWCS 0–0–ns
15
Write command to RAS lead time tRWL 13 – 15 – ns
Write command to CAS lead time tCWL 13 – 15 – ns
Data setup time tDS 0–0–ns
16
Data hold time tDH 10 – 10 – ns 16
Data to CAS low delay tDZC 0–0–ns
13
Read-Modify-Write Cycle
Read-write cycle time tRWC 126 – 150 – ns
RAS to WE delay time tRWD 68 – 80 – ns 15
CAS to WE delay time tCWD 31 – 35 – ns 15
Column address to WE delay time tAWD 43 – 50 – ns 15
OE command hold time tOEH 13 – 15 – ns
Fast Page Mode Cycle
Fast page mode cycle time tPC 35 – 40 – ns
CAS precharge time tCP 10 – 10 – ns
Access time from CAS precharge tCPA – 30 – 35 ns 7
RAS pulse width tRAS 50 200k 60 200k ns
CAS precharge to RAS Delay tRHPC 30 – 35 – ns
AC Characteristics (cont’d) 5, 6
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 5 ns
Parameter Symbol Limit Values Unit Note
-50 -60
min. max. min. max.
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 8 1998-10-01
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle time tPRWC 71 – 80 – ns
CAS precharge to WE tCPWD 48 – 55 – ns
CAS-before-RAS Refresh Cycle
CAS setup time tCSR 10 – 10 – ns
CAS hold time tCHR 10 – 10 – ns
RAS to CAS precharge time tRPC 5–5–ns
Write to RAS precharge time tWRP 10 – 10 – ns
Write hold time referenced to RAS tWRH 10 – 10 – ns
CAS-before-RAS Counter Test Cycle
CAS precharge time tCPT 35 – 40 – ns
Test Mode
CAS hold time tCHRT 30 – 30 – ns
Write command setup time tWTS 10 – 10 – ns
Write command hold time tWTH 10 – 10 – ns
RAS hold time in test mode tRAHT 30 – 30 – ns
AC Characteristics (cont’d) 5, 6
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 5 ns
Parameter Symbol Limit Values Unit Note
-50 -60
min. max. min. max.
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 9 1998-10-01
Notes
1. All voltages are referenced to VSS.
2. ICC1,ICC3,ICC4 and ICC6 depend on cycle rate.
3. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4. Address can be changed once or less while RAS = VIL. In the case ofICC4 it can be changed once
or less during a fast page mode cycle (tPC).
5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS
cycles are required.
6. AC measurements assume tT = 5 ns.
7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times
are also measured between VIH and VIL.
8. Measured with a load equivalent to 2 TTL loads and 100 pF.
9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as
a reference point only: If tRCD is greater than the specified tRCD (MAX.) limit, then access time is
controlled by tCAC.
10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as
a reference point only: If tRAD is greater than the specified tRAD (MAX.) limit, then access time is
controlled by tAA.
11.Either tRCH or tRRH must be satisfied for a read cycle.
12.tOFF (MAX.) and tOEZ (MAX.) define the time at which the outputs achieve the open-circuit condition
and are not referenced to output voltage levels.
13.Either tDZC or tDZO must be satisfied.
14.Either tCDD or tODD must be satisfied.
15.tWCS,tRWD,tCWD,tAWD andtCPWD are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only. If tWCS >tWCS (MIN.), the cycle is an early write cycle
and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD >
tRWD (MIN.),tCWD >tCWD (MIN.), tAWD >tAWD (MIN.) and tCPWD >tCPWD (MIN.) , the cycle is a read-write cycle
and I/O pins will contain data read from the selected cells. If neither of the above sets of
conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.
16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
leading edge in read-write cycles.
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 10 1998-10-01
Read Cycle
SPT03025
"H" or "L"
OEA
CAC
RAL
t
OH
OL
V
(Inputs)
(Outputs)
I/O
I/O
V
IH
V
IL
V
OE
WE
V
IL
V
IH
V
IL
V
IH
RAC
t
Hi
DZO
Z
t
CLZ
tt
DZC
t
RCS
AA
tt
V
Address
V
IL
V
IH
IL
CAS
RAS
IL
V
IH
V
V
IH
t
RAD
ASR
t
Row
t
Column
RAH
ASC
t
CAH
tt
RCD
t
CSH
t
t
RAS
t
t
ODD
RRH
Valid Data OUT
OEZ
t
t
CDD
OFF
t
Hi Z
t
t
RSH
CAS
t
RC
t
RCH
ASR
t
Row
CRP
t
t
RP
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 11 1998-10-01
Write Cycle (Early Write)
SPT03026
"H" or "L"
RWL
RAL
WCS
OH
(Inputs)
(Outputs)
I/O
I/O
IL
V
OL
V
V
V
IH
OE
WE
IH
V
IL
V
V
IL
V
IH
t
Valid
DS
t
DH
Data IN
WCH
t
t
WP
t
V
Address
IH
V
V
IL
IL
CAS
RAS
V
IH
IH
V
V
IL
t
RAD
ASR
t
t
RAH
Row
t
Column
ASC
t
CWL
t
CAH
tt
RCD
t
CSH
t
t
RAS
t
ZHi
t
RC
CAS
RSH
t
ASR
t
Row
CRP
t
t
RP
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 12 1998-10-01
Write Cycle (OE Controlled Write)
SPT03027
"H" or "L"
DS
RAL
CAS
V
OH
V
(Inputs)
(Outputs)
I/O
I/O
V
V
OL
IL
V
IH
OE
WE
V
IL
IL
V
IH
V
IH
t
DZO
Hi Z
t
CLZ
t
OEA
t
OEZ
t
DZC
ODD
t
t
V
Address
IL
V
V
IH
CAS
RAS
V
IL
V
IH
IL
V
IH
RAD
ASR
t
RAH
t
Row
tt
Column
ASC
t
CAH
RCD
t
t
t
CSH
t
RAS
t
Hi
Valid Data
t
DH
OEH
t
Z
RWL
CWL
tt
WP
t
RSH
t
ASR
t
Row
CRP
t
t
RC
t
RP
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 13 1998-10-01
Read-Write (Read-Modify-Write) Cycle
SPT03028
"H" or "L"
AWD
OEA
CSH
RWD
OH
I/O
(Outputs)
V
OL
(Inputs)
I/O
IL
V
V
V
IH
OE
WE
V
IL
V
IH
V
IL
V
IH
RAC
t
t
DZC
t
DZO
t
CLZ
t
CAC
t
RCS
t
AA
t
V
Address
V
IL
V
IH
CAS
RAS
IH
V
IL
V
V
IL
IH
RAH
Row
ASR
t
t
RAD
t
Column
ASC
t
t
t
CAH
t
RCD
t
t
t
WP
Data
OUT
DS
ODD
OEZ
t
t
t
t
Data IN
Valid
t
DH
OEH
Row
t
CWD
t
CAS
tt
RSH
RWL
t
t
CWL
ASR
t
CRP
t
RP
t
RWC
t
RAS
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 14 1998-10-01
Fast Page Mode Read Cycle
SPT03029
"H" or "L"
Column
WE
OH
OL
IH
IH
(Outputs)
I/O
V
V
(Inputs)
I/O
V
IL
V
OE
V
IL
V
V
IL
t
CLZ
t
CAC
Data
Valid
OUT
RAC
t
t
DZC
t
DZO
t
OEZ
OFF
t
ODD
t
OEA
AA
tt
DZC
t
IH
IH
IH
IH
Address
V
V
IL
V
CAS
V
IL
V
RAS
V
IL
V
t
Column
tt
Row
ASR
RAD
RCS
t
t
ASC
t
RAH
RCD
t
t
t
RCH
ASC
PC
CAH
CSH
t
t
CAS
t
CP
t
t
OUT
OFF
tt
CLZ
t
CAC
Valid
Data OUT
CLZ
t
CAC
Data
Valid
t
DZO
OEZ
t
OFF
t
ODD
t
AA
t
CPA
t
OEA
t
DZC
tt
DZO
t
OEZ
t
t
ODD
OEA
AA
t
CPA
t
t
CDD
t
t
RCS
ASC
Column
RCS
tt
t
CAH
t
CAS
t
t
RRH
CAH
t
RHCP
t
tt
RSH
CAS
CRP
RASP
RP
t
t
t
RCH
Row
ASR
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 15 1998-10-01
Fast Page Mode Early Write Cycle
SPT03030
"H" or "L"
Data IN
ASC
Column
WCS
tt
WCS
IL
IH
IL
IH
OH
IH
IL
(Outputs)
V
OE
I/O
(Inputs)
I/O
V
V
V
V
WE
V
V
V
Data IN
DS
t
Valid
DH
t
DS
t
WCH
WP
tt
IH
IL
IL
IH
IH
IL
Address
V
V
RAS
CAS
V
V
V
V
Column
Row
ASR
t
RAD
t
ASC
RAH
t
t
t
RCD
CWL
t
CAH
tt
PC
t
CAS
t
CP
t
t
t
WCS
Valid
Hi Z
DH
tt
DS
WCH
WP
tt
Valid
Data IN
DH
t
WCH
WP
tt
ASR
CRP
RASP
ASC
Column
t
CWL
CAH
t
t
t
CAS
t
RWL
CWL
t
RAL
CAH
t
t
t
t
RSH
CAS
tt
t
RP
Row
OL
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 16 1998-10-01
Fast Page Mode Late Write and Read-Modify Write Cycle
SPT03031
"H" or "L"
IL
Data
RAC
(Outputs)
I/O
V
OH
OL
V
OUT
Data
OEZ
t
I/O
(Inputs)
OE
CLZ
t
V
IL
V
IH
DZC
t
t
CAC
t
DS
DZO
t
ODD
t
V
IL
IH
V
t
AWD
t
AA
t
OEA
t
t
OEH
AADSAA
OUT
Data
t
OUT
Data
OEZ OEZ
t
ODD
IN
DH
t
t
CPA
t
DZC
tt
INData
DH
t
tt
CAC
t
DZC
tt
CPA
OEH
CLZ
t
WP
tt
OEA
t
AWD
t
CLZ
t
WP
t
OEA
t
AWD
t
INData
DS
t
DH
t
ODD
t
WP
t
OEH
t
Address
WE
CAS
V
RCS
V
V
IH
t
Row
V
IL
IH
t
CWD
t
CWL
RWD
t
Column
IL
V
ASR
tt
RAH ASC
t
RAD
t
IH
V
RCD
t
t
CAH
CAS
t
RAS
IL
V
V
IH
t
CSH
CWD
CWL
t
CWD
t
Column
CPWD
tt
t
CPWD
Column
PRWC
ASC
t
CAH
t
t
CP
CAS
tt
ASC
t
t
CAH
CWL
t
RWL
t
Row
CRP
t
RAL
RSH
CAS
ttt
ASR
t
RAS
t
t
RP
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 17 1998-10-01
RAS-only Refresh Cycle
SPT03032
"H" or "L"
OH
OL
(Outputs)
Address
I/O
V
V
V
IL
IH
V
Row
CAS
RAS
IL
V
V
IH
V
IL
IH
V
RAH
ASR
tt
RAS
t
Row
ZHi
t
RC
t
RPC
ASR
t
CRP
t
RP
t
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 18 1998-10-01
CAS-before-RAS Refresh Cycle
SPT03033
"H" or "L"
V
IL
IH
IH
IL
OL
OH
IL
(Outputs)
I/O
V
V
(Inputs)
OE
I/O
V
V
V
V
t
OFF
OEZ
t
t
CDD
ODD
t
IH
IL
IH
IH
IL
WE
CAS
V
V
V
RAS
V
V
WRP
CSR
t
t
CP
t
RPC
t
RP
t
t
WRH
t
CHR
Hi Z
RAS
t
RC
t
t
RPC
t
RP
t
CRP
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 19 1998-10-01
Hidden Refresh Cycle (Read) Cycle
V
CLZ
I/O
(Outputs)
OL
V
"H" or "L"
OH
V
I/O
(Inputs)
IL
V
IH
V
t
RAC
t
DZO
t
OE
V
IL
IH
V
WE
IL
IH
V
DZC
t
Valid Data OUT
SPT03034
t
CAC
OEA
AA
t
t
OFF
OEZ
t
t
Hi
t
ODD
Z
CDD
t
Column
RAS
ASR
V
Address
IL
IH
V
t
RCS
t
Row
RAH
ASC
tt
CAS
IL
V
IH
V
RAS
IL
V
IH
V
t
RCD
RAD
t
t
WRP
t
RRH
CAH
t
t
WRH
t
t
RSH
t
CHR
RAS
t
ASR
t
Row
CRP
t
RC
tt
RP
RC
t
RP
t
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 20 1998-10-01
Hidden Refresh Early Write Cycle
SPT03035
"H" or "L"
WRP
ColumnRow
Address
(Output)
(Input)
I/O
I/O
OL
V
OH
V
IN
V
V
IL
WE
IL
V
IH
V
V
IL
Valid Data
t
DS
t
WCS
t
DH
WP
t
WCH
tt
ASR
V
CAS
IH
V
t
IL
IH
V
RAS
V
IL
IH
V
RAS
ASC
RAH
tt
t
RAD
RCD
t
t
CAH
t
RSH
t
RC
t
RP
t
Row
Hi Z
t
WRH
RC
t
RAS
CHR
tt
ASR
t
CRP
t
RP
t
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 21 1998-10-01
CAS-before-RAS Refresh Counter Test Cycle
SPT03036
"H" or "L"
t
WCH
t
t
DZC
t
(Inputs)
I/O
(Outputs)
I/O
OH
OL
V
IL
V
V
IH
V
OE
WE
Write Cycle
IL
IL
V
IH
V
V
IH
V
I/O
(Inputs)
I/O
(Outputs)
OL
V
OH
V
IL
V
IH
V
t
DS
ZHi
Data IN
t
WRP
WRH
t
DH
t
t
DZO
WCS
t
tt
CLZ
OE
WE
IL
V
IH
V
IL
V
IH
V
Address
CAS
IH
IL
V
V
V
IL
IH
V
Read Cycle
RAS
V
IH
IL
V
WRP
t
WRH
t t
RCS
AA
t
CAC
t
ASC
tt
CAH
Column
CSR
t
CHR
t
CP
t
RAS
t
RWL
CWL
t
Data OUT
t
OEZ
t
OFF
t
ODD
OEA
t
RRH
RAL
CAS
t
CDD
t
RCH
t
t
ASR
Row
RSH
t
t
RP
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 22 1998-10-01
Test Mode Entry
SPT03042
"H" or "L"
OL
OH
I/O
(Inputs)
(Outputs)
I/O
V
V
V
IL
OE
WE
V
IH
V
IH
V
IL
V
IL
V
IH
OFF
t
OEZ
t
CDD
t
Hi Z
ODD
t
CAS
Address
IH
V
V
IL
V
IL
RAS
V
IH
V
IH
V
IL
RPC
t
t
CP
t
RP
RAH
WTS
t
Row
ASR
tt
t
WTH
CSR
tt
CHR
Hi Z
t
RC
RAS
t
t
RPC
CRP
t
t
RP
HYB 5(3)117800/BSJ-50/-60
2M ×8 DRAM
Semiconductor Group 23 1998-10-01
Package Outlines
Plastic Package P-SOJ-28-3 (400mil) (SMD)
(Plastic small outline J-leaded)
GPJ05699
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm
SMD = Surface Mounted Device
