LTM8047
1
8047fc
For more information www.linear.com/LTM8047
VIN (V)
0
MAXIMUM V
OUT
LOAD (mA)
400
350
250
150
300
200
100 10 20
8047 TA01b
30
5 15 25
TYPICAL APPLICATION
FEATURES DESCRIPTION
3.1VIN to 32VIN Isolated
µModule DC/DC Converter
The LT M
®
8047 is an isolated flyback µModule DC/DC
converter. The LTM8047 has an isolation rating of 725VDC.
For a similar product with LDO post regulator, see the
LTM8048. Included in the package are the switching
controller, power switches, transformer, and all support
components. Operating over an input voltage range of 3.1V
to 32V, the LTM8047 supports an output voltage range of
2.5V to 12V, set by a single resistor. Only output, input,
and bypass capacitors are needed to finish the design.
Other components may be used to control the soft-start
control and biasing.
The LTM8047 is packaged in a thermally enhanced, com-
pact (11.25mm × 9mm × 4.92mm) over-molded ball grid
array (BGA) package suitable for automated assembly by
standard surface mount equipment. The LTM8047 is avail-
able with SnPb (BGA) or RoHS compliant terminal finish.
L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIONS
n Complete Switch Mode Power Supply
n 725VDC Isolation
n Wide Input Voltage Range: 3.1V to 32V
n Up to 440mA Output Current (VOUT = 2.5V)
n 2.5V to 12V Output Voltage
n Current Mode Control
n Programmable Soft-Start
n User Configurable Undervoltage Lockout
n SnPb or RoHS Compliant Finish
n Low Profile (11.25mm × 9mm × 4.92mm) Surface
Mount BGA Package
n Industrial Sensors
n Industrial Switches
n Ground Loop Mitigation
Maximum Load vs VIN
725VDC ISOLATION
LTM8047
8047 TA01
VIN
3.1V TO 29V
VOUT
5V
280mA
(15VIN
)
22µF
2.2µF
4.7µF 6.98k
VOUT
VIN
RUN
ADJ
SS
BIAS
GND VOUT–
ISOLATION BARRIER
725V DC Isolated Low Noise µModule Regulator
LTM8047
2
8047fc
For more information www.linear.com/LTM8047
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
VIN, RUN, BIAS ........................................................32V
ADJ, SS .......................................................................5V
VOUT Relative to VOUT– .............................................. 16V
(VIN – GND) + (VOUT – VOUT–) ................................... 36V
BIAS Above VIN ........................................................ 0.1V
GND to VOUT– Isolation (Note 2) ........................725VDC
Maximum Internal Temperature (Note 3) .............. 125°C
Maximum Solder Temperature .............................. 250°C
(Note 1)
TOP VIEW
H
G
F
E
D
C
B
A
1234567
BANK 2
VOUT–BANK 1
VOUT
BANK 4
GND
BIAS
RUN
ADJ
SS
BANK 3
VIN
BGA PACKAGE
45-LEAD (11.25mm × 9mm × 4.92mm)
TJMAX = 125°C, θJA = 16°C/W, θJCbottom = 4.1°C/W, θJCtop = 15°C/W, θJB = 4°C/W
WEIGHT = 1.1g, θ VALUES DETERMINED PER JEDEC 51-9, 51-12
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, RUN = 12V (Note 3).
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Input DC Voltage BIAS = VIN l3.1 V
VOUT DC Voltage RADJ = 12.4k
RADJ = 6.98k
RADJ = 3.16k
l
4.75
2.5
5
12
5.25
V
V
V
VIN Quiescent Current VRUN = 0V
Not Switching
850
1 µA
µA
VOUT Line Regulation 6V ≤ VIN ≤ 31V, IOUT = 0.15A 1.7 %
PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(Note 3)
DEVICE CODE
LTM8047EY#PBF SAC305 (RoHS) LTM8047Y e1 BGA 3 –40°C to 125°C
LTM8047IY#PBF SAC305 (RoHS) LTM8047Y e1 BGA 3 –40°C to 125°C
LTM8047MPY#PBF SAC305 (RoHS) LTM8047Y e1 BGA 3 –55°C to 125°C
LTM8047MPY SnPb (63/37) LTM8047Y e0 BGA 3 –55°C to 125°C
ORDER INFORMATION
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Pb-free and Non-Pb-free Part Markings:
www.linear.com/leadfree
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• BGA Package and Tray Drawings:
www.linear.com/packaging
LTM8047
3
8047fc
For more information www.linear.com/LTM8047
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM8047 isolation is tested at 725VDC for one second in each
polarity.
Note 3: The LTM8047E is guaranteed to meet performance specifications
from 0°C to 125°C. Specifications over the –40°C to 125°C internal
temperature range are assured by design, characterization and correlation
with statistical process controls. LTM8047I is guaranteed to meet
specifications over the full –40°C to 125°C internal operating temperature
range. The LTM8047MP is guaranteed to meet specifications over the
full –55°C to 125°C internal operating temperature range. Note that
the maximum internal temperature is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.
Note 4: This is the BIAS pin voltage at which the internal circuitry is
powered through the BIAS pin and not the integrated regulator. See BIAS
Pin Considerations for details.
PARAMETER CONDITIONS MIN TYP MAX UNITS
VOUT Load Regulation 0.05A ≤ IOUT ≤ 0.2A 1.5 %
VOUT Ripple (RMS) IOUT = 0.1A 20 mV
Input Short Circuit Current VOUT Shorted 30 mA
RUN Pin Input Threshold RUN Pin Rising 1.18 1.24 1.30 V
RUN Pin Current VRUN = 1V
VRUN = 1.3V
2.5
0.1
µA
µA
SS Threshold 0.7 V
SS Sourcing Current SS = 0V –10 µA
BIAS Current VIN = 12V, BIAS = 5V, ILOAD1 = 100mA 8 mA
Minimum BIAS Voltage (Note 4) ILOAD1 = 100mA 3.1 V
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, RUN = 12V (Note 3).
ELECTRICAL CHARACTERISTICS
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Efficiency vs Load Efficiency vs Load
VOUT CURRENT (mA)
0
EFFICIENCY (%)
90
70
80
60
50 100 300
8047 G01
500
200 400
12VIN
24VIN
VOUT = 2.5V
BIAS = 5V
VOUT CURRENT (mA)
0
EFFICIENCY (%)
90
70
80
60
50 100 300
8047 G02
400
200
12VIN
24VIN
VOUT = 3.3V
BIAS = 5V
VOUT CURRENT (mA)
0
EFFICIENCY (%)
90
70
80
60
50 100 300
8047 G03
350
200 25015050
12VIN
24VIN
VOUT = 5V
BIAS = 5V
LTM8047
4
8047fc
For more information www.linear.com/LTM8047
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Efficiency vs Load BIAS Current vs VOUT Load
BIAS Current vs VOUT Load Maximum Load vs VIN Maximum Load vs VIN
BIAS Current vs VOUT Load BIAS Current vs VOUT Load BIAS Current vs VOUT Load
VOUT CURRENT (mA)
0
BIAS CURRENT (mA)
8.5
8.0
6.0
7.0
5.0
4.0
6.5
7.5
5.5
4.5
100 300
8047 G07
400
200
12VIN
24VIN
VOUT = 3.3V
BIAS = 5V
0 100
250
20015050
VOUT CURRENT (mA)
BIAS CURRENT (mA)
13
12
11
10
6
8
4
7
9
5
8047 G10
12VIN
24VIN
VOUT = 12V
BIAS = 5V
VOUT CURRENT (mA)
0
EFFICIENCY (%)
100
90
70
80
60 100 300
8047 G04
350
200 25015050
12VIN
24VIN
VOUT = 8V
BIAS = 5V
VOUT CURRENT (mA)
0
EFFICIENCY (%)
100
90
70
80
60 100
8047 G05
250
20015050
12VIN
24VIN
VOUT = 12V
BIAS = 5V
8.5
8.0
6.0
7.0
5.0
4.0
6.5
7.5
5.5
4.5
VOUT CURRENT (mA)
0
BIAS CURRENT (mA)
100 300
8047 G06
500
200 400
12VIN
24VIN
VOUT = 2.5V
BIAS = 5V
VOUT CURRENT (mA)
BIAS CURRENT (mA)
10
6
8
4
7
9
5
8047 G08
12VIN
24VIN
VOUT = 5V
BIAS = 5V
0 100 300
350
200 25015050
VIN (V)
MAXIMUM V
OUT
LOAD (mA)
500
450
400
200
300
100
250
350
150
8047 G11
BIAS = VIN IF VIN ≤ 5V
BIAS = 5V IF VIN > 5V
0 10
30
20 25155
2.5VOUT
3.3VOUT
5VOUT
VOUT CURRENT (mA)
BIAS CURRENT (mA)
12
11
10
6
8
4
7
9
5
8047 G09
12VIN
24VIN
VOUT = 8V
BIAS = 5V
0 100 300
350
200 25015050
VIN (V)
MAXIMUM V
OUT
LOAD (mA)
350
200
300
0
100
250
150
50
8047 12
BIAS = VIN IF VIN ≤ 5V
BIAS = 5V IF VIN > 5V
0 10
25
20155
8VOUT
12VOUT
LTM8047
5
8047fc
For more information www.linear.com/LTM8047
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Load vs VIN Minimum Load vs VIN
Input Current vs VIN
VOUT Shorted
VIN (V)
MINIMUM V
OUT
LOAD (mA)
40
35
30
10
20
0
15
25
5
8047 G13
0 10
30
20 25155
2.5VOUT
3.3VOUT
5VOUT
VIN (V)
MINIMUM V
OUT1
LOAD (mA)
15
12
9
3
0
6
8047 G14
0 10
30
20 25155
8VOUT1
12VOUT1
VIN (V)
INPUT CURRENT (mA)
80
70
60
20
40
10
30
50
8047 G15
0 12
32
20 28241684
Junction Temperature Rise vs
Load Current
Junction Temperature Rise vs
Load Current
Junction Temperature Rise vs
Load Current
VOUT LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
9
8
4
6
0
5
7
2
3
1
8047 G17
0 100
400
200 35030025015050
3.3VIN
5VIN
12VIN
24VIN
VOUT = 3.3V
VOUT LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
10
9
8
4
6
0
5
7
2
3
1
8047 G18
0 100
350
200 30025015050
3.3VIN
5VIN
12VIN
24VIN
VOUT = 5V
VOUT LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
8
4
6
0
5
7
2
3
1
8047 G16
0 100
400
200 35030025015050
3.3VIN
5VIN
12VIN
24VIN
VOUT = 2.5V
Junction Temperature Rise vs
Load Current
Junction Temperature Rise vs
Load Current Output Noise and Ripple
VOUT LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
12
10
8
4
6
0
2
8047 G19
0 100
300
200 25015050
3.3VIN
5VIN
12VIN
24VIN
VOUT = 8V
VOUT LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
12
10
8
4
6
0
2
8047 G20
0 100
250
20015050
3.3VIN
5VIN
12VIN
24VIN
VOUT = 12V
10mV/DIV
8047
G21
2µs/DIV
12VIN, 5VOUT at 250mA
0.1μF 250V SAFETY CAPACITOR APPLIED
BETWEEN GND AND V
OUT
–
LTM8047
6
8047fc
For more information www.linear.com/LTM8047
PIN FUNCTIONS
VOUT (Bank 1): VOUT and VOUT– comprise the isolated
output of the LTM8047 flyback stage. Apply an external
capacitor between VOUT and VOUT–. Do not allow VOUT– to
exceed VOUT.
VOUT– (Bank 2): VOUT– is the return for VOUT. VOUT and
VOUT– comprise the isolated output of the LTM8047. In
most applications, the bulk of the heat flow out of the
LTM8047 is through the GND and VOUT– pads, so the
printed circuit design has a large impact on the thermal
performance of the part. See the PCB Layout and Thermal
Considerations sections for more details. Apply an external
capacitor between VOUT and VOUT–.
GND (Bank 4): This is the primary side local ground of the
LTM8047 primary. In most applications, the bulk of the heat
flow out of the LTM8047 is through the GND and VOUT–
pads, so the printed circuit design has a large impact on
the thermal performance of the part. See the PCB Layout
and Thermal Considerations sections for more details.
VIN (Bank 3): VIN supplies current to the LTM8047’s inter-
nal regulator and to the integrated power switch. These
pins must be locally bypassed with an external, low ESR
capacitor.
RUN (Pin F3): A resistive divider connected to VIN and this
pin programs the minimum voltage at which the LTM8047
will operate. Below 1.24V, the LTM8047 does not deliver
power to the secondary. Above 1.24V, power will be de-
livered to the secondary and 10µA will be fed into the SS
pin. When RUN is less than 1.24V, the pin draws 2.5µA,
allowing for a programmable hysteresis. Do not allow a
negative voltage (relative to GND) on this pin.
ADJ (Pin G7): Apply a resistor from this pin to GND to set
the output voltage, using the recommended value given
in Table 1. If Table 1 does not list the desired VOUT value,
the equation
RADJ = 28.4 VOUT–0.879
(
)
kΩ
may be used to approximate the value. To the seasoned
designer, this exponential equation may seem unusual.
The equation is exponential due to non-linear current
sources that are used to temperature compensate the
output regulation.
BIAS (Pin H5): This pin supplies the power necessary to
operate the LTM8047. It must be locally bypassed with a
low ESR capacitor of at least 4.7μF. Do not allow this pin
voltage to rise above VIN.
SS (Pin H6): Place a soft-start capacitor here to limit inrush
current and the output voltage ramp rate. Do not allow a
negative voltage (relative to GND) on this pin.
LTM8047
8
8047fc
For more information www.linear.com/LTM8047
OPERATION
The LTM8047 is a stand-alone isolated flyback switching
DC/DC power supply that can deliver up to 440mA of output
current. This module provides a regulated output voltage
programmable via one external resistor from 2.5V to 12V.
The input voltage range of the LTM8047 is 3.1V to 32V.
Given that the LTM8047 is a flyback converter, the output
current depends upon the input and output voltages, so
make sure that the input voltage is high enough to support
the desired output voltage and load current. The Typical
Performance Characteristics section gives several graphs
of the maximum load versus VIN for several output voltages.
A simplified block diagram is given. The LTM8047 contains
a current mode controller, power switching element, power
transformer, power Schottky diode, a modest amount of
input and output capacitance.
The LTM8047 has a galvanic primary to secondary isola-
tion rating of 725VDC. This is verified by applying 725VDC
between the primary to secondary for 1 second and then
applying –725VDC for 1 second. For details please refer
to the Isolation and Working Voltage section.
An internal regulator provides power to the control cir-
cuitry. The bias regulator normally draws power from the
VIN pin, but if the BIAS pin is connected to an external
voltage higher than 3.1V, bias power will be drawn from
the external source, improving efficiency. VBIAS must not
exceed VIN. The RUN pin is used to turn on or off the
LTM8047, disconnecting the output and reducing the input
current to 1μA or less.
The LTM8047 is a variable frequency device. For a fixed
input and output voltage, the frequency increases as the
load increases. For light loads, the current through the
internal transformer may be discontinuous.
LTM8047
9
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For more information www.linear.com/LTM8047
APPLICATIONS INFORMATION
For most applications, the design process is straight-
forward, summarized as follows:
1. Look at Table 1 and find the row that has the desired
input range and output voltage.
2. Apply the recommended CIN, COUT and RADJ.
3. Connect BIAS as indicated, or tie to an external source
up to 15V or VIN, whichever is less.
While these component combinations have been tested for
proper operation, it is incumbent upon the user to verify
proper operation over the intended system’s line, load and
environmental conditions. Bear in mind that the maximum
output current may be limited by junction temperature,
the relationship between the input and output voltage
magnitude and polarity and other factors. Please refer
to the graphs in the Typical Performance Characteristics
section for guidance.
Capacitor Selection Considerations
The CIN and COUT capacitor values in Table 1 are the
minimum recommended values for the associated oper-
ating conditions. Applying capacitor values below those
indicated in Table 1 is not recommended, and may result
in undesirable operation. Using larger values is generally
acceptable, and can yield improved dynamic response, if
it is necessary. Again, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions.
Ceramic capacitors are small, robust and have very low
ESR. However, not all ceramic capacitors are suitable.
X5R and X7R types are stable over temperature and ap-
plied voltage and give dependable service. Other types,
including Y5V and Z5U have very large temperature and
voltage coefficients of capacitance. In an application cir-
cuit they may have only a small fraction of their nominal
capacitance resulting in much higher output voltage ripple
than expected.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM8047. A
ceramic input capacitor combined with trace or cable
inductance forms a high-Q (underdamped) tank circuit. If
the LTM8047 circuit is plugged into a live supply, the input
voltage can ring to much higher than its nominal value,
possibly exceeding the device’s rating. This situation is
easily avoided; see the Hot-Plugging Safely section.
LTM8047 Table 1. Recommended Component Values and Configuration for Specific VOUT Voltages (TA = 25°C)
VIN VOUT VBIAS CIN COUT RADJ
3.1V to 32V 2.5V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 12.4k
3.1V to 32V 3.3V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10k
3.1V to 29V 5V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 16V, 1210 6.98k
3.1V to 26V 8V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 10V, 1206 4.53k
3.1V to 24V 12V 3.1V to 15V or Open 2.2µF, 25V, 0805 10µF, 16V, 1210 3.16k/12pF*
9V to 15V 2.5V VIN 2.2µF, 50V, 1206 100µF, 6.3V, 1210 12.4k
9V to 15V 3.3V VIN 2.2µF, 50V, 1206 47µF, 6.3V, 1210 10k
9V to 15V 5V VIN 2.2µF, 50V, 1206 22µF, 16V, 1210 6.98k
9V to 15V 8V VIN 2.2µF, 50V, 1206 22µF, 10V, 1206 4.53k
9V to 15V 12V VIN 2.2µF, 25V, 0805 10µF, 16V, 1210 3.16k
18V to 32V 2.5V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 12.4k
18V to 32V 3.3V 3.1V to 15V or Open 2.2µF, 50V, 1206 47µF, 6.3V, 1210 10k
18V to 29V 5V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 16V, 1210 6.98k
18V to 26V 8V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 10V, 1206 4.53k
18V to 24V 12V 3.1V to 15V or Open 2.2µF, 50V, 1206 10µF, 16V, 1210 3.16k/12pF*
Note: Do not allow BIAS to exceed VIN, a bulk input capacitor is required.
*Connect 3.16k in parallel with 12pF from ADJ to GND.
LTM8047
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APPLICATIONS INFORMATION
BIAS Pin Considerations
The BIAS pin is the output of an internal linear regulator
that powers the LTM8047’s internal circuitry. It is set to
3V and must be decoupled with a low ESR capacitor of at
least 4.7μF. The LTM8047 will run properly without apply-
ing a voltage to this pin, but will operate more efficiently
and dissipate less power if a voltage greater than 3.1V is
applied. At low VIN, the LTM8047 will be able to deliver
more output current if BIAS is 3.1V or greater. Up to 40V
may be applied to this pin, but a high BIAS voltage will
cause excessive power dissipation in the internal circuitry.
For applications with an input voltage less than 15V, the
BIAS pin is typically connected directly to the VIN pin. For
input voltages greater than 15V, it is preferred to leave the
BIAS pin separate from the VIN pin, either powered from
a separate voltage source or left running from the internal
regulator. This has the added advantage of keeping the
physical size of the BIAS capacitor small. Do not allow
BIAS to rise above VIN.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at start-up. The built-in soft-start circuit
significantly reduces the start-up current spike and output
voltage overshoot by applying a capacitor from SS to GND.
When the LTM8047 is enabled, whether from VIN reaching
a sufficiently high voltage or RUN being pulled high, the
LTM8047 will source approximately 10µA out of the SS
pin. As this current gradually charges the capacitor from
SS to GND, the LTM8047 will correspondingly increase
the power delivered to the output, allowing for a graceful
turn-on ramp.
Isolation and Working Voltage
The LTM8047 isolation is 100% hi-pot tested by tying
all of the primary pins together, all of the secondary pins
together and subjecting the two resultant circuits to a dif-
ferential of 725VDC for one second and then –725VDC for
one second. This establishes the isolation voltage rating
of the L
TM8047 component, and is most often used to
satisfy component safety specifications issued by agencies
such as UL, TUV, CSA and others.
The isolation rating of the LTM8047 is not the same as
the working or operational voltage that the application
will experience. This is subject to the application’s power
source, operating conditions, the industry where the end
product is used and other factors that dictate design re-
quirements such as the gap between copper planes, traces
and component pins on the printed circuit board, as well
as the type of connector that may be used. To maximize
the allowable working voltage, the LTM8047 has a row of
solder balls removed to facilitate the printed circuit board
design. The ball to ball pitch is 1.27mm, and the typical ball
diameter is 0.78mm. Accounting for the missing row and
the ball diameter, the printed circuit board may be designed
for a metal-to-metal separation of up to 1.76mm. This may
have to be reduced somewhat to allow for tolerances in
solder mask or other printed circuit board design rules.
To reiterate, the manufacturer’s isolation voltage rating
and the required operational voltage are often different
numbers. In the case of the LTM8047, the isolation voltage
rating is established by 100% hi-pot testing. The working
or operational voltage is a function of the end product
and its system level specifications. The actual required
operational voltage is often smaller than the manufacturer’s
isolation rating.
For those situations where information about the spacing
of LTM8047 internal circuitry is required, the minimum
metal to metal separation of the primary and secondary
is 0.44mm.
ADJ and Line Regulation
For VOUT greater than 8V, a capacitor connected from ADJ
to GND improves line regulation. Figure 1 shows the ef-
fect of three capacitance values applied to ADJ for a load
of 15mA. No capacitance has poor line regulation, while
12pF has improved line regulation. As the capacitance
increases, the line regulation begins to degrade again, but
in the opposite direction as having too little capacitance.
Furthermore, too much capacitance from ADJ to GND may
increase the minimum load required for proper regulation.
LTM8047
11
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For more information www.linear.com/LTM8047
APPLICATIONS INFORMATION
A few rules to keep in mind are:
1. Place the RADJ resistor as close as possible to its re-
spective pin.
2. Place the CIN capacitor as close as possible to the VIN
and GND connections of the LTM8047.
3. Place the COUT capacitor as close as possible to VOUT
and VOUT–.
4. Place the CIN and COUT capacitors such that their
ground current flow directly adjacent or underneath
the LTM8047.
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8047.
6. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
board. Pay attention to the location and density of the
thermal vias in Figure 2. The LTM8047 can benefit from
the heat sinking afforded by vias that connect to internal
GND planes at these locations, due to their proximity
to internal power handling components. The optimum
Figure 2. Layout Showing Suggested External Components,
Planes and Thermal Vias
8047 F02
BIAS
RUN
GND
ADJ
LTM8047
SS
COUT
VOUT–
VIN
VOUT
CIN
THERMAL/INTERCONNECT VIAS
VOUT to VOUT– Reverse Voltage
The LTM8047 cannot tolerate a reverse voltage from VOUT
to VOUT– during operation. If VOUT– raises above VOUT dur-
ing operation, the LTM8047 may be damaged. To protect
against this condition, a low forward drop power Schottky
diode has been integrated into the LTM8047, anti-parallel
to VOUT/VOUT–. This can protect the output against many
reverse voltage faults. Reverse voltage faults can be both
steady state and transient. An example of a steady state
voltage reversal is accidentally misconnecting a powered
LTM8047 to a negative voltage source. An example of
transient voltage reversals is a momentary connection to
a negative voltage. It is also possible to achieve a VOUT
reversal if the load is short-circuited through a long cable.
The inductance of the long cable forms an LC tank circuit
with the VOUT capacitance, which drives VOUT negative.
Avoid these conditions.
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8047. The LTM8047 is neverthe-
less a switching power supply, and care must be taken to
minimize electrical noise to ensure proper operation. Even
with the high level of integration, you may fail to achieve
specified operation with a haphazard or poor layout. See
Figure 2 for a suggested layout. Ensure that the grounding
and heat sinking are acceptable.
Figure 1. For higher output voltages, the LTM8047 requires some
capacitance from ADJ to GND for proper line regulation
LTM8047 Line Regulation
12VOUT, 15mA Output Current
VIN (V)
V
OUT
(V)
12.50
11.75
12.25
10.75
11.25
12.00
11.50
11.00
8047 F01
0 10
25
20155
NO CAP
12pF
18pF
LTM8047
12
8047fc
For more information www.linear.com/LTM8047
APPLICATIONS INFORMATION
number of thermal vias depends upon the printed
circuit board design. For example, a board might use
very small via holes. It should employ more thermal
vias than a board that uses larger holes.
The printed circuit board construction has an impact on
the isolation performance of the end product. For example,
increased trace and layer spacing, as well as the choice
of core and prepreg materials (such as using polyimide
versus FR4) can significantly affect the isolation withstand
of the end product.
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of the LTM8047. However, these capaci-
tors can cause problems if the LTM8047 is plugged into a
live supply (see Linear Technology Application Note 88 for
a complete discussion). The low loss ceramic capacitor
combined with stray inductance in series with the power
source forms an underdamped tank circuit, and the volt-
age at the VIN pin of the LTM8047 can ring to more than
twice the nominal input voltage, possibly exceeding the
LTM8047’s rating and damaging the part. If the input
supply is poorly controlled or the user will be plugging
the LTM8047 into an energized supply, the input network
should be designed to prevent this overshoot. This can
be accomplished by installing a small resistor in series
to VIN, but the most popular method of controlling input
voltage overshoot is adding an electrolytic bulk capacitor
to VIN. This capacitor’s relatively high equivalent series
resistance damps the circuit and eliminates the voltage
overshoot. The extra capacitor improves low frequency
ripple filtering and can slightly improve the efficiency of the
circuit, though it can be a large component in the circuit.
Thermal Considerations
The LTM8047 output current may need to be derated if it
is required to operate in a high ambient temperature. The
amount of current derating is dependent upon the input
voltage, output power and ambient temperature. The
temperature rise curves given in the Typical Performance
Characteristics section can be used as a guide. These curves
were generated by the LTM8047 mounted to a 58cm2
4-layer FR4 printed circuit board. Boards of other sizes
and layer count can exhibit different thermal behavior, so
it is incumbent upon the user to verify proper operation
over the intended system’s line, load and environmental
operating conditions.
For increased accuracy and fidelity to the actual application,
many designers use FEA to predict thermal performance.
To that end, the Pin Configuration section of the data sheet
typically gives four thermal coefficients:
θ
JA: Thermal resistance from junction to ambient
θ
JCbottom: Thermal resistance from junction to the bot-
tom of the product case
θ
JCtop: Thermal resistance from junction to top of the
product case
θ
JB: Thermal resistance from junction to the printed
circuit board.
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confusion
and inconsistency. These definitions are given in JESD
51-12, and are quoted or paraphrased as follows:
θJA is the natural convection junction-to-ambient air
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as still air although natural convection causes the air to
move. This value is determined with the part mounted to a
JESD 51-9 defined test board, which does not reflect an
actual application or viable operating condition.
θJCbottom is the junction-to-board thermal resistance with
all of the component power dissipation flowing through the
bottom of the package. In the typical µModule converter,
the bulk of the heat flows out the bottom of the package,
but there is always heat flow out into the ambient envi-
LTM8047
13
8047fc
For more information www.linear.com/LTM8047
APPLICATIONS INFORMATION
ronment. As a result, this thermal resistance value may
be useful for comparing packages but the test conditions
don’t generally match the user’s application.
θJCtop is determined with nearly all of the component power
dissipation flowing through the top of the package. As the
electrical connections of the typical µModule converter are
on the bottom of the package, it is rare for an application
to operate such that most of the heat flows from the junc-
tion to the top of the part. As in the case of θJCbottom, this
value may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
θJB is the junction-to-board thermal resistance where
almost all of the heat flows through the bottom of the
µModule converter and into the board, and is really the
sum of the θJCbottom and the thermal resistance of the
bottom of the part through the solder joints and through a
portion of the board. The board temperature is measured
a specified distance from the package, using a two-sided,
two-layer board. This board is described in JESD 51-9.
Given these definitions, it should now be apparent that none
of these thermal coefficients reflects an actual physical
operating condition of a µModule converter. Thus, none
of them can be individually used to accurately predict the
thermal performance of the product. Likewise, it would
be inappropriate to attempt to use any one coefficient to
correlate to the junction temperature vs load graphs given
in the product’s data sheet. The only appropriate way to
use the coefficients is when running a detailed thermal
analysis, such as FEA, which considers all of the thermal
resistances simultaneously.
A graphical representation of these thermal resistances
is given in Figure 3.
The blue resistances are contained within the µModule
converter, and the green are outside.
The die temperature of the LTM8047 must be lower than
the maximum rating of 125°C, so care should be taken in
the layout of the circuit to ensure good heat sinking of the
LTM8047. The bulk of the heat flow out of the LTM8047
is through the bottom of the module and the BGA pads
into the printed circuit board. Consequently a poor printed
circuit board design can cause excessive heating, result-
ing in impaired performance or reliability. Please refer to
the PCB Layout section for printed circuit board design
suggestions.
Figure 3.
8047 F03
µMODULE DEVICE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
JUNCTION
AMBIENT
CASE (BOTTOM)-TO-BOARD
RESISTANCE
LTM8047
14
8047fc
For more information www.linear.com/LTM8047
TYPICAL APPLICATIONS
3.3V Isolated Flyback Converter
Maximum Load vs VIN
Maximum Load Current vs VIN
725VDC ISOLATION
LTM8047
8047 TA02
VIN
9V TO 15V
VOUT
3.3V
280mA
(10VIN
)
10k
4.7µF
VOUT
VIN
RUN
ADJ
SS
BIAS
GND VOUT–
ISOLATION BARRIER
47µF
2.2µF
VIN (V)
9
MAXIMUM V
OUT
LOAD (mA)
350
340
330
320
300
310
260
270
280
290
250 11 13
8047 TA02b
15
10 12 14
VIN (V)
5
MAXIMUM V
OUT
LOAD (mA)
400
350
300
100
150
200
250
15 25
8047 TA03b
30
10 20
Use Two LTM8047 Flyback Converters to Generate ±5V
LTM8047
8047 TA03
–5V
280mA
(15VIN
)
6.98k
4.7µF
VOUT
VIN
RUN
ADJ
SS
BIAS
GND VOUT–
1µF
ISOLATION BARRIER
725VDC ISOLATION
2.2µF
22µF
LTM8047
VIN
3.5V TO 31V
5V
280mA
(15VIN
)
6.98k
4.7µF
VOUT
VIN
RUN
ADJ
SS
BIAS
GND VOUT–
1µF
ISOLATION BARRIER
725VDC ISOLATION
22µF
22µF
2.2µF
LTM8047
15
8047fc
For more information www.linear.com/LTM8047
PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME
A1 VOUT–B1 VOUT–C1 VOUT–D1 - E1 GND F1 - G1 VIN H1 VIN
A2 VOUT–B2 VOUT–C2 VOUT–D2 - E2 GND F2 - G2 VIN H2 VIN
A3 VOUT–B3 VOUT–C3 VOUT–D3 - E3 GND F3 RUN G3 - H3 -
A4 VOUT–B4 VOUT–C4 VOUT–D4 - E4 GND F4 GND G4 GND H4 GND
A5 VOUT–B5 VOUT–C5 VOUT–D5 - E5 GND F5 GND G5 GND H5 BIAS
A6 VOUT B6 VOUT C6 VOUT D6 - E6 GND F6 GND G6 GND H6 SS
A7 VOUT B7 VOUT C7 VOUT D7 - E7 GND F7 GND G7 ADJ H7 GND
Pin Assignment Table
(Arranged by Pin Number)
PACKAGE DESCRIPTION
PACKAGE PHOTO
LTM8047
16
8047fc
For more information www.linear.com/LTM8047
PACKAGE DESCRIPTION
BGA Package
45-Lead (11.25mm × 9.00mm × 4.92mm)
(Reference LTC DWG # 05-08-1869 Rev A)
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
!
PACKAGE TOP VIEW
4
PIN “A1”
CORNER
YX
aaa Z
aaa Z
DETAIL A
PACKAGE BOTTOM VIEW
3
SEE NOTES
H
G
F
E
D
C
B
A
1234567
PIN 1
BGA 45 1212 REV A
TRAY PIN 1
BEVEL PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1”
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
BALL DESIGNATION PER JESD MS-028 AND JEP95
4
3
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
DETAIL A
Øb (45 PLACES)
DETAIL B
SUBSTRATE
0.27 – 0.37
3.95 – 4.05
// bbb Z
A
A1
b1
ccc Z
DETAIL B
PACKAGE SIDE VIEW
MOLD
CAP
Z
MX YZddd
MZeee
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
aaa
bbb
ccc
ddd
eee
MIN
4.72
0.50
4.22
0.71
0.60
NOM
4.92
0.60
4.32
0.78
0.63
11.25
9.0
1.27
8.89
7.62
MAX
5.12
0.70
4.42
0.85
0.66
0.15
0.10
0.20
0.30
0.15
NOTES
DIMENSIONS
TOTAL NUMBER OF BALLS: 45
A2
D
E
e
b
F
G
SUGGESTED PCB LAYOUT
TOP VIEW
0.000
0.635
1.905
0.635
3.175
1.905
4.445
3.175
4.445
3.810
2.540
1.270
3.810
2.540
1.270
0.3175
0.3175
0.000
4.1275
4.7625
LTMXXXXXX
µModule
BGA Package
45-Lead (11.25mm × 9.00mm × 4.92mm)
(Reference LTC DWG # 05-08-1869 Rev A)
7
SEE NOTES
LTM8047
17
8047fc
For more information www.linear.com/LTM8047
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 1/14 Correct ADJ resistor on Typical Application schematic.
Add Min/Max limits to Output Voltage parameter.
Correct the 5VOUT RADJ value in Table 1.
Correct the 5VOUT RADJ value in schematic.
1
2
9
14
B 1/14 Added SnPb terminal finish product option. 1, 2
C 7/15 Added a new section: ADJ and Line Regulation. 10, 11
LTM8047
18
8047fc
For more information www.linear.com/LTM8047
LINEAR TECHNOLOGY CORPORATION 2011
LT 0715 REV C • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTM8047
RELATED PARTS
TYPICAL APPLICATION
12V Isolated Flyback Converter
725VDC ISOLATION
LTM8047
8047 TA04
VIN
15VDC TO 24VDC
VOUT
12V
180mA
(15VIN
)
3.16k
4.7µF
VOUT
VIN
RUN
ADJ
SS
BIAS
GND VOUT–
ISOLATION BARRIER
10µF
2.2µF
Maximum Load vs VIN
VIN (V)
15
MAXIMUM V
OUT
LOAD (mA)
8047 TA04b
24
2118
250
240
230
220
200
210
160
170
180
190
150
PART NUMBER DESCRIPTION COMMENTS
LTM8031 Ultralow Noise EMC 1A µModule Regulator EN55022 Class B Compliant, 3.6V ≤ VIN ≤ 36V; 0.8V ≤ VOUT ≤ 10V
LTM8032 Ultralow Noise EMC 2A µModule Regulator EN55022 Class B Compliant, 3.6V ≤ VIN ≤ 36V; 0.8V ≤ VOUT ≤ 10V
LTM8033 Ultralow Noise EMC 3A µModule Regulator EN55022 Class B Compliant, 3.6V ≤ VIN ≤ 36V; 0.8V ≤ VOUT ≤ 24V
LTM4612 Ultralow Noise EMC 5A µModule Regulator EN55022 Class B Compliant, 5V ≤ VIN ≤ 36V; 3.3V ≤ VOUT ≤ 15V
LTM8061 Li-Ion/Polymer µModule Battery Charger 4.95V ≤ VIN ≤ 32V, 2A, 1-Cell and 2-Cell, 4.1V or 4.2V per Cell
LTM8048 Isolated DC/DC µModule Regulator with LDO
Post Regulator
Low Noise LDO Post Regulator, Similar to the LTM8047
