AP63201WU-7 - DIODES INC - Datasheet.Directory

AP63200/AP63201/AP63203/AP63205

3.8V TO 32V INPUT, 2A LOW IQ SYNCHRONOUS BUCK WITH ENHANCED EMI REDUCTION

Description

The AP63200/AP63201/AP63203/AP63205

is a 2A, synchronous

buck converter with a wide input voltage

range of 3.8V to 32V and

fully integrates a 125mΩ high-side power MOSFET and a 68mΩ low-

side power MOSFET to provide high-efficiency step-

down DC/DC

conversion.

The AP63200/AP63201/AP63203/AP63205 device is

easily used by

minimizing the external component count due to its adoption of peak

current mode control along with its integrat ed com pensat i on network.

The AP63200/AP 63201/AP63203/AP63205 has optimized designs for

Electromagnetic Interference (EMI) reduc

tion. The converter features

Frequency Spread Spectrum (FSS) with a switching frequency jitter of

±6%, which

reduces EMI by not allowing emi tted energy to stay in any

one frequency for a significant period of time.

It also has a proprietary

gate driver scheme to resist switching node ringing

without sacrificing

MOSFET turn-on and turn-off times, which further erases high-

frequency radiat ed EMI noise caused by MOSFET switching.

The device is available in a low-profil e, TSOT26 pack age.

Features

• VIN 3.8V to 32V

• 2A Continuous Output Current

• 0.8V ± 1% Reference Voltage

• 22µA Ultralow Quiescent Current

• Switching Frequency

o 500kHz: AP63200 and AP63201

o 1.1MHz: AP63203 and AP63205

• Pulse Width Modulation (PW M) Regardless of Output Load

o AP63201

• Supports Pulse Frequency Modulati on (PFM)

o AP63200, AP63203, and AP63205

o Up to 80% Efficiency at 1mA Light Load

o Up to 88% Efficiency at 5mA Light Load

• Fixed Output Voltage

o 3.3V: AP63203

o 5.0V: AP63205

• Proprietary Gate Dri ver Design f or Best EMI Reducti on

• Frequency Spread Spect rum (FSS) to Reduce EMI

• Precision Enable Threshold to Adjust UVLO

• Protection Ci rcuitry

o Overvoltage Protecti on

o Cycle-by-Cycle P eak Current Limi t

o Thermal Shutdown

• Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)

• Halogen and Antimony Free. “Green” Device (Note 3)

Pin Assignme nts

3 4

VIN GND

BST

TSOT26

TOP VIEW

Applications

• 12V and 24V Distributed Power Bus Supplies

• Flat Screen TV Sets and Monitors

• Power Tools and Laser Printers

• White Goods and Small Home Appliances

• FPGA, DSP, and ASIC Supplies

• Home Audio

• Network Systems

• Set Top Boxes

• Gaming Consoles

• Consumer Electronics

Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant.

2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and

Lead-free.

3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and

<1000ppm antimony compounds.

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AP63200/AP63201/AP63203/AP63205

Typical Application Circuit

AP63205

4.7µH

100nF

2x22μF

10μF

VIN

BST

GND

OUTPUT

OUT

INPUT

Figure 1. Typical Application Circuit

Figure 2. Efficiency vs. Output Current

Pin Descriptions

Pin Num ber Pin Name Function

1 FB

Feedback sensing terminal for the output voltage. Connect this pin to the resistive divider of the output.

See

Setting the Output Voltage

section for more details.

2 EN Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator and low

to turn it off. Attach to VIN or leave open for automatic startup. The EN has a precision threshold of 1.18V for

programing the UVLO. See Enable section for more details.

3 VIN

Power Input. VIN supplies the power to the IC, as well as the step-down converter switches. Drive VIN with a

3.8V to 32V power source. Bypass VIN to GND with a suitably large capacitor to eliminate noise due to the

switching of the IC. See I nput Capacitor section for more details.

GND

Power Ground.

5 SW

Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC filter

from SW to the output load. Note that a capacitor is required from SW to BST to power the high-side switch.

6 BST

High-Side Gate Drive Boost Input. BST supplies the drive for the high-side N-Channel MOSFET. A 100nF

capacitor is recommended from SW to BST to power the high-side switch.

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Functional Block Diagram

0.4V

0.8V

1.1V

0.6V

0.8V

Internal SS Error

Amplifier

PWM

Comparator

Oscillator +

Logic

Ref OCP

7.6nF

18kΩ

SE = 0.84V/T

RT = 0.2V/A

UVP

4GND

5SW

6BST

3VIN

20kΩ

Internal

Reference

VCC

Regulator

1.18V

1.5µA 4µA

VSUM

COMP

CSA

Figure 3. Functional Block Diagram

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Absolute Maximum Ratings (Note 4) (@TA = +25°C, unless otherwise specified.)

Symbol

Parameter

Rating

Unit

VIN Supply Voltage -0.3 to +35.0 (DC) V

-0.3 to +40.0 (400ms) V

Switch Node Voltage -1.0 to V

+ 0.3 V

BST

Bootstrap Voltage V

- 0.3 to V

+ 6.0 V

Feedback Voltage

-0.3V to +6.0

VEN

Enable/UV LO Voltage

-0.3V to +35.0

TST

Storage Temperature -65 to +150 °C

Junction Temperature +160 °C

Lead Temperature

+260

°C

ESD Susceptibility (Note 5)

HBM

Human Body Mode

2000

CDM

Charge Device Model

1000

Notes: 4. Stresses greater than the 'Absolute Maximum Ratings' specified above may cause permanent damage to the device. These are stress ratings only;

functional operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. Device reliability may

be affected by exposure to absolute maximum rating conditions for extended periods of time.

5. Semiconductor devices are ESD sensitive and may be damaged by exposure to ESD events. Suitable ESD precautions should be taken when

handling and transporting these devices.

Thermal Resistance (Note 6)

Symbol

Parameter

Rating

Unit

θJA

Junction to Ambient TSOT26 89 °C/W

θJC

Junction to Case TSOT26 39 °C/W

Note: 6. Test condition for TSOT26: D evice mount ed on FR-4 substrate, single-layer PC board, 2oz copper, with minimum recommended pad layout.

Recommended Operating Conditions (Note 7) (@TA = +25°C, unless otherwise specified.)

Symbol

Parameter

Min

Max

Unit

Supply Voltage

3.8

32 V

Operating Ambient Temperature Range

-40

+85

°C

Note: 7. The device function is not guaranteed outside of the recommended operating conditions.

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Electrical Characteristics (TA = +25°C, VIN = 12V, unless otherwise specified. Min/Max limits apply across the recommended

ambient temperature range, -40°C to +85°C, and input voltage range, 3.8V to 32V).

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

ISHDN

Shutdown Supply Current

VEN = 0V

—

µA

IQ Supply Current (Quiescent)

AP63201:

VEN = OPEN, VFB = 1.0V

— 258 — µA

AP63200/AP63203/AP63205:

= OPEN , V

= 1.0V — 22 — µA

UVLO V

Under Voltage Threshold (Rising) — 3.30 3.50 3.70 V

Under Voltage Threshold Hysteresis — — 440 — mV

RDS(ON)1

High-Side S witc h On-Resistance (Note 8)

—

125

—

mΩ

RDS(ON)2

Low-Side Switch On-Resistance (Note 8) — — 68 — mΩ

IPEAK_LIMIT

HS Peak Current Limit (Note 8) — 2.5 2.8 3.1 A

IVALLEY_LIMIT

LS Valley Current Limit (Note 8) — 2.5 3.2 3.9 A

fSW Oscillat or Frequency

AP63200/AP63201

—

500

—

kHz

AP63203/AP63205

—

1100

—

kHz

FSS

Frequency Spread Spect rum

—

±6

—

tON

Minimum O n Time — — 80 — ns

VFB Feedback Voltage

CCM, AP63200/AP63201

792

800

808

CCM, AP63203

3.27

3.30

3.33

CCM, AP63205

4.95

5.00

5.05

VEN_H

EN Logic High — 1.15 1.18 1.23 V

VEN_L

EN Logic Low — 1.05 1.10 1.15 V

IEN EN Input Current

VEN = 1.5V

— 5.5 — μA

VEN = 1V

—

1.5

—

μA

tSS

Soft-Start Peri od

—

TSD Thermal Shutdown (Note 8) — — +160 — °C

HYS

Thermal Hysteresis (Not e 8) — — +25 — °C

Note: 8. Compliance to the datasheet limits is assured by one or more methods: production test, characterization, and/or design.

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Typical Performance Characteristics (AP63200 @TA = +25°C, VIN = 12V, VOUT = 5V, unless otherwise specifi ed. )

Figure 4. Efficiency vs. Output Current, VIN = 12V

Figure 5. Efficiency vs. Output Current, VIN = 24V

Figure 6. Load Regulation, VOUT = 5V

Figure 7. Line Regulation, VOUT = 5V

Figure 8. Feedback Voltage vs. Temperature

Figure 9. Power Switch R

DS(ON)

vs. Temperature

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Typical Performance Characteristics (continued)

Figure 10. I

vs. Temperature

Figure 11. I

SHDN

vs. Temperature

Figure 12. F

vs. Temperature

Figure 13. VIN POR and UVLO vs. Temperature

Figure 14. Startup using EN, Iout = 2A

Figure 15. Shutdown using EN, Iout = 2A

EN (5V/div)

VOUT (2V/div)

IL (2A/div)

SW (10V/div)

2ms/div

EN (5V/div)

VOUT (2V/div)

IL (2A/div)

SW (10V/div)

50µs/div

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Typical Performance Characteristics (continued)

Figure 16. Output Ripple, Iout = 2A

Figure 17. Load Transient, Iout = 1A to 2A

Figure 18. Output Short Prote ct i on, Iout = 2 A

Figure 19. Output Short Recovery, Iout = 2A

VOUT Ripple (20mV/div)

IL (1A/div)

SW (10V/div)

2µs/div

VOUT Ripple (500mV/div)

IOUT (1A/div)

1ms/div

VOUT (2V/div)

IL (2A/div)

SW (10V/div)

10ms/div

VOUT (2V/div)

IL (2A/div)

SW (10V/div)

10ms/div

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Appli cation Information

AP63200

AP63201

2.2μH

30.9kΩ

62kΩ

100nF

2x22μF

10μF

VIN

BST

GND

OUTPUT

OUT

1.2V

INPUT

100pF

Figure 20. Typical Application Circuit of AP63200/AP63201

AP63203

AP63205

100nF

2x22μF

10μF

VIN

BST

GND

OUTPUT

OUT

INPUT

Figure 21. Typical Application Circuit of AP63203/AP63205

1 PWM Operation Co nt rol

The AP63200/AP63201/AP63203/AP63205 device is a 3.8V-to-32V input, 2A output, EMI friendly, fully integrated synchronous buck converter.

Refer to the bl ock diagram in Figure 3. The devi ce employs fixed-fre quency peak c urrent mode c ontrol. The internal c l ock’s rising edge (500kHz for

AP6300 and AP63201, 1.1MHz for AP63203 and AP63205) initiat es turning on the integrated high-side power MOSFET, Q1, for each cycl e. When

Q1 is on, the inductor current rises linearly, and the device charges the output capacitor. The current across Q1 is sensed and converted to a

voltage with a ratio of RT via the CS A block. The CSA output is combined with an internal slope compensation, SE, resulting in V SUM. When VSUM

rises higher than the i nternal COMP node, the device turns off Q1 and turns on the low-side power MOSFET, Q2. T he inductor current decreases

when Q2 is on. On the rising edge of next clock cycle, Q2 turns off, and Q1 turns on. This sequenc e repeats every clock cycle.

The peak current mode control with the internal loop compensation network and built-in 4ms soft-start simplifies the

AP63200/AP63201/AP63203/AP63205 footprint as well as minimizes the external component count.

The error amplif i er generates the COMP voltage by c omparing t he voltage on t he FB pin with an internal 0. 8V reference. An increase in load current

causes the feedback voltage to drop. The error amplifier thus raises the COMP voltage until the average inductor current matches the increased

load current. This feedback loop regulates the output voltage. The device also integrates internal slope compensation circuitry to prevent

subharmonic osci llat i on when the duty c ycle is great er than 50% for peak current mode control.

The AP63200/AP63201/AP63203/AP63205 device implements Frequency Spread Spectrum (FSS) with a switching frequency jitter of ±6%. FSS

reduces EMI by not allowing emitted energy to stay in any one frequency for a significant period of time. The converter further dampens high

frequency radiated EMI noise through the use of its proprietary gate driver scheme to achieve a ringing-free switching node voltage without

sacrificing the MOSFET switching times.

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Appli cation Information (continued)

In order to provide a small output ripple in light load conditions, t he AP63201 offers a fixed 500kHz switching frequenc y with FSS and Puls e Wi dth

Modulation (PW M).

The hiccup mode minim izes power dis sipation during prolonged output overcurrent or short condi tions. The hi ccup wait time is 512 cycles and the

hiccup restart time is 8192 cycles. The AP63200/AP63201/AP63203/AP63205 also features full protections including cycle-by-cycle high-side

MOSFET peak current limit, overvoltage prot ect i on, and overtemperature protection.

2 Pulse Frequency Modulation

In heavy load conditions, t he AP63200, AP63203, and AP63205 operate at forced PW M mode. The internal COMP node voltage decreases as the

load current decreases. At a certain limit, if the load current is low enough, the COMP node voltage is clamped and is prevented from decreas ing

any further. The voltage at which COMP is clamped corresponds to the 450mA peak inductor current. As the load current approaches zero, the

AP63200, AP63203, and AP63205 enter Pulse Frequency Modulat ion (PFM) to increase the converter power efficiency at light load conditions. The

AP63201 remains in continuous conduction mode at light load conditions. When the inductor current decreases to zero, zero-cross detection

circuitry on the low-side power MOSFET, Q2, forces it off until the beginning of t he next switc hing cycle. The buck converter does not sink current

from the output when the output load is light and while the device is in PFM. Because the AP63200, AP63203, and AP 63205 work in PFM during

light load conditions, they c an achieve power effici ency of up to 88% at a 5mA load condition.

The quiescent current of AP63200, AP63203 and AP63205 is 2 2μA typical under a no-load, non-switching condition.

3 Enable

When disabled, the devic e shutdown supply current is only 1μA. When applying a voltage higher t han the EN upper threshold (typical 1.18V, rising),

the AP63200/AP63201/AP63203/AP63205 enables all functions, and the device initiates the soft-start phase. The

AP63200/AP63201/AP63203/AP63205 has a built-in 4ms soft-start time to prevent output voltage overshoot and inrush current. When the EN

voltage falls bel ow its lower threshold (t ypical 1.1V, falling), the internal SS volt age is discharged to ground and device operation is disabled.

An internal 1.5µA pull-up current source connected from the internal LDO-regulated VCC to the EN pin guarantees that a high on the EN pin

automatically enables the device. For applications requiring a higher VIN UVLO voltage than is provided by the default setup, there is a 4µA

hysteresis pul l -up current source on the EN pin that configures the VIN UVLO volt age with an external resistive divider (R5 and R6) shown in Figure

22. The resistive divider resistor values are calculated by equations Eq.1 and Eq. 2.

EN 20kΩ

1.18V

1.5µA I

4µA

VIN

Figure 22. Programming UVLO

=.    

.

Eq. 1

=.

  . +.  

Eq. 2

Where:

• VON is the rising edge voltage to enable the regulator

• VOFF is the falling edge voltage to disable the regulator

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Appli cation Information (continued)

Alternatively, a small ceramic capacitor can be added from EN to GND. This delays t he output startup voltage, which is useful when sequencing

multipl e power rails to minimize i nput inrush current. The amount of capacitance is calculated by equation Eq.3.

[] = .  []

Eq. 3

Where:

• Cd is the time delay capacitance in nF

• ts is the delay time in ms

The EN pin is a high voltage pin and can be directly connected to VIN to automatically start up the device as VIN increases.

4 Undervoltage Loc kout

Undervoltage lockout is implemented to prevent the IC from insufficient input voltages. The AP63200/AP63201/AP63203/AP63205 device has a

UVLO comparator that monitors the input voltage and the internal bandgap reference. If the input voltage falls below 3.1V, the

AP63200/AP63201/AP63203/AP63205 is disabled. In this event, both the high-side and low-side power MOSFETs are turned off.

5 EMI Reduction with Frequency Spread Spectrum and Ringing-free Switching Node

In the some applications, the system must meet EMI standards. To improve EMI reduction, the AP63200/AP63201/AP63203/AP63205 adopts FSS

to spread the switching noise over a wider frequency band and therefore reduces conducted and radiated interferenc e at a particular frequency.

In buck converters, t he switching node’s (SW’s) ringi ng amplitude and cycles are critical , especially in relation to t he high frequency radiation EMI

noise. The AP63200/AP63201/AP63203/AP63205 device implements a multi-level gate driver scheme to achieve a ringing-free switching node

without sacrificing neither the switc hing node’s rise and fall slew rates nor the convert er’s power effic iency. The AP63203 and AP63205 also have

the feature to remove the resonance ringing of the SW pin when the inductor current is 0A and the device operates in PFM. The zoomed in

waveform for SW is shown in Figure 23.

Figure 23. AP63203/AP63205 SW Node Waveform

6 Overcurrent Protection

The AP63200/AP63201/AP63203/AP63205 has cycle-by-cycle peak current limit protection by sensing the current through the internal high-side

power MOSFET Q1. While Q1 is on, its c onduction current is monitored by the internal sensi ng circuitry. Once the current through Q1 exceeds the

current peak limit, Q1 immediately turns off. If Q1 consistently hits the peak current limit for 2ms, the buck converter enters hiccup mode and shuts

down. After 16ms of off time, the buck converter restarts powering up. Hiccup mode reduces t he power dissipation in the overcurrent condition.

7 Thermal Shutdown

If the juncti on t em perature of t he device reaches the thermal shut down limi t of +150°C, the AP63200/AP63201/AP63203/AP63205 shuts down both

their high-si de and low-side power MOSFETs. When the junction temperat ure reduces to the required level (+130°C nominal), the device initi ates a

normal power-up cycle with soft-start.

SW (5V/div)

IL (1A/div)

No SW Ringing

2µs/div

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Appli cation Information (continued)

8 Power Derating Characteristi cs

To prevent the regulator from exceeding the maximum junct i on temperature, some thermal analysis is required. The temperature rise is given by:

 = ()

Eq. 4

Where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature.

The junction temperat ure, TJ, is given by:

=+

Eq. 5

Where TA is the ambient temperature of the environment. For the TSOT26 package, the θJA is 89 °C/W. The actual junction temperature s hould not

exceed the absolute maximum junction temperature of +125°C when considering the thermal design. A typical derating curve versus ambient

temperature is shown in Figure 24.

Figure 24. Output Current Derating Curve vs. Temperature, VIN = 12V

9 Setting the Output Voltage

The AP63203 and AP63205 have fixed output voltages of 3.3V and 5V, respectively. The AP63200 and AP63201 have adjustable output

voltages starting from 0.8V using an external resistive divider. An optional in Figure 20, of 10pF to 220pF is used to improve the transient

response. Resisto r R2 is selected based on a design tradeoff between efficiency and output voltage accuracy. There is less current consumption

in the feedback network for high values of R2. R1 can be determined by the following equation:

=(

.  )

Eq. 6

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Appli cation Information (continued)

Table 1 shows a list of recommended component selections f or common output voltages for AP6300 and AP63201 referenc i ng Figure 20.

AP63200/AP63201

Output Voltage (V)

R1 (kΩ)

R2 (kΩ)

L (µH)

C1 (µF)

C2 (µF)

C3 (nF)

C4 (pF)

1.2

30.9

2.2

2 x 22

100

1.5

54.2

2.2

2 x 22

100

1.8

77.5

3.3

2 x 22

100

2.5

131

3.3

2 x 22

100

3.3

182

6.8

2 x 22

100

157

2 x 22

100

249

2 x 22

100

Table 1. Recommended Component Selections for AP63200/AP63201

Tables 2 and 3 show recommended component selections for AP63203 and AP63205 referencing Figure 21.

AP63203

Output Voltage (V)

L (µH)

C1 (µF)

C2 (µF)

C3 (nF)

3.3

3.9

2 x 22

100

Table 2. Recommended Component Selections for AP63203

AP63205

Output Voltage (V)

L (µH)

C1 (µF)

C2 (µF)

C3 (nF)

4.7

2 x 22

100

Table 3. Recommended Component Selections for AP63205

10 Inductor

Calculating the inductor value is a critical factor in designing a buck converter. For most designs, the following equation can be used to calc ulate

the inductor value:

=()



Eq. 7

Where ∆IL is the inductor ripple current, and fSW is the buck converter switching frequency. For AP63200/AP63201/AP63203/AP63205, choose ∆IL

to be 30% to 50% of the maximum load current of 2A.

The inductor peak current is calculated by:

 = +



Eq. 8

Peak current determines the required saturation current rating, which influences the size of the inductor. Saturating the inductor decreases the

converter eff iciency while increas ing the temperat ures of the inductor and the internal power MOSFETs. Therefore, choosing an inductor with the

appropriate saturation current rating is important. For most applications, it is recommended to select an inductor of approximately 2.2µH to 10µH

with a DC current rating of at least 35% higher than the m aximum load current. F or highest efficiency, the inductor’s DC resistanc e should be less

than 100mΩ. Use a larger inductance for improved efficiency under light load conditions.

11 Input Capacitor

The input capacitor reduc es the surge current drawn from the input supply as well as the switc hing noise from the device. The input capacit or has

to sustain the ripple current produced during the on time of Q1. It must have a low ESR to mi nimi ze t he losses.

The RMS current rat ing of the input c apacitor is a c ritical paramet er and must be hi gher than the RMS input current . As a rule of thumb, select an

input capacitor which has an RMS rating greater than half of the maximum load current.

Due to large dI/dt through the input capacitor, electrolytic, or ceramics with l ow ES R should be used. If a tantalum capacitor is used it must be

surge protected or els e c apacitor failure could occur. Using a ceramic capacitor greater than 10µF is suffici ent f or most applicati ons.

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Appli cation Information (continued)

12 Output Capacitor

The output capacitor keeps the output voltage ripple small, ensures f eedback loop stability, and reduces the overshoot /undershoot of the output

voltage during load transients. During the first few milliseconds of a load transient, the output capacitor supplies the current to the load. The

converter recogni zes the load transi ent and sets the duty cycle to maximum but the current slope is limited by the inductor value.

The output capacitor, COUT, requirements can be calculated from equations Eq. 9 and Eq. 10.

The ESR of the output capacitor dominates the output voltage ri ppl e. The amount of ripple can be calculated from Eq. 9:

 = 

Eq. 9

An output capacitor with large capacitance and low ESR is the best option. For most applications, a 22µF to 6 8µF ceramic capac itor is sufficient.

To meet the load transient requirement, COUT should be greater than the following calc ul at ed from Eq. 10:

 >󰇡

󰇢

()



Eq. 10

Where

ΔV

is the maximum output overshoot voltage.

13 Bootstrap Capacito r

To ensure the proper operation, a ceramic capacitor must be connected between the BST and SW pins. A 100nF ceramic capacitor is sufficient. If

the BST c apacitor volt age falls below 2.3V, the boot undervoltage prot ection c ircuit turns Q2 on f or 220ns to refresh t he BST capacitor and raise its

voltage back above 2.85V. The BST capacitor voltage threshold is always maintained to ensure enough driving capability for Q1. This operation

may arise during long periods of no switching such as in PFM with light load conditions. Another event requires the refres hing of the BST capacitor

is when the input voltage drops close to the output voltage. Under this condition, the regulator enters low dropout mode by holding Q1 on for

multipl e clock cycl es. To prevent the BST capacitor from discharging, Q2 is forced to refres h. The effective dut y cycl e is approximat el y 100% so that

it acts as an LDO to maintain the output voltage regulation.

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Layout

PCB Layout

1. The AP63200/AP63201/AP63203/AP63205 device works at 2A current load, so heat dissi pation is a major concern in the layout of the P CB.

2oz copper for both the top and bottom layers is recommended.

2. Provide s uffic i ent vias for the input and output capacitors’ GND side to dissipate heat to the bottom layer.

3. Make the bottom layer under the device as the GND layer for heat dissipation. The GND layer should be as large as possible to provide

better thermal effect.

4. Place the VIN capacitors as close to the device as possible.

5. Place the feedback components as clos e t o F B as possible.

6. See Figure 25 for reference.

C1 C2

VIN VOUT

3 4

6FB

VIN GND

BST

GND

Figure 25. Recommended Layout

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Ordering Information

Please see http://www.diodes.com/package-outli nes. html for additional lat est inf orm ation such as Mechanical Data and Devic e Tape Orientati on.

AP6320X XX - X

Packing

Product Version Package

7 : Tape & Reel

WU : TSOT26

0: AP63200

1: AP63201

3: AP63203

5: AP63205

Part Number Mode Frequency VOUT P ackag e Co de

Tape and Reel

Quantity

Part Number Suffix

AP63200WU-7 PWM/PFM 500kHz Adjustable WU 3000 -7

AP63201WU-7 PWM Only 500kHz Adjustable WU 3000 -7

AP63203WU-7 PWM/PFM 1100kHz 3.3V WU 3000 -7

AP63205WU-7

PWM/PFM

1100kHz

3000

-7

Marking Information

TSOT26

123

XX Y WX

XX : Identification Code

Y : Year 0~9

X : Internal Code

(Top View)

W : Week : A~Z : 1~26 week;

a~z : 27~52 week; z represents

52 and 53 week

Part Number Package Identification Code

AP63200WU-7

TSOT26

AP63201WU-7

TSOT26

AP63203WU-7

TSOT26

AP63205WU-7

TSOT26

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Package Ou t lin e Dim en sio ns

Please see http://www.diodes.com/package-outlines.html for the latest version.

TSOT26

Dim

Min

Max

Typ



1.00

—

0.010

0.100

—

0.840

0.900

—

2.800

3.000

2.900

2.800 BSC

1.500

1.700

1.600

0.300

0.450

—

0.120

0.200

—

0.950 BSC

1.900 BSC

0.30

0.50

—

0.250 BSC

0°

8°

4°

θ1

4°

12°

—

All Dimensions in mm

Suggested Pad Layout

Please see http://www.diodes.com/package-outlines.html for the latest version.

TSOT26

Dimensions

Value (in mm)

0.950

0.700

1.000

3.199

E1/2

E/2

Seating Plane

Gauge Plane

01( 4x)

Seating Plane

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IMPORTANT NOTICE

DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT,

INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).

Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes

without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the

application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or

trademark ri ghts, nor the rights of others. Any Customer or user of this document or products descri bed herein in such applic ations shall assume

all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on Diodes Incorporated

website, harml ess against all damages.

Diodes Incorporated does not warrant or acc ept any li ability whatsoever in respect of any products purchased through unauthori zed sales channel.

Should Customers purchase or use Diodes Incorporat ed products for any unintended or unauthorized application, Customers shall indemnify and

hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or

indirect l y, any claim of personal injury or death associat ed with such unintended or unauthorized application.

Products desc ribed herein may be covered by one or more United S tates, international or f oreign patents pending. Product names an d ma rkings

noted herein may also be covered by one or more United States, international or f orei gn trademarks.

This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the

final and determinative f orm at released by Diodes I ncorporat ed.

LIFE SU PP O R T

Diodes Incorporated products are specifical ly not authorized for use as critical components in life support devices or systems without the express

written approval of the Chief Executive Off icer of Diodes I ncorporat ed. As us ed herein:

A. Life support devices or systems are devices or systems which:

1. are intended to implant into the body, or

2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the

labeling can be reasonably expected to result in significant injury to the user.

B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the

failure of the life support device or to affect its safety or effectivenes s.

Customers represent that they have all necessary expertise in t he safety and regulatory ramif ications of their life support devices or systems, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safet y-related requirem ents concerning their products and any

use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related

information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its

representati ves against any dam ages arising out of the use of Diodes Incorporat ed products i n such safety-cri tical, life support devices or systems.

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