256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 1 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
Document Title
256Kx36 & 256Kx32 & 512Kx18-Bit Pipelined NtRAMTM
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
0.2
1.0
2.0
2.1
Remark
Preliminary
Preliminary
Preliminary
Final
Final
Final
History
1. Initial document.
1. Add x32 org part and industrial temperature part
1. change scan order(1) form 4T to 6T at 119BGA(x18)
1. Final spec release
2. Change ISB2 form 50mA to 60mA
Change ordering information( remove 225MHz at Nt-Pipelined)
1. Delete 119BGA package
Draft Date
May. 18. 2001
Aug. 11. 2001
Aug. 28 .2001
Nov. 16. 2001
April. 01. 2002
April. 04. 2003
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 2 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
8Mb NtRAM(Flow Through / Pipelined) Ordering Information
NOTE : 119BGA is Only Supported with K7N801845B-HC13, K7N803649B-HC25, K7N803601B-HC13 and K7M803625B-HC75.
Org. Part Number Mode VDD Speed
FT ; Access Time(ns)
Pipelined ; Cycle Time(MHz) PKG Temp
512Kx18
K7M801825B-QC(I)65/75/85 FlowThrough 3.3 6.5/7.5/8.5 ns
Q:
100TQFP
C:
Commercial
Temperature
Range
I:
Industrial
Temperature
Range
K7N801801B-QC(I)16/13 Pipelined 3.3 167/133 MHz
K7N801809B-QC(I)25/20 Pipelined 3.3 250/200 MHz
K7N801845B-QC(I)16/13 Pipelined 2.5 167/133 MHz
K7N801849B-QC(I)25/20 Pipelined 2.5 250/200 MHz
256Kx32
K7M803225B-QC(I)65/75/85 FlowThrough 3.3 6.5/7.5/8.5 ns
K7N803201B-QC(I)16/13 Pipelined 3.3 167/133 MHz
K7N803209B-QC(I)25/20 Pipelined 3.3 250/200 MHz
K7N803245B-QC(I)C16/13 Pipelined 2.5 167/133 MHz
K7N803249B-QC(I)25/20 Pipelined 2.5 250/200 MHz
256Kx36
K7M803625B-QC(I)65/75/85 FlowThrough 3.3 6.5/7.5/8.5 ns
K7N803601B-QC(I)16/13 Pipelined 3.3 167/133 MHz
K7N803609B-QC(I)25/20 Pipelined 3.3 250/200 MHz
K7N803645B-QC(I)16/13 Pipelined 2.5 167/133 MHz
K7N803649B-QC(I)25/20 Pipelined 2.5 250/200 MHz
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 3 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
256Kx32 & 256Kx36 & 512Kx18-Bit Pipelined NtRAMTM
The K7N803601B, K7N803201B and K7N801801B are
9,437,184 bits Synchronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N803601B, K7N803201B and K7N801801B are imple-
mented with SAMSUNG′s high performance CMOS technology
and is available in 100pin TQFP and Multiple power and
ground pins minimize ground bounce.
GENERAL DESCRIPTIONFEATURES
LOGIC BLOCK DIAGRAM
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
• Α interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• 100-TQFP-1420A
• Operating in commercial and industrial temperature range.
FAST ACCESS TIMES
PARAMETER Symbol -16 -13 Unit
Cycle Time tCYC 6.0 7.5 ns
Clock Access Time tCD 3.5 4.2 ns
Output Enable Access Time tOE 3.5 3.8 ns
WE
BWx
CLK
CKE
CS1
CS2
CS2
ADV
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb8
ADDRESS
ADDRESS
REGISTER
CONTROL
LOGIC
A′0~A′1
36/32 or 18
DQPa ~ DQPd
OUTPUT
BUFFER
REGISTER
DATA-IN
REGISTER
DATA-IN
REGISTER
K
K
K
REGISTER
BURST
ADDRESS
COUNTER
WRITE
ADDRESS
REGISTER
WRITE
CONTROL
LOGIC
CONTROL
REGISTER
K
A [0:17] or LBO
A2~A17 or A2~A18
A0~A1
(x=a,b,c,d or a,b)
256Kx36/32 , 512Kx18
MEMORY
ARRAY
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung,
and its architecture and functionalities are supported by NEC and Toshiba.
A [0:18]
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 4 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
PIN CONFIGURATION(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
DQPc/NC
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
VDD
VDD
VDD
VSS
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd/NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
VDD
VDD
ZZ
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa/NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A6
A7
CS1
CS2
BWd
BWc
BWb
BWa
CS2
VDD
VSS
CLK
WE
CKE
OE
ADV
N.C.
A17
A8
81 A9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
A16
A15
A14
A13
A12
A11
A10
N.C.
N.C.
VDD
VSS
N.C.
N.C.
A0
A1
A2
A3
A4
A5
31LBO
PIN NAME
Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.
2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
3. DQPa~DQPd are NC for K7N803201B.
SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.
A0 - A17
ADV
WE
CLK
CKE
CS1
CS2
CS2
BWx(x=a,b,c,d)
OE
ZZ
LBO
Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
32,33,34,35,36,37,44
45,46,47,48,49,50,81
82,83,99,100
85
88
89
87
98
97
92
93,94,95,96
86
64
31
VDD
VSS
N.C.
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
/NC
VDDQ
VSSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(3.3V or 2.5V)
Output Ground
14,15,16,41,65,66,91
17,40,67,90
38,39,42,43,84
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
K7N803601B(256Kx36)
K7N803201B(256Kx32)
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 5 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
PIN CONFIGURATION(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb8
DQb7
VSSQ
VDDQ
DQb6
DQb5
VDD
VDD
VDD
VSS
DQb4
DQb3
VDDQ
VSSQ
DQb2
DQb1
DQb0
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQa0
DQa1
DQa2
VSSQ
VDDQ
DQa3
DQa4
VSS
VDD
VDD
ZZ
DQa5
DQa6
VDDQ
VSSQ
DQa7
DQa8
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A6
A7
CS1
CS2
BWb
BWa
CS2
VDD
VSS
CLK
WE
CKE
OE
ADV
N.C.
A18
A8
81 A9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
A17
A16
A15
A14
A13
A12
A11
N.C.
N.C.
VDD
VSS
N.C.
N.C.
A0
A1
A2
A3
A4
A5
31LBO
K7N801801B(512Kx18)
N.C.
N.C.
PIN NAME
Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.
2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.
A0 - A18
ADV
WE
CLK
CKE
CS1
CS2
CS2
BWx(x=a,b)
OE
ZZ
LBO
Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
32,33,34,35,36,37,44
45,46,47,48,49,50,80
81,82,83,99,100
85
88
89
87
98
97
92
93,94
86
64
31
VDD
VSS
N.C.
DQa0~a8
DQb0~b8
VDDQ
VSSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(3.3V or 2.5V)
Output Ground
14,15,16,41,65,66,91
17,40,67,90
1,2,3,6,7,25,28,29,30,
38,39,42,43,51,52,53,
56,57,75,78,79,84,95,96
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 6 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
Only for K7N803601B - HC13 (256Kx36)
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
** Pin 4A is reserved for address expansion to 16Mb.
1234567
AVDDQ A A NC** A A VDDQ
BNC CS2AADV ACS2NC
CNC A A VDD A A NC
DDQc DQPc VSS NC VSS DQPb DQb
EDQc DQc VSS CS1VSS DQb DQb
FVDDQ DQc VSS OE VSS DQb VDDQ
GDQc DQc BWcABWbDQb DQb
HDQc DQc VSS WE VSS DQb DQb
JVDDQ VDD NC VDD NC VDD VDDQ
KDQd DQd VSS CLK VSS DQa DQa
LDQd DQd BWdNC BWaDQa DQa
MVDDQ DQd VSS CKE VSS DQa VDDQ
NDQd DQd VSS A1*VSS DQa DQa
PDQd DQPd VSS A0*VSS DQPa DQa
RNC A LBO VDD NC ANC
TNC NC AAANC ZZ
UVDDQ TMS TDI TCK TDO NC VDDQ
PIN NAME
SYMBOL PIN NAME SYMBOL PIN NAME
A
A0,A1
ADV
WE
CLK
CKE
CS1
CS2
CS2
BWx
(x=a,b,c,d)
OE
ZZ
LBO
TCK
TMS
TDI
TDO
Address Inputs
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
VDD
VSS
N.C.
DQa
DQb
DQc
DQd
DQPa~Pd
VDDQ
Power Supply
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Output Power Supply
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 7 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
FUNCTION DESCRIPTION
The K7N803601B, K7N803201B and K7N801801B is NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround
cycle when there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven
high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must
be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipe-
lined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
BURST SEQUENCE TABLE (Interleaved Burst, LBO=High)
LBO PIN HIGH Case 1 Case 2 Case 3 Case 4
A1A0A1A0A1A0A1A0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
BQ TABLE (Linear Burst, LBO=Low)
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
LBO PIN LOW Case 1 Case 2 Case 3 Case 4
A1A0A1A0A1A0A1A0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 8 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
STATE DIAGRAM FOR NtRAMTM
BEGIN
WRITE
BURST
WRITE
BEGIN
READ
WRITE
DS
READ
BURST
READ
DS
WRITE
DS
READ
DS
READ
DS
WRITE
BURST
DESELECT
BURST
READ
BURST
WRITE
READ WRITE
BURST BURST
Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does
not change the state of the device.
2. States change on the rising edge of the clock(CLK)
COMMAND ACTION
DS DESELECT
READ BEGIN READ
WRITE BEGIN WRITE
BURST BEGIN READ
BEGIN WRITE
CONTINUE DESELECT
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 9 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
SYNCHRONOUS TRUTH TABLE
Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by (↑).
3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins(ZZ and OE).
CS1CS2CS 2ADV WE BWxOE CKE CLK ADDRESS ACCESSED OPERATION
HX X LXXX L↑N/A Not Selected
XLXLXXX L↑N/A Not Selected
X X HLXXX L↑N/A Not Selected
XXXHXXX L↑N/A Not Selected Continue
LHL L HXLL↑External Address Begin Burst Read Cycle
XXXHX X LL↑Next Address Continue Burst Read Cycle
LHL L HXHL↑External Address NOP/Dummy Read
XXXHXXHL↑Next Address Dummy Read
LHL L L L XL↑External Address Begin Burst Write Cycle
XXXHXLXL↑Next Address Continue Burst Write Cycle
LHLLLHXL↑N/A NOP/Write Abort
XXXHXHXL↑Next Address Write Abort
XXXXXXXH↑Current Address Ignore Clock
WRITE TRUTH TABLE(x36/32)
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
WE BWaBWbBW cBW dOPERATION
HXXXX READ
LLHHH WRITE BYTE a
LHLH H WRITE BYTE b
LHHLHWRITE BYTE c
LHHHLWRITE BYTE d
LLLLL WRITE ALL BYTEs
LH H H H WRITE ABORT/NOP
TRUTH TABLES
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 10 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
ASYNCHRONOUS TRUTH TABLE
Operation ZZ OE I/O STATUS
Sleep Mode HXHigh-Z
Read L L DQ
LHHigh-Z
Write LXDin, High-Z
Deselected LXHigh-Z
Notes
1. X means "Don′t Care".
2. Sleep Mode means power Sleep Mode of which stand-by current does
not depend on cycle time.
3. Deselected means power Sleep Mode of which stand-by current
depends on cycle time.
OPERATING CONDITIONS at 3.3V I/O(0°C ≤ TA ≤ 70°C)
* The above parameters are also guaranteed at industrial temperature range.
PARAMETER SYMBOL MIN Typ. MAX UNIT
Supply Voltage VDD 3.135 3.3 3.465 V
VDDQ 3.135 3.3 3.465 V
Ground VSS 000V
CAPACITANCE*(TA=25°C, f=1MHz)
*Note : Sampled not 100% tested.
PARAMETER SYMBOL TEST CONDITION MIN MAX UNIT
Input Capacitance CIN VIN=0V -5pF
Output Capacitance COUT VOUT=0V -7pF
OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C)
* The above parameters are also guaranteed at industrial temperature range.
PARAMETER SYMBOL MIN Typ. MAX UNIT
Supply Voltage VDD 3.135 3.3 3.465 V
VDDQ 2.375 2.5 2.9 V
Ground VSS 000V
ABSOLUTE MAXIMUM RATINGS*
*Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PARAMETER SYMBOL RATING UNIT
Voltage on VDD Supply Relative to VSS VDD -0.3 to 4.6 V
Voltage on Any Other Pin Relative to VSS VIN -0.3 to VDD+0.3 V
Power Dissipation PD1.6 W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature Commercial TOPR 0 to 70 °C
Industrial TOPR -40 to 85 °C
Storage Temperature Range Under Bias TBIAS -10 to 85 °C
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 11 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. Reference AC Operating Conditions and Characteristics for input and timing.
3. Data states are all zero.
4. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT NOTES
Input Leakage Current(except ZZ) IIL VDD=Max ; VIN=VSS to VDD -2 +2 µA
Output Leakage Current IOL Output Disabled, Vout=VSS to VDDQ -2 +2 µA
Operating Current ICC Device Selected, IOUT=0mA,
ZZ≤VIL , Cycle Time ≥ tCYC Min
-16 -350 mA 1,2
-13 -300
Standby Current
ISB Device deselected, IOUT=0mA, ZZ≤VIL,
f=Max, All Inputs≤0.2V or ≥ VDD-0.2V
-16 -130 mA
-13 -120
ISB1 Device deselected, IOUT=0mA, ZZ≤0.2V, f=0,
All Inputs=fixed (VDD-0.2V or 0.2V) -100 mA
ISB2 Device deselected, IOUT=0mA, ZZ≥VDD-0.2V,
f=Max, All Inputs≤VIL or ≥VIH -60 mA
Output Low Voltage(3.3V I/O) VOL IOL=8.0mA -0.4 V
Output High Voltage(3.3V I/O) VOH IOH=-4.0mA 2.4 -V
Output Low Voltage(2.5V I/O) VOL IOL=1.0mA -0.4V
Output High Voltage(2.5V I/O) VOH IOH=-1.0mA 2.0 -V
Input Low Voltage(3.3V I/O) VIL -0.3* 0.8 V
Input High Voltage(3.3V I/O) VIH 2.0 VDD+0.3** V3
Input Low Voltage(2.5V I/O) VIL -0.3* 0.7 V
Input High Voltage(2.5V I/O) VIH 1.7 VDD+0.3** V3
(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ =2.5V+0.4V/-0.125V, TA=0to70°C)
TEST CONDITIONS
* The above parameters are also guaranteed at industrial temperature range.
Parameter Value
Input Pulse Level(for 3.3V I/O) 0 to 3.0V
Input Pulse Level(for 2.5V I/O) 0 to 2.5V
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O) 1.0V/ns
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O) 1.0V/ns
Input and Output Timing Reference Levels for 3.3V I/O 1.5V
Input and Output Timing Reference Levels for 2.5V I/O VDDQ/2
Output Load See Fig. 1
VSS
VIH
VSS-1.0V
20% tCYC(MIN)
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 12 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0 to 70°C)
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
4. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
5. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC.
The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,3.465V) than tHZC, which is a Max. parameter(worst case at 70°C,3.135V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
PARAMETER SYMBOL -16 -13 UNIT
MIN MAX MIN MAX
Cycle Time tCYC 6.0 -7.5 -ns
Clock Access Time tCD -3.5 -4.2 ns
Output Enable to Data Valid tOE -3.5 -4.2 ns
Clock High to Output Low-Z tLZC 1.5 -1.5 -ns
Output Hold from Clock High tOH 1.5 -1.5 -ns
Output Enable Low to Output Low-Z tLZOE 0-0-ns
Output Enable High to Output High-Z tHZOE -3.0 -3.5 ns
Clock High to Output High-Z tHZC -3.0 -3.5 ns
Clock High Pulse Width tCH 2.2 -3.0 -ns
Clock Low Pulse Width tCL 2.2 -3.0 -ns
Address Setup to Clock High tAS 1.5 -1.5 -ns
CKE Setup to Clock High tCES 1.5 -1.5 -ns
Data Setup to Clock High tDS 1.5 -1.5 -ns
Write Setup to Clock High (WE, BWX)tWS 1.5 -1.5 -ns
Address Advance Setup to Clock High tADVS 1.5 -1.5 -ns
Chip Select Setup to Clock High tCSS 1.5 -1.5 -ns
Address Hold from Clock High tAH 0.5 -0.5 -ns
CKE Hold from Clock High tCEH 0.5 -0.5 -ns
Data Hold from Clock High tDH 0.5 -0.5 -ns
Write Hold from Clock High (WE, BWEX)tWH 0.5 -0.5 -ns
Address Advance Hold from Clock High tADVH 0.5 -0.5 -ns
Chip Select Hold from Clock High tCSH 0.5 -0.5 -ns
ZZ High to Power Down tPDS 2-2-cycle
ZZ Low to Power Up tPUS 2-2-cycle
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
353Ω / 1538Ω5pF*
+3.3V for 3.3V I/O
319Ω / 1667Ω
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Zo=50Ω
RL=50ΩVL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
/+2.5V for 2.5V I/O
30pF*
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 13 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
SLEEP MODE
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SLEEP MODE is dictated by the length of time the ZZ is in a High state.
After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z
The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP
MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-
ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given
while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS
Current during SLEEP MODE ZZ ≥ VIH ISB2 60 mA
ZZ active to input ignored tPDS 2cycle
ZZ inactive to input sampled tPUS 2cycle
ZZ active to SLEEP current tZZI 2cycle
ZZ inactive to exit SLEEP current tRZZI 0
K
tPDS
ZZ setup cycle
tRZZI
ZZ
Isupply
All inputs
(except ZZ)
Outputs
(Q)
tZZI
tPUS
ZZ recovery cycle
Deselect or Read Only
High-Z
DON′T CARE
ISB2
SLEEP MODE WAVEFORM
Normal
operation
cycle
Deselect or Read Only
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 14 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
TAP Controller State Diagram
JTAG Block Diagram
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg.
Control Signals
TAP Controller
TDO
TDI
TMS
TCK
Test Logic Reset
Run Test Idle
01 1 1
1
00
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
1
1
1
1
JTAG Instruction Coding
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
IR2 IR1 IR0 Instruction TDO Output Notes
0 0 0 EXTEST Boundary Scan Register 1
0 0 1 IDCODE Identification Register 3
0 1 0 SAMPLE-Z Boundary Scan Register 2
0 1 1 BYPASS Bypass Register 4
1 0 0 SAMPLE Boundary Scan Register 5
1 0 1 RESERVED Do Not Use 6
1 1 0 BYPASS Bypass Register 4
1 1 1 BYPASS Bypass Register 4
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 15 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
ID REGISTER DEFINITION
Part Revision Number
(31:28) Part Configuration
(27:18) Vendor Definition
(17:12) Samsung JEDEC Code
(11: 1) Start Bit(0)
256Kx36 0000 00110 00100 XXXXXX 00001001110 1
512Kx18 0000 00111 00011 XXXXXX 00001001110 1
SCAN REGISTER DEFINITION
Part Instruction Register Bypass Register ID Register Boundary Scan
256Kx36 3 bits 1 bits 32 bits 70 bits
512Kx18 3 bits 1 bits 32 bits 70 bits
119BGA BOUNDARY SCAN EXIT ORDER(x36)
36 4B ADV OE 4F 35
37 4E CS1A 4G 34
38 4H WE CLK 4K 33
39 3G BWcCKE 4M 32
40 3C ANC 4A 31
41 3B ABWb5G 30
42 3A A A 5C 29
43 2B CS2 A5B 28
44 2C A A 5A 27
45 2A ACS26B 26
46 2D DQPc A6A 25
47 1E DQc A6C 24
48 2F DQc DQPb 6D 23
49 1G DQc DQb 6E 22
50 2H DQc DQb 6G 21
51 1D DQc DQb 7H 20
52 2E DQc DQb 7D 19
53 2G DQc DQb 7E 18
54 1H DQc DQb 6F 17
55 2K DQd DQb 7G 16
56 1L DQd DQb 6H 15
57 2M DQd DQa 7K 14
58 1N DQd DQa 6L 13
59 1P DQd DQa 6N 12
60 1K DQd DQa 7P 11
61 2L DQd DQa 6K 10
62 2N DQd DQa 7L 9
63 2P DQPd DQa 6M 8
64 3R LBO DQa 7N 7
65 3L BWdDQPa 6P 6
66 2R AZZ 7T 5
67 3T A A 6R 4
68 4N A1 BWa 5L 3
69 4P A0 A5T 2
70 2T NC A4T 1
119BGA BOUNDARY SCAN EXIT ORDER(x18)
36 4B ADV OE 4F 35
37 4E CS1A 4G 34
38 4H WE CLK 4K 33
39 3G BWbCKE 4M 32
40 3C ANC 4A 31
41 3B ANC 5G 30
42 3A A A 5C 29
43 2B CS2 A5B 28
44 2C A A 5A 27
45 2A ACS26B 26
46 2D NC A6A 25
47 1E NC A6C 24
48 2F NC NC 7D 23
49 1G NC NC 6E 22
50 2H NC NC 6G 21
51 1D DQb NC 7H 20
52 2E DQb DQPa 6D 19
53 2G DQb DQa 7E 18
54 1H DQb DQa 6F 17
55 2K DQb DQa 7G 16
56 1L DQb DQa 6H 15
57 2M DQb DQa 7K 14
58 1N DQb DQa 6L 13
59 2P DQPb DQa 6N 12
60 1K NC DQa 7P 11
61 2L NC NC 6K 10
62 2N NC NC 7L 9
63 1P NC NC 6M 8
64 3R LBO NC 7N 7
65 3L NC NC 6P 6
66 2R AZZ 7T 5
67 3T A A 6R 4
68 4N A1 BWa 5L 3
69 4P A0 A5T 2
70 2T A A 6T 1
NOTE : 1. NC ; Don’t care.
2. 119BGA is Only Supported with K7N801845B-HC13, K7N803649B-HC25, K7N803601B-HC13 and K7M803625B-HC75.
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 16 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
JTAG TIMING DIAGRAM
JTAG AC Characteristics
Parameter Symbol Min Max Unit Note
TCK Cycle Time tCHCH 50 -ns
TCK High Pulse Width tCHCL 20 -ns
TCK Low Pulse Width tCLCH 20 -ns
TMS Input Setup Time tMVCH 5-ns
TMS Input Hold Time tCHMX 5-ns
TDI Input Setup Time tDVCH 5-ns
TDI Input Hold Time tCHDX 5-ns
SRAM Input Setup Time tSVCH 5-ns
SRAM Input Hold Time tCHSX 5-ns
Clock Low to Output Valid tCLQV 0 10 ns
TCK
TMS
TDI
PI
tCHCH
tMVCH tCHMX
tCHCL tCLCH
tDVCH tCHDX
tCLQV
TDO
(SRAM)
tSVCH tCHSX
JTAG DC OPERATING CONDITIONS
NOTE : The input level of SRAM pin is to follow the SRAM DC specification.
1. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
Parameter Symbol Min Typ Max Unit Note
Power Supply Voltage VDD 3.135 3.3 3.465 V
Input High Level ( 3.3V I/O / 2.5V I/O ) VIH 2.0 / 1.7 -VDD+0.3 V1
Input Low Level ( 3.3V I/O / 2.5V I/O ) VIL -0.3 -0.8 / 0.7 V
Output High Voltage ( 3.3V I/O / 2.5V I/O ) VOH 2.4 / 2.0 - - V
Output Low Voltage ( 3.3V I/O / 2.5V I/O ) VOL --0.4 / 0.4 V
JTAG AC TEST CONDITIONS
Parameter Symbol Min Unit Note
Input High/Low Level ( 3.3V I/O / 2.5V I/O ) VIH/VIL 3.0 / 0 , 2.5 / 0 V
Input Rise/Fall Time ( 3.3V I/O / 2.5V I/O ) TR/TF 1.0 / 1.0 , 1.0 /1 .0 ns
Input and Output Timing Reference Level VDDQ/2 V
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 17 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
Clock
CKE
Address
WRITE
CS
ADV
OE
Data Out
TIMING WAVEFORM OF READ CYCLE
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tCH tCL
tCES tCEH
tAS tAH
A1A2A3
tWStWH
tCSS tCSH
tOEtHZOE
tLZOE
tCD
tOHtHZC
Q3-4Q3-3Q3-2Q3-1Q2-4Q2-3Q2-2Q2-1Q1-1
Don′t Care
Undefined
tCYC
tADVS tADVH
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 18 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
TIMING WAVEFORM OF WRTE CYCLE
Clock
Address
WRITE
CS
ADV
Data In
tCH tCL
A2A3
D2-1D1-1D2-2D2-3D2-4D3-1D3-2D3-3
OE
Data Out
tDStDH
Don′t Care
Undefined
tCYC
CKE
A1
D3-4
tCES tCEH
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
Q0-4
tHZOE
Q0-3
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 19 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
TIMING WAVEFORM OF SINGLE READ/WRITE
Clock
Address
WRITE
CS
ADV
OE
Data In
tCH tCL
tDStDH
Data Out
A2A4A5
D2
tOE
tLZOE
Q1
Don′t Care
Undefined
tCYC
CKE
tCES tCEH
A1A3A7A6
Q3Q4Q7Q6
D5
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
A9
A8
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 20 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
TIMING WAVEFORM OF CKE OPERATION
Clock
Address
WRITE
CS
ADV
OE
Data In
tCH tCL
Data Out
A1A2A3A4A5
tCES tCEH
Don′t Care
Undefined
tCYC
CKE
tDStDH
D2
Q4Q1
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tCD
tLZCtHZC
Q3
A6
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 21 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
TIMING WAVEFORM OF CS OPERATION
Clock
Address
WRITE
CS
ADV
OE
Data In
tCH tCL
Data Out
A1A2A3A4A5
Don′t Care
Undefined
tCYC
CKE
D5
Q4
tCES tCEH
Q1Q2
tOE
tLZOE
D3
tCD
tLZC
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tHZC
tDHtDS
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 22 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
PACKAGE DIMENSIONS
0.10 MAX
0~8°22.00 ±0.30
20.00 ±0.20
16.00 ±0.30
14.00 ±0.20
1.40 ±0.10 1.60 MAX
0.05 MIN
(0.58)
0.50 ±0.10
#1
(0.83) 0.50 ±0.10
100-TQFP-1420A
0.65 0.30 ±0.10
0.10 MAX
+ 0.10
- 0.05
0.127
Units ; millimeters/Inches
256Kx36/x32 & 512Kx18 Pipelined NtRAMTM
- 23 - Rev 2.1
April 2003
K7N803601B
K7N801801B
K7N803201B
119BGA PACKAGE DIMENSIONS
0.750±0.15
1.27
1.27
12.50±0.10
0.60±0.10 0.60±0.10
1.50REF
C1.00 C0.70
14.00±0.10
22.00±0.10
20.50±0.10
Notes
1. All Dimensions are in Millimeters.
2. Solder Ball to PCB Offset : 0.10 MAX.
3. PCB to Cavity Offset : 0.10 MAX.
Indicator of
Ball(1A) Location
NOTE :
119BGA is Only Supported with K7N801845B-HC13, K7N803649B-HC25, K7N803601B-HC13 and K7M803625B-HC75.
