© 2006 Device Engineering Inc. Page 7 of 17 DS-MW-01016-01 Rev D
1/15/07
FIFO Buffer (continued)
The buffer data is transmitted until the last word in the buffer is
shifted out. At this time a transmitter ready signal (TXR) is set to a
logic “1” indicating that the buffer is empty and ready to receive up
to eight more data words. Writing into the buffer memory is
disabled when ENTX is set to logic “1”.
Transmitter Ready Signal (TXR)
The transmitter ready flag (TXR) is set to logic “0” with the first
occurrence of an /LD2 pulse to indicate that the buffer is not
empty.
Output Register
The output register is designed such that it can shift out a word of
25 bits or 32 bits. The length is controlled by control register bit
"WLSEL".
TX Word Gap Timer
The TX word gap timer circuit inserts a 4 bit time gap between
words. This gives a minimum requirement of a 29 bit time or a 36
bit time for each word transmission. The 4 bit time gap is also
automatically maintained when the next new block of data is
loaded into the buffer, which may take less than one bit time.
Parity Generator
The parity generator calculates either odd or even parity as
specified by control register bit "PARCK". Odd parity is normally
used; even parity is available to test the receiver parity check
circuit. Odd parity means that there is an odd number of 1's in the
25 or 32 bit serial word. Bit 8 of word one is replaced with a parity
bit if parity is selected by the control register bit "PAREN" and the
/DBCEN pin. Otherwise, bit 8 is passed through as data.
Transmitter Output
The transmitter driver outputs three TTL compatible signals: 1)
DO(A), 2) DO(B), and 3) TXCLK. DO(A) and DO(B) are the
transmitter data in two rail, return-to-zero format. DO(A) indicates
a logic "1" data bit by going to a "1" for the 1st half of a bit time,
then returning to "0" for the 2nd half; DO(B) remains at "0" for the
whole bit time. In the same fashion, DO(B) indicates a logic "0"
data bit by pulsing HI while DO(A) remains LO. A null bit is
indicated when both signals remain LO. It is illegal for both signals
to be logic "1". The TXCLK is a free running clock signal of 50%
duty cycle and in phase with transmitter data. The clock will
always be logic "1" during the first half of a bit time.
Power-Up Reset
An internal power-up reset circuit prevents erroneous data
transmission before an external master reset has been applied.
25-bit Word Operation:
The TRANSCEIVER implements a 25 bit word format which may
be used in non-ARINC applications to enhance data transfer rate.
The format is a simplified version of the 32 bit ARINC word and is
described in Figure 3. It consists of an 8 bit label, a 16 bit data
word, and a parity bit. The parity bit can optionally be replaced
with a 17th data bit. The Source/Destination code checking option
can be enabled in either receiver. It will operate on bits 9 and 10 of
the 25 bit word.
Self-Test Operation:
By selecting the control register bit (/SLFTST) self test option,
the user may perform a functional test of the TRANSCEIVER
and support circuitry. The user can write data into the
transmitter and it will be internally wrapped around into both
receivers. The user can then verify reception and integrity of
the data. The receiver line interface and the user's line drivers
will not be tested.
By setting the transmitter to use even parity, the user can test
the receiver's parity circuit operation.
Power-up reset and Master Reset:
The user must apply an active Lo pulse to the Master Reset pin
(/MR) after power up or upon system reset. Preceding the
master reset at power-up an internal power-up reset occurs
which will clear the transmitter such that no erroneous serial
data stream will be transmitted before master reset. Receivers,
control register, and internal control logic are reset by master
reset.
After resetting the device, the user must program the control
register before beginning normal operation. The control
register may be reprogrammed without additional reset pulses.
Processor Interface:
Figure 7 shows a typical reset and initialization sequence. The
user must pulse the /MR pin low to reset the device. To load
the Control Register from the data bus, the /LDCW pin is
pulsed low while the desired control data is applied on the data
bus.
Figure 5 shows a typical transmitter loading sequence. It
begins with the transmitter completing transmission of the
previous data block. The TXR flag goes HI to notify the user
that data may be loaded into the buffer. The user sets ENTX to
LO to disable the Transmitter and proceeds to load a total of
six ARINC words into the buffer. (Note that up to eight words
could have been loaded). The user then enables the transmitter
by setting ENTX to a logic "1" and the transmitter begins it's
sequence of sending out data words. Although not shown in the
figure, the transmitter loading sequence can be interrupted by
receiver reading cycle with no interference between the two
operations.
Figure 6 shows a typical receiver reading sequence. Both
receivers notify the user of valid data ready by setting their
respective /DRn lines to logic "0". The user responds by first
reading the two data words from Receiver 1 and then from
Receiver 2. The SEL line is normally a system address line and
may assume any state, but must be valid when the /OEn line is
pulsed low.