CD4066BCCW - Fairchild Semiconductor

November 1983

Revised October 2005

CD4066BC Quad Bilateral Switch

CD4066BC

Quad Bilateral Switch

General Description

The CD4066BC is a quad bilateral switch intended for the

transmission or multiplexing of analog or digital signals. It is

pin-for-pin compatible with CD4016BC, but has a much

lower “ON” resistance, and “ON” resistance is relatively

constant over the input-signal range.

Features

■Wide supply voltage range 3V to 15V

■High noise immunity 0.45 VDD (typ.)

■Wide range of digital and ±7.5 VPEAK

analog switching

■“ON” resistance for 15V operation 80Ω

■Matched “ON” resistance ∆RON = 5Ω (typ.)

over 15V signal input

■“ON” res ist an ce flat over pea k-to-peak signa l range

■High “ON”/“OFF” 65 dB (typ.)

output voltage ratio @ fis = 10 kHz, RL = 10 kΩ

■Control Line Biasi ng:

Switch On (Logic 1), VC = VDD

Switch Off (Logic 0), VC = VSS

■High degree linearity 0.1% distortion (typ.)

High degree linearity @ fis = 1 kHz, Vis = 5Vp-p,

High degre e line ari t y VDD−VSS = 10V, RL = 10 kΩ

■Extremely low “OFF” 0.1 nA (typ.)

switch leakage: @ VDD−VSS = 10V, TA = 25°C

■Extremely high control input impedance 1012Ω(typ.)

■Low crosstalk −50 dB (typ.)

between switches @ fis = 0.9 MHz, RL = 1 kΩ

■Frequency response, switch “ON” 40 MHz (typ.)

Applications

• Analog signal switching/multiplexing

• Signal gating

• Squelch control

• Chopper

• Modulator/Demodulator

• Commutating switch

• Digital signal switching/multiplexing

• CMOS logic im ple me ntat i on

• Analog-to-digital/digital-to-analog conversion

• Digital control of frequency, impedance, phase, and

analog-signal-gain

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ord ering code.

Connection Diagram Schematic Diagram

Order Number Package Number Package Description

CD4066BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

CD4066BCSJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

CD4066BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

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CD4066BC

Absolute Maximum Ratings

(Note 1)

(Note 2)

Recommended Operating

Conditions (Note 2)

Note 1: “Absolute Maximum Ratings” are those values beyond which the

safety of the device cannot be guaranteed. They are not meant to imply

that the de vices sh ould be oper ated at thes e limits. T he tables of “Recom-

mend ed Operating Condit ions” and “Electrical Characteristics” prov ide c on-

ditions f or ac t ual dev ic e operation.

Note 2: VSS = 0V unless otherwise specified.

DC Electrical Characteristics (Note 2)

Supply Voltage (VDD) −0.5V to +18V

Input Voltage (VIN) −0.5V to VCC+0.5V

Storage Temperature Range (TS) −65°C to +150°C

Power Dissipation (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperatu re (TL)

(Soldering, 10 seconds) 300°C

Supply Voltage (VDD) 3V to 15V

Input Voltage (VIN) 0V to VDD

Operating Temperature Range (TA)−55°C to +125°C

Symbol Parameter Conditions −55°C +25°C +125°CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device Current VDD = 5V 0.25 0.01 0.25 7.5 µAVDD = 10V 0.5 0.01 0.5 15

VDD = 15V 1.0 0.01 1.0 30

SIGNAL INPUTS AND OUTPUTS

RON “ON” Resistance RL = 10 kΩ to (VDD − VSS/2)

VC = VDD, VSS to VDD

VDD = 5V 800 270 1050 1300 ΩVDD = 10V 310 120 400 550

VDD = 15V 200 80 240 320

∆RON ∆“ON” Resistance Between RL = 10 kΩ to (VDD − VSS/2)

Any 2 of 4 Switches VCC = V DD, VIS = VSS to VDD

VDD = 10V 10 Ω

VDD = 15V 5

IIS Input or Output Leakage VC = 0 ±50 ±0.1 ±50 ±500 nA

Switch “OFF”

CONTROL INPUTS

VILC LOW Level Input VIS = V SS and VDD

Voltage VOS = V DD and VSS

IIS = ± 10µA

VDD = 5V 1.5 2.25 1.5 1.5 VVDD = 10V 3.0 4.5 3.0 3.0

VDD = 15V 4.0 6.75 4.0 4.0

VIHC HIGH Level Input VDD = 5V 3.5 3.5 2.75 3.5 VVoltage VDD = 10V (Note 7) 7.0 7.0 5.5 7.0

VDD = 15V 11 .0 11 .0 8.25 11 .0

IIN Input Current VDD−VSS = 15V −0.1 −10−5−0.1 −0.1 µA

VDD≥VIS≥V SS 0.1 10−50.1 0.1

VDD≥VC≥V SS

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CD4066BC

AC Electrical Characteristics (Note 3)

TA = 25°C, tr = tf = 20 ns and VSS = 0V unless otherwise noted

Note 3: AC Paramet ers are guaranteed by DC co rrelated te s tin g.

Note 4: These devices should not be connected to circuits with the power “ON”.

Note 5: In all cases, there is ap proximately 5 pF of probe and jig c apacitance in th e output; how ever, this capaci ta nce is inc luded in CL wherever it is

specified.

Note 6: VIS is the voltage at th e in/out pin and VOS is the voltage at the out/in pin. VC is the voltage at the control input.

Note 7: Conditions for VIHC: a) VIS = VDD, IOS = standar d B s eries IOH b) VIS = 0V, IOL = standard B series IOL.

Symbol Parameter Conditions Min Typ Max Units

tPHL, tPLH Propagation Delay Time Signal VC = VDD, CL = 50 pF, (Figure 1)

Input to Signal Output RL = 200k

VDD = 5V 25 55 ns

VDD = 10V 15 35 ns

VDD = 15V 10 25 ns

tPZH, tPZL Propagation Delay Time RL = 1.0 kΩ, CL = 50 pF, (Figure 2, Figure 3)

Control Input to Signal VDD = 5V 125 ns

Output High Impedance to VDD = 10V 60 ns

Logical Level VDD = 15V 50 ns

tPHZ, tPLZ Propagation Delay Time RL = 1.0 kΩ, CL = 50 pF, (Figure 2, Figure 3)

Control Input to Signal VDD = 5V 125 ns

Output Logical Level to VDD = 10V 60 ns

High Impedance VDD = 15V 50 ns

Sine Wave Distortion VC = VDD = 5V, VSS = −5V 0.1 %

RL = 10 kΩ, VIS = 5Vp-p, f= 1 kHz, (Figure 4)

Frequency Response-Switch VC = VDD = 5V, VSS = −5V, 40 MHz

“ON” (Frequency at −3 dB) RL = 1 kΩ, VIS = 5Vp-p,

20 Log10 VOS/VOS (1 kHz)−dB,

(Figure 4)

Feedthrough — Switch “OFF” VDD = 5.0V, VCC = VSS = −5.0V, 1.25

(Frequency at −50 dB) RL = 1 kΩ, VIS = 5.0Vp-p, 20 Log10,

VOS/VIS = −50 dB, (Figure 4)

Crosstalk Between Any Two VDD = VC(A) = 5.0V; VSS = VC(B) = 5.0V, 0.9 MHz

Switches (Frequency at −50 dB) RL1 kΩ, VIS(A) = 5.0 Vp-p, 20 Log10,

VOS(B)/VIS(A) = −50 dB (Figure 5)

Crosstalk; Control Input to VDD = 10V, RL = 10 kΩ, RIN = 1.0 kΩ, 150 mV

p-p

Signal Output VCC = 10V Square Wave, CL = 50 pF

(Figure 6)

Maximum Control Input RL = 1.0 kΩ, CL = 50 pF, (Figure 7)

VOS(f) = ½ VOS(1.0 kHz)

VDD = 5.0V 6.0 MHz

VDD = 10V 8.0 MHz

VDD = 15V 8.5 MHz

CIS Signal Input Capacitance 8.0 pF

COS Signal Output Capacitance VDD = 10V 8.0 pF

CIOS Feedthrough Capacitance VC = 0V 0.5 pF

CIN Control Input Capacitance 5.0 7.5 pF

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CD4066BC

Typical Performance Characteristics

“ON” Resi st an ce vs Sign al

Voltage for TA = 25°C“ON” Resistance as a Function

of Temperatur e for

VDD−VSS = 15V

“ON” Resistance as a Function

of Temperature for

VDD−VSS = 10V

“ON” Resistance as a Function

of Temperatur e for

VDD−VSS = 5V

Special Considerations

In appl ication s where sep arate pow er sources are us ed to

drive VDD and the signal input, the VDD current capability

should exceed VDD/RL (RL = effective external load of the 4

CD4066BC bilateral switches). This provision avoids any

permanent current flow or clamp action of the VDD supply

when power is applied or removed from CD4066BC.

In certain applications, the external load-resistor current

may include both VDD and signal-line components. To

avoid drawing VDD current when switch current flows into

terminals 1, 4, 8 or 11, the voltage drop across the

bidirect ional switch mu st not exceed 0 .6V at TA ≤ 25°C, or

0.4V at TA > 25°C (calculated from RON values shown).

No VDD current will flow through RL if the switch current

flows into terminals 2, 3, 9 or 10.

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CD4066BC

AC Test Circuits and Switching Time Waveforms

FIGURE 1. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output

FIGURE 2. tPZH, tPHZ Propagation Dela y Time Control to Signal Output

FIGURE 3. tPZL, tPLZ Propagation Delay Time Control to Signal Output

VC = VDD for distort ion and f requency res ponse te s t s

VC = VSS for feedthrough test

FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthroug h

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CD4066BC

AC Test Circuits and Switching Time Waveforms (Co ntinu ed )

FIGURE 5. Crosstalk Between Any Two Switches

FIGURE 6. Crosstalk: Control Input to Signal Output

FIGURE 7. Maximum Control Input Freque ncy

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CD4066BC

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

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CD4066BC

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

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CD4066BC Quad Bilateral Switch

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does not assume an y responsibility for u se of any circuitry descr ibed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

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which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.