PCS3PS550AG-08CR - ON Semiconductor L.L.C.

July, 2010 − Rev. 1

1Publication Order Number:

PCS3PS550A/D

PCS3PS550A

General Purpose Peak EMI

Reduction IC

Product Description

The PCS3PS550A is a versatile 2.3 V to 3.6 V, Timing−Safe™,

spectrum frequency modulator designed specifically for a wide range

of clock frequencies. The PCS3PS550A reduces electromagnetic

interference (EMI) at the clock source, allowing system wide

reduction of EMI of all clock dependent signals. The PCS3PS550A

allows significant system cost savings by reducing the number of

circuit board layers ferrite beads, shielding that are traditionally

required to pass EMI regulations.

Features

•LVCMOS Peak EMI reduction IC

•Input Clock Frequency: 18 MHz − 36 MHz

•Output Clock Frequency: 18 MHz − 36 MHz

•Eight different selectable Spread options

•Power Down option for power save

•Supply Voltage: 2.3 V − 3.6 V

•8−pin WDFN , 2 mm x 2 mm (TDFN) Package

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Applications

•The PCS3PS550A is targeted towards consumer electronic

applications.

WDFN8

CASE 511AQ

MARKING

DIAGRAMS

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PIN CONFIGURATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

SR2

SR1

SR0

PD#

VSS ModOUT

CLKIN

PCS3PS550A

VDD

1CAMG

CA = Specific Device Code

M = Date Code

G= Pb−Free Device

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VSS

VDD

CLKIN ModOUT

PLL

SR0 SR1 SR2

PD#

Figure 1. Block Diagram

PCS3PS550A modulates the output of a single PLL in

order to “spread” the bandwidth of a synthesized clock, and

more importantly, decreases the peak amplitudes of its

harmonics. This results in significantly lower system EMI

compared to the typical narrow band signal produced by

oscillators and most frequency generators. Lowering EMI

by increasing a signal’s bandwidth is called ‘spread

spectrum clock generation’.

PCS3PS550A accepts an input from an external reference

clock and locks to a 1x modulated clock output. SR0, SR1

and SR2 pins enable selecting one of the eight different

frequency deviations (Refer Frequency Deviation Selection

table). PCS3PS550A also features power down option for

power save. PCS3PS550A operates over a supply voltage

range of 2.3 V to 3.6 V. PCS3PS550A is available in an 8 Pin

WDFN, (2 mm x 2 mm) Package.

Table 1. PIN DESCRIPTION

Pin# Pin Name Type Description

1 CLKIN I External reference clock input.

2 SR2 I Digital logic input used to select Spreading Range. There is NO default state.

Refer Frequency Deviation Selection Table.

3 PD# I Power−down control pin. Powers down the entire chip. There is NO default state. Pull low to

enable power−down mode. Connect to VDD to disable Power Down.

Output Clock will be LOW when power down is enabled

4 VSS P Ground connection.

5 ModOUT O Spread Spectrum Clock Output.

6 SR1 I Digital logic input used to select Spreading Range. This pin has an internal pull−up resistor.

Refer Modulation Selection Table.

7 SR0 I Digital logic input used to select Spreading Range. There is NO default state.

Refer Frequency Deviation Selection Table.

8 VDD P Power supply for the entire chip

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Table 2. FREQUENCY DEVIATION SELECTION TABLE

SR2 SR1 SR0

Spreading Range

($%) (@ 24 MHz)

0 0 0 1

0 0 1 2.5

0 1 0 1.25

0 1 1 1.5

1 0 0 0.4

1 0 1 0.75

1 1 0 1.75

1 1 1 2

Table 3. OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VDD Supply Voltage with respect to VSS 2.3 3.6 V

TAOperating temperature −20 +85 °C

CLLoad Capacitance 15 pF

CIN Input Capacitance 7 pF

Table 4. ABSOLUTE MAXIMUM RATING

Symbol Parameter Rating Unit

VDD, VIN Voltage on any input pin with respect to VSS −0.5 to +4.6 V

TSTG Storage temperature −65 to +125 °C

TAOperating temperature −40 to +85 °C

TsMax. Soldering Temperature (10 sec) 260 °C

TJJunction Temperature 150 °C

TDV Static Discharge Voltage (As per JEDEC STD22−A114−B) 2 kV

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may

affect device reliability.

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Table 5. DC ELECTRICAL CHARACTERISTICS

Symbol Parameter Min Typ Max Unit

VDD Supply Voltage with respect to VSS 2.3 2.8 3.6 V

VIH Input high voltage 0.65 * VDD V

VIL Input low voltage 0.3 * VDD V

IIH Input high current (SR1 control pin) 50 mA

IIL Input low current (SR1 control pin) 50 mA

VOH Output high voltage (IOH = −8 mA) 0.75 * VDD V

VOL Output low voltage (IOL = 8 mA) 0.2 * VDD V

ICC Static supply current (PD# pulled to VSS) 1 mA

IDD Dynamic supply current (Unloaded Output @ 24 MHz) 6 9 mA

ZOUT Output impedance 40 W

Table 6. AC ELECTRICAL CHARACTERISTICS

Symbol Parameter Min Typ Max Unit

CLKIN Input Clock frequency 18 24 36 MHz

ModOUT Output Clock frequency 18 24 36 MHz

tLH (Note 1) Output rise time

(Measured between 20% to 80%)

Unloaded Output 0.8 1.2 ns

CL = 15 pF 2.4 3

tHL (Note 1) Output fall time

(Measured between 80% to 20%)

Unloaded Output 0.6 1 ns

CL = 15 pF 1.9 2.8

tJC (Note 1) Jitter (cycle to cycle) Unloaded Output $175 $250 ps

tD (Note 1) Output duty cycle 45 50 55 %

tON (Note 1) PLL lock Time (Stable power supply, valid clock presented on

CLKIN pin, PD# toggled from Low to High)

3 ms

fdvar Frequency Deviation Variation across PVT $2.5 $5 %

1. Parameter is guaranteed by design and characterization. Not 100% tested in production

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NOTE: Refer Pin Description table for Functionality details.

CLKIN

VSS

VDD

2.2mF

ModOUT ModOUT Clock

PCS3PS550A

SR2, SR1, SR0

Frequency Deviation

Selection Control

VDD

0 W

0.1mF

M Clock

0 W

VDD

PD#

SR2/SR1/SR0 Power Down

Control

VDDIN

Figure 2. Typical Application Schematic

2,6,7

PCB Layout Recommendation

For optimum device performance, following guidelines are recommended.

•Dedicated VDD and GND planes.

•The device must be isolated from system power supply noise. A 0.1mF and a 2.2 mF decoupling capacitor should be

mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the

decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as possible.

All the VDD pins should have decoupling capacitors.

•In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers.

A typical layout is shown in the figure

As short as

possible

VDD

GND

CLKIN

PD#

SR0

SR2

Modout

VSS

SR1

As short as

possible

Figure 3.

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ORDERING INFORMATION

Part Number Top Marking Temperature Package Type Shipping†

PCS3PS550AG−08CR CA −20°C to +85°C8L− WDFN(TDFN)

(Pb−Free)

Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−Free.

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PACKAGE DIMENSIONS

WDFN8 2x2, 0.5P

CASE 511AQ−01

ISSUE A

ÍÍÍ

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30mm FROM TERMINAL.

SEATING

PLANE

0.10 C

DIM

MIN

MILLIMETERS

0.70

A1 0.00

A3 0.20 REF

b0.20

D2.00 BSC

E2.00 BSC

e0.50 BSC

PIN ONE

REFERENCE

0.05 C

A0.10 C

NOTE 3

0.05 C

0.50

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

2.30

0.50

0.78

DIMENSIONS: MILLIMETERS

BOTTOM VIEW

0.35 PITCH

0.80

0.05

0.30

0.60

MAX

DETAIL A

OPTIONAL

CONSTRUCTIONS

ÉÉ

DETAIL B

MOLD CMPDEXPOSED Cu

OPTIONAL

CONSTRUCTION

---

L1 0.15

TOP VIEW

SIDE VIEW

e/2 1

PACKAGE

OUTLINE

DETAIL B

DETAIL A

RECOMMENDED

0.88

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PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

PCS3PS550A/D

Timing−Safe is a trademark of Semiconductor Components Industries, LLC (SCILLC).

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