MM54HC00/MM74HCO0O Quad 2-Input NAND Gate General Description These NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs. All de- vices have high noise immunity and the ability to drive 10 LS-TTL loads. The 54HC/74HC logic family is functionally as well as pin-out compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to Vcc and ground. (AV vational Semiconductor January 1988 Features @ Typical propagation delay: 8 ns m@ Wide power supply range: 2-6V m Low quiescent current: 20 wA maximum (74HC Series) @ Low input current: 1 2A maximum @ Fanout of 10 LS-TTL loads Connection and Logic Diagrams Dual-In-Line Package vec Ba A4 4 83 A3 3 [a 13 12 11 10 9 8 1 2 3 4 5 6 | Al B1 v1 A2 B2 Y2 GND TL/F/5292-1 Top View Order Number MM54HCO0 or MM74HC00 3 B yof>of>o TL/F/5292-2 1995 National Semiconductor Corporation TL/F/5292 RRD-B30M105/Printed in U.S. A. 375 GNVWN iNdul-z pend OOOHPZININ/OOOHPSINN Absolute Maximum Ratings (notes 1 a 2) Operating Conditions If Military/Aerospace specified devices are required, Min Max Units please contact the National Semiconductor Sales Supply Voltage (Vcc) 2 6 Vv Office/Distributors for availability and specifications. DC Input or Output Voltage 0 Voc V Supply Voltage (Vcc) 0.5 to +7.0V (Vins Vout) C Input Voltage (V 1.5 10 Voc + 1.5V , bc Out tv ta 0 : to Vect 0 ey Operating Temp. Range (Ta) uiput Voltage (Vour) TU 10 Voo* 0. MM74HG 40 +85 C Clamp Diode Current (lik, lox) +20mA MM54HC 55 4125 C DC Output Current, per pin (lour) +25mA Input Rise or Fall Times DC Vcc or GND Current, per pin (loc) +50 mA (ist) = Voc=2V 4000 ns Storage Temperature Range (Tstq) 65C to + 150C Voc =4.5V 500 ns Power Dissipation (Pp) Voc =6.0V 400 ns (Note 3) 600 mw S.O. Package only 500 mw Lead Temperature (T,) (Soldering 10 seconds) 260C DC Electrical Characteristics (note 4) 74HC 54HC Ta=25C Symbol Parameter Conditions Voc Ta= 40 to 85C | Ta= 55 to 125C | Units Typ Guaranteed Limits Vi Minimum High Level 2.0V 1.5 1.5 1.5 Vv Input Voltage 4.5V 3.15 3.15 3.15 Vv 6.0V 4.2 4.2 4.2 Vv Vit Maximum Low Level 2.0V 0.5 0.5 0.5 Vv Input Voltage** 4.5V 1.35 1.35 1.35 Vv 6.0V 1.8 1.8 1.8 v VoH Minimum High Level | Vin=Vin Or Vit Output Voltage llout| <20 pA 20V}] 20 | 1.9 1.9 1.9 v 45V ) 45 4.4 4.4 4.4 Vv 6.0V | 6.0 5.9 5.9 5.9 V Vin= Vin OF Vit llout| <4.0 mA 4.5V | 4.2 | 3.98 3.84 3.7 v lloyt| <5.2 mA 6.0V | 5.7 | 5.48 5.34 5.2 v VoL Maximum Low Level | Vin=Vin Output Voltage llout| <20 pA 2.0V| 0 0.1 0.1 0.1 Vv 4.5V 0 01 0.1 0.41 v 6.0V 0 0.1 0.1 0.1 V Vin=VIH llout| <4.0 mA 4.5V | 0.2 | 0.26 0.33 0.4 Vv llourl <5.2 mA 6.0V | 0.2 | 0.26 0.33 0.4 v lin Maximum Input Vin=Vcc or GND | 6.0V +01 +1.0 +1.0 pA Current loc Maximum Quiescent | Vin=Vcc or GND | 6.0V 2.0 20 40 pA Supply Current louT=0 pA Note 1; Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating plastic N package: 12 mW/C from 65C to 85C; ceramic J package: 12 mW/C from 100C to 125C, Note 4: For a power supply of 5V +10% the worst case output voltages (Voy, and Vo.) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case Vi} and Vi, occur at Voc = 5.5V and 4.5V respectively. (The V4 value at 5.5V is 3.85V.) The worst case leakage current (lin, loc, and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used. **Viz limits are currently tested at 20% of Voc. The above Vi_ specification (30% of Voc) will be implemented no later than Q1, CY89. AC Electrical Characteristics v..=sv, T,= 25C, C, =15 pF, ,=1;=6 ns Delay Symbol Parameter Conditions Typ oe Units TPHL: tPLH Maximum Propagation 8 15 ns AC Electrical Characteristics voc =2.0v to 6.0v, C, =50 pF, t=} =6 ns (unless otherwise specified) Ta= 25C 74HC 54HC Symbol Parameter Conditions | Vcc A Ta=40 to 85C | Ta=55to 125C | Units Typ Guaranteed Limits tPpHL. tpLH | Maximum Propagation 2.0V 45 90 113 134 ns Delay 4.5V 9 18 23 27 ns 6.0V 8 15 19 23 ns tro. tTHL | Maximum Output Rise 2.0V 30 75 95 110 ns and Fall Time 4.5V 8 15 19 22 ns 6.0V 7 13 16 19 ns Cpp Power Dissipation (per gate) 20 pF Capacitance (Note 5) Cin Maximum Input 5 10 10 10 pF Capacitance Note 5: Cpp determines the no load dynamic power consumption, Pp = Cpp Voc? f+ loc Voc, and the no load dynamic current consumption, Is =Cpp Vcc f+ loc. MM54HC00/MM74HC00 Quad 2-Input NAND Gate Physical Dimensions inches (milimeters) 0.785 (19.938) = MAX 01.028 _ (0638) 0.220-0.310 (5.5887.874) 0,290-0.320 0.005 0.200 {7.366-8.128) (027) GLASS 0.060 +0.005 (5.080) ee _. | SEALANT (71.524 =0.127) MAX qnonn.o60 0.190 t | (0.508-1.524) (4.572) =a 4 f aeoa tye ; ra 10 MAX 0.008-0.012 | 0,310-0.410 (0.203-D.305) | | p.018 #0,003 (7.874-10.41) 0.088 | LL | (0.457 20, we | oie 0200 2.489) meray (3.175-5.080) MAX BOTH ENDS 0.100 +0.010 ago ~~ 17 RAD (D254) (2.540 (0.254) aan MIN 2148 (REV G; Cavity Dual-in Line Package (J) Order Number MM54HCO0J or MM74HCOOJ NS Package J14A 0.7400.770 * (18.8019.56) 0.090. i Te za6) [4 {e) fo) [e1 1! INOEK_ AREA ~~ 0.2502 0.010 O GC {6.350+0.254) PINNO. 1 RE PINNO.1 IDENT BI LI Tal 14] ey 167 LJ IDENT 0.092 pj, 0.000 max _/ (2.337) (0.762) DEPTH OPTION 1 OPTION D2 0.135= 0.005 0.3009.320 @az9t0.127) acco (7.6208.128) 0.085 9.145 0.200 >| <a eee Tey (3.683 5.080) (1.524) \ OPTIONAL L tl Y | t k 4 wee _ 0.008 =0.018 typ at | 90 +4 Te la -* ine {0-203 0.406) (0.508) T MIN. 0.1250.150 | toy o.07s 20.015 @i7saa10) |! | io08=0.381) a> 0.0140.023 ae Typ >| 0.356 0.504 H 0,100 + 0.010 MIN ' | 4 wore 10 i 5ato25H +| le i tan? 0.2 Ns (028 ya) Nig isey FL Molded Dual-In Line Package (N) Order Number MM74HCOON NS Package N14A LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (6) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. 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