ISP1506BBS-T - NXP Semiconductors / Philips Semiconductors

34.807IRELESS

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34.807IRELESS

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1. General description

The ISP1506 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully

compliant with Ref. 1 “Universal Serial Bus Speciﬁcation Rev. 2.0”,Ref. 2 “On-The-Go

Supplement to the USB 2.0 Speciﬁcation Rev. 1.3” and Ref. 3 “UTMI+ Low Pin Interface

(ULPI) Speciﬁcation Rev. 1.1”.

The ISP1506 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed

(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer

front-end attachment to USB host, peripheral and OTG devices.

It is ideal for use in portable electronic devices, such as mobile phones, digital still

cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio

players. It allows USB Application-Speciﬁc Integrated Circuits (ASICs), Programmable

Logic Devices (PLDs) and any system chip set to interface with the physical layer of the

USB through an 8-pin interface.

The ISP1506 can interface to devices with digital I/O voltages in the range of 1.65 V to

1.95 V.

The ISP1506 is available in HVQFN24 package.

2. Features

nFully complies with:

uRef. 1 “Universal Serial Bus Speciﬁcation Rev. 2.0”

uRef. 2 “On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.3”

uRef. 3 “UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1”

nInterfaces to host, peripheral and OTG device cores; optimized for portable devices or

system ASICs with built-in USB OTG device core

nComplete Hi-Speed USB physical front-end solution that supports high-speed

(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)

uIntegrated 45 Ω±10 % high-speed termination resistors, 1.5 kΩ±5 % full-speed

device pull-up resistor, and 15 kΩ±5 % host termination resistors

uIntegrated parallel-to-serial and serial-to-parallel converters to transmit and receive

uUSB clock and data recovery to receive USB data up to ±500 ppm

uInsertion of stuff bits during transmit and discarding of stuff bits during receive

uNon-Return-to-Zero Inverted (NRZI) encoding and decoding

uSupports bus reset, suspend, resume and high-speed detection handshake (chirp)

nComplete USB OTG physical front-end that supports Host Negotiation Protocol (HNP)

and Session Request Protocol (SRP)

ISP1506A; ISP1506B

ULPI Hi-Speed USB OTG transceiver

Rev. 02 — 28 August 2008 Product data sheet

Product data sheet Rev. 02 — 28 August 2008 2 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

uIntegrated 5 V charge pump; also supports external charge pump or 5 V VBUS

switch

uComplete control over bus resistors

uData line and VBUS pulsing session request methods

uIntegrated VBUS voltage comparators

uIntegrated cable (ID) detector

nHighly optimized ULPI compliant

u60 MHz, 8-bit interface between the core and the transceiver

uSupports 4-bit dual-edge data bus

uSupports 60 MHz output clock conﬁguration

uIntegrated Phase-Locked Loop (PLL), supporting one crystal or clock frequency:

19.2 MHz (ISP1506ABS) and 26 MHz (ISP1506BBS)

uFully programmable ULPI-compliant register set

uInternal Power-On Reset (POR) circuit

nFlexible system integration and very low current consumption, optimized for portable

devices

uPower-supply input range is 3.0 V to 3.6 V

uInternal voltage regulator supplies 3.3 V and 1.8 V

uCharge pump regulator outputs 4.75 V to 5.25 V at a current of up to 50 mA,

tunable using an external capacitor

uSupports interfacing I/O voltage of 1.65 V to 1.95 V; separate I/O voltage pins

minimize crosstalk

uTypical operating current of 10 mA to 48 mA, depending on the USB speed and

bus utilization; not including the charge pump

uTypical suspend current of 35 µA

nFull industrial grade operating temperature range from −40 °C to +85 °C

n4 kV ElectroStatic Discharge (ESD) protection at pins DP, DM, ID, VBUS and GND

nAvailable in a small HVQFN24 (4 mm ×4 mm) Restriction of Hazardous Substances

(RoHS) compliant, halogen-free and lead-free package

3. Applications

nDigital still camera

nDigital TV

nDigital Video Disc (DVD) recorder

nExternal storage device, for example:

uMagneto-Optical (MO) drive

uOptical drive: CD-ROM, CD-RW, DVD

uZip drive

nMobile phone

nMP3 player

nPDA

nPortable Media Player (PMP)

nPrinter

nScanner

Product data sheet Rev. 02 — 28 August 2008 3 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

nSet-Top Box (STB)

nVideo camera

4. Ordering information

[1] The package marking is the ﬁrst line of text on the IC package and can be used for IC identiﬁcation.

Table 1. Ordering information

Part Package

Type number Marking Crystal or

clock

frequency

Name Description Version

ISP1506ABS 06A[1] 19.2 MHz HVQFN24 plastic thermal enhanced very thin quad ﬂat package;

no leads; 24 terminals; body 4 ×4×0.85 mm SOT616-1

ISP1506BBS 06B[1] 26 MHz HVQFN24 plastic thermal enhanced very thin quad ﬂat package;

no leads; 24 terminals; body 4 ×4×0.85 mm SOT616-1

Product data sheet Rev. 02 — 28 August 2008 4 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

5. Block diagram

Fig 1. Block diagram

MAP

ULPI

INTERFACE

CONTROLLER

USB DATA

SERIALIZER

USB DATA

DESERIALIZER

HS USB ATX

STP

DIR

NXT

DATA[3:0] 4

20, 22,

23, 24

004aaa598

CLOCK 19

TERMINATION

RESISTORS

DETECTOR

VBUS

COMPARATORS

OTG MODULE

SRP CHARGE

AND DISCHARGE

RESISTORS

5 V CHARGE

PUMP SUPPLY

POWER-ON

RESET

PLL

CRYSTAL

OSCILLATOR

VOLTAGE

REGULATOR

BAND GAP

REFERENCE

VOLTAGE RREF

internal power

VCC 9

REG3V3

REG1V8

RESET_N/

PSW_N global

reset

global

clocks

XTAL2

XTAL1 12

VCC(I/O) 1, 21 interface voltage

DRV VBUS

VBUS/

FAULT

CPGND

8C_A

C_B

ISP1506

ULPI

INTERFACE

USB

CABLE

VREF

DRV VBUS external

VBUS valid external

Product data sheet Rev. 02 — 28 August 2008 5 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 2. Pin conﬁguration HVQFN24; top view

004aaa599

ISP1506

Transparent top view

XTAL2

CPGND

RESET_N/PSW_N

DP REG1V8

DM DIR

RREF STP

VCC(I/O) NXT

C_B

C_A

VCC

VBUS/FAULT

REG3V3

XTAL1

DATA0

DATA1

DATA2

VCC(I/O)

DATA3

CLOCK

terminal 1

index area

613

514

4 15

3 16

2 17

118

Table 2. Pin description

Symbol[1][2][3] Pin Type[4] Description

VCC(I/O) 1 P I/O supply rail

RREF 2 AI/O resistor reference

DM 3 AI/O data minus (D−) pin of the USB cable

DP 4 AI/O data plus (D+) pin of the USB cable

ID 5 I identiﬁcation (ID) pin of the micro-USB cable

If this pin is not used, it is recommended to connect it to REG3V3.

plain input; TTL level

CPGND 6 P charge pump ground

C_B 7 AI/O ﬂying capacitor pin connection for the charge pump

C_A 8 AI/O ﬂying capacitor pin connection for the charge pump

VCC 9 P input supply voltage or battery source

VBUS/FAULT 10 AI/O This pin has two possible functions:

VBUS (analog input and output) — VBUS pin of the USB cable

FAULT (input) — Input pin for the external VBUS digital overcurrent or fault detector

signal

If this pin is not used as either VBUS or FAULT, it must be connected to ground.

plain input; 5 V tolerant

REG3V3 11 P 3.3 V regulator output

XTAL1 12 AI crystal oscillator or clock input

XTAL2 13 AO crystal oscillator output

Product data sheet Rev. 02 — 28 August 2008 6 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

[1] A detailed description of these pins can be found in Section 7.9.

[2] Symbol names ending with an underscore N (for example, NAME_N) indicate active LOW signals.

[3] For details on external components required on each pin, see bill of materials and application diagrams in Section 16.

[4] I = input; O = output; I/O = digital input/output; AI = analog input; AO = analog output; AI/O = analog input/output; P = power or ground

pin.

RESET_N/

PSW_N 14 I/O This pin has two possible functions:

RESET_N (input) — Active LOW asynchronous reset input

3.3 V tolerant; plain input

PSW_N (output) — Active LOW external VBUS power switch or external charge pump

enable

open-drain; 3.3 V tolerant

If not used, this pin must be connected to VCC(I/O).

REG1V8 15 P 1.8 V regulator output

DIR 16 O ULPI direction signal

slew-rate controlled output (1 ns)

STP 17 I ULPI stop signal

plain input; programmable pull up

NXT 18 O ULPI next signal

slew-rate controlled output (1 ns)

CLOCK 19 O 60 MHz clock output

2 mA output drive

DATA3 20 I/O pin 3 of the bidirectional ULPI data bus

2 mA output drive; plain input; programmable pull down

VCC(I/O) 21 P I/O supply rail

DATA2 22 I/O pin 2 of the bidirectional ULPI data bus

2 mA output drive; plain input; programmable pull down

DATA1 23 I/O pin 1 of the bidirectional ULPI data bus

2 mA output drive; plain input; programmable pull down

DATA0 24 I/O pin 0 of the bidirectional ULPI data bus

2 mA output drive; plain input; programmable pull down

GND die

pad P ground supply; down bonded to the exposed die pad (heat sink); to be connected to the

PCB ground

Table 2. Pin description

…continued

Symbol[1][2][3] Pin Type[4] Description

Product data sheet Rev. 02 — 28 August 2008 7 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

7. Functional description

7.1 ULPI interface controller

The ISP1506 provides an 8-pin interface that is compliant with Ref. 3 “UTMI+ Low Pin

Interface (ULPI) Speciﬁcation Rev. 1.1”. This interface must be connected to the USB link.

The ULPI interface controller provides the following functions:

•ULPI compliant and register set

•Allows full control over the USB peripheral, host and OTG functionality

•Parses the USB transmit and receive data

•Prioritizes the USB receive data, USB transmit data, interrupts and register operations

•Control of the VBUS charge pump or external source

•VBUS monitoring, charging and discharging

•Low-power mode

•3-pin serial mode

•Generates RXCMDs (status updates)

•Maskable interrupts

•Control over the ULPI bus state; can attach weak pull-down resistors to DATA[3:0]

For more information on the ULPI protocol, see Section 9.

7.2 USB data serializer and deserializer

The USB data serializer prepares data to transmit on the USB bus. To transmit data, the

USB link sends a transmit command and data on the ULPI bus. The serializer performs

parallel-to-serial conversion, bit stufﬁng and NRZI encoding. For packets with a PID, the

serializer adds a SYNC pattern to the start of the packet, and an EOP pattern to the end

of the packet. When the serializer is busy and cannot accept any more data, the ULPI

interface controller deasserts NXT.

The USB data deserializer decodes data received from the USB bus. When data is

received, the deserializer strips the SYNC and EOP patterns, and then performs

serial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the data

payload. The ULPI interface controller sends data to the USB link by asserting DIR, and

then asserting NXT whenever a byte is ready. The deserializer also detects various

receive errors, including bit stuff errors, elasticity buffer underrun or overrun, and

byte-alignment errors.

7.3 Hi-Speed USB (USB 2.0) ATX

The Hi-Speed USB ATX block is an analog front-end containing the circuitry needed to

transmit, receive and terminate the USB bus in high-speed, full-speed and low-speed, for

USB peripheral, host and OTG implementations. The following circuitry is included:

•Differential drivers to transmit data at high-speed, full-speed and low-speed

•Differential and single-ended receivers to receive data at high-speed, full-speed and

low-speed

Product data sheet Rev. 02 — 28 August 2008 8 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

•Squelch circuit to detect high-speed bus activity

•High-speed disconnect detector

•45 Ω high-speed bus terminations on DP and DM for peripheral and host modes

•1.5 kΩ pull-up resistor on DP for full-speed peripheral mode

•15 kΩ bus terminations on DP and DM for host and OTG modes

For details on controlling resistor settings, see Table 7.

7.4 Voltage regulator

The ISP1506 contains a built-in voltage regulator that conditions the VCC supply for use

inside the ISP1506. The voltage regulator:

•Supports input supply range of 3.0V<V

CC < 3.6 V

•Supplies internal circuitry with 1.8 V and 3.3 V

Remark: The REG1V8 and REG3V3 pins require external decoupling capacitors. For

details, see Section 16.

7.5 Crystal oscillator and PLL

The ISP1506 has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock

generation.

The crystal oscillator takes a sine-wave input from an external crystal, on the XTAL1 pin,

and converts it to a square wave clock for internal use. Alternatively, a square wave clock

of the same frequency can also be directly driven into the XTAL1 pin. Using an existing

square wave clock can save the cost of the crystal and also reduce the board size.

The PLL takes the square wave clock from the crystal oscillator, and multiplies or divides it

into various frequencies for internal use.

The PLL produces the following frequencies, irrespective of the clock source:

•60 MHz clock for the ULPI interface controller

•1.5 MHz for the low-speed USB data

•12 MHz for the full-speed USB data

•480 MHz for the high-speed USB data

•Other internal frequencies for data conversion and data recovery

7.6 OTG module

This module contains several sub-blocks that provide all the functionality required by the

USB OTG speciﬁcation. Speciﬁcally, it provides the following circuits:

•The ID detector to sense the ID pin of the micro-USB cable. The ID pin dictates which

device is initially conﬁgured as the host and which as the peripheral.

•VBUS comparators to determine the VBUS voltage level. This is required for the VBUS

detection, SRP and HNP.

•Resistors to temporarily charge and discharge VBUS. This is required for SRP.

Product data sheet Rev. 02 — 28 August 2008 9 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

•Charge pump to provide 5 V power on VBUS. The downstream peripheral can draw its

power from the ISP1506 VBUS.

7.6.1 ID detector

The ID detector detects which end of the micro-USB cable is plugged in. The detector

must ﬁrst be enabled by setting the ID_PULLUP register bit to logic 1. If the ISP1506

senses a value on ID that is different from the previously reported value, an RXCMD

status update will be sent to the USB link, or an interrupt will be asserted.

•If the micro-B end of the cable is plugged in, the ISP1506 will report that ID_GND is

logic 1. The USB link must change to peripheral mode.

•If the micro-A end of the cable is plugged in, the ISP1506 will report that ID_GND is

logic 0. The USB link must change to host mode.

7.6.2 VBUS comparators

The ISP1506 provides three comparators, VBUS valid comparator, session valid

comparator and session end comparator, to detect the VBUS voltage level.

7.6.2.1 VBUS valid comparator

This comparator is used by hosts and A-devices to determine whether the voltage on

VBUS is at a valid level for operation. The ISP1506 minimum threshold for the VBUS valid

comparator is VA_VBUS_VLD. Any voltage on VBUS below VA_VBUS_VLD is considered invalid.

During power-up, it is expected that the comparator output will be ignored.

7.6.2.2 Session valid comparator

The session valid comparator is a TTL-level input that determines when VBUS is high

enough for a session to start. Peripherals, A-devices and B-devices use this comparator to

detect when a session is started. The A-device also uses this comparator to determine

when a session is completed. The session valid threshold of the ISP1506 is VB_SESS_VLD,

with a hysteresis of Vhys(B_SESS_VLD).

7.6.2.3 Session end comparator

The ISP1506 session end comparator determines when VBUS is below the B-device

session end threshold. The B-device uses this threshold to determine when a session has

ended. The session end threshold of the ISP1506 is VB_SESS_END.

7.6.3 SRP charge and discharge resistors

The ISP1506 provides on-chip resistors for short-term charging and discharging of VBUS.

These are used by the B-device to request a session, prompting the A-device to restore

the VBUS power. First, the B-device makes sure that VBUS is fully discharged from the

previous session by setting the DISCHRG_VBUS register bit to logic 1 and waiting for

SESS_END to be logic 1. Then the B-device charges VBUS by setting the CHRG_VBUS

threshold and starts a session by turning on the VBUS power.

7.6.4 Charge pump

The ISP1506 uses a built-in charge pump to supply current to VBUS at a nominal voltage

of 5 V. The charge pump works as a capacitive DC-DC converter. An external holding

capacitor, Ccp(C_A)-(C_B), is required between the C_A and C_B pins as shown in Figure 3,

Product data sheet Rev. 02 — 28 August 2008 10 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

which also shows a typical OTG VBUS load. The value of Ccp(C_A)-(C_B) depends on the

amount of current drive required. If the internal charge pump is not used, the Ccp(C_A)-(C_B)

capacitor is not required.

For details on the C_A and C_B pins, see Section 7.9.7.

7.7 Band gap reference voltage

The band gap circuit provides a stable internal voltage reference to bias the analog

circuitry. The band gap requires an accurate external reference resistor RRREF connected

between the RREF and GND pins. For details, see Section 16.

7.8 Power-On Reset (POR)

The ISP1506 has an internal power-on-reset circuit that resets all internal logic on

power-up. The ULPI interface is also reset on power-up.

Remark: When CLOCK starts toggling after power-up, the USB link must issue a reset

command over the ULPI bus to ensure correct operation of the ISP1506.

7.9 Detailed description of pins

7.9.1 DATA[3:0]

The ISP1506 is a Physical layer (PHY) containing a USB transceiver. DATA[7:0] is a

dual-edge bidirectional data bus. The USB link must drive DATA[3:0] to LOW when the

ULPI bus is idle. When the link has data to transmit to the PHY, it drives a nonzero value.

The data bus can be reconﬁgured to carry various data types, as given in Section 8 and

Section 9.

7.9.2 VCC(I/O)

The input power pin that sets the I/O voltage level. For details, see Section 12,Section 13

and Section 16. VCC(I/O) provides power to on-chip pads of the following pins:

•CLOCK

•DATA[3:0]

•DIR

•NXT

•RESET_N/PSW_N

Fig 3. External capacitors connection

004aaa600

ISP1506

VBUS

C_B

C_A

Ccp(C_A)-(C_B)

OTG VBUS

4.7 µF0.1 µF

Product data sheet Rev. 02 — 28 August 2008 11 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

•STP

7.9.3 RREF

Resistor reference analog I/O pin. A resistor, RRREF, must be connected between RREF

and GND, as shown in Section 16. This provides an accurate voltage reference that

biases internal analog circuitry. Less accurate resistors cannot be used and will render the

ISP1506 unusable.

7.9.4 DP and DM

DP (data plus) and DM (data minus) are USB differential data pins. These must be

connected to the D+ and D− pins of the USB receptacle.

7.9.5 ID

For OTG implementations, the ID (identiﬁcation) pin is connected to the ID pin of the

micro-USB receptacle. As deﬁned in Ref. 2 “On-The-Go Supplement to the USB 2.0

Speciﬁcation Rev. 1.3”, the ID pin dictates the initial role of the link. If ID is detected as

HIGH, the link must assume the role of a peripheral. If ID is detected as LOW, the link

must assume a host role. Roles can be swapped at a later time by using HNP.

If the ISP1506 is not used as an OTG PHY, but as a standard USB host or peripheral PHY,

the ID pin must be connected to REG3V3.

7.9.6 CPGND

CPGND indicates the analog ground for the on-board charge pump. CPGND must always

be connected to ground, even when the charge pump is not used.

7.9.7 C_A and C_B

The C_A and C_B pins are to connect the ﬂying capacitor of the charge pump. The output

current capability of the charge pump depends on the value of the capacitor used, as

shown in Table 3. For maximum efﬁciency, place capacitors as close as possible to pins.

For details, see Section 16.

If the charge pump is not used, C_A and C_B must be left ﬂoating (not connected).

Fig 4. Charge pump capacitor

004aaa601

ISP1506

VBUS

C_A

C_B Ccp(C_A)-(C_B)

Product data sheet Rev. 02 — 28 August 2008 12 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

7.9.8 VCC

VCC is the main input supply voltage for the ISP1506. Decoupling capacitors are

recommended. For details, see Section 16.

7.9.9 VBUS/FAULT

This pin provides two options for VBUS driving and monitoring. If neither function is used,

this pin must be connected to ground.

7.9.9.1 VBUS

This pin acts as an input to VBUS comparators, and also as a power pin for the charge

pump, and SRP charge and discharge resistors.

The VBUS pin requires a capacitive load as shown in Section 16.

To prevent electrical overstress, it is strongly recommended that you attach a series

resistor on the VBUS pin (RVBUS). RVBUS must not be attached when using the ISP1506

internal charge pump. For details, see Section 16.

7.9.9.2 FAULT (external overcurrent or fault detector)

If an external VBUS overcurrent or fault circuit is used, the output fault indicator of that

circuit can be connected to the ISP1506 FAULT input pin. The ISP1506 will inform the link

of VBUS fault events by sending RXCMDs on the ULPI bus. To use the FAULT pin, the link

must:

•Set the USE_EXT_VBUS_IND register bit to logic 1.

•Set the polarity of the external fault signal using the IND_COMPL register bit.

7.9.10 REG3V3 and REG1V8

Regulator output voltage. These supplies are used to power the ISP1506 internal digital

and analog circuits, and must not be used to power external circuits.

For correct operation of the regulator, it is recommended that you connect REG3V3 and

REG1V8 to decoupling capacitors. For examples, see Section 16.

7.9.11 XTAL1 and XTAL2

XTAL1 is the crystal input, and XTAL2 is the crystal output. The allowed frequency on the

XTAL1 pin depends on the ISP1506 product version.

The ISP1506 requires external load capacitors to GND on each terminal of the crystal. For

details, see Section 16.

If at any time the system wants to stop the clock on XTAL1, the link must ﬁrst put the

ISP1506 into low-power mode. The clock on XTAL1 must be restarted before low-power

mode is exited.

Table 3. Recommended charge pump capacitor value

Ccp(C_A)-(C_B) IL (max)

22 nF 8 mA

270 nF 50 mA

Product data sheet Rev. 02 — 28 August 2008 13 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

7.9.12 RESET_N/PSW_N

This pin provides two optional functions. If neither function is used, this pin must be

connected to VCC(I/O).

7.9.12.1 RESET_N

An active LOW asynchronous reset pin that resets all circuits in the ISP1506. The

ISP1506 contains an internal power-on reset circuit, and therefore using the RESET_N

pin is optional. If RESET_N is not used, it must be connected to VCC(I/O).

For details on using RESET_N, see Section 9.3.2.

7.9.12.2 PSW_N

PSW_N is an active LOW, open-drain output pin. This pin can be connected to an active

LOW, external VBUS switch or charge pump enable circuit to control the external VBUS

power source. An external pull-up resistor, Rpullup, is required when PSW_N is used. This

pin is open-drain, allowing ganged-mode power control for multiple USB ports. For

application details, see Section 16.

To use the PSW_N pin, the link must disable the reset input by setting the

IGNORE_RESET bit in the Power Control register to logic 1. This will ensure that PSW_N

is not misinterpreted as a reset.

If the link is in host mode, it can enable the external VBUS power source by setting the

DRV_VBUS_EXT bit in the OTG Control register to logic 1. The ISP1506 will drive

PSW_N to LOW to enable the external VBUS power source. If the link detects an

overcurrent condition (the VBUS state in RXCMD is not 11b), it must disable the external

VBUS power source by setting DRV_VBUS_EXT to logic 0.

7.9.13 DIR

ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1506

holds DIR at LOW, causing the data bus to be an input. When DIR is LOW, the ISP1506

listens for data from the link. The ISP1506 pulls DIR to HIGH only when it has data to

send to the link, which is for one of two reasons:

•To send the USB receive data, RXCMD status updates and register reads data to the

link.

•To block the link from driving the data bus during power-up, reset and low-power

mode (suspend).

For details on DIR usage, refer to Ref. 3 “UTMI+ Low Pin Interface (ULPI) Speciﬁcation

Rev. 1.1”.

7.9.14 STP

ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet

or a register write operation. When DIR is asserted, the link can optionally assert STP to

abort the ISP1506, causing it to deassert DIR in the next clock cycle. A weak pull-up

resistor is incorporated into the STP pin as part of the interface protect feature. For details,

see Section 9.3.1.

For details on STP usage, refer to Ref. 3 “UTMI+ Low Pin Interface (ULPI) Speciﬁcation

Rev. 1.1”.

Product data sheet Rev. 02 — 28 August 2008 14 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

7.9.15 NXT

ULPI next data output pin. The ISP1506 holds NXT at LOW by default. When DIR is LOW

and the link is sending data to the ISP1506, NXT will be asserted to notify the link to

provide the next data byte. When DIR is at HIGH and the ISP1506 is sending data to the

link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is not

used for register read data or the RXCMD status update.

For details on NXT usage, refer to Ref. 3 “UTMI+ Low Pin Interface (ULPI) Speciﬁcation

Rev. 1.1”.

7.9.16 CLOCK

A 60 MHz output interface clock to synchronize the ULPI bus. The ISP1506 provides two

clocking options:

•A crystal is attached between the XTAL1 and XTAL2 pins.

•A clock is driven into the XTAL1 pin, with the XTAL2 pin left ﬂoating.

For details on CLOCK usage, refer to Ref. 3 “UTMI+ Low Pin Interface (ULPI)

Speciﬁcation Rev. 1.1”.

7.9.17 GND (die pad)

Global ground signal, except for the charge pump that uses CPGND. The die pad is

exposed on the underside of the package as a ground plate. This acts as a ground to all

circuits in the ISP1506, except the charge pump. To ensure correct operation of the

ISP1506, GND must be soldered to the cleanest ground available.

Product data sheet Rev. 02 — 28 August 2008 15 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

8. Modes of operation

8.1 ULPI modes

The ISP1506 ULPI bus can be programmed to operate in three modes. Each mode

reconﬁgures the signals on the data bus as described in the following subsections. Setting

more than one mode will lead to undeﬁned behavior.

8.1.1 Synchronous mode

This is default mode. At power-up, and when CLOCK is stable, the ISP1506 will enter

synchronous mode. The link must synchronize all ULPI signals to CLOCK, meeting the

set-up and hold times as deﬁned in Section 15. A description of the ULPI pin behavior in

synchronous mode is given in Table 4.

This mode is used by the link to perform the following tasks:

•High-speed detection handshake (chirp)

•Transmit and receive USB packets

•Read and write to registers

•Receive USB status updates (RXCMDs)

For more information on the various synchronous mode protocols, see Section 9.

Table 4. ULPI signal description

Signal name Direction on

ISP1506 Signal description

CLOCK I/O 60 MHz interface clock. If a crystal is attached or a clock is driven into the XTAL1 pin, the

ISP1506 will drive a 60 MHz output clock.

DATA[3:0] I/O 4-bit data bus. In synchronous mode, the link drives DATA[3:0] to LOW by default. The link

initiates transfers by sending a nonzero data pattern called TXCMD (transmit command). In

synchronous mode, the direction of DATA[3:0] is controlled by DIR. Contents of DATA[3:0]

lines must be ignored for exactly one clock cycle whenever DIR changes value. This is called

the turnaround cycle. Bytes of data are transferred between the link and PHY in 4-bit nibbles.

The least signiﬁcant nibble, DATA[3:0], is transferred ﬁrst on the rising edge of clock. The

most signiﬁcant nibble, DATA[7:4], is transferred next on the falling edge of clock. Transferring

an odd number of 4-bit nibbles is not allowed.

Data lines have ﬁxed direction and different meaning in low-power and 3-pin serial modes.

Product data sheet Rev. 02 — 28 August 2008 16 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

8.1.2 Low-power mode

When the USB is idle, the link can place the ISP1506 into low-power mode (also called

suspend mode). In low-power mode, the data bus deﬁnition changes to that shown in

Table 5. To enter low-power mode, the link sets the SUSPENDM bit in the Function

Control register to logic 0. To exit low-power mode, the link asserts the STP signal. The

ISP1506 will draw only suspend current from the VCC supply (see Table 45).

During low-power mode, the clock on XTAL1 may be stopped. The clock must be started

again before asserting STP to exit low-power mode. After exiting low-power mode, the

ISP1506 will send an RXCMD to the link if a change was detected in any interrupt source,

and the change still exists. An RXCMD may not be sent if the interrupt condition is

removed before exiting.

For more information on low-power mode enter and exit protocols, refer to Ref. 3 “UTMI+

Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1”.

DIR O Direction: Controls the direction of data bus DATA[3:0]. In synchronous mode, the ISP1506

drives DIR to LOW by default, making the data bus an input so that the ISP1506 can listen

for TXCMDs from the link. The ISP1506 drives DIR to HIGH only when it has data for the

link. When DIR and NXT are HIGH, the byte on the data bus contains decoded USB data.

When DIR is HIGH and NXT is LOW, the byte contains status information called RXCMD

(receive command). The only exception to this rule is when the PHY returns register read

data, where NXT is also LOW, replacing the usual RXCMD byte. Every change in DIR

causes a turnaround cycle on the data bus, during which DATA[3:0] is not valid and must be

ignored by the link.

DIR is always asserted during low-power and 3-pin serial modes.

STP I Stop: In synchronous mode, the link drives STP to HIGH for one cycle after the last byte of

data is sent to the ISP1506. The link can optionally assert STP to force DIR to be

deasserted.

In low-power and 3-pin serial modes, the link holds STP at HIGH to wake up the ISP1506,

causing the ULPI bus to return to synchronous mode.

NXT O Next: In synchronous mode, the ISP1506 drives NXT to HIGH to throttle data. If DIR is LOW,

the ISP1506 asserts NXT to notify the link to place the next data byte on DATA[3:0] in the

following clock cycle. If DIR is HIGH, the ISP1506 asserts NXT to notify the link that a valid

USB data byte is on DATA[3:0] in the current cycle. The ISP1506 always drives an RXCMD

when DIR is HIGH and NXT is LOW, unless register read data is to be returned to the link in

the current cycle.

NXT is not used in low-power or 3-pin serial modes.

Table 4. ULPI signal description

…continued

Signal name Direction on

ISP1506 Signal description

Table 5. Signal mapping during low-power mode

Signal Maps to Direction Description

LINESTATE0 DATA0 O combinatorial LINESTATE0 directly driven by the analog receiver

LINESTATE1 DATA1 O combinatorial LINESTATE1 directly driven by the analog receiver

Reserved DATA2 O reserved; the ISP1506 will drive this pin to LOW

INT DATA3 O active HIGH interrupt indication; will be asserted whenever any

unmasked interrupt occurs

Product data sheet Rev. 02 — 28 August 2008 17 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

8.1.3 3-pin full-speed or low-speed serial mode

If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed

USB data, it can set the ISP1506 to 3-pin serial mode. In 3-pin serial mode, the data bus

deﬁnition changes to that shown in Table 6. To enter 3-pin serial mode, the link sets the

3PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 3-pin serial

mode, the link asserts STP. This is primarily provided for links that contain legacy

full-speed or low-speed functionality, providing a more cost-effective upgrade path to

high-speed. An interrupt pin is also provided to inform the link of USB events. If the link

requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM

For more information on 3-pin serial mode enter and exit protocols, refer to Ref. 3 “UTMI+

Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1”.

8.2 USB and OTG state transitions

A Hi-Speed USB peripheral, host or OTG device handles more than one electrical state as

deﬁned in Ref. 1 “Universal Serial Bus Speciﬁcation Rev. 2.0” and Ref. 2 “On-The-Go

Supplement to the USB 2.0 Speciﬁcation Rev. 1.3”. The ISP1506 accommodates various

states through register bit settings of XCVRSELECT[1:0], TERMSELECT, OPMODE[1:0],

DP_PULLDOWN and DM_PULLDOWN.

Table 7 summarizes operating states. The values of register settings in Table 7 will force

resistor settings as also given in Table 7. Resistor setting signals are deﬁned as follows:

•RPU_DP_EN enables the 1.5 kΩ pull-up resistor on DP

•RPD_DP_EN enables the 15 kΩ pull-down resistor on DP

•RPD_DM_EN enables the 15 kΩ pull-down resistor on DM

•HSTERM_EN enables the 45 Ω termination resistors on DP and DM

The link is responsible for setting the desired USB and OTG states.

Table 6. Signal mapping for 3-pin serial mode

Signal Maps to Direction Description

TX_ENABLE DATA0 I active HIGH transmit enable

DAT DATA1 I/O transmit differential data on DP and DM when TX_ENABLE is HIGH

receive differential data from DP and DM when TX_ENABLE is LOW

SE0 DATA2 I/O transmit single-ended zero on DP and DM when TX_ENABLE is HIGH

receive single-ended zero from DP and DM when TX_ENABLE is LOW

INT DATA3 O active HIGH interrupt indication; will be asserted whenever any

unmasked interrupt occurs

Product data sheet Rev. 02 — 28 August 2008 18 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

Table 7. Operating states and their corresponding resistor settings

Signaling mode Register settings Internal resistor settings

XCVR

SELECT

[1:0]

TERM

SELECT OPMODE

[1:0] DP_PULL

DOWN DM_PULL

DOWN RPU_

DP_EN RPD_

DM_EN HSTERM

_EN

General settings

3-state drivers XXb Xb 01b Xb Xb 0b 0b 0b 0b

Power-up or

VBUS <V

B_SESS_END

01b 0b 00b 1b 1b 0b 1b 1b 0b

Host settings

Host chirp 00b 0b 10b 1b 1b 0b 1b 1b 1b

Host high-speed 00b 0b 00b 1b 1b 0b 1b 1b 1b

Host full-speed X1b 1b 00b 1b 1b 0b 1b 1b 0b

Host high-speed or

full-speed suspend 01b 1b 00b 1b 1b 0b 1b 1b 0b

Host high-speed or

full-speed resume 01b 1b 10b 1b 1b 0b 1b 1b 0b

Host low-speed 10b 1b 00b 1b 1b 0b 1b 1b 0b

Host low-speed

suspend 10b 1b 00b 1b 1b 0b 1b 1b 0b

Host low-speed

resume 10b 1b 10b 1b 1b 0b 1b 1b 0b

Host Test J or Test K 00b 0b 10b 1b 1b 0b 1b 1b 1b

Peripheral settings

Peripheral chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b

Peripheral

high-speed 00b 0b 00b 0b 0b 0b 0b 0b 1b

Peripheral full-speed 01b 1b 00b 0b 0b 1b 0b 0b 0b

Peripheral

high-speed or

full-speed suspend

01b 1b 00b 0b 0b 1b 0b 0b 0b

Peripheral

high-speed or

full-speed resume

01b 1b 10b 0b 0b 1b 0b 0b 0b

Peripheral Test J or

Test K 00b 0b 10b 0b 0b 0b 0b 0b 1b

OTG settings

OTG device

peripheral chirp 00b 1b 10b 0b 1b 1b 0b 1b 0b

OTG device

peripheral

high-speed

00b 0b 00b 0b 1b 0b 0b 1b 1b

OTG device

peripheral full-speed 01b 1b 00b 0b 1b 1b 0b 1b 0b

Product data sheet Rev. 02 — 28 August 2008 19 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

OTG device

peripheral

high-speed and

full-speed suspend

01b 1b 00b 0b 1b 1b 0b 1b 0b

OTG device

peripheral

high-speed and

full-speed resume

01b 1b 10b 0b 1b 1b 0b 1b 0b

OTG device

peripheral Test J or

Test K

00b 0b 10b 0b 1b 0b 0b 1b 1b

Table 7. Operating states and their corresponding resistor settings

…continued

Signaling mode Register settings Internal resistor settings

XCVR

SELECT

[1:0]

TERM

SELECT OPMODE

[1:0] DP_PULL

DOWN DM_PULL

DOWN RPU_

DP_EN RPD_

DM_EN HSTERM

_EN

Product data sheet Rev. 02 — 28 August 2008 20 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

9. Protocol description

The following subsections describe the protocol for using the ISP1506.

Remark: In all ﬁgures, the ULPI data is shown in a generic form and not as nibbles on the

rising and falling edges of the clock.

9.1 ULPI references

The ISP1506 provides an 8-pin ULPI interface to communicate with the link. It is highly

recommended that you read Ref. 3 “UTMI+ Low Pin Interface (ULPI) Speciﬁcation

Rev. 1.1” and Ref. 4 “UTMI+ Speciﬁcation Rev. 1.0”.

9.2 Power-On Reset (POR)

An internal POR is generated when REG1V8 rises above VPOR(trip), for at least

tw(REG1V8_H). The internal POR pulse will also be generated whenever REG1V8 drops

below VPOR(trip) for more than tw(REG1V8_L), and then rises above VPOR(trip) again. The

voltage on REG1V8 is generated from VCC.

To give a better view of the functionality, Figure 5 shows a possible curve of REG1V8. The

internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip

level so that POR turns to logic 1 and a delay element will add another tPORP before it

drops to logic 0. If REG1V8 dips from t2 to t3 for > tw(REG1V8_L), another POR pulse is

generated. If the dip at t4 to t5 is too short, that is, < tw(REG1V8_L), the internal POR pulse

will not react and will remain LOW.

9.3 Power-up, reset and bus idle sequence

Figure 6 shows a typical start-up sequence.

On power-up, the ISP1506 performs an internal power-on reset and asserts DIR to

indicate to the link that the ULPI bus cannot be used. When the internal PLL is stable, the

ISP1506 deasserts DIR. The power-up time depends on the VCC supply rise time, the

crystal start-up time, and PLL start-up time tstartup(o)(CLOCK). Whenever DIR is asserted,

the ISP1506 drives the NXT pin to LOW and drives DATA[3:0] with RXCMD values. When

DIR is deasserted, the link must drive the data bus to a valid level. By default, the link

must drive data to LOW. When the ISP1506 initially deasserts DIR on power-up, the link

must ignore all RXCMDs until it resets the ISP1506. Before beginning USB packets, the

link must set the RESET bit in the Function Control register to reset the ISP1506. After the

RESET bit is set, the ISP1506 will assert DIR until the internal reset completes. The

ISP1506 will automatically deassert DIR and clear the RESET bit when reset has

Fig 5. Internal power-on reset timing

004aaa751

REG1V8

t0 t1 t2 t3 t4 t5

VPOR(trip)

tPORP POR

tPORP

Product data sheet Rev. 02 — 28 August 2008 21 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

completed. After every reset, an RXCMD is sent to the link to update USB status

information. After this sequence, the ULPI bus is ready for use and the link can start USB

operations.

When the internal PLL is stable, the ISP1506 will drive a 60 MHz clock out from the

CLOCK pin when DIR deasserts. An example start-up sequence is shown in Figure 6.

The recommended power-up sequence for the link is as follows:

1. The link waits for 1 ms, ignoring all the ULPI pin status.

2. The link may start to detect DIR status level. If DIR is detected as LOW for three clock

cycles, the link may send a RESET command.

The ULPI interface is ready for use.

Product data sheet Rev. 02 — 28 August 2008 22 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

9.3.1 Interface protection

By default, the ISP1506 enables a weak pull-up resistor on STP. If the STP pin is

unexpectedly HIGH at any time, the ISP1506 will protect the ULPI interface by enabling

weak pull-down resistors on DATA[3:0].

t1 = VCC and VCC(I/O) are applied to the ISP1506. The ISP1506 regulator starts to turn on.

t2 = ULPI pads detect REG1V8 rising above the REG1V8 regulator threshold and are not in 3-state. These pads may drive

either LOW or HIGH. It is recommended that the link ignores the ULPI pins status during tPWRUP.

t3 = The POR threshold is reached and a POR pulse is generated. After the POR pulse, ULPI pins are driven to a deﬁned level.

DIR is driven to HIGH and the other pins are driven to LOW.

t4 = The internal PLL is stabilized after tstartup(PLL). If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL will

be stabilized after tstartup(PLL) from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH to LOW.

The DIR pin will remain LOW before the link issues a RESET command to the ISP1506.

t5 = The power-up sequence is completed and the ULPI bus interface is ready for use.

Fig 6. Power-up and reset sequence required before the ULPI bus is ready for use

CLOCK

TXCMD

DIR

DATA[3:0]

STP

NXT

004aaa886

RESET command

internal clocks stable

internal reset RXCMD

update

bus idle

VCC

VCC(I/O)

REG1V8

internal

REG1V8

detector

internal

POR

XTAL1

tstartup(PLL)

t1 t2 t3 t4 t5

tPWRUP

Product data sheet Rev. 02 — 28 August 2008 23 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

The interface protect feature prevents unwanted activity of the ISP1506 whenever the

ULPI interface is not correctly driven by the link. For example, when the link powers up

more slowly than the ISP1506.

The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.

9.3.2 Interface behavior with respect to RESET_N

The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the

ISP1506 will assert DIR. All logic in the ISP1506 will be reset, including the analog

circuitry and ULPI registers. During reset, the link must drive DATA[3:0] and STP to LOW;

otherwise undeﬁned behavior may result. When RESET_N is deasserted (HIGH), the DIR

output will deassert (LOW) four or ﬁve clock cycles later. Figure 7 shows the ULPI

interface behavior when RESET_N is asserted (LOW), and subsequently deasserted

(HIGH). If RESET_N is not used, it must be connected to VCC(I/O).

9.4 VBUS power and fault detection

9.4.1 Driving 5 V on VBUS

The ISP1506 provides a built-in charge pump. To enable the charge pump, the link must

set the DRV_VBUS bit in the OTG Control register.

The ISP1506 also supports external 5 V supplies. The ISP1506 can control the external

supply using the active-LOW PSW_N open-drain output pin. To enable the external supply

by driving PSW_N to LOW, the link must set the DRV_VBUS_EXT bit in the OTG Control

bits to logic 1 to enable the external supply.

Table 8 summarizes settings to drive 5 V on VBUS.

Fig 7. Interface behavior with respect to RESET_N

CLOCK

004aaa890

STP

RESET_N

DATA[3:0]

DIR

NXT

Hi-Z (input)

Hi-Z (link must drive)

Product data sheet Rev. 02 — 28 August 2008 24 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

9.4.2 Fault detection

The ISP1506 supports external VBUS fault detector circuits that output a digital fault

indicator signal. The indicator signal must be connected to the FAULT pin. To enable the

ISP1506 to monitor the digital fault input, the link must set the USE_EXT_VBUS_IND bit

in the OTG Control register and the IND_PASSTHRU bit in the Interface Control register to

logic 1. For details, see Figure 9.

The FAULT input pin is mapped to the A_VBUS_VLD bit in RXCMD. Any changes for the

FAULT input will trigger RXCMD carrying the FAULT condition with A_VBUS_VLD.

9.5 TXCMD and RXCMD

Commands between the ISP1506 and the link are described in the following subsections.

9.5.1 TXCMD

By default, the link must drive the ULPI bus to its idle state of 00h. To send commands and

USB packets, the link drives a nonzero value on DATA[3:0] to the ISP1506 by sending a

byte called TXCMD. Commands include USB packet transmissions, and register reads

and writes. Once the TXCMD is interpreted and accepted by the ISP1506, the NXT signal

is asserted and the link can follow up with the required number of data bytes. The TXCMD

byte format is given in Table 9. Any values other than those in Table 9 are illegal and may

result in undeﬁned behavior.

Various TXCMD packet and register sequences are shown in later sections.

Table 8. OTG Control register power control bits

DRV_VBUS DRV_VBUS_EXT Power source used

0 0 internal and external VBUS power sources are disabled

1 0 internal VBUS charge pump is enabled

X 1 external 5 V VBUS supply is enabled

Table 9. TXCMD byte format

Command

type name Command code Command

payload Command

name Command description

Idle 00b 00 0000b NOOP No operation. 00h is the idle value of the data bus. The

link must drive NOOP by default.

Packet

transmit 01b 00 0000b NOPID Transmit USB data that does not have a PID, such as

chirp and resume signaling. The ISP1506 starts

transmitting only after accepting the next data byte.

00 XXXXb PID Transmit USB packet. DATA[3:0] indicates USB packet

identiﬁer PID[3:0].

write 10b 10 1111b EXTW Extended register write command (optional). The 8-bit

address must be provided after the command is

accepted.

XX XXXXb REGW Register write command with 6-bit immediate address.

address must be provided after the command is

accepted.

XX XXXXb REGR Register read command with 6-bit immediate address.

Product data sheet Rev. 02 — 28 August 2008 25 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

9.5.2 RXCMD

The ISP1506 communicates status information to the link by asserting DIR and sending

an RXCMD byte on the data bus. The RXCMD data byte format is given in Table 10.

The ISP1506 will automatically send an RXCMD whenever there is a change in any of the

RXCMD data ﬁelds. The link must be able to accept an RXCMD at any time; including

single RXCMDs, back-to-back RXCMDs, and RXCMDs at any time during USB receive

packets when NXT is LOW. An example is shown in Figure 8. For details and diagrams,

refer to Ref. 3 “UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1”.

An RXCMD may not be sent when exiting low-power mode or serial mode, if the interrupt

condition is removed before exiting.

9.5.2.1 Linestate encoding

LINESTATE[1:0] reﬂects the current state of DP and DM. Whenever the ISP1506 detects

a change in DP or DM, an RXCMD will be sent to the link with the new LINESTATE[1:0]

value. The value given on LINESTATE[1:0] depends on the setting of various registers.

Table 11 shows the LINESTATE[1:0] encoding for upstream facing ports, which applies to

peripherals. Table 12 shows the LINESTATE[1:0] encoding for downstream facing ports,

which applies to host controllers. Dual-role devices must choose the correct table,

depending on whether it is in peripheral or host mode.

Table 10. RXCMD byte format

DATA Name Description and value

1 to 0 LINESTATE LINESTATE signals: For a deﬁnition of LINESTATE, see Section 9.5.2.1.

DATA0 — LINESTATE[0]

DATA1 — LINESTATE[1]

3to2 V

BUS state Encoded VBUS voltage state: For an explanation of the VBUS state, see Section 9.5.2.2.

5 to 4 RxEvent Encoded USB event signals: For an explanation of RxEvent, see Section 9.5.2.4.

6 ID Set to the value of the ID pin.

7 ALT_INT By default, this signal is not used and is not needed in typical designs. Optionally, the link can

enable the BVALID_RISE and/or BVALID_FALL bits in the Power Control register. Corresponding

changes in BVALID will cause an RXCMD to be sent to the link with the ALT_INT bit asserted.

Fig 8. Single and back-to-back RXCMDs from the ISP1506 to the link

CLOCK

RXCMD

DATA[3:0]RXCMD RXCMD

004aaa760

DIR

STP

NXT

single RXCMD back-to-back RXCMDs

turnaround turnaround turnaround turnaround

Product data sheet Rev. 02 — 28 August 2008 26 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

[1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output.

9.5.2.2 VBUS state encoding

USB devices must monitor the VBUS voltage for purposes such as overcurrent detection,

starting a session and SRP. The VBUS state ﬁeld in the RXCMD is an encoding of the

voltage level on VBUS.

The A_VBUS_VLD, SESS_VLD and SESS_END indicators in the VBUS state are directly

taken from internal comparators built-in to the ISP1506, and encoded as shown in

Table 10 and Table 13.

For high-power USB hosts supplying more than 100 mA, it is recommended that you use

an external FAULT indicator. Internal comparators must not be used.

Note that VBUS and FAULT share the same pin and cannot be used simultaneously.

A_VBUS_VLD and FAULT will be interpreted by the ISP1506 as shown in Figure 9.

A description on how to use and select the VBUS state encoding is given in

Section 9.5.2.3.

Table 11. LINESTATE[1:0] encoding for upstream facing ports: peripheral

DP_PULLDOWN = 0.

[1]

Mode Full-speed High-speed Chirp

XCVRSELECT[1:0] 01, 11 00 00

TERMSELECT 1 0 1

LINESTATE[1:0] 00 SE0 squelch squelch

01 FS-J !squelch !squelch and HS_Differential_Receiver_Output

10 FS-K invalid !squelch and !HS_Differential_Receiver_Output

11 SE1 invalid invalid

Table 12. LINESTATE[1:0] encoding for downstream facing ports: host

DP_PULLDOWN and DM_PULLDOWN = 1.

[1]

Mode Low-speed Full-speed High-speed Chirp

XCVRSELECT[1:0] 10 01, 11 00 00

TERMSELECT 1 1 0 0

OPMODE[1:0] X X 00, 01 or 11 10

LINESTATE[1:0] 00 SE0 SE0 squelch squelch

01 LS-K FS-J !squelch !squelch and HS_Differential_Receiver_Output

10 LS-J FS-K invalid !squelch and !HS_Differential_Receiver_Output

11 SE1 SE1 invalid invalid

Table 13. Encoded VBUS voltage state

Value VBUS voltage SESS_END SESS_VLD A_VBUS_VLD

00 VBUS <V

B_SESS_END 100

01 VB_SESS_END ≤VBUS < VB_SESS_VLD 000

10 VB_SESS_VLD ≤VBUS < VA_VBUS_VLD X1 0

11 VBUS ≥VA_VBUS_VLD XX1

Product data sheet Rev. 02 — 28 August 2008 27 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

9.5.2.3 Using and selecting the VBUS state encoding

The VBUS state encoding is shown in Table 13. The ISP1506 will send an RXCMD to the

link whenever there is a change in the VBUS state. To receive VBUS state updates, the link

must ﬁrst enable the corresponding interrupts in the USB Interrupt Enable Rising Edge

and USB Interrupt Enable Falling Edge registers.

The link can use the VBUS state to monitor VBUS and take appropriate action. Table 14

shows the recommended usage for typical applications.

Standard USB host controllers: For standard hosts, the system must be able to provide

500 mA on VBUS in the range of 4.75 V to 5.25 V. An external circuit must be used to

detect overcurrent conditions. If the external overcurrent detector provides a digital fault

signal, then the fault signal must be connected to the ISP1506 FAULT input pin, and the

link must do the following:

1. Set the IND_COMPL bit in the Interface Control register to logic 0 or logic 1,

depending on the polarity of the external fault signal.

2. Set the USE_EXT_VBUS_IND bit in the OTG Control register to logic 1.

3. Set the IND_PASSTHRU bit in the Interface Control register to logic 1 (mandatory).

Standard USB peripheral controllers: Standard peripherals must be able to detect

when VBUS is at a sufﬁcient level for operation. SESS_VLD must be enabled to detect the

start and end of USB peripheral operations. Detection of A_VBUS_VLD and SESS_END

thresholds is not needed for standard peripherals.

Fig 9. RXCMD A_VBUS_VLD indicator source

004aaa752

VBUS/FAULT (0, X)

IND_COMPL

(1, 1)

USE_EXT_VBUS_IND,

IND_PASSTHRU

RXCMD

A_VBUS_VLD

A_VBUS_VLD comparator

(VBUS < 4.4 V)

internal A_VBUS_VLD

complement output

Table 14. VBUS indicators in RXCMD required for typical applications

Application A_VBUS_VLD SESS_VLD SESS_END

Standard host yes no no

Standard peripheral no yes no

OTG A-device yes yes no

OTG B-device no yes yes

Product data sheet Rev. 02 — 28 August 2008 28 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

OTG devices: When an OTG device is conﬁgured as an OTG A-device, it must be able to

provide a minimum of 8 mA on VBUS. If the OTG A-device provides less than 100 mA, then

there is no need for an overcurrent detection circuit because the internal A_VBUS_VLD

comparator is sufﬁcient. If the OTG A-device provides more than 100 mA on VBUS, an

overcurrent detector must be used and Section “Standard USB host controllers” applies.

The OTG A-device also uses SESS_VLD to detect when an OTG B-device is initiating

VBUS pulsing SRP.

When an OTG device is conﬁgured as an OTG B-device, SESS_VLD must be used to

detect when VBUS is at a sufﬁcient level for operation. SESS_END must be used to detect

when VBUS has dropped to a LOW level, allowing the B-device to safely initiate VBUS

pulsing SRP.

9.5.2.4 RxEvent encoding

The RxEvent ﬁeld (see Table 15) of the RXCMD informs the link of information related

packets received on the USB bus. RxActive and RxError are deﬁned in Ref. 5 “USB 2.0

Transceiver Macrocell Interface (UTMI) Speciﬁcation Ver. 1.05”. HostDisconnect is

deﬁned in Ref. 4 “UTMI+ Speciﬁcation Rev. 1.0”. A short deﬁnition is also given in the

following subsections.

RxActive: When the ISP1506 has detected a SYNC pattern on the USB bus, it signals an

RxActive event to the link. An RxActive event can be communicated using two methods.

The ﬁrst method is for the ISP1506 to simultaneously assert DIR and NXT. The second

method is for the ISP1506 to send an RXCMD to the link with the RxActive ﬁeld in

RxEvent bits set to logic 1. The link must be able to detect both methods. RxActive frames

the receive packet from the ﬁrst byte to the last byte.

The link must assume that RxActive is set to logic 0 when indicated in an RXCMD or when

DIR is deasserted, whichever occurs ﬁrst.

The link uses RxActive to time high-speed packets and ensure that bus turnaround times

are met. For more information on the USB packet timing, see Section 9.8.1.

RxError: When the ISP1506 has detected an error while receiving a USB packet, it

deasserts NXT and sends an RXCMD with the RxError ﬁeld set to logic 1. The received

packet is no longer valid and must be dropped by the link.

HostDisconnect: HostDisconnect is encoded into the RxEvent ﬁeld of the RXCMD.

HostDisconnect is valid only when the ISP1506 is conﬁgured as a host (both

DP_PULLDOWN and DM_PULLDOWN are set to logic 1), and indicates to the host

controller when a peripheral is connected or disconnected. The host controller must

enable HostDisconnect by setting the HOST_DISCON_R and HOST_DISCON_F bits in

the USB Interrupt Enable Rising Edge and USB Interrupt Enable Falling Edge registers,

respectively. Changes in HostDisconnect will cause the PHY to send an RXCMD to the

link with the updated value.

Table 15. Encoded USB event signals

Value RxActive RxError HostDisconnect

00000

01100

11110

10XX1

Product data sheet Rev. 02 — 28 August 2008 29 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

9.6 Register read and write operations

Figure 10 shows the register read and write sequences. The ISP1506 supports immediate

addressing and extended addressing register operations. Extended register addressing is

optional for links. Note that register operations will be aborted if the ISP1506 unexpectedly

asserts DIR during the operation. When a register operation is aborted, the link must retry

until successful. For more information on register operations, refer to Ref. 3 “UTMI+ Low

Pin Interface (ULPI) Speciﬁcation Rev. 1.1”.

9.7 USB reset and high-speed detection handshake (chirp)

Figure 11 shows the sequence of events for USB reset and high-speed detection

handshake (chirp). The sequence is shown for hosts and peripherals. Figure 11 does not

show all RXCMD updates, and timing is not to scale. The sequence is as follows:

1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and

as full-speed if DP is HIGH. If a host detects a low-speed peripheral, it does not follow

the remainder of this protocol. If a host detects a full-speed peripheral, it resets the

peripheral by writing to the Function Control register and setting

XCVRSELECT[1:0] = 00b (high-speed) and TERMSELECT = 0b, which drives SE0

on the bus (DP and DM connected to ground through 45 Ω). The host also sets

OPMODE[1:0] = 10b for correct chirp transmit and receive. The start of SE0 is labeled

T0.

Remark: To receive chirp signaling, the host must also consider the high-speed

differential receiver output. The host controller must interpret LINESTATE[1:0] as

shown in Table 12.

2. High-speed detection handshake (chirp)

a. Peripheral chirp: After detecting SE0 for no less than 2.5 µs, if the peripheral is

capable of high-speed, it sets XCVRSELECT[1:0] = 00b (high-speed) and

OPMODE[1:0] = 10b (chirp). The peripheral immediately follows this with a

TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more

AD indicates the address byte, and D indicates the data byte.

Fig 10. Example of register write, register read, extended register write and extended register read

CLOCK

DIR

DATA[3:0]

NXT

004aaa761

DTXCMD

(EXTW) AD D

immediate

TXCMD

(REGW) TXCMD

(REGR) DAD

TXCMD

(EXTW) D

STP

extended

Product data sheet Rev. 02 — 28 August 2008 30 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

than 7 ms after reset time T0. If the peripheral is in low-power mode, it must wake

up its clock within 5.6 ms, leaving 200 µs for the link to start transmitting the

Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock).

b. Host chirp: If the host does not detect the peripheral chirp, it must continue

asserting SE0 until the end of reset. If the host detects the peripheral Chirp K for

no less than 2.5 µs, then no more than 100 µs after the bus leaves the Chirp K

state, the host sends a TXCMD (NOPID) with an alternating sequence of Chirp Ks

and Chirp Js. Each Chirp K or Chirp J must last no less than 40 µs and no longer

than 60 µs.

c. High-speed idle: The peripheral must detect a minimum of Chirp K-J-K-J-K-J. Each

Chirp K and Chirp J must be detected for at least 2.5 µs. After seeing that

minimum sequence, the peripheral sets TERMSELECT = 0b and

OPMODE[1:0] = 00b. The peripheral is now in high-speed mode and sees !squelch

(01b on LINESTATE). When the peripheral sees squelch (10b on LINESTATE), it

knows that the host has completed chirp and waits for Hi-Speed USB trafﬁc to

begin. After transmitting the chirp sequence, the host changes OPMODE[1:0] to

00b and begins sending USB packets.

For more information, refer to Ref. 3 “UTMI+ Low Pin Interface (ULPI) Speciﬁcation

Rev. 1.1”.

Product data sheet Rev. 02 — 28 August 2008 31 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

Timing is not to scale.

Fig 11. USB reset and high-speed detection handshake (chirp) sequence

004aaa762

DATA

[3:0]

TXCMD

NOPID J ... TXCMD

(REGW)

TXCMD

(REGW) SE0 K

DIR

STP

NXT

XCVR

SELECT

TERM

SELECT

01 (FS) 00 (HS)

MODE

00 (normal) 01 (chirp) 00 (normal)

LINE

STATE

J (01b) SE0 (00b) peripheral chirp K (10b) squelch (00b)

host chirp K (10b) or chirp J (01b)

squelch

(00b)

ULPI host

DATA

[3:0]

TXCMD

NOPID K...

SE0 TXCMD

(REGW) 00 KJKJKJTXCMD

(REGW) 00

DIR

STP

NXT

XCVR

SELECT

01 (FS) 00 (HS)

TERM

SELECT

MODE

00 (normal) 10 (chirp) 00 (normal)

LINE

STATE

J (01b) SE0 (00b) peripheral chirp K (10b) !squelch

(01b)

host chirp K or J (10b or 01b)

squelch

(00b) squelch (00b)

ULPI peripheral

USB signals

USB reset high-speed detection handshake (chirp)

peripheral chirp host chirp HS idle

RXCMDs

Product data sheet Rev. 02 — 28 August 2008 32 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

9.8 USB packet transmit and receive

An example of a packet transmit and receive is shown in Figure 12. For details on USB

packets, refer to Ref. 3 “UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1”.

9.8.1 USB packet timing

9.8.1.1 ISP1506 pipeline delays

The ISP1506 delays are shown in Table 16. For detailed description, refer to Ref. 3

“UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1”, Section 3.8.2.6.2.

9.8.1.2 Allowed link decision time

The amount of clock cycles allocated to the link to respond to a received packet and

correctly receive back-to-back packets is given in Table 17. Link designs must follow

values given in Table 17 for correct USB system operation. Examples of high-speed

packet sequences and timing are shown in Figure 13 and Figure 14. For details, refer to

Ref. 3 “UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1”, Section 3.8.2.6.3.

Fig 12. Example of using the ISP1506 to transmit and receive USB data

CLOCK

TXCMD DATA

DATA[3:0]RXCMD DATA

DIR

STP

NXT

004aaa763

link sends

TXCMD

ISP1506

accepts

TXCMD

link sends

the next data;

ISP1506

accepts link signals

end of data ULPI bus

is idle

ISP1506

asserts DIR,

causing

turnaround

cycle

ISP1506

sends

RXCMD

(NXT LOW)

ISP1506

sends

USB data

(NXT HIGH)

ISP1506

deasserts

DIR, causing

turnaround

cycle

turnaround turnaround

Table 16. PHY pipeline delays

Parameter name High-speed PHY delay Full-speed PHY delay Low-speed PHY delay

RXCMD delay (J and K) 4 4 4

RXCMD delay (SE0) 4 4 to 6 16 to 18

TX start delay 1 to 2 6 to 10 74 to 75

TX end delay (packets) 3 to 4 not applicable not applicable

TX end delay (SOF) 6 to 9 not applicable not applicable

RX start delay 5 to 6 not applicable not applicable

RX end delay 5 to 6 17 to 18 122 to 123

Product data sheet Rev. 02 — 28 August 2008 33 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

Table 17. Link decision times

Packet sequence High-speed

link delay Full-speed

link delay Low-speed

link delay Deﬁnition

Transmit-Transmit

(host only) 15 to 24 7 to 18 77 to 247 Number of clocks a host link must wait before driving the

TXCMD for the second packet.

In high-speed, the link starts counting from the assertion of

STP for the ﬁrst packet.

In full-speed, the link starts counting from the RXCMD,

indicating LINESTATE has changed from SE0 to J for the ﬁrst

packet. The timing given ensures inter-packet delays of 2 bit

times to 6.5 bit times.

Receive-Transmit

(host or

peripheral)

1 to 14 7 to 18 77 to 247 Number of clocks the link must wait before driving the

TXCMD for the transmit packet.

In high-speed, the link starts counting from the end of the

receive packet; deassertion of DIR or an RXCMD indicating

RxActive is LOW.

In full-speed or low-speed, the link starts counting from the

RXCMD, indicating LINESTATE has changed from SE0 to J

for the receive packet. The timing given ensures inter-packet

delays of 2 bit times to 6.5 bit times.

Receive-Receive

(peripheral only) 1 1 1 Minimum number of clocks between consecutive receive

packets. The link must be able to receive both packets.

Transmit-Receive

(host or

peripheral)

92 80 718 Host or peripheral transmits a packet and will time-out after

this number of clock cycles if a response is not received. Any

subsequent transmission can occur after this time.

Fig 13. High-speed transmit-to-transmit packet timing

004aaa891

DP or

DM DATA EOP IDLE SYNC

CLOCK

DN−1DN

DATA

[3:0]

TXCMD D1

DIR

STP

NXT

TX end delay (two to five clocks)

link decision time (15 to 24 clocks)

TX start delay

(one to two clocks)

USB interpacket delay (88 to 192 high-speed bit times)

Product data sheet Rev. 02 — 28 August 2008 34 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

9.9 Preamble

Preamble packets are headers to low-speed packets that must travel over a full-speed

bus, between a host and a hub. To enter preamble mode, the link sets

XCVRSELECT[1:0] = 11b in the Function Control register. When in preamble mode, the

ISP1506 operates just as in full-speed mode, and sends all data with the full-speed rise

time and fall time. Whenever the link transmits a USB packet in preamble mode, the

ISP1506 will automatically send a preamble header at full-speed bit rate before sending

the link packet at low-speed bit rate. The ISP1506 will ensure a minimum gap of four

full-speed bit times between the last bit of the full-speed PRE PID and the ﬁrst bit of the

low-speed packet SYNC. The ISP1506 will drive a J for at least one full-speed bit time

after sending the PRE PID, after which the pull-up resistor can hold the J state on the bus.

An example transmit packet is shown in Figure 15.

In preamble mode, the ISP1506 can also receive low-speed packets from the full-speed

bus.

Fig 14. High-speed receive-to-transmit packet timing

004aaa892

DP or

DM DATA EOP IDLE SYNC

CLOCK

DN−4

DN−3

DATA

[3:0]

TXCMD D1

DIR

STP

NXT

RX end delay

(three to eight clocks) link decision time (1 to 14 clocks) TX start delay

(one to two clocks)

USB interpacket delay (8 to 192 high-speed bit times)

DN−2

DN−1

turnaround

Product data sheet Rev. 02 — 28 August 2008 35 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

9.10 USB suspend and resume

9.10.1 Full-speed or low-speed host-initiated suspend and resume

Figure 16 illustrates how a host or a hub places a full-speed or low-speed peripheral into

suspend and sometime later initiates resume signaling to wake up the downstream

peripheral. Note that Figure 16 timing is not to scale, and does not show all RXCMD

LINESTATE updates.

The sequence of events for a host and a peripheral, both with ISP1506, is as follows.

1. Idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ pull-down

resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b), and 45 Ω

terminations disabled (TERMSELECT is set to 1b). The peripheral has the 1.5 kΩ

pull-up resistor connected to DP for full-speed or DM for low-speed (TERMSELECT is

set to 1b).

2. Suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend

state. The peripheral link places the PHY into low-power mode by clearing the

SUSPENDM bit in the Function Control register, causing the PHY to draw only

suspend current. The host may or may not be powered down.

3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE[1:0] to

10b and transmits a K for at least 20 ms. The peripheral link sees the resume K on

LINESTATE, and asserts STP to wake up the PHY.

4. EOP: When STP is asserted, the ISP1506 on the host side automatically appends an

EOP of two bits of SE0 at low-speed bit rate, followed by one bit of J. The ISP1506 on

the host side knows to add the EOP because DP_PULLDOWN and DM_PULLDOWN

are set to 1b for a host. After the EOP is completed, the host link sets OPMODE[1:0]

to 00b for normal operation. The peripheral link sees the EOP and also resumes

normal operation.

DP and DM timing is not to scale.

Fig 15. Preamble sequence

CLOCK

TXCMD (low-speed packet ID) D1

DATA[3:0]

DIR

STP

NXT

004aaa764

DP or DM FS SYNC FS

PRE ID IDLE (min

4 FS bits) LS SYNC LS PID LS D0 LS D1

Product data sheet Rev. 02 — 28 August 2008 36 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

9.10.2 High-speed suspend and resume

Figure 17 illustrates how a host or a hub places a high-speed enabled peripheral into

suspend and then initiates resume signaling. The high-speed peripheral will wake up and

return to high-speed operations. Note that Figure 17 timing is not to scale, and does not

show all RXCMD LINESTATE updates.

Timing is not to scale.

Fig 16. Full-speed suspend and resume

DATA

[3:0]

TXCMD

NOPID K...

TXCMD

(REGW)

DIR

STP

NXT

OPMODE 00b 10b 00b

K TXCMD

LINE

STATE J K SE0 J

CLOCK

DATA

[3:0]

TXCMD

(REGW) LINESTATE J LINESTATE K SE0 J

DIR

STP

NXT

OPMODE 00b 10b 00b

SUSPENDM

LINE

STATE J K SE0 J

004aaa765

FS or LS host (XCVRSELECT = 01b (FS)

or 10b (LS), DP_PULLDOWN = 1b,

DM_PULLDOWN = 1b, TERMSELECT = 1b)

FS or LS peripheral (XCVRSELECT = 01b (FS)

or 10b (LS), DP_PULLDOWN = 0b, TERMSELECT = 1b)

USB signals

(only FS is shown)

idle suspend resume K EOP idle

Product data sheet Rev. 02 — 28 August 2008 37 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

The sequence of events related to a host and a peripheral, both with ISP1506, is as

follows.

1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ

pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b)

and 45 Ω terminations enabled (TERMSELECT is set to 0b). The peripheral has its

45 Ω terminations enabled (TERMSELECT is set to 0b).

2. Full-speed suspend: When the peripheral sees no bus activity for 3 ms, it enters the

suspend state. The peripheral link places the ISP1506 into full-speed mode

(XCVRSELECT is set to 01b), removes 45 Ω terminations, and enables the 1.5 kΩ

pull-up resistor on DP (TERMSELECT is set to 1b). The peripheral link then places

the ISP1506 into low-power mode by clearing SUSPENDM, causing the ISP1506 to

draw only suspend current. The host also changes the ISP1506 to full-speed

(XCVRSELECT is set to 01b), removes 45 Ω terminations (TERMSELECT is set to

1b), and then may or may not be powered down.

3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE to 10b

and transmits a full-speed K for at least 20 ms. The peripheral link sees the resume K

(10b) on LINESTATE, and asserts STP to wake up the ISP1506.

4. High-speed trafﬁc: The host link sets high-speed (XCVRSELECT is set to 00b) and

enables its 45 Ω terminations (TERMSELECT is set to 0b). The peripheral link sees

SE0 on LINESTATE and also sets high-speed (XCVRSELECT is set to 00b) and

enables its 45 Ω terminations (TERMSELECT is set to 0b). The host link sets

OPMODE to 00b for normal high-speed operation.

Product data sheet Rev. 02 — 28 August 2008 38 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

Timing is not to scale.

Fig 17. High-speed suspend and resume

DATA

[3:0]

TXCMD

NOPID K...

TXCMD

(REGW)

DIR

STP

NXT

MODE 00b 10b 00b

KTXCMD

(REGW)

CLOCK

DATA

[3:0]

TXCMD

(REGW) LINESTATE J LINESTATE K SE0 TXCMD

(REGW)

DIR

STP

NXT

OPMODE 00b 10b 00b

SUSPENDM

LINE

STATE

004aaa766

ULPI HS host (DP_PULLDOWN = 1b,

DM_PULLDOWN = 1b)

ULPI HS peripheral (DP_PULLDOWN = 0b)

USB signals

HS idle FS suspend resume K

TXCMD

(REGW)

HS idle

XCVR

SELECT 00b 01b 00b

TERM

SELECT

LINE

STATE

!squelch

(01b) squelch

(00b) FS J (01b) !squelch (01b)squelch (00b)FS K (10b)

XCVR

SELECT 00b 01b 00b

TERM

SELECT

!squelch

(01b) squelch

(00b) FS J (01b) !squelch

(01b)

squelch (00b)FS K (10b)

Product data sheet Rev. 02 — 28 August 2008 39 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

9.10.3 Remote wake-up

The ISP1506 supports peripherals that initiate remote wake-up resume. When placed into

USB suspend, the peripheral link remembers at what speed it was originally operating.

Depending on the original speed, the link follows one of the protocols detailed here. In

Figure 18, timing is not to scale, and not all RXCMD LINESTATE updates are shown.

The sequence of events related to a host and a peripheral, both with ISP1506, is as

follows.

1. Both the host and the peripheral are assumed to be in low-power mode.

2. The peripheral begins remote wake-up by re-enabling its clock and setting its

SUSPENDM bit to 1b.

3. The peripheral begins driving K on the bus to signal resume. Note that the peripheral

link must assume that LINESTATE is K (01b) while transmitting because it will not

receive any RXCMDs.

4. The host recognizes the resume, re-enables its clock and sets its SUSPENDM bit.

5. The host takes over resume driving within 1 ms of detecting the remote wake-up.

6. The peripheral stops driving resume.

7. The peripheral sees the host continuing to drive the resume.

8. The host stops driving resume and the ISP1506 automatically adds the EOP to the

end of the resume. The peripheral recognizes the EOP as the end of resume.

9. Both the host and the peripheral revert to normal operation by writing 00b to

OPMODE. If the host or the peripheral was previously in high-speed mode, it must

revert to high-speed before the SE0 of the EOP is completed. This can be achieved

by writing XCVRSELECT[1:0] = 00b and TERMSELECT = 0b after LINESTATE

indicates SE0.

Product data sheet Rev. 02 — 28 August 2008 40 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

9.11 No automatic SYNC and EOP generation (optional)

This setting allows the link to turn off the automatic SYNC and EOP generation, and must

be used for high-speed packets only. It is provided for backward compatibility with legacy

controllers that include SYNC and EOP bytes in the data payload when transmitting

packets. The ISP1506 will not automatically generate SYNC and EOP patterns when

OPMODE[1:0] is set to 11b. The ISP1506 will still NRZI encode data and perform bit

stufﬁng. An example of a sequence is shown in Figure 19. The link must always send

packets using the TXCMD (NOPID) type. The ISP1506 does not provide a mechanism to

control bit stufﬁng in individual bytes, but will automatically turn off bit stufﬁng for EOP

when STP is asserted with data set to FEh. If data is set to 00h when STP is asserted, the

Timing is not to scale.

Fig 18. Remote wake-up from low-power mode

DATA

[3:0]

LINESTATE TXCMD

REGW TXCMD

REGW

00h

TXCMD

NOPID

DIR

STP

NXT

XCVR

SELECT 01b (FS), 10b (LS) 00b (HS only)

TERM

SELECT

MODE 10b 00b

DATA

[3:0]

LINESTATE TXCMD

REGW RXCMD

00h

TXCMD

NOPID RXCMD RXCMD TXCMD

REGW

DIR

STP

NXT

XCVR

SELECT 00b (HS), 01b (FS), 10b (LS) 00b (HS only)

TERM

SELECT

MODE 10b 00b

ULPI host

ULPI peripheral

004aaa767

0b (HS only)

Product data sheet Rev. 02 — 28 August 2008 41 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

PHY will not transmit any EOP. The ISP1506 will also detect if the PID byte is A5h,

indicating an SOF packet, and automatically send a long EOP when STP is asserted. To

transmit chirp and resume signaling, the link must set OPMODE to 10b.

9.12 On-The-Go operations

On-The-Go (OTG) is a supplement to Ref. 1 “Universal Serial Bus Speciﬁcation Rev. 2.0”

that allows a portable USB device to assume the role of a limited USB host by deﬁning

improvements, such as a small connector and low power. Non-portable devices, such as

standard hosts and embedded hosts, can also beneﬁt from OTG features.

The ISP1506 OTG PHY is designed to support all the tasks speciﬁed in the OTG

supplement. The ISP1506 provides the front-end analog support for Host Negotiation

Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices. The

supporting components include:

•Built-in 5 V charge pump

•Voltage comparators

–A_VBUS_VLD

–SESS_VLD (session valid, can be used for both A-session and B-session valid)

–SESS_END (session end)

•Pull-up and pull-down resistors on DP and DM

•ID detector indicates if micro-A or micro-B plug is inserted

•Charge and discharge resistors on VBUS

The following subsections describe how to use the ISP1506 OTG components.

Fig 19. Transmitting USB packets without the automatic SYNC and EOP generation

CLOCK

DATA

[3:0]

TXCMD 00h 00h 00h 80h PID D1 D2 D3 ... ... DN − 1 FEhDN

DIR

STP

NXT

ULPI signals

TXVALID

TXREADY

TXBIT

STUFF

ENABLE

DP, DM

IDLE SYNC PID IDLEEOPDATA PAYLOAD

004aaa893

UTMI+ equivalent

signals

USB bus

Product data sheet Rev. 02 — 28 August 2008 42 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

9.12.1 OTG charge pump

A description of the charge pump is given in Section 7.6.4. When the controller is

conﬁgured as an A-device, it can provide the VBUS power by turning on the charge pump.

Control of the charge pump is described in Section 9.4.1 and Section 10.1.4.

9.12.2 OTG comparators

The ISP1506 provides comparators that conform to Ref. 2 “On-The-Go Supplement to the

USB 2.0 Speciﬁcation Rev. 1.3” requirements of VA_VBUS_VLD, VA_SESS_VLD, VB_SESS_VLD

and VB_SESS_END. In this data sheet, VA_SESS_VLD and VB_SESS_VLD are combined into

VB_SESS_VLD. Comparators are described in Section 7.6.2. Changes in comparator values

are communicated to the link by RXCMDs as described in Section 9.5.2.2. Control over

comparators is described in Section 10.1.5 to Section 10.1.8.

9.12.3 Pull-up and pull-down resistors

The USB resistors on DP and DM can be used to initiate data-line pulsing SRP. The link

must set the required bus state using mode settings in Table 7.

9.12.4 ID detection

The ISP1506 provides an internal pull-up resistor to sense the value of the ID pin. The

pull-up resistor must ﬁrst be enabled by setting the ID_PULLUP register bit to logic 1. If

the value on ID has changed, the ISP1506 will send an RXCMD or interrupt to the link by

time tID. If the link does not receive any RXCMD or interrupt by tID, then the ID value has

not changed.

9.12.5 VBUS charge and discharge resistors

A pull-up resistor, RUP(VBUS), is provided to perform VBUS pulsing SRP. A B-device is

allowed to charge VBUS above the session valid threshold to request the host to turn on

the VBUS power.

A pull-down resistor, RDN(VBUS), is provided for a B-device to discharge VBUS. This is done

whenever the A-device turns off the VBUS power. The B-device can use the pull-down

resistor to ensure VBUS is below VB_SESS_END before starting a session.

For details, refer to Ref. 2 “On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.3”.

9.13 Serial mode

The ISP1506 supports 3-pin serial mode, controlled by bit 3PIN_FSLS_SERIAL of the

Interface Control register. For details, refer to Ref. 3 “UTMI+ Low Pin Interface (ULPI)

Speciﬁcation Rev. 1.1”, Section 3.10.

Figure 20 provides an example of 3-pin serial mode.

Product data sheet Rev. 02 — 28 August 2008 43 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

9.14 Aborting transfers

The ISP1506 supports aborting transfers on the ULPI bus. For details, refer to Ref. 3

“UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1”, Section 3.8.4.

9.15 Avoiding contention on the ULPI data bus

Because the ULPI data bus is bidirectional, avoid situations in which both the link and the

PHY simultaneously drive the data bus.

The following points must be considered while implementing the data bus drive control on

the link.

After power-up and clock stabilization, default states are as follows:

•The ISP1506 drives DIR to LOW.

•The data bus is input to the ISP1506.

•The ULPI link data bus is output, with all data bus lines driven to LOW.

When the ISP1506 wants to take control of the data bus to initiate a data transfer, it

changes the DIR value from LOW to HIGH.

At this point, the link must disable its output buffers. This must be as fast as possible so

the link must use a combinational path from DIR.

The ISP1506 will not immediately enable its output buffers, but will delay the enabling of

its buffers until the next clock edge, avoiding bus contention.

When the data transfer is no longer required by the ISP1506, it changes DIR from HIGH to

LOW and starts to immediately turn off its output drivers. The link senses the change of

DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle,

avoiding data bus contention.

Fig 20. Example of transmit followed by receive in 3-pin serial mode

DATA0

(TX_ENABLE)

DATA1

(DAT)

DATA2

(SE0)

004aaa982

SYNC DATA EOP

TRANSMIT RECEIVE

SYNC DATA EOP

Product data sheet Rev. 02 — 28 August 2008 44 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

10. Register map

[1] Read (R): A register can be read. Read-only if this is the only mode given.

[2] Write (W): The pattern on the data bus will be written over all bits of a register.

[3] Set (S): The pattern on the data bus is OR-ed with and written to a register.

[4] Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero

(cleared).

[1] Read (R): A register can be read. Read-only if this is the only mode given.

[2] Write (W): The pattern on the data bus will be written over all bits of a register.

[3] Set (S): The pattern on the data bus is OR-ed with and written to a register.

[4] Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero

(cleared).

Table 18. Immediate register set overview

Field name Size

(bit) Address (6 bit) References

R[1] W[2] S[3] C[4]

Vendor ID Low register 8 00h - - - Section 10.1.1 on page 45

Vendor ID High register 8 01h - - -

Product ID Low register 8 02h - - -

Product ID High register 8 03h - - -

Function Control register 8 04h to 06h 04h 05h 06h Section 10.1.2 on page 45

Interface Control register 8 07h to 09h 07h 08h 09h Section 10.1.3 on page 46

OTG Control register 8 0Ah to 0Ch 0Ah 0Bh 0Ch Section 10.1.4 on page 47

USB Interrupt Enable Rising Edge

USB Interrupt Enable Falling Edge

USB Interrupt Status register 8 13h - - - Section 10.1.7 on page 49

USB Interrupt Latch register 8 14h - - - Section 10.1.8 on page 50

Debug register 8 15h - - - Section 10.1.9 on page 51

Scratch register 8 16h to 18h 16h 17h 18h Section 10.1.10 on page 51

Reserved (do not use) - 19h to 2Eh Section 10.1.11 on page 51

Access extended register set 8 - 2Fh - - Section 10.1.12 on page 51

Vendor-speciﬁc register 8 30h to 3Ch Section 10.1.13 on page 51

Power Control register 8 3Dh to 3Fh Section 10.1.14 on page 51

Table 19. Extended register set overview

Field name Size

(bit) Address (6 bit) References

R[1] W[2] S[3] C[4]

Maps to immediate register set above 8 00h to 3Fh Section 10.2 on page 52

Reserved (do not use) 8 40h to FFh

Product data sheet Rev. 02 — 28 August 2008 45 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

10.1 Immediate register set

10.1.1 Vendor ID and Product ID registers

10.1.1.1 Vendor ID Low register

Table 20 shows the bit description of the register.

10.1.1.2 Vendor ID High register

The bit description of the register is given in Table 21.

10.1.1.3 Product ID Low register

The bit description of the Product ID Low register is given in Table 22.

10.1.1.4 Product ID High register

The bit description of the register is given in Table 23.

10.1.2 Function Control register

This register controls UTMI function settings of the PHY. The bit allocation of the register

is given in Table 24.

Table 20. Vendor ID Low register (address R = 00h) bit description

Bit Symbol Access Value Description

7 to 0 VENDOR_ID_

LOW[7:0] R CCh Vendor ID Low: Lower byte of the NXP vendor ID supplied by USB-IF;

has a ﬁxed value of CCh

Table 21. Vendor ID High register (address R = 01h) bit description

Bit Symbol Access Value Description

7 to 0 VENDOR_ID_

HIGH[7:0] R 04h Vendor ID High: Upper byte of the NXP vendor ID supplied by USB-IF;

has a ﬁxed value of 04h

Table 22. Product ID Low register (address R = 02h) bit description

Bit Symbol Access Value Description

7 to 0 PRODUCT_ID_

LOW[7:0] R 06h Product ID Low: Lower byte of the NXP product ID number; has a ﬁxed

value of 06h

Table 23. Product ID High register (address R = 03h) bit description

Bit Symbol Access Value Description

7 to 0 PRODUCT_ID_

HIGH[7:0] R 15h Product ID High: Upper byte of the NXP product ID number; has a ﬁxed

value of 15h

Table 24. Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit allocation

Bit 76 543210

Symbol reserved SUSPENDM RESET OPMODE[1:0] TERM

SELECT XCVRSELECT[1:0]

Reset 01 000001

Access R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C

Product data sheet Rev. 02 — 28 August 2008 46 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

10.1.3 Interface Control register

The Interface Control register enables alternative interfaces. All of these modes are

optional features provided for legacy link cores. Setting more than one of these ﬁelds

results in undeﬁned behavior. Table 26 provides the bit allocation of the register.

Table 25. Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit description

Bit Symbol Description

7 - reserved

6 SUSPENDM Suspend LOW: Active LOW PHY suspend.

Places the PHY into low-power mode. The PHY will power down all blocks, except the full-speed

receiver, OTG comparators and ULPI interface pins.

To come out of low-power mode, the link must assert STP. The PHY will automatically clear this

bit when it exits low-power mode.

0b — Low-power mode

1b — Powered (default)

5 RESET Reset: Active HIGH transceiver reset.

After the link sets this bit, the PHY will assert DIR and reset the digital core. This does not reset

the ULPI interface or the ULPI register set.

When reset is completed, the PHY will deassert DIR and automatically clear this bit, followed by

an RXCMD update to the link.

0b — Do not reset (default)

1b — Reset

The link must wait for DIR to deassert before using the ULPI bus. Does not reset the ULPI

interface or ULPI register set.

4 to 3 OPMODE

[1:0] Operation Mode: Selects the required bit-encoding style during transmit.

00b — Normal operation (default)

01b — Non-driving

10b — Disable bit-stufﬁng and NRZI encoding

11b — Do not automatically add SYNC and EOP when transmitting; must be used only for

high-speed packets

2 TERMSELECT Termination Select: Controls the internal 1.5 kΩ full-speed pull-up resistor and 45 Ω

high-speed terminations. Control over bus resistors changes, depending on

XCVRSELECT[1:0], OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN, as shown in

Table 7.

1 to 0 XCVRSELECT

[1:0] Transceiver Select: Selects the required transceiver speed.

00b — Enable the high-speed transceiver

01b — Enable the full-speed transceiver (default)

10b — Enable the low-speed transceiver

11b — Enable the full-speed transceiver for low-speed packets (full-speed preamble is

automatically preﬁxed)

Table 26. Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol INTF_

PROT_DIS IND_PASS

THRU IND_

COMPL reserved CLOCK_

SUSPENDM reserved 3PIN_FSLS

_SERIAL reserved

Reset 00000000

Access R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C

Product data sheet Rev. 02 — 28 August 2008 47 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

10.1.4 OTG Control register

This register controls various OTG functions of the ISP1506. The bit allocation of the OTG

Control register is given in Table 28.

Table 27. Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit description

Bit Symbol Description

7 INTF_PROT_DIS Interface Protect Disable: Controls circuitry built into the ISP1506 to protect the ULPI interface

when the link 3-states STP and DATA[3:0]. When this bit is enabled, the ISP1506 will

automatically detect when the link stops driving STP.

0b — Enables the interface protect circuit (default). The ISP1506 attaches a weak pull-up

resistor on STP. If STP is unexpectedly HIGH, the ISP1506 attaches weak pull-down resistors

on DATA[3:0], protecting data inputs.

1b — Disables the interface protect circuit, detaches weak pull-down resistors on DATA[3:0],

and a weak pull-up resistor on STP.

6 IND_PASSTHRU Indicator Pass-through: The ISP1506 does not support the qualiﬁcation of an external FAULT

with the internal VA_VBUS_VLD comparator. Either a digital FAULT is input on the VBUS/FAULT pin

or the VBUS power is connected to the VBUS/FAULT pin, not both. This bit must always be set to

logic 1.

0b — Not supported.

1b — The complement output signal is not qualiﬁed with the internal A_VBUS_VLD comparator.

The link must always set this bit to logic 1.

5 IND_COMPL Indicator Complement: Informs the PHY to invert the FAULT input signal, generating the

complement output. For details, see Section 9.5.2.2.

0b — The ISP1506 will not invert the FAULT signal (default).

1b — The ISP1506 will invert the FAULT signal.

4 - reserved

3 CLOCK_

SUSPENDM Clock Suspend LOW: Active LOW clock suspend.

Powers down the internal clock circuitry only. By default, the clock will not be powered in 3-pin

serial mode.

Valid only in 3-pin serial mode. Valid only when SUSPENDM is set to logic 1, otherwise this bit

is ignored.

0b — Clock will not be powered in 3-pin serial mode (default).

1b — Clock will be powered in 3-pin serial mode.

2 - reserved

1 3PIN_FSLS_

SERIAL 3-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 3-bit serial

interface. The PHY will automatically clear this bit when 3-pin serial mode is exited.

0b — Full-speed or low-speed packets are sent using the parallel interface (default).

1b — Full-speed or low-speed packets are sent using the 3-pin serial interface.

0 - reserved

Table 28. OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation

Bit 76543210

Symbol USE_EXT_

VBUS_IND DRV_

VBUS_EXT DRV_

VBUS CHRG_

VBUS DISCHRG_

VBUS DM_PULL

DOWN DP_PULL

DOWN ID_PULL

Reset 00000110

Access R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C

Product data sheet Rev. 02 — 28 August 2008 48 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

10.1.5 USB Interrupt Enable Rising Edge register

The bits in this register enable interrupts and RXCMDs to be sent when the corresponding

bits in the USB Interrupt Status register change from logic 0 to logic 1. By default, all

transitions are enabled. Table 30 shows the bit allocation of the register.

Table 29. OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit description

Bit Symbol Description

7 USE_EXT_

VBUS_IND Use External VBUS Indicator: Informs the PHY to use an external VBUS overcurrent indicator.

0b — Use the internal OTG comparator (default).

1b — Use the external VBUS valid indicator signal input from the FAULT pin.

6 DRV_VBUS_

EXT Drive VBUS External: Selects between the internal and external 5 V VBUS supply. Using an

external charge pump or a 5 V supply is optional.

0b — Drives VBUS using the internal charge pump. Also ensures PSW_N is not driven to LOW

(default).

1b — Drives VBUS using the external charge pump or the 5 V supply. Drives PSW_N to LOW.

5 DRV_VBUS Drive VBUS: Signals the ISP1506 to drive 5 V on VBUS. If DRV_VBUS_EXT is set to logic 1, then

setting DRV_VBUS is optional.

0b — Do not drive VBUS (default).

1b — Drive 5 V on VBUS.

4 CHRG_VBUS Charge VBUS: Charges VBUS through a resistor. Used for the VBUS pulsing SRP. The link must ﬁrst

check that VBUS is discharged (see bit DISCHRG_VBUS), and that both the DP and DM data lines

have been LOW (SE0) for 2 ms.

0b — Do not charge VBUS (default).

1b — Charge VBUS.

3 DISCHRG_

VBUS Discharge VBUS: Discharges VBUS through a resistor. If the link sets this bit to logic 1, it waits for

an RXCMD indicating that SESS_END has changed from 0 to 1, and then resets this bit to 0 to

stop the discharge.

0b — Do not discharge VBUS (default).

1b — Discharge VBUS.

2 DM_PULL

DOWN DM Pull Down: Enables the 15 kΩ pull-down resistor on DM.

0b — Pull-down resistor is not connected to DM.

1b — Pull-down resistor is connected to DM (default).

1 DP_PULL

DOWN DP Pull Down: Enables the 15 kΩ pull-down resistor on DP.

0b — Pull-down resistor is not connected to DP.

1b — Pull-down resistor is connected to DP (default).

0 ID_PULLUP ID Pull Up: Connects a pull-up to the ID line and enables sampling of the ID level. Disabling the ID

line sampler will reduce the PHY power consumption.

0b — Disables sampling of the ID line (default).

1b — Enables sampling of the ID line.

Table 30. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit

allocation

Bit 76543210

Symbol reserved ID_GND_R SESS_

END_R SESS_

VALID_R VBUS_

VALID_R HOST_

DISCON_R

Reset 00011111

Access R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C

Product data sheet Rev. 02 — 28 August 2008 49 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

10.1.6 USB Interrupt Enable Falling Edge register

The bits in this register enable interrupts and RXCMDs to be sent when the corresponding

bits in the USB Interrupt Status register change from logic 1 to logic 0. By default, all

transitions are enabled. See Table 32.

10.1.7 USB Interrupt Status register

This register (see Table 34) indicates the current value of the interrupt source signal.

Table 31. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit

description

Bit Symbol Description

7 to 5 - reserved

4 ID_GND_R ID Ground Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on ID_GND.

3 SESS_END_R Session End Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on

SESS_END.

2 SESS_VALID_R Session Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on

SESS_VLD.

1 VBUS_VALID_R VBUS Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on

VBUS_VLD.

0 HOST_DISCON_

RHost Disconnect Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on

HOST_DISCON.

Table 32. USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit

allocation

Bit 76543210

Symbol reserved ID_GND_F SESS_

END_F SESS_

VALID_F VBUS_

VALID_F HOST_

DISCON_F

Reset 00011111

Access R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C

Table 33. USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit

description

Bit Symbol Description

7 to 5 - reserved

4 ID_GND_F ID Ground Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on ID_GND.

3 SESS_END_F Session End Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

SESS_END.

2 SESS_VALID_F Session Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

SESS_VLD.

1 VBUS_VALID_F VBUS Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

VBUS_VLD.

0 HOST_DISCON_

FHost Disconnect Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

HOST_DISCON.

Product data sheet Rev. 02 — 28 August 2008 50 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

10.1.8 USB Interrupt Latch register

The bits of the USB Interrupt Latch register are automatically set by the ISP1506 when an

unmasked change occurs on the corresponding interrupt source signal. The ISP1506 will

automatically clear all bits when the link reads this register, or when the PHY enters

low-power mode.

Remark: It is optional for the link to read this register when the clock is running because

all signal information will automatically be sent to the link through the RXCMD byte.

The bit allocation of this register is given in Table 36.

Table 34. USB Interrupt Status register (address R = 13h) bit allocation

Bit 76543210

Symbol reserved ID_GND SESS_

END SESS_

VALID VBUS_

VALID HOST_

DISCON

Reset XXX00000

Access RRRRRRRR

Table 35. USB Interrupt Status register (address R = 13h) bit description

Bit Symbol Description

7 to 5 - reserved

4 ID_GND ID Ground: Reﬂects the current value of the ID detector circuit.

3 SESS_END Session End: Reﬂects the current value of the session end voltage comparator.

2 SESS_VALID Session Valid: Reﬂects the current value of the session valid voltage comparator.

1 VBUS_VALID VBUS Valid: Reﬂects the current value of the VBUS valid voltage comparator.

0 HOST_DISCON Host Disconnect: Reﬂects the current value of the host disconnect detector.

Table 36. USB Interrupt Latch register (address R = 14h) bit allocation

Bit 76543210

Symbol reserved ID_GND_L SESS_

END_L SESS_

VALID_L VBUS_

VALID_L HOST_

DISCON_L

Reset 00000000

Access RRRRRRRR

Table 37. USB Interrupt Latch register (address R = 14h) bit description

Bit Symbol Description

7 to 5 reserved -

4 ID_GND_L ID Ground Latch: Automatically set when an unmasked event occurs on ID_GND. Cleared

when this register is read.

3 SESS_END_L Session End Latch: Automatically set when an unmasked event occurs on SESS_END.

Cleared when this register is read.

2 SESS_VALID_L Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD.

Cleared when this register is read.

1 VBUS_VALID_L VBUS Valid Latch: Automatically set when an unmasked event occurs on VBUS_VLD.

Cleared when this register is read.

0 HOST_DISCON_L Host Disconnect Latch: Automatically set when an unmasked event occurs on

HOST_DISCON. Cleared when this register is read.

Product data sheet Rev. 02 — 28 August 2008 51 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

10.1.9 Debug register

The bit allocation of the Debug register is given in Table 38. This register indicates the

current value of signals useful for debugging.

10.1.10 Scratch register

Table 40 shows the bit description of the Scratch register. It is an empty register for testing

purposes.

10.1.11 Reserved

Registers 19h to 2Eh are not implemented. Operating on these addresses will have no

effect on the PHY.

10.1.12 Access extended register set

Address 2Fh does not contain register data. Instead it links to the extended register set.

The immediate register set maps to the lower end of the extended register set.

10.1.13 Vendor-speciﬁc registers

Addresses 30h to 3Fh contain vendor-speciﬁc registers.

10.1.14 Power Control register

This register controls various aspects of the ISP1506. Table 41 shows the bit allocation of

the register.

Table 38. Debug register (address R = 15h) bit allocation

Bit 76543210

Symbol reserved LINE

STATE1 LINE

STATE0

Reset 00000000

Access RRRRRRRR

Table 39. Debug register (address R = 15h) bit description

Bit Symbol Description

7 to 2 - reserved

1 LINESTATE1 Line State 1: Contains the current value of LINESTATE 1

0 LINESTATE0 Line State 0: Contains the current value of LINESTATE 0

Table 40. Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description

Bit Symbol Access Value Description

7 to 0 SCRATCH[7:0] R/W/S/C 00h Scratch: This is an empty register byte for testing purposes. Software

can read, write, set and clear this register, and the functionality of the

PHY will not be affected.

Table 41. Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation

Bit 76543210

Symbol reserved BVALID_

FALL BVALID_

RISE reserved IGNORE_

RESET

Reset 00000000

Access R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C

Product data sheet Rev. 02 — 28 August 2008 52 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

10.2 Extended register set

Addresses 00h to 3Fh of the extended register set directly map to the immediate set. This

means a read, write, set or clear operation to these extended addresses will operate on

the immediate register set.

Addresses 40h to FFh are not implemented. Operating on these addresses may result in

undeﬁned behavior of the PHY.

Table 42. Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description

Bit Symbol Description

7 to 4 - reserved; the link must never write logic 1 to these bits

3 BVALID_FALL BVALID Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID

changes from HIGH to LOW, the ISP1506 will send an RXCMD to the link with the ALT_INT bit

set to logic 1.

This bit is optional and is not necessary for OTG devices. This bit is provided for debugging

purposes. The session valid comparator should be used instead.

2 BVALID_RISE BVALID Rise: Enables RXCMDs for LOW-to-HIGH transitions on BVALID. When BVALID

changes from LOW to HIGH, the ISP1506 will send an RXCMD to the link with the ALT_INT bit

set to logic 1.

This bit is optional and is not necessary for OTG devices. This bit is provided for debugging

purposes. The session valid comparator should be used instead.

1 reserved -

0 IGNORE_RESET Ignore Reset: Selects between the RESET_N and PSW_N functions of the RESET_N/PSW_N

pin. The link must set this bit to logic 1 if PSW_N is used in a ganged mode conﬁguration.

0b — The RESET_N/PSW_N pin behaves as an active-LOW reset input (RESET_N) (default).

1b — The RESET_N/PSW_N pin behaves as an active-LOW power switch output (PSW_N).

Product data sheet Rev. 02 — 28 August 2008 53 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

11. ElectroStatic Discharge (ESD)

11.1 ESD protection

The pins that are connected to the USB connector (DP, DM, ID, VBUS and GND) have a

minimum of ±4 kV ESD protection. Capacitors 0.1 µF and 1 µF must be connected in

parallel from VBUS to GND to achieve this ±4 kV ESD protection (see Figure 21).

Remark: Capacitors 0.1 µF and 1 µF are also required by Ref. 1 “Universal Serial Bus

Speciﬁcation Rev. 2.0”. For details on the requirements for CVBUS, see Section 16.

11.2 ESD test conditions

A detailed report on test set up and results is available on request.

Fig 21. Human body ESD test model

1500 Ω

1 MΩ

HIGH VOLTAGE

DC SOURCE 0.1 µF1 µF

VBUS

DEVICE UNDER

TEST

100 pF storage

capacitor

charge current

limit resistor discharge

resistance

GND

004aaa881

Product data sheet Rev. 02 — 28 August 2008 54 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

12. Limiting values

[1] The ISP1506 has been tested according to the additional requirements listed in Ref. 1 “Universal Serial Bus Speciﬁcation Rev. 2.0”,

Section 7.1.1. The short circuit withstand test and the AC stress test were performed for 24 hours, and the ISP1506 was found to be fully

operational after the test completed.

[2] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor (Human Body Model JESD22-A114D).

13. Recommended operating conditions

Table 43. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +4.6 V

VCC(I/O) input/output supply

voltage −0.5 +2.5 V

VIinput voltage on pins STP, DATA[3:0] and

RESET_N/PSW_N −0.5 VCC(I/O) + 0.5 V

on pin VBUS/FAULT −0.5 +6.0 V

on pin XTAL1 −0.5 +2.5 V

on pin ID −0.5 +4.6 V

on pins DP and DM [1] −0.5 +4.6 V

VESD electrostatic discharge

voltage pins DP, DM, ID, VBUS and GND; ILI < 1 µA[2] −4+4 kV

all other pins; ILI < 1 µA[2] −1.5 +1.5 kV

Ilu latch-up current −0.5 ×VCC < V < +1.5 ×VCC - 100 mA

Tstg storage temperature −40 +125 °C

Table 44. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 3.0 3.3 3.6 V

VCC(I/O) input/output supply voltage 1.65 - 1.95 V

VIinput voltage on pins STP, DATA[3:0] and

RESET_N/PSW_N 0- V

CC(I/O) V

on pin VBUS/FAULT 0 - 5.5 V

on pins DP, DM and ID 0 - 3.6 V

on pin XTAL1 0 - 1.95 V

Tamb ambient temperature −40 +25 +85 °C

Tjjunction temperature −40 - +125 °C

Product data sheet Rev. 02 — 28 August 2008 55 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

14. Static characteristics

[1] A continuous stream of 1 kB packets with minimum inter-packet gap and all data bits set to logic 0 for continuous toggling.

Table 45. Static characteristics: supply pins

= 3.0 V to 3.6 V; V

CC(I/O)

= 1.65 V to 1.95 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.3 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

V(REG3V3) voltage on pin REG3V3 3.0 3.3 3.6 V

V(REG1V8) voltage on pin REG1V8 1.65 1.8 1.95 V

VPOR(trip) power-on reset trip voltage 1.0 - 1.5 V

ICC supply current charge pump disabled

low-power mode; VBUS valid detector

disabled; 1.5 kΩ pull-up resistor on

pin DP disconnected

-3085µA

low-power mode; VBUS valid detector

disabled; 1.5 kΩ pull-up resistor on

pin DP connected

- 210 280 µA

full-speed idle; no USB activity - 10 - mA

high-speed idle; no USB activity - 19 - mA

full-speed continuous data transmit;

50 pF load on pins DP and DM [1] -15-mA

full-speed continuous data receive [1] -11-mA

high-speed continuous data transmit;

45 Ω load on pins DP and DM to

ground

[1] -48-mA

high-speed continuous data receive [1] -28-mA

charge pump enabled

IO(VBUS) = 8 mA; charge pump supply

current only -2023mA

IO(VBUS) = 0 mA; charge pump supply

current only - 300 - µA

ICC(I/O) supply current on

pin VCC(I/O)

ULPI interface pins are static - - 1 µA

Table 46. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[3:0], RESET_N/PSW_N)

= 3.0 V to 3.6 V; V

CC(I/O)

= 1.65 V to 1.95 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.3 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Input levels

VIL LOW-level input voltage - - 0.25 ×VCC(I/O) V

VIH HIGH-level input voltage 0.8 ×VCC(I/O) -- V

IIL LOW-level input current VI= 0 V - - 1 µA

IIH HIGH-level input current VI= VCC(I/O) --1µA

ILI input leakage current −1 +0.1 +1 µA

Output levels

VOL LOW-level output voltage IOL = +2 mA - - 0.4 V

Product data sheet Rev. 02 — 28 August 2008 56 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

VOH HIGH-level output voltage IOH =−2mA V

CC(I/O) −0.4 - - V

IOH HIGH-level output current VO= VCC(I/O) −0.4 V −3.8 - - mA

IOL LOW-level output current VO= 0.4 V 2.8 - - mA

IOZ off-state output current 0 V < VO<V

CC(I/O) --1µA

Impedance

ZLload impedance 40 - 75 Ω

Pull-up and pull-down

Ipd pull-down current interface protect enabled;

DATA[3:0] pins only;

VI=V

CC(I/O)

25 50 90 µA

Ipu pull-up current interface protect enabled;

STP pin only; VI=0V −30 −50 −75 µA

Capacitance

Cin input capacitance pins STP, RESET_N,

CLOCK, DATA[3:0] - - 3.5 pF

Table 46. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[3:0], RESET_N/PSW_N)

…continued

= 3.0 V to 3.6 V; V

CC(I/O)

= 1.65 V to 1.95 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.3 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Table 47. Static characteristics: digital pin FAULT

= 3.0 V to 3.6 V; V

CC(I/O)

= 1.65 V to 1.95 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Input levels

VIL LOW-level input voltage - - 0.8 V

VIH HIGH-level input voltage 2.0 - - V

IIL LOW-level input current VI= 0 V - - 1 µA

IIH HIGH-level input current VI= VCC(I/O) -- 1µA

Table 48. Static characteristics: analog I/O pins (DP, DM)

= 3.0 V to 3.6 V; V

CC(I/O)

= 1.65 V to 1.95 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.3 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Original USB transceiver (low-speed and full-speed)

Input levels (differential receiver)

VDI differential input sensitivity voltage |VDP −VDM|0.2 - - V

VCM differential common mode voltage

range includes VDI range 0.8 - 2.5 V

Input levels (single-ended receivers)

VIL LOW-level input voltage - - 0.8 V

VIH HIGH-level input voltage 2.0 - - V

Output levels

VOL LOW-level output voltage pull-up on pin DP; RL= 1.5 kΩ

to 3.6 V 0.0 0.18 0.3 V

VOH HIGH-level output voltage pull-down on pins DP and DM;

RL=15kΩ to GND 2.8 3.2 3.6 V

Product data sheet Rev. 02 — 28 August 2008 57 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

[1] For high-speed USB and full-speed USB.

Termination

VTERM termination voltage for upstream

facing port pull-up for 1.5 kΩ pull-up resistor 3.0 - 3.6 V

Resistance

RUP(DP) pull-up resistance on pin DP 1425 1500 1575 Ω

High-speed USB transceiver

Input levels (differential receiver)

VHSSQ high-speed squelch detection

threshold voltage (differential

signal amplitude)

100 - 150 mV

VHSDSC high-speed disconnect detection

threshold voltage (differential

signal amplitude)

525 - 625 mV

VHSDI high-speed differential input

sensitivity |VDP −VDM|300 - - mV

VHSCM high-speed data signaling

common mode voltage range

(guideline for receiver)

includes VDI range −50 - +500 mV

VHSOI high-speed idle level voltage −10 - +10 mV

VHSOL high-speed data signaling

LOW-level voltage −10 - +10 mV

Output levels

VHSOH high-speed data signaling

HIGH-level voltage 360 - 440 mV

VCHIRPJ Chirp J level (differential voltage) 700 - 1100 mV

VCHIRPK Chirp K level (differential voltage) −900 - −500 mV

Leakage current

ILZ off-state leakage current −1- +1µA

Capacitance

Cin input capacitance pin to GND - - 5 pF

Resistance

RDN(DP) pull-down resistance on pin DP 14.25 15 15.75 kΩ

RDN(DM) pull-down resistance on pin DM 14.25 15 15.75 kΩ

Termination

ZO(drv)(DP) driver output impedance on pin DP steady-state drive [1] 40.5 45 49.5 Ω

ZO(drv)(DM) driver output impedance on

pin DM steady-state drive [1] 40.5 45 49.5 Ω

ZINP input impedance exclusive of

pull-up/pull-down (for

low-/full-speed)

10 - - MΩ

Table 48. Static characteristics: analog I/O pins (DP, DM)

…continued

= 3.0 V to 3.6 V; V

CC(I/O)

= 1.65 V to 1.95 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.3 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 02 — 28 August 2008 58 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

Table 49. Static characteristics: charge pump

= 3.0 V to 3.6 V; V

CC(I/O)

= 1.65 V to 1.95 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.3 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Voltage

VO(VBUS) output voltage on pin VBUS IO(VBUS) = 50 mA;

Ccp(C_A)-(C_B) = 270 nF 4.65 5.0 5.25 V

VL(VBUS) leakage voltage on pin VBUS charge pump disabled - - 0.2 V

Current

IO(VBUS) output current on pin VBUS Ccp(C_A)-(C_B) = 270 nF 45 75 - mA

Efﬁciency

ηcp charge pump efﬁciency IO(VBUS) = 50 mA 60 72 78 %

Table 50. Static characteristics: VBUS comparators

= 3.0 V to 3.6 V; V

CC(I/O)

= 1.65 V to 1.95 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.3 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

VA_VBUS_VLD A-device VBUS valid voltage 4.4 4.5 4.65 V

VA_SESS_VLD A-device session valid voltage for A-device and

B-device 0.8 1.6 2.0 V

Vhys(A_SESS_VLD) A-device session valid hysteresis voltage 70 90 120 mV

VB_SESS_END B-device session end voltage 0.2 0.5 0.8 V

Table 51. Static characteristics: VBUS resistors

= 3.0 V to 3.6 V; V

CC(I/O)

= 1.65 V to 1.95 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.3 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

RUP(VBUS) pull-up resistance on

pin VBUS

connect to REG3V3 when

CHRG_VBUS is logic 1 281 680 - Ω

RDN(VBUS) pull-down resistance on

pin VBUS

connect to GND when

DISCHRG_VBUS is logic 1 656 1100 - Ω

RI(idle)(VBUS)(A) idle input resistance on

pin VBUS (A-device) ID pin LOW and charge pump

disabled 40 54 80 kΩ

RI(idle)(VBUS)(B) idle input resistance on

pin VBUS (B-device) ID pin HIGH or charge pump

enabled 170 230 310 kΩ

Table 52. Static characteristics: ID detection circuit

= 3.0 V to 3.6 V; V

CC(I/O)

= 1.65 V to 1.95 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.3 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

tID ID detection time 50 - - ms

Vth(ID) ID detector threshold voltage 0.8 1.2 2.0 V

RUP(ID) ID pull-up resistance ID_PULLUP is logic 1 40 50 60 kΩ

Product data sheet Rev. 02 — 28 August 2008 59 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

Table 53. Static characteristics: resistor reference

= 3.0 V to 3.6 V; V

CC(I/O)

= 1.65 V to 1.95 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.3 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

VO(RREF) output voltage on pin RREF SUSPENDM is logic 1 - 1.22 - V

ICC(cp) denotes the charge pump supply current.

Fig 22. Charge pump supply current as a function of

VBUS output current Fig 23. VBUS output voltage as a function of VBUS

output current

VCC(cp) denotes the charge pump supply voltage. ICC(cp) denotes the charge pump supply current.

Fig 24. VBUS output voltage as a function of charge

pump supply voltage Fig 25. Charge pump supply current as a function of

temperature

004aaa876

100

120

0 1020304050

VCC = 3.6 V

3.3 V

3.0 V

CC(cp)

(mA)

O(VBUS)

(mA)

004aaa877

4.00

4.50

5.00

5.50

0 1020304050

VCC = 3.6 V

3.3 V

3.0 V

O(VBUS)

(V)

O(VBUS)

(mA)

004aaa878

4.00

4.50

5.00

5.50

3 3.1 3.2 3.3 3.4 3.5 3.6

IO(VBUS) = 0 mA

8 mA

50 mA

O(VBUS)

(V)

CC(cp)

(V)

004aaa879

100

102

104

106

108

−40

−20

0 +20 +40 +60 +80 +100

IO(VBUS) = 50 mA

amb

(°C)

CC(cp)

(mA)

Product data sheet Rev. 02 — 28 August 2008 60 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

15. Dynamic characteristics

[1] The internal PLL is triggered only on the positive edge from the crystal oscillator. Therefore, the duty cycle is not critical.

Table 54. Dynamic characteristics: reset and clock

= 3.0 V to 3.6 V; V

CC(I/O)

= 1.65 V to 1.95 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.3 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Reset

tW(POR) internal power-on reset pulse

width 0.2 - - µs

tw(REG1V8_H) REG1V8 HIGH pulse width 2 - - µs

tw(REG1V8_L) REG1V8 LOW pulse width 11 - - µs

tW(RESET_N) external RESET_N pulse width 200 - - ns

tPWRUP regulator start-up time 4.7 µF±20 % capacitor

each on pins REG1V8

and REG3V3

--1ms

Crystal or clock applied to XTAL1

fi(XTAL1) input frequency on pin XTAL1 ISP1506ABS - 19.2 - MHz

ISP1506BBS - 26 - MHz

tjit(i)(XTAL1)RMS RMS input jitter on pin XTAL1 ISP1506ABS - - 200 ps

ISP1506BBS - - 300 ps

δi(XTAL1) input duty cycle on pin XTAL1 applicable only when

clock is applied on

pin XTAL1

[1] -50-%

∆fi(XTAL1) input frequency tolerance on

pin XTAL1 - 50 200 ppm

tr(XTAL1) rise time on pin XTAL1 only for square wave

input --5ns

tf(XTAL1) fall time on pin XTAL1 only for square wave

input --5ns

V(XTAL1)(p-p) peak-to-peak voltage on

pin XTAL1 only for square wave

input 0.566 - 1.95 V

Output CLOCK characteristics

fo(CLOCK) output frequency on pin CLOCK - 60 - MHz

tjit(o)(CLOCK)RMS RMS output jitter on pin CLOCK - - 500 ps

δo(CLOCK) output clock duty cycle on

pin CLOCK 45 50 55 %

tstartup(PLL) PLL start-up time - 650 - µs

tstartup(o)(CLOCK) output CLOCK start-up time measured from power

good or assertion of

pin STP

450 650 900 µs

Product data sheet Rev. 02 — 28 August 2008 61 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

Table 55. Dynamic characteristics: digital I/O pins

= 3.0 V to 3.6 V; V

CC(I/O)

= 1.65 V to 1.95 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

tsu(DATA) DATA set-up time with respect to

the rising edge of pin CLOCK 20 pF total external load

per pin 3.0 - - ns

th(DATA) DATA hold time with respect to

the rising edge of pin CLOCK 20 pF total external load

per pin 0- - ns

td(DATA) DATA output delay with respect

to the rising edge of pin CLOCK 20 pF total external load

per pin - - 5.0 ns

tsu(STP) STP set-up time with respect to

the rising edge of pin CLOCK 20 pF total external load

per pin 4.7 - - ns

th(STP) STP hold time with respect to

the rising edge of pin CLOCK 20 pF total external load

per pin 0- - ns

td(DIR) DIR output delay with respect to

the rising edge of pin CLOCK 20 pF total external load

per pin - - 8.7 ns

td(NXT) NXT output delay with respect to

the rising edge of pin CLOCK 20 pF total external load

per pin - - 8.7 ns

Table 56. Dynamic characteristics: analog I/O pins (DP and DM)

= 3.0 V to 3.6 V; V

CC(I/O)

= 1.65 V to 1.95 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

High-speed driver

tHSR rise time (10 % to 90 %) 500 - - ps

tHSF fall time (10 % to 90 %) 500 - - ps

Full-speed driver

tFR rise time CL= 50 pF; 10 % to 90 % of

|VOH −VOL|4 - 20 ns

tFF fall time CL= 50 pF; 10 % to 90 % of

|VOH −VOL|4 - 20 ns

tFRFM differential rise and fall

time matching excluding the ﬁrst transition from

the idle state 90 - 111.1 %

VCRS output signal crossover

voltage excluding the ﬁrst transition from

the idle state 1.3 - 2.0 V

Low-speed driver

tLR transition time: rise time CL= 200 pF to 600 pF; 1.5 kΩ

pull-up on pin DM enabled; 10 %

to 90 % of |VOH −VOL|

75 - 300 ns

tLF transition time: fall time CL= 200 pF to 600 pF; 1.5 kΩ

pull-up on pin DM enabled; 10 %

to 90 % of |VOH −VOL|

75 - 300 ns

tLRFM rise and fall time matching tLR/tLF; excluding the ﬁrst

transition from the idle state 80 - 125 %

Driver timing

tPLH(drv) driver propagation delay

(LOW to HIGH) DAT, SE0 to DP, DM;

see Figure 27 --11ns

tPHL(drv) driver propagation delay

(HIGH to LOW) DAT, SE0 to DP, DM;

see Figure 27 --11ns

Product data sheet Rev. 02 — 28 August 2008 62 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

15.1 ULPI timing

ULPI interface timing requirements are given in Figure 30. This timing applies to

synchronous mode only. All timing is measured with respect to the ISP1506 CLOCK pin.

All signals are clocked on the rising edge of CLOCK.

tPHZ driver disable delay from

HIGH level TX_ENABLE to DP, DM;

see Figure 28 --12ns

tPLZ driver disable delay from

LOW level TX_ENABLE to DP, DM;

see Figure 28 --12ns

tPZH driver enable delay to

HIGH level TX_ENABLE to DP, DM;

see Figure 28 --20ns

tPZL driver enable delay to

LOW level TX_ENABLE to DP, DM;

see Figure 28 --20ns

Receiver timing

Differential receiver

tPLH(rcv) receiver propagation

delay (LOW to HIGH) DP, DM to DAT, SE0;

see Figure 29 --17ns

tPHL(rcv) receiver propagation

delay (HIGH to LOW) DP, DM to DAT, SE0;

see Figure 29 --17ns

Table 56. Dynamic characteristics: analog I/O pins (DP and DM)

…continued

= 3.0 V to 3.6 V; V

CC(I/O)

= 1.65 V to 1.95 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Fig 26. Rise time and fall time Fig 27. Timing of DAT and SE0 when transmitting to

DP and DM

Fig 28. Timing of TX_ENABLE to DP and DM Fig 29. Timing of DAT and SE0 when receiving from

DP and DM

004aaa861

VOL

tHSR, tFR, tLR tHSF, tFF, tLF

VOH 90 %

10 % 10 %

90 %

004aaa573

VOL

VOH

tPHL(drv)

tPLH(drv)

VCRS VCRS

0.9 V

1.8 V

0 V

logic input

differential

data lines

004aaa574

VOL

VOH

tPZH

tPZL tPHZ

tPLZ

VOH − 0.3 V

VOL + 0.3 V

VCRS

0.9 V

1.8 V

0 V

logic

input

differential

data lines

004aaa985

VOL

VOH

tPHL(rcv)

tPLH(rcv)

VCRS VCRS

0.9 V

2.0 V

0.8 V

logic output

differential

data lines

Product data sheet Rev. 02 — 28 August 2008 63 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

Fig 30. ULPI timing interface

CLOCK

CONTROL IN

(STP)

DATA IN

(8-BIT)

tsu(STP) th(STP)

tsu(DATA) th(DATA)

CONTROL OUT

(DIR, NXT)

DATA OUT

(8-BIT)

004aaa722

td(DIR),

td(NXT)

td(DATA) td(DIR),

td(NXT)

Product data sheet Rev. 02 — 28 August 2008 64 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

16. Application information

[1] For detailed information, refer to application note Ref. 7 “Interfacing to the ISP1504/5/6 (AN10048)”.

Table 57. Recommended bill of materials

Designator[1] Application Value Comment

Cbypass highly recommended for

all applications 0.1 µF-

Ccp(C_A)-(C_B) charge pump is used 22 nF (8 mA), 270 nF (50 mA);

up to 470 nF (50 mA) -

Cﬁlter highly recommended for

all applications 4.7 µF±20 %; use a LOW ESR

capacitor (0.2 Ωto 2 Ω) for best

performance

CVBUS mandatory for peripherals 0.1 µF and 1 µFto10µF in

parallel -

mandatory for host 0.1 µF and 120 µF±20 % (min)

in parallel -

mandatory for OTG 0.1 µF and 1 µF to 6.5 µF in

parallel -

DESD recommended for all

ESD-sensitive applications IP4359CX4/LF Wafer-Level Chip-Scale Package (WLCSP);

ESD IEC 61000-4-2 level 4; ±15 kV contact;

±15 kV air discharge compliant protection

Rpullup recommended; for

applications with an

external VBUS supply

controlled by PSW_N

4.7 kΩ (recommended) maximum value is determined by the voltage

drop on PSW_N caused by leakage into

PSW_N and the external supply control pin

RRREF mandatory in all

applications 12 kΩ±1% -

RVBUS strongly recommended for

peripheral or external 5 V

applications only

1kΩ±5% -

RXTAL required only for

applications driving a

square wave into the

XTAL1 pin

47 kΩ±5 % used to avoid ﬂoating input on the XTAL1 pin

XTAL crystal is used 19.2 MHz CL= 10 pF; RS< 220 Ω; CXTAL =18pF

26 MHz CL= 10 pF; RS< 130 Ω; CXTAL =18pF

C(XTAL)SQ required only for

applications driving a

square wave into the

XTAL1 pin that has a DC

offset

100 pF used to AC couple the input square wave to

the XTAL1 pin

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Product data sheet Rev. 02 — 28 August 2008 65 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

(1) Frequency is version dependent: ISP1506A: 19.2 MHz; ISP1506B: 26 MHz.

Fig 31. Using the ISP1506 with an OTG controller; internal charge pump is utilized and crystal is attached

ISP1506

VCC(I/O)

RREF

CPGND

C_B

C_A

VCC

DATA0

DATA1

DATA2

VCC(I/O)

DATA3

CLOCK

NXT

STP

DIR

REG1V8

RESET_N/PSW_N

004aaa602

VBUS/FAULT

REG3V3

XTAL1 12

XTAL2

OTG

CONTROLLER

SHIELD

VBUS

D−

D+

GND

1DATA0

DATA3

CLOCK

NXT

STP

DIR

VCC(I/O)

VCC

Cbypass

Ccp(C_A)-(C_B)

RRREF

CVBUS

CXTAL

XTAL(1)

GND (die pad)

DATA1

DATA2

Cfilter Cbypass

CXTAL

Cbypass Cfilter

USB MICRO-AB

RECEPTACLE

Cbypass

IP4359CX4/LF

A1 A2

DESD

Cbypass

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 02 — 28 August 2008 66 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

(1) Frequency is version dependent: ISP1506A: 19.2 MHz; ISP1506B: 26 MHz.

Fig 32. Using the ISP1506 with an OTG controller; external charge pump using ISP1506 internal VBUS valid and external square wave input on XTAL1

004aaa887

VCC(I/O)

VCC

ISP1506

IP4359CX4/LF

RREF

RRREF

RVBUS

RXTAL

C(XTAL)SQ

fi(XTAL1)(1)

CPGND

C_B

DATA0

DATA1

DATA2

DATA3

CLOCK

NXT

OTG

CONTROLLER

STP

DIR

C_A

VCC

VBUS/FAULT

REG3V3

DATA0

Cbypass

Cfilter

CVBUS

Cbypass

Cfilter

Cbypass

Rpullup

DATA1

DATA2

VCC(I/O)

DATA3

CLOCK

NXT

STP

DIR

REG1V8

RESET_N/PSW_N

XTAL2

CHARGE

PUMP

+3.3 V IN +5 V

OUT

VBUS

D−

D+

A1 A2

GND

SHIELD

DESD

GND (die pad)

USB MICRO-AB

RECEPTACLE

XTAL1

Cbypass

B1 B2

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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 02 — 28 August 2008 67 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

(1) Frequency is version dependent: ISP1506A: 19.2 MHz; ISP1506B: 26 MHz.

Fig 33. Using the ISP1506 with a standard USB host controller; external 5 V source with built-in FAULT and external square wave input on XTAL1

ISP1506

VCC(I/O)

RREF

CPGND

C_B

C_A

VCC

DATA0

DATA1

VCC(I/O)

DATA2

DATA3

CLOCK

NXT

004aaa888

VBUS/FAULT

REG3V3

XTAL2

STP

DIR

REG1V8

RESET_N/PSW_N

HOST

CONTROLLER

USB

STANDARD-A

RECEPTACLE

VBUS

D−

D+

GND

DATA0

DATA1

DATA2

DATA3

CLOCK

NXT

STP

DIR

VCC(I/O)

VCC

GND (die pad)

IN FAULT

ON OUT

VBUS

SWITCH

Rpullup

Cbypass

RRREF

CVBUS

Cbypass Cfilter

SHIELD

+5 V

IP4359CX4/LF

A1 A3

Cbypass

fi(XTAL1)(1) RXTAL

XTAL1

C(XTAL)SQ

B1 B2

Cbypass

DESD

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 02 — 28 August 2008 68 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

(1) Frequency is version dependent: ISP1506A: 19.2 MHz; ISP1506B: 26 MHz.

Fig 34. Using the ISP1506 with a standard USB peripheral controller; external crystal is used

ISP1506

VCC(I/O)

RREF

CPGND

C_B

C_A

VCC

DATA0

DATA1

VCC(I/O)

DATA3

CLOCK

NXT

004aaa889

VBUS/FAULT

REG3V3

XTAL1

XTAL2 13

STP

DIR

REG1V8

RESET_N/

PSW_N

PERIPHERAL

CONTROLLER

USB

STANDARD-B

RECEPTACLE

VBUS

D−

D+

GND

DATA0

DATA1

DATA2

DATA3

CLOCK

NXT

STP

DIR

VCC(I/O)

VCC

GND (die pad)

Cbypass

Cbypass Cfilter

CXTAL CXTAL

Cbypass Cfilter

RRREF

CVBUS

SHIELD

SHIELD RVBUS

IP4359CX4/LF

A1 A2

XTAL(1)

DESD

DATA2

Cbypass

B1 B2

Product data sheet Rev. 02 — 28 August 2008 69 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

17. Package outline

Fig 35. Package outline SOT616-1 (HVQFN24)

0.51 0.2

A1Eh

UNIT ye

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.1

3.9

2.25

1.95

4.1

3.9 2.25

1.95

2.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT616-1 MO-220 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT616-1

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

712

24 19

01-08-08

02-10-22

terminal 1

index area

terminal 1

index area

1/2 e

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 02 — 28 August 2008 70 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

18. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

18.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

Product data sheet Rev. 02 — 28 August 2008 71 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

18.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 36) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 58 and 59

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 36.

Table 58. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 59. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 02 — 28 August 2008 72 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

19. Abbreviations

MSL: Moisture Sensitivity Level

Fig 36. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 60. Abbreviations

Acronym Description

ASIC Application-Speciﬁc Integrated Circuit

ATX Analog USB Transceiver

CD-RW Compact Disc-ReWritable

EOP End-Of-Packet

ESD ElectroStatic Discharge

ESR Effective Series Resistance

FS Full-Speed

HBM Human Body Model

HNP Host Negotiation Protocol

HS High-Speed

ID Identiﬁcation

IEC International Electrotechnical Commission

LS Low-Speed

NRZI Non-Return-to-Zero Inverted

OTG On-The-Go

PCB Printed-Circuit Board

PHY Physical Layer

PID Packet Identiﬁer

PLL Phase-Locked Loop

Product data sheet Rev. 02 — 28 August 2008 73 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

20. References

[1] Universal Serial Bus Speciﬁcation Rev. 2.0

[2] On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.3

[3] UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1

[4] UTMI+ Speciﬁcation Rev. 1.0

[5] USB 2.0 Transceiver Macrocell Interface (UTMI) Speciﬁcation Ver. 1.05

[6] Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)

(JESD22-A114D)

[7] Interfacing to the ISP1504/5/6 (AN10048)

POR Power-On Reset

RXCMD Receive Command

SE0 Single-Ended Zero

SOF Start-Of-Frame

SRP Session Request Protocol

SYNC Synchronous

TTL Transistor-Transistor Logic

TXCMD Transmit Command

USB Universal Serial Bus

USB-IF USB Implementers Forum

ULPI UTMI+ Low Pin Interface

UTMI USB 2.0 Transceiver Macrocell Interface

UTMI+ USB 2.0 Transceiver Macrocell Interface Plus

Table 60. Abbreviations

…continued

Acronym Description

Product data sheet Rev. 02 — 28 August 2008 74 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

21. Revision history

Table 61. Revision history

Document ID Release date Data sheet status Change notice Supersedes

ISP1506A_ISP1506B_2 20080828 Product data sheet - ISP1506A_ISP1506B_1

Modiﬁcations: •Globally changed mini-USB, mini-A and mini-B connectors to micro-USB, micro-A and

micro-B connectors, respectively.

•Section 8.2 “USB and OTG state transitions”: updated the ﬁrst sentence.

•Figure 6 “Power-up and reset sequence required before the ULPI bus is ready for use”:

updated.

•Section 9.4.2 “Fault detection”: updated.

•Section “Standard USB host controllers”: updated the ﬁrst list item.

•Section “OTG devices”: updated the last sentence.

•Section 9.10.1 “Full-speed or low-speed host-initiated suspend and resume”: updated list

item 2.

•Section 9.10.2 “High-speed suspend and resume”: updated list item 2.

•Table 42 “Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit

description”: updated description of bits 3 and 2.

•Table 43 “Limiting values” and Table 44 “Recommended operating conditions”: removed

CLOCK from the conditions column.

ISP1506A_ISP1506B_1 20070530 Product data sheet - -

Product data sheet Rev. 02 — 28 August 2008 75 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

22. Legal information

22.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

22.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

22.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

22.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

23. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

Product data sheet Rev. 02 — 28 August 2008 76 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

24. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 3. Recommended charge pump capacitor value .12

Table 4. ULPI signal description . . . . . . . . . . . . . . . . . .15

Table 5. Signal mapping during low-power mode . . . . .16

Table 6. Signal mapping for 3-pin serial mode . . . . . . .17

Table 7. Operating states and their corresponding

resistor settings . . . . . . . . . . . . . . . . . . . . . . . .18

Table 8. OTG Control register power control bits . . . . .24

Table 9. TXCMD byte format . . . . . . . . . . . . . . . . . . . . .24

Table 10. RXCMD byte format . . . . . . . . . . . . . . . . . . . . .25

Table 11. LINESTATE[1:0] encoding for upstream

facing ports: peripheral . . . . . . . . . . . . . . . . . .26

Table 12. LINESTATE[1:0] encoding for downstream

facing ports: host . . . . . . . . . . . . . . . . . . . . . . .26

Table 13. Encoded VBUS voltage state . . . . . . . . . . . . . .26

Table 14. VBUS indicators in RXCMD required for

typical applications . . . . . . . . . . . . . . . . . . . . . .27

Table 15. Encoded USB event signals . . . . . . . . . . . . . .28

Table 16. PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .32

Table 17. Link decision times . . . . . . . . . . . . . . . . . . . . .33

Table 18. Immediate register set overview . . . . . . . . . . .44

Table 19. Extended register set overview . . . . . . . . . . . .44

Table 20. Vendor ID Low register (address R = 00h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 21. Vendor ID High register (address R = 01h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 22. Product ID Low register (address R = 02h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 23. Product ID High register (address R = 03h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 24. Function Control register (address R = 04h

to 06h, W = 04h, S = 05h, C = 06h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 25. Function Control register (address R = 04h

to 06h, W = 04h, S = 05h, C = 06h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 26. Interface Control register (address R = 07h

to 09h, W = 07h, S = 08h, C = 09h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 27. Interface Control register (address R = 07h

to 09h, W = 07h, S = 08h, C = 09h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 28. OTG Control register (address R = 0Ah

to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 29. OTG Control register (address R = 0Ah

to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 30. USB Interrupt Enable Rising Edge register

(address R = 0Dh to 0Fh, W = 0Dh,

S = 0Eh, C = 0Fh) bit allocation . . . . . . . . . . . .48

Table 31. USB Interrupt Enable Rising Edge register

(address R = 0Dh to 0Fh, W = 0Dh,

S = 0Eh, C = 0Fh) bit description . . . . . . . . . .49

Table 32. USB Interrupt Enable Falling Edge register

(address R = 10h to 12h, W = 10h,

S = 11h, C = 12h) bit allocation . . . . . . . . . . . .49

Table 33. USB Interrupt Enable Falling Edge

W = 10h, S = 11h, C = 12h) bit description . . .49

Table 34. USB Interrupt Status register

(address R = 13h) bit allocation . . . . . . . . . . .50

Table 35. USB Interrupt Status register

(address R = 13h) bit description . . . . . . . . . .50

Table 36. USB Interrupt Latch register

(address R = 14h) bit allocation . . . . . . . . . . .50

Table 37. USB Interrupt Latch register

(address R = 14h) bit description . . . . . . . . . .50

Table 38. Debug register (address R = 15h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 39. Debug register (address R = 15h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 40. Scratch register (address R = 16h to 18h,

W = 16h, S = 17h, C = 18h) bit description . . .51

Table 41. Power Control register (address R = 3Dh

to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 42. Power Control register (address R = 3Dh

to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 43. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 44. Recommended operating conditions . . . . . . . .54

Table 45. Static characteristics: supply pins . . . . . . . . . .55

Table 46. Static characteristics: digital pins

(CLOCK, DIR, STP, NXT, DATA[3:0],

RESET_N/PSW_N) . . . . . . . . . . . . . . . . . . . . .55

Table 47. Static characteristics: digital pin FAULT . . . . .56

Table 48. Static characteristics: analog I/O pins

(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 49. Static characteristics: charge pump . . . . . . . .58

Table 50. Static characteristics: VBUS comparators . . . .58

Table 51. Static characteristics: VBUS resistors . . . . . . . .58

Table 52. Static characteristics: ID detection circuit . . . .58

Table 53. Static characteristics: resistor reference . . . . .59

Table 54. Dynamic characteristics: reset and clock . . . .60

Table 55. Dynamic characteristics: digital I/O pins . . . . .61

Table 56. Dynamic characteristics: analog I/O pins

(DP and DM) . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 57. Recommended bill of materials . . . . . . . . . . . .64

Table 58. SnPb eutectic process (from J-STD-020C) . . .71

Table 59. Lead-free process (from J-STD-020C) . . . . . .71

Table 60. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 61. Revision history . . . . . . . . . . . . . . . . . . . . . . . .74

Product data sheet Rev. 02 — 28 August 2008 77 of 79

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

25. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 2. Pin conﬁguration HVQFN24; top view . . . . . . . . . .5

Fig 3. External capacitors connection . . . . . . . . . . . . . .10

Fig 4. Charge pump capacitor . . . . . . . . . . . . . . . . . . . .11

Fig 5. Internal power-on reset timing . . . . . . . . . . . . . . .20

Fig 6. Power-up and reset sequence required before

the ULPI bus is ready for use. . . . . . . . . . . . . . . .22

Fig 7. Interface behavior with respect to RESET_N. . . .23

Fig 8. Single and back-to-back RXCMDs from the

ISP1506 to the link. . . . . . . . . . . . . . . . . . . . . . . .25

Fig 9. RXCMD A_VBUS_VLD indicator source. . . . . . .27

Fig 10. Example of register write, register read,

extended register write and extended

Fig 11. USB reset and high-speed detection handshake

(chirp) sequence . . . . . . . . . . . . . . . . . . . . . . . . .31

Fig 12. Example of using the ISP1506 to transmit and

receive USB data. . . . . . . . . . . . . . . . . . . . . . . . .32

Fig 13. High-speed transmit-to-transmit packet timing. . .33

Fig 14. High-speed receive-to-transmit packet timing . . .34

Fig 15. Preamble sequence. . . . . . . . . . . . . . . . . . . . . . .35

Fig 16. Full-speed suspend and resume . . . . . . . . . . . . .36

Fig 17. High-speed suspend and resume . . . . . . . . . . . .38

Fig 18. Remote wake-up from low-power mode . . . . . . .40

Fig 19. Transmitting USB packets without the automatic

SYNC and EOP generation . . . . . . . . . . . . . . . . .41

Fig 20. Example of transmit followed by receive in 3-pin

serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Fig 21. Human body ESD test model. . . . . . . . . . . . . . . .53

Fig 22. Charge pump supply current as a function

of VBUS output current . . . . . . . . . . . . . . . . . . . . .59

Fig 23. VBUS output voltage as a function of VBUS

output current. . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Fig 24. VBUS output voltage as a function of charge

pump supply voltage . . . . . . . . . . . . . . . . . . . . . .59

Fig 25. Charge pump supply current as a function of

temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Fig 26. Rise time and fall time . . . . . . . . . . . . . . . . . . . . .62

Fig 27. Timing of DAT and SE0 when transmitting to

DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Fig 28. Timing of TX_ENABLE to DP and DM. . . . . . . . .62

Fig 29. Timing of DAT and SE0 when receiving from

DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Fig 30. ULPI timing interface . . . . . . . . . . . . . . . . . . . . . .63

Fig 31. Using the ISP1506 with an OTG controller;

internal charge pump is utilized and crystal

is attached . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Fig 32. Using the ISP1506 with an OTG controller;

external charge pump using ISP1506

internal VBUS valid and external square

wave input on XTAL1 . . . . . . . . . . . . . . . . . . . . . .66

Fig 33. Using the ISP1506 with a standard USB host

controller; external 5 V source with built-in FAULT

and external square wave input on XTAL1. . . . . .67

Fig 34. Using the ISP1506 with a standard USB

peripheral controller; external crystal is used . . .68

Fig 35. Package outline SOT616-1 (HVQFN24) . . . . . . .69

Fig 36. Temperature proﬁles for large and small

components. . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Product data sheet Rev. 02 — 28 August 2008 78 of 79

continued >>

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

26. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Functional description . . . . . . . . . . . . . . . . . . . 7

7.1 ULPI interface controller . . . . . . . . . . . . . . . . . . 7

7.2 USB data serializer and deserializer. . . . . . . . . 7

7.3 Hi-Speed USB (USB 2.0) ATX . . . . . . . . . . . . . 7

7.4 Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . 8

7.5 Crystal oscillator and PLL. . . . . . . . . . . . . . . . . 8

7.6 OTG module. . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.6.1 ID detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.6.2 VBUS comparators. . . . . . . . . . . . . . . . . . . . . . . 9

7.6.2.1 VBUS valid comparator . . . . . . . . . . . . . . . . . . . 9

7.6.2.2 Session valid comparator . . . . . . . . . . . . . . . . . 9

7.6.2.3 Session end comparator. . . . . . . . . . . . . . . . . . 9

7.6.3 SRP charge and discharge resistors . . . . . . . . 9

7.6.4 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.7 Band gap reference voltage . . . . . . . . . . . . . . 10

7.8 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 10

7.9 Detailed description of pins . . . . . . . . . . . . . . 10

7.9.1 DATA[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.9.2 VCC(I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.9.3 RREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.9.4 DP and DM. . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.9.5 ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.9.6 CPGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.9.7 C_A and C_B . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.9.8 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.9.9 VBUS/FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.9.9.1 VBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.9.9.2 FAULT (external overcurrent or fault detector) 12

7.9.10 REG3V3 and REG1V8 . . . . . . . . . . . . . . . . . . 12

7.9.11 XTAL1 and XTAL2. . . . . . . . . . . . . . . . . . . . . . 12

7.9.12 RESET_N/PSW_N . . . . . . . . . . . . . . . . . . . . . 13

7.9.12.1 RESET_N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.9.12.2 PSW_N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.9.13 DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.9.14 STP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.9.15 NXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.9.16 CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.9.17 GND (die pad). . . . . . . . . . . . . . . . . . . . . . . . . 14

8 Modes of operation . . . . . . . . . . . . . . . . . . . . . 15

8.1 ULPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.1.1 Synchronous mode . . . . . . . . . . . . . . . . . . . . 15

8.1.2 Low-power mode . . . . . . . . . . . . . . . . . . . . . . 16

8.1.3 3-pin full-speed or low-speed serial mode . . . 17

8.2 USB and OTG state transitions . . . . . . . . . . . 17

9 Protocol description . . . . . . . . . . . . . . . . . . . . 20

9.1 ULPI references . . . . . . . . . . . . . . . . . . . . . . . 20

9.2 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 20

9.3 Power-up, reset and bus idle sequence . . . . . 20

9.3.1 Interface protection. . . . . . . . . . . . . . . . . . . . . 22

9.3.2 Interface behavior with respect to RESET_N. 23

9.4 VBUS power and fault detection . . . . . . . . . . . 23

9.4.1 Driving 5 V on VBUS . . . . . . . . . . . . . . . . . . . . 23

9.4.2 Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 24

9.5 TXCMD and RXCMD. . . . . . . . . . . . . . . . . . . 24

9.5.1 TXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.5.2 RXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9.5.2.1 Linestate encoding. . . . . . . . . . . . . . . . . . . . . 25

9.5.2.2 VBUS state encoding. . . . . . . . . . . . . . . . . . . . 26

9.5.2.3 Using and selecting the VBUS state encoding. 27

9.5.2.4 RxEvent encoding . . . . . . . . . . . . . . . . . . . . . 28

9.6 Register read and write operations . . . . . . . . 29

9.7 USB reset and high-speed detection

handshake (chirp) . . . . . . . . . . . . . . . . . . . . . 29

9.8 USB packet transmit and receive. . . . . . . . . . 32

9.8.1 USB packet timing . . . . . . . . . . . . . . . . . . . . . 32

9.8.1.1 ISP1506 pipeline delays. . . . . . . . . . . . . . . . . 32

9.8.1.2 Allowed link decision time . . . . . . . . . . . . . . . 32

9.9 Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9.10 USB suspend and resume. . . . . . . . . . . . . . . 35

9.10.1 Full-speed or low-speed host-initiated suspend

and resume . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.10.2 High-speed suspend and resume . . . . . . . . . 36

9.10.3 Remote wake-up . . . . . . . . . . . . . . . . . . . . . . 39

9.11 No automatic SYNC and EOP generation

(optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.12 On-The-Go operations. . . . . . . . . . . . . . . . . . 41

9.12.1 OTG charge pump . . . . . . . . . . . . . . . . . . . . . 42

9.12.2 OTG comparators. . . . . . . . . . . . . . . . . . . . . . 42

9.12.3 Pull-up and pull-down resistors . . . . . . . . . . . 42

9.12.4 ID detection . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.12.5 VBUS charge and discharge resistors. . . . . . . 42

9.13 Serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.14 Aborting transfers. . . . . . . . . . . . . . . . . . . . . . 43

9.15 Avoiding contention on the ULPI data bus. . . 43

10 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10.1 Immediate register set . . . . . . . . . . . . . . . . . . 45

NXP Semiconductors ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 28 August 2008

Document identifier: ISP1506A_ISP1506B_2

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

10.1.1 Vendor ID and Product ID registers . . . . . . . . 45

10.1.1.1 Vendor ID Low register . . . . . . . . . . . . . . . . . . 45

10.1.1.2 Vendor ID High register . . . . . . . . . . . . . . . . . 45

10.1.1.3 Product ID Low register . . . . . . . . . . . . . . . . . 45

10.1.1.4 Product ID High register . . . . . . . . . . . . . . . . . 45

10.1.2 Function Control register . . . . . . . . . . . . . . . . 45

10.1.3 Interface Control register . . . . . . . . . . . . . . . . 46

10.1.4 OTG Control register . . . . . . . . . . . . . . . . . . . 47

10.1.5 USB Interrupt Enable Rising Edge register . . 48

10.1.6 USB Interrupt Enable Falling Edge register . . 49

10.1.7 USB Interrupt Status register . . . . . . . . . . . . . 49

10.1.8 USB Interrupt Latch register. . . . . . . . . . . . . . 50

10.1.9 Debug register . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.10 Scratch register. . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.11 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.12 Access extended register set . . . . . . . . . . . . . 51

10.1.13 Vendor-speciﬁc registers . . . . . . . . . . . . . . . . 51

10.1.14 Power Control register . . . . . . . . . . . . . . . . . . 51

10.2 Extended register set . . . . . . . . . . . . . . . . . . . 52

11 ElectroStatic Discharge (ESD) . . . . . . . . . . . . 53

11.1 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . 53

11.2 ESD test conditions . . . . . . . . . . . . . . . . . . . . 53

12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 54

13 Recommended operating conditions. . . . . . . 54

14 Static characteristics. . . . . . . . . . . . . . . . . . . . 55

15 Dynamic characteristics . . . . . . . . . . . . . . . . . 60

15.1 ULPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 62

16 Application information. . . . . . . . . . . . . . . . . . 64

17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 69

18 Soldering of SMD packages . . . . . . . . . . . . . . 70

18.1 Introduction to soldering . . . . . . . . . . . . . . . . . 70

18.2 Wave and reﬂow soldering . . . . . . . . . . . . . . . 70

18.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 70

18.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 71

19 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 72

20 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

21 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 74

22 Legal information. . . . . . . . . . . . . . . . . . . . . . . 75

22.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 75

22.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

22.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 75

22.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 75

23 Contact information. . . . . . . . . . . . . . . . . . . . . 75

24 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

25 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

26 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78