YDA147 D- 515 STEREO 5W-15W DIGITAL AUDIO POWER AMPLIFIER General Description YDA147 (D-515) is a high-efficiency digital audio power amplifier IC with the maximum output of 15W x 2ch. YDA147 has a "Pure Pulse Direct Speaker Drive Circuit" that directly drives speakers while reducing distortion of pulse output signal and reducing noise on the signal, which realizes the highest standard low distortion rate characteristics and low noise characteristics among digital amplifier ICs in the same class. In addition, supporting filterless design allows circuit design with fewer external parts to be realized depending on use conditions. YDA147 features Power Limit Function, Non-clip Function, and DRC (Dynamic Range Control) Function that were developed by Yamaha original digital amplifier technology. YDA147 has overcurrent protection function for speaker output terminals, high temperature protection function, and lowsupply voltage malfunction prevention function. Features Operating supply voltage range PVDD: 8.0V to 16.5V Maximum momentary output 20 Wx2ch (VDDP=14V, RL=4, THD+N=10%) 15 Wx2ch (VDDP=12V, RL=4, THD+N=10%) Maximum continuous output 15 W*1x2ch (VDDP=15V, RL=8, THD+N=10%, Ta=70C, SQFP48, 4 layers) 10.5W*1x2ch (VDDP=15V, RL=4, THD+N=10%, Ta=25C, SQFP48, 4 layers) 10 W*1x2ch (VDDP=12V, RL=8, THD+N=10%, Ta=25C, LQFP48, 1 layer) Distortion Rate (THD+N) 0.01 % (VDDP=12V, RL=8, Po=0.1W, 1kHz) Residual Noise 48Vrms (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L) Efficiency 92 % (VDDP=12V, RL=8) S/N Ratio 105 dB (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L) Channel separation -80 dB (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L) PSRR 60dB (VDDP=12V,Vripple=100mV, 1kHz, GAIN[1:0]=L,L, NCDRC[1:0]=L,L) Non-clip function/DRC function (switchable) Power limit function Clock External Synchronization Function Master/Slave Synchronization Function using clock outputs Over-current Protection Function, High Temperature Protection Function, Low Voltage Malfunction Prevention Function, and DC Detection Function Sleep Function using SLEEPN terminal and Output Mute Function using MUTEN terminal Stereo/Monaural Switching Function Spread Clock Function Pop Noise Reduction Function Package Lead-free 48-pin Plastic SQFP (Exposed stage) Lead-free 48-pin Plastic LQFP Note) *1: A value based on Yamaha's board implementation conditions (See Note *2,*3 of page 28) YDA147 CATALOG CATALOG No.:LSI-4DA147A61 2009.1 YDA147 PVDDPL PVDDPL OUTPL OUTPL OUTPL PVSSL PVSSL OUTML OUTML OUTML PVDDML PVDDML Terminal Configuration 48 47 46 45 44 43 42 41 40 39 38 37 N.C. 1 36 N.C. N.C. 2 35 N.C. PVDDREG 3 34 GAIN1 AVDD 4 33 GAIN0 INLP 5 32 NCDRC1 INLM 6 31 NCDRC0 VREF 7 30 CKIN INRM 8 29 CKOUT INRP 9 28 MUTEN AVSS 10 27 PROTN PLIMIT 11 26 SLEEPN N.C. 12 25 N.C. 18 19 20 21 22 23 24 OUTMR OUTMR OUTMR PVDDMR PVDDMR OUTPR 17 PVSSR PVDDPR 16 PVSSR 15 OUTPR 14 OUTPR 13 PVDDPR SQFP48 < 48-pin SQFP Top View > 2 CATALOG No.:LSI-4DA147A61 VSS VSS VSS PVDDPL OUTPL OUTPL PVSSL OUTML OUTML PVDDML VSS VSS YDA147 48 47 46 45 44 43 42 41 40 39 38 37 VSS 1 36 VSS PVDDREG 2 35 N.C. AVDD 3 34 GAIN1 N.C. 4 33 GAIN0 INLP 5 32 NCDRC1 INLM 6 31 NCDRC0 VREF 7 30 CKIN INRM 8 29 CKOUT INRP 9 28 MUTEN AVSS 10 27 PROTN PLIMIT 11 26 SLEEPN VSS 12 25 VSS 13 14 15 16 17 18 19 20 21 22 23 24 VSS VSS PVDDPR OUTPR OUTPR PVSSR OUTMR OUTMR PVDDMR VSS VSS VSS LQFP48 < 48-pin LQFP Top View > (Note) VSS pin should be connected to the ground pattern as wide as possible to improve the heat radiation. CATALOG No.:LSI-4DA147A61 3 YDA147 Terminal Function <48-pin SQFP > No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name *4) NC NC PVDDREG AVDD INLP INLM VREF INRM INRP AVSS PLIMIT NC PVDDPR PVDDPR OUTPR OUTPR OUTPR PVSSR PVSSR OUTMR OUTMR OUTMR PVDDMR PVDDMR NC SLEEPN PROTN MUTEN CKOUT CKIN NCDRC0 NCDRC1 GAIN0 GAIN1 NC NC PVDDML PVDDML OUTML OUTML OUTML PVSSL PVSSL OUTPL OUTPL OUTPL PVDDPL PVDDPL I/O *1), *2), *3) PVDD OA IA IA OA IA IA GND IA PVDD PVDD O O O GND GND O O O PVDD PVDD I O/D I O I I I I I PVDD PVDD O O O GND GND O O O PVDD PVDD Function Normally, use this terminal with nothing connected. Normally, use this terminal with nothing connected. Power supply terminal for regulators 3.3V regulator output terminal Analog input terminal (Lch+) Analog input terminal (Lch-) Reference voltage output terminal Analog input terminal (Rch-) Analog input terminal (Rch+) Analog ground terminal Power limit setting terminal Normally, use this terminal with nothing connected. Power supply terminal for digital amplifier output (Rch+) Power supply terminal for digital amplifier output (Rch+) Digital amplifier output terminal (Rch+) Digital amplifier output terminal (Rch+) Digital amplifier output terminal (Rch+) Ground terminal for digital amplifier output (Rch) Ground terminal for digital amplifier output (Rch) Digital amplifier output terminal (Rch-) Digital amplifier output terminal (Rch-) Digital amplifier output terminal (Rch-) Power supply terminal for digital amplifier output (Rch-) Power supply terminal for digital amplifier output (Rch-) Normally, use this terminal with nothing connected. Sleep control terminal *5) Error flag output terminal MUTE control terminal Clock output terminal for synchronization External clock input terminal Non-clip/DRC1/DRC2 mode selection terminal 0 Non-clip/DRC1/DRC2 mode selection terminal 1 GAIN setting terminal 0 GAIN setting terminal 1 Normally, use this terminal with nothing connected. Normally, use this terminal with nothing connected. Power supply terminal for digital amplifier output (Lch-) Power supply terminal for digital amplifier output (Lch-) Digital amplifier output terminal (Lch-) Digital amplifier output terminal (Lch-) Digital amplifier output terminal (Lch-) Ground terminal for digital amplifier output (Lch) Ground terminal for digital amplifier output (Lch) Digital amplifier output terminal (Lch+) Digital amplifier output terminal (Lch+) Digital amplifier output terminal (Lch+) Power supply terminal for digital amplifier output (Lch+) Power supply terminal for digital amplifier output (Lch+) (Notes) *1: I: Input terminal, O: Output terminal, A: Analog terminal, O/D: Open/Drain output terminal *2: PVDD should be connected each other on a board. *3: GND should be connected each other on a board. *4: Each output terminal with the same name (OUTPR, OUTMR, OUTPL, and OUTML) should be connected on a board. *5: Don't use the terminal AVDD to apply "H" level to the terminal SLEEPN. When the terminal SLEEPN is "L" level, the terminal AVDD is not supplied. 4 CATALOG No.:LSI-4DA147A61 YDA147 < 48-pin LQFP > No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name *4) VSS PVDDREG AVDD NC INLP INLM VREF INRM INRP AVSS PLIMIT VSS VSS VSS PVDDPR OUTPR OUTPR PVSSR OUTMR OUTMR PVDDMR VSS VSS VSS VSS SLEEPN PROTN MUTEN CKOUT CKIN NCDRC0 NCDRC1 GAIN0 GAIN1 NC VSS VSS VSS PVDDML OUTML OUTML PVSSL OUTPL OUTPL PVDDPL VSS VSS VSS I/O *1), *2), *3) GND PVDD OA IA IA OA IA IA GND IA GND GND GND PVDD O O GND O O PVDD GND GND GND GND I O/D I O I I I I I GND GND GND PVDD O O GND O O PVDD GND GND GND Function Power supply terminal for regulators 3.3V regulator output terminal Normally, use this terminal with nothing connected. Analog input terminal (Lch+) Analog input terminal (Lch-) Reference voltage output terminal Analog input terminal (Rch-) Analog input terminal (Rch+) Analog ground terminal Power limit setting terminal Power supply terminal for digital amplifier output (Rch+) Digital amplifier output terminal (Rch+) Digital amplifier output terminal (Rch+) Ground terminal for digital amplifier output (Rch) Digital amplifier output terminal (Rch-) Digital amplifier output terminal (Rch-) Power supply terminal for digital amplifier output (Rch-) Sleep control terminal *5) Error flag output terminal MUTE control terminal Clock output terminal for synchronization External clock input terminal Non-clip/DRC1/DRC2 mode selection terminal 0 Non-clip/DRC1/DRC2 mode selection terminal 1 GAIN setting terminal 0 GAIN setting terminal 1 Normally, use this terminal with nothing connected. Power supply terminal for digital amplifier output (Lch-) Digital amplifier output terminal (Lch-) Digital amplifier output terminal (Lch-) Ground terminal for digital amplifier output (Lch) Digital amplifier output terminal (Lch+) Digital amplifier output terminal (Lch+) Power supply terminal for digital amplifier output (Lch+) (Notes) *1: I: Input terminal, O: Output terminal, A: Analog terminal, O/D: Open/Drain output terminal *2: PVDD should be connected each other on a board. *3: GND should be connected each other on a board. *4: Each output terminal with the same name (OUTPR, OUTMR, OUTPL, and OUTML) should be connected on a board. *5: Don't use the terminal AVDD to apply "H" level to the terminal SLEEPN. When the terminal SLEEPN is "L" level, the terminal AVDD is not supplied. CATALOG No.:LSI-4DA147A61 5 YDA147 Block Diagram 6 CATALOG No.:LSI-4DA147A61 YDA147 Functional Description Digital Amplifier Function YDA147 has digital amplifiers with analog input, PWM pulse output, the maximum output of 20W x 2ch. Adopting "Pure Pulse Direct Speaker Drive Circuit" reduces distortion and noise on PWM pulse output signal. Digital Amplifier Gain The total gain of the digital amplifier varies depending on operation modes, as shown below. NCDRC1 NCDRC0 L L L H H L H H GAIN1 L L H H L L H H L L H H L L H H GAIN0 L H L H L H L H L H L H L H L H Total Gain +22dB +28dB +34dB +16dB +34dB +40dB +46dB +28dB +34dB +40dB +46dB +28dB +34dB +40dB +46dB +28dB Operation Mode Normal mode Non-clip: OFF DRC: OFF Non-clip mode DRC1 mode DRC2 mode Audio Signal Input For a differential input, the signal should be input to INLP and INLM terminals (Lch) and to INRP and INRM terminals (Rch) through a DC-cut capacitor (CIN). On the contrary, for a single-ended input, the signal should be input to INLP terminal (Lch) and to INRP terminal (Rch) through a DC-cut capacitor (CIN). At this time, INLM and INRM terminals should be connected to AVSS through DC-cut capacitors (CIN) with the same value. In the differential input mode, use signal sources with the same impedance to reduce pop-noise. Its value should be 10k or less. Use a DC-cut capacitor (CIN) of 1F. (The capacitance value should be less than 1.5F throughout the operating temperature range.) (Cautions) When inputting audio signals in Power-off state ( PVDD < VHUVLL ) or Sleep state, current may flow toward the former device from YDA147's ground, through each protection circuit of analog pins (INLP, INLM, INRP, and INRM). For this reason, audio signals should not be input in Power-off state ( PVDD < VHUVLL ) or Sleep state. CATALOG No.:LSI-4DA147A61 7 YDA147 Input Impedance The input impedance (ZIN) is 18.8k regardless of a Gain setting. Reference Voltage Output Function Half a voltage of AVDD terminal is output to the reference voltage terminal (VREF). Connect a capacitor of 0.1F for voltage stabilization. Maximum Output The output varies depending on load impedance and a supply voltage, as shown below. Maximum Momentary Output: 20W x 2ch (PVDD=14V, RL=4, THD+N=10%) 15W x 2ch (PVDD=12V, RL=4, THD+N=10%) Maximum Continuous Output: 15W x 2ch (VDDP=15V, RL=8, THD+N=10%, Ta=70C, SQFP48, 4-layer board) 10.5W x 2ch (VDDP=15V, RL=4, THD+N=10%, Ta=25C, SQFP48, 4-layer board) 10W x 2ch (VDDP=12V, RL=8, THD+N=10%, Ta=25C, LQFP48, 1 layer board) The maximum momentary output means a possible maximum output by considering heat problems due to power loss separately. The maximum continuous output means a maximum output with Tjmax not exceeding 150C at a given temperature while outputting a sine wave continuously. In addition, this value is based on Yamaha's board implementation conditions. (See Note *2, *3 at Page 28) A possible maximum continuous output in other settings can be converted by the following data: 1. Graph of Power Dissipation vs Output Power of Example of typical characteristics. (See Page 32) 2. Power Dissipation of Electrical Characteristics. (See Page 28) Control Function Output Power limit Function This is the function to set a voltage at which the output is clipped. At this time, a value at which the output is clipped is defined as a power limit value (VPL). Using this function prevents increase of temperature in a device as well as allowing the maximum output power to be limited. The output power limit value is determined by a voltage (voltage dividing resistor 1, 2) applied to PLIMIT terminal. In addition, changing the voltage at PLIMIT terminal during power-on is prohibited. The relation between a resistor ratio (R2/(R1+R2)(between voltage dividing resistor 1 and 2) and an output power with a 10% distortion is shown below. Since it may vary between MIN and MAX due to variation of internal AVDD, select resistors in consideration of the variation. The setting values shown here are common to stereo and monaural mode. PLIMIT resistor R1 and R2 should be set as follows. R1+R2=500k or less R1//R2=50k to 70k (R1//R2 means a parallel resistance between R1 and R2) AVDD Voltage Dividing Resistor R1 PLIMIT Voltage Dividing Resistor R2 AVSS PLIMIT terminal setting circuit Example 1: 4 max30W (8 max15W) R1=220k+4.7k, R2=75k Example 2: 8 min10W R1=200k, R2=75k+1.5k 8 CATALOG No.:LSI-4DA147A61 YDA147 * Minimum value restriction on the output power limit. The minimum value of the output-power limit values is restricted by the value determined with the resistance voltage division ratio of "0.45." Even though the resistance voltage division ratio is set beyond "0.45," the output-power limit value wouldn't be set lower. * Cancellation of the output power limit function. It is possible to disable the power limit by setting "0"V (voltage division ratio "0") to the PLIMIT pin. However, it is necessary to set the power limit value when the following function is used. Non-clip function (Non-clip/DRC Function : P.11). DRC function (Non-clip/DRC Function : P.11). High Temperature Power Limiter State of High Temperature Protection (High Temperature Protection Function : P.20). For the relation between each function and the power limit value, see the item of each function. CATALOG No.:LSI-4DA147A61 9 YDA147 Enlarged Figures PLIMIT Voltage Dividing Ratio vs Output Power at 10 distortion 4 PLIMIT Voltage Dividing Ratio vs Output Power at 10 distortion 4 35 10 Typ MIN MAX Typ MIN MAX 9 Output Power at 10 distortion [W] Output Power at 10 distortion [W] 30 25 20 15 10 8 7 6 5 4 3 2 5 PLIMIT Voltage Dividing Ratio vs Output Power at 10 distortion 8 10 16 Output Power at 10 distortion [W] 14 Typ MIN MAX 9 Typ MIN MAX 12 10 8 6 4 8 7 6 5 4 3 PLIMIT Voltage Dividing Ratio 0.450 0.400 PLIMIT Voltage Dividing Ratio PLIMIT Voltage Dividing Ratio vs Output Power at 10 distortion 16 PLIMIT Voltage Dividing Ratio vs Output Power at 10 distortion 16 9 5 4 3 2 2.5 2 1.5 1 PLIMIT Voltage Dividing Ratio 0.250 0.450 0.400 0 0.350 0 0.300 0.5 0.250 1 0.450 4 3 0.400 5 0.350 6 3.5 0.300 Output Power at 10 distortion [W] 7 Typ MIN MAX 4.5 Typ MIN MAX 8 0.200 0.350 0.250 0.450 0.400 0.350 0.300 0 0.250 1 0 0.300 2 2 0.200 Output Power at 10 distortion [W] 0.500 PLIMIT Voltage Dividing Ratio vs Output Power at 10 distortion 8 18 Output Power at 10 distortion [W] 0.450 PLIMIT Voltage Dividing Ratio PLIMIT Voltage Dividing Ratio 10 0.400 0.300 0.500 0.450 0.400 0.350 0.300 0.200 0.250 0 0.350 1 0 PLIMIT Voltage Dividing Ratio CATALOG No.:LSI-4DA147A61 YDA147 Non-clip/DRC Function This is the function to change the gain by detecting an input level to the PWM amplifier and to raise an average output level while suppressing clipping. A mode is determined by the combination of NCDRC[1:0] terminals, as shown below. NCDRC1 L L H H NCDRC0 L H L H Mode Non-clip & DRC mode OFF Non-clip mode DRC1 mode DRC2 mode In Non-clip mode, the gain increases by 12dB. The gain is automatically adjusted so that an output peak voltage becomes a power limit value. The maximum attenuation is -12dB. Attack Time is 0 second. The release time from -12dB to 0dB is 7.7 s (typ.). In DRC1 mode, the gain increases by 12dB. Dynamic Range Compression (a half of gain in dB) is performed within an output range of -12dB (-24dB for input range) from the power limit value. Attack Time is 0 s. The release time from -12dB to 0dB is 3.9 s (typ.). In DRC2 mode, the gain increases by 12dB. As with DRC1, similar compression is performed, but power-limit operation is not performed. PLIMIT terminal can be used to set a DRC operating point. Therefore, the setting of a gain curve is possible regardless of the maximum output power, and this allows for DRC operation from a low output power. NCDRC [1:0] terminal should be switched under either of the following conditions. Before PVDD power-on (lower than the PVDD start-up threshold voltage (VHUVLH)) SLEEPN=L Pop noise may occur when switching it under an operating condition other than the above. CATALOG No.:LSI-4DA147A61 11 YDA147 A condition in which the power limit is being applied. Power Limit Value VPL Output Voltage [dB] Output Voltage [dB] OFF NCDRC[1:0]=00 Input Voltage [dB] 0 Non-clip/DRC Gain Curve (OFF) A condition in which the power limit is being applied. Power Limit Value VPL Non-clip NCDRC[1:0]=01 Output Voltage [dB] Output Voltage [dB] OFF NCDRC[1:0]=00 Input Voltage [dB] -12 0 Non-clip/DRC Gain Curve (Non-clip) 12 CATALOG No.:LSI-4DA147A61 YDA147 A Condition in which the power limit is being applied. V Power Limit Value (VPL) PL DRC1 NCDRC[1:0]=10 OFF NCDRC[1:0]=00 [dB] VPL - 12dB Output Voltage [dB] -24 [dB] Input Voltage [dB] 0 Non-clip/DRC Gain Curve (DRC1) A condition in which it is not applied even if exceeding the power limit. Power Limit Value VPL DRC2 NCDRC[1:0]=11 OFF NCDRC[1:0]=00 Output Voltage [dB] VPL - 12dB Output Voltage [dB] -24 Input Voltage [dB] 0 Non-clip/DRC Gain Curve (DRC2) CATALOG No.:LSI-4DA147A61 13 YDA147 Sleep Function YDA147 shifts into sleep mode when SLEEPN terminal goes to "L" level. In the sleep mode, all functions stop and consumption current is minimized (SLEEP). When shifting into sleep mode during any protection mode, the protection mode is cancelled and PROTN terminal output becomes Hi-Z state. The digital amplifier output becomes Weak Low (a state grounded through a high resistance). AVDD and VREF outputs are pulled down. When the level at SLEEPN terminal is changed from "L" to "H" under the condition that the voltage at PVDDREG terminal is higher than the threshold voltage (VHUVLH) for low voltage malfunction prevention cancellation, the sleep mode is cancelled and the state shifts into the normal operation state after the period of sleep recovery time (tWU). Mute Function YDA147 shifts into mute mode when MUTEN terminal goes to "L" level. In the mute mode, the digital amplifier output becomes Weak Low (a state grounded through a high resistance). When the level at MUTEN terminal is changed from "L" to "H" under the condition that the voltage at PVDDREG terminal is higher than the threshold voltage (VHUVLH) for low voltage malfunction prevention cancellation and state of SLEEPN terminal=H, the mute mode is cancelled and the state shifts into the normal operation state after the period of mute recovery time (tMRCV). Clock Control Function The setting of CKIN terminal controls the clock mode as shown below. CKIN terminal Setting L fixed H fixed Mode Internal Clock mode Internal Clock (Spread clock) mode Clock input External Clock mode CKOUT Internal Clock (frequency: fCK) output Internal Clock (Spread Clock) frequency: (fCK) output CKIN input buffer output (frequency: fCKIN) When CKIN terminal is held L or H level, internal clock mode is selected to generate a clock internally. And, when CKIN terminal is held H level, Spread Clock function operates to reduce EMI. When an external clock is input to CKIN terminal, its frequency should be fCKIN. Do not use with CKIN terminal left open. Stereo/Monaural Switching Function When INRP and INRM terminals (Rch input) are connected to AVDD, monaural mode is selected. In the monaural mode, input signals input to INLP and INLM terminals (Lch input) are output from Lch and Rch digital amplifiers. With the monaural mode, parallel operation can be realized by connecting OUTPL to OUTPR and connecting OUTML to OUTMR. For details of connections, see "Single operation in monaural mode" (See page 24) in the "Examples of Application Circuits." The switching between stereo and monaural modes should be performed under the following conditions. Before PVDD power-on (lower than the PVDD shutdown threshold voltage) Digital Amplifier Pop Noise Reduction Function Pop noise that may occur at the power-on, power-off, power-down, and power-down cancel operations, etc. is reduced by minimizing an output offset voltage. Multi-chip Synchronization Function The external clock synchronization function and clock output function are prepared and the use of master/slave configuration realizes carrier clock synchronization. When using it with multi chips synchronized, one is used as a master chip and the other is used as a slave chip. At this time, connect CKOUT terminal of a master chip to CKIN terminal of a slave chip. When using 3 chips (master/slave1/slave2), connect CKOUT terminal of a slave1 chip to CKIN terminal of a slave2 chip. For details of connections, see "MASTER-SLAVE operation" (See page 26 and 27) in the "Examples of Application Circuits." PVDD pins should be connected each other on a board. 14 CATALOG No.:LSI-4DA147A61 YDA147 Startup Sequence, Shutdown Sequence VDDP PVDD AVDD VHUVLH VDDA tWU OUTPL/OUTPR OUTML/OUTMR Digital Amplifier Output Power Supply Startup Sequence VDDP PVDD VHUVLH VDDA AVDD OUTPL /OUTPR OUTML /OUTMR Digital Amplifier Output Stopping Digital Amplifier Output Power Supply Shutdown Sequence CATALOG No.:LSI-4DA147A61 15 YDA147 SLEEPN VIH_SLPN AVDD tWU OUTPL /OUTPR OUTML /OUTMR Digital Amplifier Output Startup Sequence from Sleep State SLEEPN VIL_SLPN AVDD OUTPL /OUTPR OUTML /OUTMR Digital Amplifier Output Stopping Digital Amplifier Output Transient Sequence to Sleep State 16 CATALOG No.:LSI-4DA147A61 YDA147 Regulator Output When SLEEPN terminal is at H, YDA147 outputs VDDA to AVDD terminal. Connect a capacitor of 1F to 4.7F to AVDD terminal for stabilization. (0.8F or more should be secured including its variation and temperature change.) AVDD output must be used only for YDA147. If this output is used in a peripheral circuit of YDA147, the maximum current that can be driven will be IDDA. LC Filter YDA147 adopts the modulation method that reduces speaker loss sufficiently at mute state by the use of only an inductance the speaker has, and this allows for direct connection to a speaker without an LC filter. When an LC filter is used, use the LC filter circuits shown below. At this time, the following constant should be used according to an impedance of a speaker. Using these constants makes a low-pass filter with a cut-off frequency of 50kHz or so, Q=0.7 or so. LC filter constants: RL L1 4 10H 8 22H C1 0.33F 0.22F C2 0.22F 0.1F L1 L1 L1 C2 RL C1 L1 C2 RL C1 C2 C2 LC Filter circuit (Stereo) LC Filter circuit (Monaural) * With use of LC filters, if there is a possibility of not using a speaker, audio signals within 20kHz should be input. And, if its band limitation is not possible, remove the speaker under the following conditions: SLEEPN terminal = L or MUTEN terminal = L, or PVDD = Power Off. Speaker Inductance In the following cases, use a speaker with an inductance of 20H or more (at around the switching frequency (fCKIN or fCK)). 1. Direct connection of a speaker to an output pin of the digital amplifier without an LC filter. 2. Connection of a speaker to a position after components for EMI measures such as ferrite beads etc. (filterless). With an inductance of less than 20H, power loss in the speaker and this device may increase. CATALOG No.:LSI-4DA147A61 17 YDA147 Protection Function YDA147 has the following four digital amplifier protection functions: overcurrent protection function, high temperature protection function, low voltage malfunction prevention function, and DC detection function. Protection Functions Over current Protection Function High Temperature Protection Function (High Temp. power limiter state) High Temperature Protection Function (High Temp. shutdown state) Low Voltage Malfunction Prevention Function DC Detection Function PROTN terminal Output PROTN terminal Latch Digital Amplifier Output State Low Latched WL*1) Not latched Power Limit (-6dB) Low Not latched WL*1) (Hi-Z) WL*1) Low Latched WL*1) Protection Mode Cancel SLEEPN terminal=L or PVDD shutdown SLEEPN terminal=L or PVDD shutdown or lower temperature SLEEPN terminal=L or PVDD shutdown or lower temperature SLEEPN terminal=L or PVDD shutdown *1: WL=Weak Low (a state grounded with a high resistance) Use a circuit as shown below when pulling up PROTN terminal output externally. 1) Pull up the terminal to a voltage obtained by dividing the voltage between PVDD and GND with voltage-dividing resistors. Find values with reference to the following formula so that a voltage at the terminal becomes 3.3V or less when PROTN terminal is in "H" output (Hi-Z). 2.0V (R2 / (R1 + R2)) x VDDP 3.3V ;however, R1 > 100k, 10k < R2 < 100k 2) The pull-up should be performed to an external supply voltage lower than 3.3V. The pull-up resistor R3 should be a value as follows. 40k < R3 < 200k (47k is recommended.) In each case, select these values so that 0.4mA or more current will not flow into the terminal while PROTN terminal is in L state. PROTN terminal Pull-Up Connection 1 (A pull-up to PVDD) 18 CATALOG No.:LSI-4DA147A61 YDA147 VCC(3.3V) R3 PROTN Error Flag PROTN terminal Pull-Up Connection 2 (A pull-up to 3.3V) * If automatic return setting is given by connecting PROTN terminal to SLEEPN terminal, use a separate power supply as VCC, not the same power supply as AVDD. * When VCC is used as AVDD, see Startup Sequence (page 14 and 15). CATALOG No.:LSI-4DA147A61 19 YDA147 Digital Amplifier Over current Protection Function This is the function to protect the device by detecting short-circuiting (to the supply voltage, to the ground, and between terminals) at digital amplifier output terminals. In the protection mode, PROTN terminal becomes L level and output terminals become Weak Low state (a state grounded through a high resistance). The protection mode can be cancelled by turning off the power supply or inputting an L level signal to SLEEPN terminal momentarily. And, when PROTN terminal is externally connected to SLEEPN terminal, automatic return mode is selected. At this time, the protection mode is cancelled even if the protection mode is established by detecting an overcurrent state, and PROTN terminal output is turned from L level into Hi-Z state and a normal operation state is given after a given standby time (tWU). (Automatic Return Function) The current value to detect a short-circuiting between terminals is 8A (typ,VDDP=12V), 10A (typ,VDDP=15V). High Temperature Protection Function This is the function to protect the device by detecting an unusual temperature in YDA147. The protection mode operates in the following two modes according to the temperature. 1) High Temperature Power Limiter State If the temperature rises and reaches 155C (typ.), the high temperature power limiter state is given. This state decreases the power limit level by 6dB in order to limit the digital amplifier output power, and attempts to lower the temperature. In this way, when the temperature falls and lowers than 130C (typ.), the high temperature power limiter state is automatically cancelled and the gain is restored to the original setting value. In the power limiter state, this does not affect on PROTN terminal. 2) High Temperature Shutdown State If the temperature rises and reaches 165C (typ.) during the high temperature power limiter state, the high temperature cutoff state is given. This state outputs an L level signal from PROTN terminal and digital amplifier output terminals become Weak Low state (a state grounded through a high resistance). In this way, when the temperature goes down and lowers than 130C (typ.), the high temperature shutdown state is automatically cancelled. And, even if the cutoff state is established by detecting an unusual temperature, when PROTN terminal is externally connected to SLEEPN terminal, the cutoff state is cancelled and PROTN terminal output is turned from L into Hi-Z state and a normal operation state is given if the temperature is sufficiently lowered after a given standby time (tWU). (Automatic Return Function) If the temperature is not sufficiently lowered, the high temperature protection mode will be established. Low Voltage Malfunction Prevention Function This is the function to protect the device when the supply voltage at PVDDREG terminal is unusually lowered. In this protection mode, the digital amplifier output terminals become Weak Low state (a state grounded through a high resistance). This protection mode is given if the supply voltage at PVDDREG terminal becomes a voltage lower than PVDD shutdown threshold voltage (VHUVLL). When the supply voltage at PVDDREG terminal exceeds PVDD startup threshold voltage (VHUVLH), the protection mode is cancelled and a normal operation mode is given after a given standby time (tWU). (Automatic Return Function) 20 CATALOG No.:LSI-4DA147A61 YDA147 DC Detection Function This is the function to protect the speaker connected to the digital amplifier output when a DC signal is continuously output from the digital amplifier. When MUTEN terminal=L, the DC detection function is disabled. When a voltage in excess of a given time (tDCDET) and a given level (VDCDET) is output to the digital amplifier output, the DC detection mode is given. This state outputs an L level signal from PROTN terminal and digital amplifier output terminals become Weak Low state (a state grounded through a high resistance). Once the DC detection mode is given, an L level signal keeps outputting from PROTN terminal even if the DC output state is cancelled. The protection mode is cancelled by turning off the power supply or inputting an L level signal to SLEEPN terminal momentarily. And, even if DC protection mode is established by detecting a DC signal, when PROTN terminal is externally connected to SLEEPN terminal, the protection mode is cancelled and PROTN terminal output is turned from L into Hi-Z state and a normal operation state is given after a given standby time (tWU). CATALOG No.:LSI-4DA147A61 21 YDA147 Examples of Application Circuits (Caution) A ceramic capacitor of 1F should be used as a bypass capacitor between the following terminals: PVDDPL-PVSSL, PVDDML-PVSSL, PVDDPR-PVSSR, and PVDDMR-PVSSR. Please mount the capacitor as close as possible to each terminal. A former-stage impedance of input terminals should be 10k or less. Select resistor values so that a voltage becomes 2.0V to 3.3V when PROTN terminal is at H level and current becomes 0.4mA or less when PROTN terminal is at L. For PLIMIT terminal setting, see page 8 and 9. For a pull-up resistor for PROTN terminal, see page 18 and 19. Single operation in stereo mode (differential-input, external clock operation) V DDP VSSP VDDP VDDP 1uF 1uF PVDDML OUTML OUTML PVSSL OUTML PVSSL OUTPL OUTPL PVDDML NC OUTPL PVDDPL VDDP PVDDPL 220uF NC NC NC PVDDREG GAIN1 AVDD GAIN0 0.1uF 1uF 1uF Lch Input+ INLP NCDRC1 INLM NCDRC0 1uF Lch Input0.1uF Rch Input- Gain Select Non-Clip/DRC1/DRC2 mode select External Clock VREF CKIN INRM CKOUT (open) INRP MUTEN Mute Control AVSS PROTN PLIMIT SLEEPN 1uF Rch Input+ 1uF V CC 1uF PVDDMR PVDDMR OUTMR OUTMR OUTMR PVSSR PVSSR OUTPR OUTPR OUTPR NC PVDDPR V SSA PVDDPR Error Flag Sleep Control NC 1uF VDDP V DDP VSSP 22 CATALOG No.:LSI-4DA147A61 YDA147 : Single operation in stereo mode (single-ended input, external clock operation) VDDP V SSP V DDP V DDP 1uF 1uF PVDDML OUTML OUTML PVSSL OUTML PVSSL OUTPL OUTPL OUTPL PVDDML NC PVDDPL V DDP PVDDPL 220uF NC NC NC PVDDREG GAIN1 AVDD GAIN0 Gain Select 0.1uF 1uF 1uF Lch Input+ INLP NCDRC1 INLM NCDRC0 Non-Clip/DRC1/DRC2 mode select 1uF 0.1uF External Clock VREF CKIN INRM CKOUT (open) INRP MUTEN Mute Control AVSS PROTN PLIMIT SLEEPN 1uF Rch Input+ 1uF VCC 1uF NC PVDDMR PVDDMR OUTMR OUTMR OUTMR PVSSR PVSSR OUTPR OUTPR PVDDPR NC OUTPR V SSA PVDDPR Error Flag Sleep Control 1uF V DDP V DDP V SSP Single operation in stereo mode (differential-input, input signal level (externally set), external clock operation) VDDP VSSP V DDP V DDP 1uF 1uF PVDDML OUTML OUTML OUTML PVSSL PVSSL OUTPL OUTPL PVDDML NC OUTPL V DDP PVDDPL PVDDPL 220uF NC NC 0.1uF 1uF 1uF Lch Input+ NC PVDDREG GAIN1 AVDD GAIN0 INLP NCDRC1 INLM NCDRC0 1uF Lch Input0.1uF Rch Input1uF Rch Input+ Gain Select Non-Clip/DRC1/DRC2 mode select External Clock VREF CKIN INRM CKOUT (open) INRP MUTEN Mute Control AVSS PROTN PLIMIT SLEEPN 1uF V CC 1uF PVDDMR PVDDMR OUTMR OUTMR OUTMR PVSSR PVSSR OUTPR OUTPR OUTPR PVDDPR V SSA PVDDPR Error Flag NC Sleep Control NC 1uF V DDP V DDP VSSP CATALOG No.:LSI-4DA147A61 23 YDA147 Single operation in stereo mode (single-ended input, input signal level (externally set), external clock operation) VDDP V SSP V DDP V DDP 1uF 1uF PVDDML OUTML OUTML PVSSL OUTML PVSSL OUTPL OUTPL PVDDML NC OUTPL PVDDPL V DDP PVDDPL 220uF NC NC 0.1uF 1uF 1uF Lch Input+ NC PVDDREG GAIN1 AVDD GAIN0 INLP NCDRC1 INLM NCDRC0 Gain Select Non-Clip/DRC1/DRC2 mode select 1uF 0.1uF External Clock VREF CKIN INRM CKOUT (open) INRP MUTEN Mute Control AVSS PROTN PLIMIT SLEEPN 1uF Rch Input+ 1uF VCC 1uF PVDDMR PVDDMR OUTMR OUTMR OUTMR PVSSR PVSSR OUTPR OUTPR OUTPR PVDDPR NC PVDDPR Error Flag Sleep Control NC 1uF V DDP VDDP V SSP Single operation in monaural mode (differential-input, external clock operation) VDDP V DDP V DDP 1uF 1uF PVDDML OUTML OUTML PVSSL OUTML PVSSL OUTPL OUTPL PVDDML NC OUTPL PVDDPL V DDP PVDDPL 220uF NC NC 0.1uF 1uF 1uF Lch Input+ NC PVDDREG GAIN1 AVDD GAIN0 INLP NCDRC1 INLM NCDRC0 1uF Lch Input0.1uF Gain Select Non-Clip/DRC1/DRC2 mode select External Clock VREF CKIN INRM CKOUT (open) INRP MUTEN Mute Control AVSS PROTN PLIMIT SLEEPN V CC 1uF PVDDMR PVDDMR OUTMR OUTMR OUTMR PVSSR PVSSR OUTPR OUTPR OUTPR NC PVDDPR VSSA PVDDPR Error Flag Sleep Control NC 1uF V DDP V DDP V SSP 24 CATALOG No.:LSI-4DA147A61 YDA147 Single operation in stereo mode (differential-input, internal clock operation) V DDP VSSP VDDP VDDP 1uF 1uF PVDDML OUTML OUTML OUTML PVSSL PVSSL OUTPL OUTPL PVDDML NC OUTPL PVDDPL V DDP PVDDPL 220uF NC NC NC PVDDREG GAIN1 AVDD GAIN0 Gain Select 0.1uF 1uF 1uF Lch Input+ INLP NCDRC1 INLM NCDRC0 Non-Clip/DRC1/DRC2 mode select 1uF Lch Input0.1uF Rch Input- AVSS VREF CKIN INRM CKOUT (open) INRP MUTEN Mute Control AVSS PROTN PLIMIT SLEEPN 1uF Rch Input+ 1uF V CC 1uF NC PVDDMR OUTMR PVDDMR OUTMR OUTMR PVSSR PVSSR OUTPR OUTPR OUTPR PVDDPR NC V SSA PVDDPR Error Flag Sleep Control 1uF VDDP V DDP VSSP Single operation in stereo mode (differential-input, external clock operation, automatic return setting) VDDP V SSP V DDP V DDP 1uF 1uF PVDDML OUTML OUTML OUTML PVSSL PVSSL OUTPL OUTPL PVDDML NC OUTPL PVDDPL V DDP PVDDPL 220uF NC NC NC PVDDREG GAIN1 AVDD GAIN0 0.1uF 1uF 1uF Lch Input+ INLP NCDRC1 INLM NCDRC0 1uF Lch Input0.1uF Rch Input- Gain Select Non-Clip/DRC1/DRC2 mode select External Clock VREF CKIN INRM CKOUT (open) INRP MUTEN Mute Control V DDP 1uF Rch Input+ 1uF 1uF PVDDMR OUTMR PVDDMR OUTMR OUTMR PVSSR PVSSR OUTPR OUTPR OUTPR NC PVDDPR PROTN SLEEPN PVDDPR V SSA AVSS PLIMIT NC V SSP 1uF V DDP VDDP V SSP CATALOG No.:LSI-4DA147A61 25 YDA147 M A S TE R -S LA V E operation (differential-input, external clock operation) V DDP V S SP V DDP V DDP 1uF 1u F 220uF PVDDML OUTML OUTML OUTML PVSSL PVSSL OUTPL OUTPL PVDDML NC OUTPL PVDDPL V DDP PVDDPL M aster NC NC NC PV D D R EG G A IN 1 AV D D G AIN 0 0.1uF 1uF 1uF Lch In pu t+ IN LP NCDRC1 IN LM NCDRC0 1uF Lch In put0.1uF R ch Input- VR E F C K IN IN R M C KO U T G ain Select N on-C lip/D R C 1/D R C 2 m ode select E xternal C lock 1uF R ch Input+ IN R P M U T EN M ute C ontrol 1uF AV SS PR O TN PLIM IT SLEE PN VCC NC PVDDMR PVDDMR OUTMR OUTMR OUTMR PVSSR PVSSR OUTPR OUTPR OUTPR PVDDPR PVDDPR E rror F lag NC Sleep C ontrol V SS A 1uF 1u F V DDP V DDP V S SP V DDP V S SP V DDP V DDP 1uF 1u F 220uF PVDDML OUTML OUTML OUTML PVSSL PVSSL OUTPL OUTPL PVDDML NC OUTPL PVDDPL V DDP PVDDPL S lave1 NC NC NC PV D D R EG G A IN 1 AV D D G AIN 0 0.1uF 1uF 1uF Lch In pu t+ IN LP NCDRC1 IN LM NCDRC0 1uF Lch In put0.1uF R ch Input- VR E F C K IN IN R M C KO U T G ain Select N on-C lip/D R C 1/D R C 2 m ode select 1uF R ch Input+ IN R P M U T EN M ute C ontrol 1uF AV SS PR O TN PLIM IT SLEE PN VCC 1uF NC PVDDMR PVDDMR OUTMR OUTMR OUTMR PVSSR PVSSR OUTPR OUTPR OUTPR PVDDPR PVDDPR E rror F lag NC V SSA Sleep C ontrol 1u F V DDP V DDP V S SP V DDP V S SP V DDP V DDP 1uF 1u F PVDDML OUTML OUTML OUTML PVSSL PVSSL OUTPL OUTPL PVDDML NC OUTPL PVDDPL V DDP PVDDPL 220uF S lave2 NC NC NC PV D D R EG G A IN 1 AV D D G AIN 0 0.1uF 1uF 1uF Lch In pu t+ IN LP NCDRC1 IN LM NCDRC0 1uF Lch In put0.1uF R ch Input- G ain Select N on-C lip/D R C 1/D R C 2 m ode select VR E F C K IN IN R M C KO U T (open ) IN R P M U T EN M ute C ontrol AV SS PR O TN PLIM IT SLEE PN 1uF R ch Input+ 1uF VCC 1uF PVDDMR PVDDMR OUTMR OUTMR OUTMR PVSSR PVSSR OUTPR OUTPR OUTPR PVDDPR PVDDPR E rror F lag V SSA NC Sleep C ontrol NC 1u F V DDP V DDP V S SP 26 CATALOG No.:LSI-4DA147A61 YDA147 MASTER-SLAVE operation (differential-input, external clock operation, automatic return setting) VDDP VSSP VDDP VDDP 1uF 1uF 220uF PVDDML OUTML OUTML PVSSL PVSSL OUTML OUTPL OUTPL PVDDML NC OUTPL PVDDPL VDDP PVDDPL Master NC NC NC PVDDREG GAIN1 0.1uF AVDD 1uF 1uF Lch Input+ GAIN0 INLP NCDRC1 INLM NCDRC0 VREF CKIN INRM CKOUT INRP MUTEN 1uF Lch Input0.1uF Rch Input- Gain Select Non-Clip/DRC1/DRC2 mode select External Clock 1uF Rch Input+ Mute Control 1uF NC PVDDMR OUTMR OUTMR 1uF PVDDMR OUTMR PVSSR PVSSR OUTPR PVDDPR NC VSSA OUTPR SLEEPN OUTPR PROTN PLIMIT PVDDPR AVSS 1uF VDDP VDDP VSSP VDDP VSSP VDDP VDDP 1uF 1uF 220uF PVDDML OUTML OUTML OUTML PVSSL PVSSL OUTPL OUTPL PVDDML NC OUTPL PVDDPL VDDP PVDDPL Slave1 NC NC NC PVDDREG GAIN1 AVDD GAIN0 0.1uF 1uF 1uF Lch Input+ INLP NCDRC1 INLM NCDRC0 VREF CKIN INRM CKOUT 1uF Lch Input0.1uF Rch Input- Gain Select Non-Clip/DRC1/DRC2 mode select 1uF Rch Input+ MUTEN INRP Mute Control 1uF NC PVDDMR OUTMR OUTMR 1uF PVDDMR OUTMR PVSSR PVSSR OUTPR OUTPR PVDDPR NC VSSA OUTPR PROTN SLEEPN PVDDPR AVSS PLIMIT 1uF VDDP VDDP VSSP VDDP VSSP VDDP VDDP 1uF 1uF PVDDML OUTML OUTML OUTML PVSSL PVSSL OUTPL OUTPL PVDDML NC OUTPL PVDDPL VDDP PVDDPL 220uF Slave2 NC NC NC PVDDREG GAIN1 0.1uF 1uF 1uF Lch Input+ AVDD GAIN0 NCDRC1 INLM NCDRC0 VREF CKIN INRM CKOUT (open) INRP MUTEN Mute Control AVSS PROTN PLIMIT SLEEPN 1uF Lch Input0.1uF Rch Input- Gain Select INLP Non-Clip/DRC1/DRC2 mode select VDDP 1uF Rch Input+ 1uF PVDDMR OUTMR OUTMR PVDDMR OUTMR PVSSR PVSSR OUTPR OUTPR OUTPR NC PVDDPR VSSA PVDDPR 1uF NC VSSP 1uF VDDP VDDP VSSP CATALOG No.:LSI-4DA147A61 27 YDA147 Electrical Characteristics Absolute Maximum Ratings *1) Parameter Symbol Min. Max. Unit Power Supply terminal (PVDD) Voltage Range VDDP -0.3 20 V Input Terminal Voltage Range VIN -0.3 4 V PROTN Terminal Voltage Range VPROTN -0.3 4 V Power Dissipation (Ta=25C) PD25 6.5*2) W 4 layers Power Dissipation (Ta=70C) PD70 4.21*2) W Power Dissipation (Ta=85C) PD85 3.4*2) W SQFP48 Power Dissipation (Ta=25C) PD25 3.72*3) W 2 layers Power Dissipation (Ta=70C) PD70 2.38*3) W Power Dissipation (Ta=85C) PD85 1.93*3) W *4) Power Dissipation (Ta=25C) PD25 W 2.67 *4) LQFP48 1 layer Power Dissipation (Ta=70C) PD70 W 1.70 *4) Power Dissipation (Ta=85C) PD85 W 1.38 Junction Temperature TJMAX 150 C Storage Temperature TSTG -40 150 C Note) *1: Absolute Maximum Ratings is values which must not be exceeded to guarantee device reliability and life, and when using a device in excess even a moment, it may immediately cause damage to device or may significantly deteriorate its reliability. *2: A value based on the following implementation conditions: Board Layer: 4 layers (FR-4), Board Size: 136 [mm] x 85 [mm], Board Copper Foil Thickness: 35 [m], Wiring Density: 379%, Exposed stage: soldering on the board Through Hole for heat radiation: 25 (5x5) holes from a point just below the exposed stage to the inner layer (VSS) and B layer. *3: A value based on the following implementation conditions: Board Layer: 2 layers (FR-4), Board Size: 136 [mm] x 85 [mm], Board Copper Foil Thickness: 35 [m], Wiring Density: 187%, Exposed stage: soldering on the board Through Hole for heat radiation: 25 (5x5) holes from a point just below the exposed stage to B layer. *4: 1 layer board, Copper Foil Thickness: 35 [m], Wiring Density: 80%, Board Size: 114.3 [mm] x 76.2 [mm] Recommended Operating Condition Parameter Symbol Min. Typ. Max. Unit Power Supply Voltage (PVDD) VDDP 8 16.5 V Digital terminals*1) H level input voltage VIN 2.52 3.3 3.6 V SLEEPN terminal H level input voltage VIN 2.0 3.3 3.6 V Operating Ambient Temperature Ta -40 25 85 C Speaker Impedance (Stereo) RL 3.6 4 Speaker Impedance (Monaural) *2) RL 3.6 4 Note) *1: This specification is applicable to MUTEN, CKIN, NCDRC0, NCDRC1, GAIN0, and GAIN1(CMOS I/F) pins *2: Connect terminals between OUTPL and OUTPR and between OUTML and OUTMR before use. 28 CATALOG No.:LSI-4DA147A61 YDA147 DC Characteristics (VSS=0V, VDDP=8V to 16.5V, Ta=-40C to 85C, CKIN=1MHz, unless otherwise specified.) Parameter Symbol Conditions Min. Typ. Max. Unit PVDD Startup threshold voltage VHUVLH 6.5 V PVDD Shutdown threshold voltage VHUVLL 6.0 V DC Detection Voltage VDCDET PVDD=15V 4 V DC Detection Time tDCDET 0.5 s Digital terminal*1) H level input voltage VIH 2.52 V Digital terminal*1) L level input voltage VIL 0.9 V Digital terminal *1) Input Impedance RIN_D 3.3 M SLEEPN terminal H level input voltage VIH_SLPN 2.0 V SLEEPN terminal L level input voltage VIL_SLPN 0.8 V SLEEPN terminal Input Impedance RIN_ SLPN 3.3 M CKOUT Output Voltage VOL IOL=4mA 0.4 V CKOUT Output Voltage VOH IOH=-4mA 2.4 V PROTN Output Voltage VOL IOL=0.4mA 0.4 V INLP, INLM, INRP, INRM terminals RIN 18.8 k Input impedance AVDD Output Voltage VDDA 3.0 3.3 3.6 V AVDD Output Current IDDA 1 mA VREF Output Voltage VREF VDDA /2 V PVDD Consumption Current IDDP VDDP=12V, no-load 32 mA PVDD consumption current ISLEEP VDDP=15V, Ta=25C 20 A during power-down mode (SLEEPN=L) PVDD consumption current IMUTE VDDP=15V, Ta=25C 16 mA during Mute state (MUTEN=L) PVDD consumption current INOSIG VDDP=15V, Ta=25C 32 mA during no signal input Note) *1: This specification is applicable to MUTEN, CKIN, NCDRC0, NCDRC1, GAIN0, and GAIN1 (CMOS I/F) terminals. CATALOG No.:LSI-4DA147A61 29 YDA147 AC characteristics (VSS=0V, VDDP=8V to 16.5V, Ta=-40C to 85C, CKIN=1MHz, unless otherwise specified.) Parameter Symbol Min. Typ. Max. Unit CKIN Input Frequency fCKIN 0.9 1,0 1.1 MHz CKIN Input Duty DTCKEXT 40 60 % Self-excited Clock Frequency fCK 1.0 MHz Sleep Recovery Time tWU 1 1.5 s Mute Recovery Time tMRCV 1 ms Analog Characteristics (VSS=0V, VDDP=12V, Ta=25C, GAIN[1:0]=L,L, NCDRC[1:0]=L,L, CKIN= CKIN= L*2), unless otherwise specified.) Parameter Symbol Conditions Min. Typ. Max. Unit RL=4, VDDP=12V, THD+N=10% 15 W Maximum momentary Output Po R =8, V =15V, THD+N=10% 15 W L DDP (stereo) RL=4, VDDP=14V, THD+N=10%, 20 W RL=4, VDDP=12V, THD+N=10% 20 W Maximum momentary Output Po (monaural) RL=4, VDDP=15V, THD+N=10% 30 W GAIN[1:0]=L,L 22 dB GAIN[1:0]=L,H 28 dB Voltage Gain AV GAIN[1:0]=H,L 34 dB GAIN[1:0]=H,H 16 dB Total Harmonic Distortion Rate THD+N RL=4,PO=0.1W 0.01 % (stereo) (BW::20kHz) Total Harmonic Distortion Rate THD+N RL=4,PO=0.2 W 0.02 % (monaural) (BW::20kHz) Signal /Noise Ratio (stereo) SNR RL=4,GAIN[1:0]=H,H 105 dB (BW::20kHz A-Filter) Signal /Noise Ratio monaural) SNR RL=4,GAIN[1:0]=H,H 105 dB (BW::20kHz A-Filter) Residual Noise (stereo) Vn RL=4,GAIN[1:0]=H,H 48 Vrms (BW::20kHz A-Filter) Residual Noise (monaural) Vn RL=4,GAIN[1:0]=H,H 48 Vrms (BW::20kHz A-Filter) Channel Separation Ratio CS 1kHz 80 dB Power Supply Rejection Ratio (stereo) PSRR Vripple=200mV, f=1kHz 60 dB (PVDD applied) Power Supply Rejection Ratio PSRR Vripple=200mV, f=1kHz 60 dB (monaural) (PVDD applied) Common Mode Rejection Ratio CMRR f=1kHz 41 dB (stereo) Common Mode Rejection Ratio CMRR f=1kHz 41 dB (monaural) RL=4 88 % Maximum Efficiency (stereo) 92 % RL=8 RL=4, 20W output 93 % Maximum Efficiency (monaural) RL=8, 10W output 93 % *1) Output Offset Voltage (stereo) |Vo| 5 15 mV Output Offset Voltage (monaural) *1) |Vo| 5 15 mV f=20Hz -1 0 1 dB Frequency characteristics fRES f=20kHz -1 0 1 dB Note) *1: The offset voltage is denoted by considering a typical value and the maximum value as and 3, respectively. *2: The same specification is applied to the external clock mode and internal clock (spread clock mode). All the values of analog characteristics were obtained in our evaluation circumstance. Depending upon pattern layout etc., characteristics may vary. The measurement is performed with an 8 or 4 resistor connected in series with a 30H coil as an output load. 30 CATALOG No.:LSI-4DA147A61 YDA147 Example of typical characteristics (VSS=0V, VDDP=12V, Ta=25C, GAIN[1:0]=L,L, NCDRC[1:0]=L,L, CKIN=1MHz, unless otherwise specified) 100.00% POWER vs THD+N (YDA147, RL=4) (Freq=1kHz, with 20kHz filter) Lch Rch 1.00% 0.10% 0.1 1 Power [W] 10 100.00% Mono 0.10% 10 100 Mono 1.00% 0.1 1 Power [W] 10 0.01% 0.0001 0.001 100 Lch Rch 1.00% 0.01% 100 1000 10000 FREQ [Hz Lch Rch 10 Efficiency [%] 10 Lch Rch 0 CATALOG No.:LSI-4DA147A61 100 100 1000 Freq [Hz] 10000 100000 Power vs Efficiency (YDA147,PVDD=12V) 20 10000 10 -80 -100 -120 -140 -160 100000 30 1000 FREQ [Hz] 0.1 1 Power [W] 0 -20 -40 -60 Frequency Responce (YDA147) 100 0.01 Noise FFT (YDA147) FREQ vs THD+N (YDA147) (Po=0.1W with 20kHz filter) Noise Level [dBV] THD+N 0.01 0.10% Gain [dBV] 0.1 1 Power [W] 0.10% 0.01% 0.0001 0.001 10 0.01 POWER vs THD+N (YDA147, RL=8) (Freq=1kHz, with 20kHz filter) 10.00% 1.00% 10.00% 1.00% 0.01% 0.0001 0.001 100 THD+N THD+N 0.01 POWER vs THD+N (YDA147, RL=4) (Freq=1kHz, with 20kHz filter) 10.00% 100.00% Lch Rch 0.10% 0.01% 0.0001 0.001 100.00% POWER vs THD+N (YDA147, RL=8) (Freq=1kHz, with 20kHz filter) 10.00% THD+N 10.00% THD+N 100.00% 100000 100 95 90 85 80 75 70 65 60 55 50 4 8 0 5 Power [W] 10 15 31 YDA147 PVDD VS Max-Power (YDA147 mono) PVDD VS Max-Power (YDA147 stereo) 40 40 4 THD+N=1% 4 THD+N=10% 8 THD+N=1% 8 THD+N=10% 30 25 4 THD+N=1% 4 THD+N=10% 8 THD+N=1% 8 THD+N=10% 35 Max Power [W] Max Power [W] 35 20 15 10 30 25 20 15 10 5 5 0 0 5 10 PVDD [V] 15 20 5 10 Power Dissipation vs Output Power (YDA147 stereo) 15 20 Power Dissipation vs Output Power (YDA147 stereo) 8 8 12V_8_25 12V_8_70 6 Power Dissipation [W] Power Dissipation [W] PVDD [V] 4 2 0 0 2 4 6 8 10 12 14 16 18 15V_8_25 15V_8_70 6 4 2 0 20 0 Output Power [W] 2 4 6 8 10 12 14 16 18 20 16 18 20 Output Power [W] Power Dissipation vs Output Power (YDA147 stereo) 8 12V_4_25 12V_4_70 Power Dissipation [W] Power Dissipation [W] 8 Power Dissipation vs Output Power (YDA147 stereo) 6 4 2 0 6 4 2 0 0 32 15V_4_25 15V_4_70 2 4 6 8 10 12 14 Output Power [W] 16 18 20 0 2 4 6 8 10 12 14 Output Power [W] CATALOG No.:LSI-4DA147A61 YDA147 Package Outline < SQFP48 > CATALOG No.:LSI-4DA147A61 33 YDA147 < LQFP48 > 34 CATALOG No.:LSI-4DA147A61 YDA147 CATALOG No.:LSI-4DA147A61 35 YDA147 Notice The specifications of this product are subject to improvement changes without prior notice.