YDA147 CATALOG
CATALOG No.:LSI-4DA147A61
2009.1
YDA147
D- 515
STEREO 5W-15W DIGITAL AUDIO POWER AMPLIFIER
■General Description
YDA147 (D-515) is a high-efficiency digital audio power amplifier IC with the maximum output of 15W × 2ch.
YDA147 has a “Pure Pulse Direct Speaker Drive Circuit” that directly drives speakers while reducing distortion of
pulse output signal and reducing noise on the signal, which realizes the highest standard low distortion rate
characteristics and low noise characteristics among digital amplifier ICs in the same class.
In addition, supporting filterless design allows circuit design with fewer external parts to be realized depending on use
conditions.
YDA147 features Power Limit Function, Non-clip Function, and DRC (Dynamic Range Control) Function that were
developed by Yamaha original digital amplifier technology.
YDA147 has overcurrent protection function for speaker output terminals, high temperature protection function, and
lowsupply voltage malfunction prevention function.
■Features
・Operating supply voltage range
PVDD: 8.0V to 16.5V
・Maximum momentary output
20 W×2ch (VDDP=14V, RL=4Ω, THD+N=10%)
15 W×2ch (VDDP=12V, RL=4Ω, THD+N=10%)
・Maximum continuous output
15 W*1×2ch (VDDP=15V, RL=8Ω, THD+N=10%, Ta=70°C, SQFP48, 4 layers)
10.5W*1×2ch (VDDP=15V, RL=4Ω, THD+N=10%, Ta=25°C, SQFP48, 4 layers)
10 W*1×2ch (VDDP=12V, RL=8Ω, THD+N=10%, Ta=25°C, LQFP48, 1 layer)
・Distortion Rate (THD+N)
0.01 % (VDDP=12V, RL=8Ω, Po=0.1W, 1kHz)
・Residual Noise
48µVrms (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
・Efficiency
92 % (VDDP=12V, RL=8Ω)
・S/N Ratio
105 dB (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
・Channel separation
-80 dB (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
・PSRR
60dB (VDDP=12V,Vripple=100mV, 1kHz, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
・Non-clip function/DRC function (switchable)
・Power limit function
・Clock External Synchronization Function
・Master/Slave Synchronization Function using clock outputs
・Over-current Protection Function, High Temperature Protection Function,
Low Voltage Malfunction Prevention Function, and DC Detection Function
・Sleep Function using SLEEPN terminal and Output Mute Function using MUTEN terminal
・Stereo/Monaural Switching Function
・Spread Clock Function
・Pop Noise Reduction Function
・Package
Lead-free 48-pin Plastic SQFP (Exposed stage)
Lead-free 48-pin Plastic LQFP
Note) *1: A value based on Yamaha's board implementation conditions (See Note *2,*3 of page 28)
YDA147
2 CATALOG No.:LSI-4DA147A61
■Terminal Configuration
INLP
PVDDREG
AVDD
INLM
VREF
INRP
PVDDMR
INRM
GAIN1
OUTPL
PVDDPR
OUTML
PVSSL
AVSS
GAIN0
CKIN
CKOUT
PVDDML
PVDDPL
N.C.
PROTN
PVSSR
OUTPR
OUTMR
MUTEN
SLEEPN
N.C.N.C.
N.C.
PLIMIT
N.C.
PVSSR
PVDDMR
OUTMR
PVDDPR
OUTPR
OUTPR
OUTMR
N.C.
PVDDPL
OUTPL
OUTPL
PVDDML
PVSSL
OUTML
OUTML
1
2
3
4
5
6
8
9
10
11
12
15 16 2017 22 23 24
25
26
27
13 14
28
SQFP48
7
2118 19
29
30
31
32
33
34
35
36
373839404142434445464748
NCDRC1
NCDRC0
< 48-pin SQFP Top View >
YDA147
CATALOG No.:LSI-4DA147A61 3
INLP
PVDDREG
AVDD
INLM
VREF
INRP
VSS
INRM
GAIN1
OUTPL
OUTML
PVSSL
AVSS
GAIN0
CKIN
CKOUT
PVDDML
VSS
PROTN
OUTPR
OUTMR
MUTEN
SLEEPN
VSSVSS
PLIMIT
PVSSR
PVDDMR
PVDDPR
OUTPR
OUTMR
N.C.
PVDDPL
OUTPL
OUTML
1
2
3
4
5
6
8
9
10
11
12
15 16 2017 22 23 24
25
26
27
13 14
28
LQFP48
7
2118 19
29
30
31
32
33
34
35
36
373839404142434445464748
NCDRC1
NCDRC0
N.C.
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
< 48-pin LQFP Top View >
(Note) VSS pin should be connected to the ground pattern as wide as possible to improve the heat radiation.
YDA147
4 CATALOG No.:LSI-4DA147A61
■Terminal Function
<48-pin SQFP >
No. Name *4) I/O *1), *2), *3) Function
1 NC － Normally, use this terminal with nothing co nnected.
2 NC － Normally, use this terminal with nothing co nnected.
3 PVDDREG PVDD Power supply terminal for regulators
4 AVDD OA 3.3V regulator output terminal
5 INLP IA Analog input terminal (Lch+)
6 INLM IA Analog input terminal (Lch-)
7 VREF OA Reference voltage output term inal
8 INRM IA Analog input terminal (Rch-)
9 INRP IA Analog input terminal (Rch+)
10 AVSS GND Analog ground terminal
11 PLIMIT IA Power limit setting terminal
12 NC － Normally, use this terminal with nothing co nnected.
13 PVDDPR PVDD Power supply terminal for digi tal amplifier output (Rch+)
14 PVDDPR PVDD Power supply terminal for digi tal amplifier output (Rch+)
15 OUTPR O Digital amplifier output terminal (Rch+)
16 OUTPR O Digital amplifier output terminal (Rch+)
17 OUTPR O Digital amplifier output terminal (Rch+)
18 PVSSR GND Ground terminal for digital amplifier output (Rch)
19 PVSSR GND Ground terminal for digital amplifier output (Rch)
20 OUTMR O Digital ampl ifier output terminal (Rch-)
21 OUTMR O Digital ampl ifier output terminal (Rch-)
22 OUTMR O Digital ampl ifier output terminal (Rch-)
23 PVDDMR PVDD Power supply terminal for digital amplifier output (Rch-)
24 PVDDMR PVDD Power supply terminal for digital amplifier output (Rch-)
25 NC － Normally, use this terminal with nothing co nnected.
26 SLEEPN I Sleep control terminal *5)
27 PROTN O/D Error flag output terminal
28 MUTEN I MUTE control terminal
29 CKOUT O Clock output terminal for synchronizatio n
30 CKIN I External clock input terminal
31 NCDRC0 I Non-clip/DRC1/DRC2 mode selection terminal 0
32 NCDRC1 I Non-clip/DRC1/DRC2 mode selection terminal 1
33 GAIN0 I GAIN setting terminal 0
34 GAIN1 I GAIN setting terminal 1
35 NC － Normally, use this terminal with nothing co nnected.
36 NC － Normally, use this terminal with nothing co nnected.
37 PVDDML PVDD Power supply terminal for digital amplifier output (Lch-)
38 PVDDML PVDD Power supply terminal for digital amplifier output (Lch-)
39 OUTML O Digital amplifier output terminal (Lch-)
40 OUTML O Digital amplifier output terminal (Lch-)
41 OUTML O Digital amplifier output terminal (Lch-)
42 PVSSL GND Ground terminal for digital amplifier output (Lch)
43 PVSSL GND Ground terminal for digital amplifier output (Lch)
44 OUTPL O Digital amplifier output terminal (Lch+)
45 OUTPL O Digital amplifier output terminal (Lch+)
46 OUTPL O Digital amplifier output terminal (Lch+)
47 PVDDPL PVDD Power supply terminal for digital amplifier output (Lch+)
48 PVDDPL PVDD Power supply terminal for digital amplifier output (Lch+)
(Notes) *1: I: Input terminal, O: Output terminal, A: Analog terminal, O/D: Open/Drain output terminal
*2: PVDD should be connected each other on a board.
*3: GND should be connected each other on a board.
*4: Each output terminal with the same name (OUTPR, OUTMR, OUTPL, and OUTML) should be connected on a
board.
*5: Don't use the terminal AVDD to apply “H” level to the terminal SLEEPN.
When the terminal SLEEPN is "L" level, the terminal AVDD is not supplied.
YDA147
CATALOG No.:LSI-4DA147A61 5
< 48-pin LQFP >
No. Name *4) I/O *1), *2), *3) Function
1 VSS GND
2 PVDDREG PVDD Power supply terminal for regulators
3 AVDD OA 3.3V regulator output terminal
4 NC － Normally, use this terminal with nothing connected.
5 INLP IA Analog input terminal (Lch+)
6 INLM IA Analog input terminal (Lch-)
7 VREF OA Reference voltage output terminal
8 INRM IA Analog input terminal (Rch-)
9 INRP IA Analog input terminal (Rch+)
10 AVSS GND Analog ground terminal
11 PLIMIT IA Power limit setting terminal
12 VSS GND
13 VSS GND
14 VSS GND
15 PVDDPR PVDD Power supply termina l for digital amplifier output (Rch+)
16 OUTPR O Digital amplifier output terminal (Rch+)
17 OUTPR O Digital amplifier output terminal (Rch+)
18 PVSSR GND Ground terminal for digital amplifier output (Rch)
19 OUTMR O Digital amplifier output terminal (Rch-)
20 OUTMR O Digital amplifier output terminal (Rch-)
21 PVDDMR PVDD Power supply terminal for digital amplifier output (Rch-)
22 VSS GND
23 VSS GND
24 VSS GND
25 VSS GND
26 SLEEPN I Sleep control terminal *5)
27 PROTN O/D Error flag output terminal
28 MUTEN I MUTE control terminal
29 CKOUT O Clock output terminal for synchronization
30 CKIN I External clock input terminal
31 NCDRC0 I Non-clip/DRC1/DRC2 mode selection terminal 0
32 NCDRC1 I Non-clip/DRC1/DRC2 mode selection terminal 1
33 GAIN0 I GAIN setting terminal 0
34 GAIN1 I GAIN setting terminal 1
35 NC － Normally, use this terminal with nothing connected.
36 VSS GND
37 VSS GND
38 VSS GND
39 PVDDML PVDD Power supply termina l for digital amplifier output (Lch-)
40 OUTML O Digital amplifier output terminal (Lch-)
41 OUTML O Digital amplifier output terminal (Lch-)
42 PVSSL GND Ground terminal for digital amplifier output (Lch)
43 OUTPL O Digital amplifier output terminal (Lch+)
44 OUTPL O Digital amplifier output terminal (Lch+)
45 PVDDPL PVDD Power supply terminal for digital amplifier output (Lch+)
46 VSS GND
47 VSS GND
48 VSS GND
(Notes) *1: I: Input terminal, O: Output terminal, A: Analog terminal, O/D: Open/Drain output terminal
*2: PVDD should be connected each other on a board.
*3: GND should be connected each other on a board.
*4: Each output terminal with the same name (OUTPR, OUTMR, OUTPL, and OUTML) should be connected on a
board.
*5: Don't use the terminal AVDD to apply “H” level to the terminal SLEEPN.
When the terminal SLEEPN is "L" level, the terminal AVDD is not supplied.
YDA147
6 CATALOG No.:LSI-4DA147A61
■Block Diagram
YDA147
CATALOG No.:LSI-4DA147A61 7
■Functional Description
● Digital Amplifier Function
YDA147 has digital amplifiers with analog input, PWM pulse output, the maximum output of 20W × 2ch.
Adopting “Pure Pulse Direct Speaker Drive Circuit” reduces distortion and noise on PWM pulse output signal.
・Digital Amplifier Gain
The total gain of the digital amplifier varies depending on operation modes, as shown below.
NCDRC1 NCDRC0 GAIN1 GAIN0 Total Gain Operation Mode
L L +22dB
L H +28dB
H L +34dB
L L
H H +16dB
Normal mode
Non-clip: OFF
DRC: OFF
L L +34dB
L H +40dB
H L +46dB
L H
H H +28dB
Non-clip mode
L L +34dB
L H +40dB
H L +46dB
H L
H H +28dB
DRC1 mode
L L +34dB
L H +40dB
H L +46dB
H H
H H +28dB
DRC2 mode
・Audio Signal Input
For a differential input, the signal should be input to INLP and INLM terminals (Lch) and to INRP and INRM terminals
(Rch) through a DC-cut capacitor (CIN).
On the contrary, for a single-ended input, the signal should be input to INLP terminal (Lch) and to INRP terminal (Rch)
through a DC-cut capacitor (CIN). At this time, INLM and INRM terminals should be connected to AVSS through DC-cut
capacitors (CIN) with the same value.
In the differential input mode, use signal sources with the same impedance to reduce pop-noise. Its value should be 10kΩ or
less. Use a DC-cut capacitor (CIN) of 1µF. (The capacitance value should be less than 1.5µF throughout the operating
temperature range.)
(Cautions)
When inputting audio signals in Power-off state ( PVDD < VHUVLL ) or Sleep state, current may flow toward the former
device from YDA147's ground, through each protection circuit of analog pins (INLP, INLM, INRP, and INRM).
For this reason, audio signals should not be input in Power-off state ( PVDD < VHUVLL ) or Sleep state.
YDA147
8 CATALOG No.:LSI-4DA147A61
AVDD
PLIMIT
AVSS
Voltage
Dividing
Resistor R1
Voltage
Dividing
Resistor R2
PLIMIT terminal setting circuit
・Input Impedance
The input impedance (ZIN) is 18.8kΩ regardless of a Gain setting.
・Reference Voltage Output Function
Half a voltage of AVDD terminal is output to the reference voltage terminal (VREF).
Connect a capacitor of 0.1µF for voltage stabilization.
・Maximum Output
The output varies depending on load impedance and a supply voltage, as shown below.
Maximum Momentary Output:
20W × 2ch (PVDD=14V, RL=4Ω, THD+N=10%)
15W × 2ch (PVDD=12V, RL=4Ω, THD+N=10%)
Maximum Continuous Output:
15W × 2ch (VDDP=15V, RL=8Ω, THD+N=10%, Ta=70°C, SQFP48, 4-layer board)
10.5W × 2ch (VDDP=15V, RL=4Ω, THD+N=10%, Ta=25°C, SQFP48, 4-layer board)
10W × 2ch (VDDP=12V, RL=8Ω, THD+N=10%, Ta=25°C, LQFP48, 1 layer board)
The maximum momentary output means a possible maximum output by considering heat problems due to power
loss separately.
The maximum continuous output means a maximum output with Tjmax not exceeding 150°C at a given
temperature while outputting a sine wave continuously. In addition, this value is based on Yamaha's board
implementation conditions. (See Note *2, *3 at Page 28)
A possible maximum continuous output in other settings can be converted by the following data:
1. Graph of Power Dissipation vs Output Power of Example of typical characteristics. (See Page 32)
2. Power Dissipation of Electrical Characteristics. (See Page 28)
●Control Function
・Output Power limit Function
This is the function to set a voltage at which the output is clipped.
At this time, a value at which the output is clipped is defined as a power limit value
(VPL).
Using this function prevents increase of temperature in a device as well as allowing
the maximum output power to be limited.
The output power limit value is determined by a voltage (voltage dividing resistor 1,
2) applied to PLIMIT terminal.
In addition, changing the voltage at PLIMIT terminal during power-on is prohibited.
The relation between a resistor ratio (R2/(R1+R2)(between voltage dividing resistor
1 and 2) and an output power with a 10% distortion is shown below.
Since it may vary between MIN and MAX due to variation of internal AVDD, select
resistors in consideration of the variation.
The setting values shown here are common to stereo and monaural mode.
PLIMIT resistor R1 and R2 should be set as follows.
R1+R2=500kΩ or less
R1//R2=50kΩ to 70kΩ (R1//R2 means a parallel resistance between R1 and R2)
Example 1: 4Ω max30W (8Ω max15W)
R1=220k+4.7k, 、R2=75k
Example 2: 8Ω min10W
R1=200k, R2=75k+1.5k
YDA147
CATALOG No.:LSI-4DA147A61 9
* Minimum value restriction on the output power limit.
The minimum value of the output-power limit values is restricted by the value determined with the resistance voltage
division ratio of “0.45.”
Even though the resistance voltage division ratio is set beyond “0.45,” the output-power limit value wouldn’t be set lower.
* Cancellation of the output power limit function.
It is possible to disable the power limit by setting “0”V (voltage division ratio “0”) to the PLIMIT pin.
However, it is necessary to set the power limit value when the following function is used.
･ Non-clip function (Non-clip/DRC Function : P.11).
･ DRC function (Non-clip/DRC Function : P.11).
･ High Temperature Power Limiter State of High Temperature Protection
(High Temperature Protection Function : P.20).
For the relation between each function and the power limit value, see the item of each function.
YDA147
10 CATALOG No.:LSI-4DA147A61
Enlarged Figures
PLIMIT Voltage Dividing Ratio vs Output Power at 10％ distortion （4Ω）
0
5
10
15
20
25
30
35
0.200
0.250
0.300
0.350
0.400
0.450
0.500
PLIMIT Voltage Dividing Ratio
Output Power at 10％ distortion [W]
Typ
MIN
MAX
PLIMIT Voltage Dividing Ratio vs Output Power at 10％ distortion （4Ω）
0
1
2
3
4
5
6
7
8
9
10
0.300
0.350
0.400
0.450
0.500
PLIMIT Voltage Dividing Ratio
Output Power at 10％ distortion [W]
Typ
MIN
MAX
PLIMIT Voltage Dividing Ratio vs Output Power at 10％ distortion （8Ω）
0
2
4
6
8
10
12
14
16
18
0.200
0.250
0.300
0.350
0.400
0.450
PLIMIT Voltage Dividing Ratio
Output Power at 10％ distortion [W]
Typ
MIN
MAX
PLIMIT Voltage Dividing Ratio vs Output Power at 10％ distortion （8Ω）
0
1
2
3
4
5
6
7
8
9
10
0.250
0.300
0.350
0.400
0.450
PLIMIT Voltage Dividing Ratio
Output Power at 10％ distortion [W]
Typ
MIN
MAX
PLIMIT Voltage Dividing Ratio vs Output Power at 10％ distortion （16Ω）
0
1
2
3
4
5
6
7
8
9
0.200
0.250
0.300
0.350
0.400
0.450
PLIMIT Voltage Dividing Ratio
Output Power at 10％ distortion [W]
Typ
MIN
MAX
PLIMIT Voltage Dividing Ratio vs Output Power at 10％ distortion （16Ω）
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0.250
0.300
0.350
0.400
0.450
PLIMIT Voltage Dividing Ratio
Output Power at 10％ distortion [W]
Typ
MIN
MAX
YDA147
CATALOG No.:LSI-4DA147A61 11
・Non-clip/DRC Function
This is the function to change the gain by detecting an input level to the PWM amplifier and to raise an average output
level while suppressing clipping.
A mode is determined by the combination of NCDRC[1:0] terminals, as shown below.
NCDRC1 NCDRC0 Mode
L L Non-clip & DRC mode OFF
L H Non-clip mode
H L DRC1 mode
H H DRC2 mode
In Non-clip mode, the gain increases by 12dB. The gain is automatically adjusted so that an output peak voltage becomes
a power limit value. The maximum attenuation is -12dB. Attack Time is 0 second. The release time from -12dB to 0dB is
7.7 s (typ.).
In DRC1 mode, the gain increases by 12dB. Dynamic Range Compression (a half of gain in dB) is performed within an
output range of -12dB (-24dB for input range) from the power limit value. Attack Time is 0 s. The release time from
-12dB to 0dB is 3.9 s (typ.).
In DRC2 mode, the gain increases by 12dB. As with DRC1, similar compression is performed, but power-limit operation
is not performed. PLIMIT terminal can be used to set a DRC operating point. Therefore, the setting of a gain curve is
possible regardless of the maximum output power, and this allows for DRC operation from a low output power.
NCDRC [1:0] terminal should be switched under either of the following conditions.
・Before PVDD power-on (lower than the PVDD start-up threshold voltage (VHUVLH))
・SLEEPN=L
Pop noise may occur when switching it under an operating condition other than the above.
YDA147
12 CATALOG No.:LSI-4DA147A61
Output Voltage [dB]
Input Voltage [dB] 0
OFF
NCDRC[1:0]=00
Power Limit Value （VPL）
A condition in which the
power limit is being applied.
Non-clip/DRC Gain Curve (OFF)
Output Voltage [dB]
Input Voltage [dB] 0
OFF
NCDRC[1:0]=00
Power Limit Value （VPL）
A condition in which the
power limit is being applied.
-12
Non-clip
NCDRC[1:0]=01
Non-clip/DRC Gain Curve (Non-clip)
Output Voltage [dB]
Output Voltage [dB]
YDA147
CATALOG No.:LSI-4DA147A61 13
出力電圧[dB]
入力電圧[dB] 0
OFF
NCDRC[1:0]=00
パワーリミット値（VPL）
パワーリミットが掛
かっている状態
DRC1
NCDRC[1:0]=10
-24
VPL -12dB
Non-clip/DRC Gain Curve (DRC1)
Output Voltage [dB]
Input Voltage [dB] 0
OFF
NCDRC[1:0]=00
Power Limit Value （VPL）
A condition in which it is not applied
even if exceeding the power limit.
DRC2
NCDRC[1:0]=11
-24
VPL - 12dB
Non-clip/DRC Gain Curve (DRC2)
Power Limit Value (VPL)
A Condition in which the
power limit is being applied.
Output Voltage [dB]
Input Voltage [dB]
Output Voltage [dB]
YDA147
14 CATALOG No.:LSI-4DA147A61
・Sleep Function
YDA147 shifts into sleep mode when SLEEPN terminal goes to “L” level.
In the sleep mode, all functions stop and consumption current is minimized (ＩSLEEP).
When shifting into sleep mode during any protection mode, the protection mode is cancelled and PROTN terminal output
becomes Hi-Z state.
The digital amplifier output becomes Weak Low (a state grounded through a high resistance).
AVDD and VREF outputs are pulled down.
When the level at SLEEPN terminal is changed from “L” to “H” under the condition that the voltage at PVDDREG
terminal is higher than the threshold voltage (VHUVLH) for low voltage malfunction prevention cancellation, the sleep
mode is cancelled and the state shifts into the normal operation state after the period of sleep recovery time (tWU).
・Mute Function
YDA147 shifts into mute mode when MUTEN terminal goes to “L” level.
In the mute mode, the digital amplifier output becomes Weak Low (a state grounded through a high resistance).
When the level at MUTEN terminal is changed from “L” to “H” under the condition that the voltage at PVDDREG
terminal is higher than the threshold voltage (VHUVLH) for low voltage malfunction prevention cancellation and state of
SLEEPN terminal=H, the mute mode is cancelled and the state shifts into the normal operation state after the period of
mute recovery time (tMRCV).
・Clock Control Function
The setting of CKIN terminal controls the clock mode as shown below.
CKIN terminal Setting Mode CKOUT
L fixed Internal Clock mode Internal Clock (frequency: fCK) output
H fixed Internal Clock (Spread clock) mo de Internal Clock (Spread Clock) frequency: (fCK)
output
Clock input External Clock mode CKIN input buffer output (frequency: fCKIN)
When CKIN terminal is held L or H level, internal clock mode is selected to generate a clock internally.
And, when CKIN terminal is held H level, Spread Clock function operates to reduce EMI.
When an external clock is input to CKIN terminal, its frequency should be fCKIN.
Do not use with CKIN terminal left open.
・Stereo/Monaural Switching Function
When INRP and INRM terminals (Rch input) are connected to AVDD, monaural mode is selected.
In the monaural mode, input signals input to INLP and INLM terminals (Lch input) are output from Lch and Rch digital
amplifiers.
With the monaural mode, parallel operation can be realized by connecting OUTPL to OUTPR and connecting OUTML
to OUTMR.
For details of connections, see “Single operation in monaural mode” (See page 24) in the “Examples of Application
Circuits.”
The switching between stereo and monaural modes should be performed under the following conditions.
・Before PVDD power-on (lower than the PVDD shutdown threshold voltage)
・Digital Amplifier Pop Nois e Reduction Function
Pop noise that may occur at the power-on, power-off, power-down, and power-down cancel operations, etc. is reduced by
minimizing an output offset voltage.
・Multi-chip Synchronization Function
The external clock synchronization function and clock output function are prepared and the use of master/slave
configuration realizes carrier clock synchronization.
When using it with multi chips synchronized, one is used as a master chip and the other is used as a slave chip. At this
time, connect CKOUT terminal of a master chip to CKIN terminal of a slave chip.
When using 3 chips (master/slave1/slave2), connect CKOUT terminal of a slave1 chip to CKIN terminal of a slave2 chip.
For details of connections, see “MASTER-SLAVE operation” (See page 26 and 27) in the “Examples of Application
Circuits.”
PVDD pins should be connected each other on a board.
YDA147
CATALOG No.:LSI-4DA147A61 15
・Startup Sequence, Shutdown Sequence
VHUVLH
PVDD
OUTPL/OUTPR
VDDP
tWU
OUTML/OUTMR
Digital Amplifier Output
AVDD VDDA
Power Supply Startup Sequence
VHUVLH
PVDD
OUTPL
/OUTPR
VDDP
OUTML
/OUTMR
Digital Amplifier Output Stopping Digital Amplifier Output
AVDD
VDDA
Power Supply Shutdown Sequence
YDA147
16 CATALOG No.:LSI-4DA147A61
VIH_SLPN
SLEEPN
OUTPL
/OUTPR
tWU
OUTML
/OUTMR
Digital Amplifier Output
AVDD
Startup Sequence from Sleep State
VIL_SLPN
SLEEPN
OUTPL
/OUTPR
OUTML
/OUTMR
Digital Amplifier Output Stopping Digital Amplifier Output
AVDD
Transient Sequence to Sleep State
YDA147
CATALOG No.:LSI-4DA147A61 17
● Regulator Output
When SLEEPN terminal is at H, YDA147 outputs VDDA to AVDD terminal. Connect a capacitor of 1µF to 4.7µF to
AVDD terminal for stabilization. (0.8µF or more should be secured including its variation and temperature change.)
AVDD output must be used only for YDA147. If this output is used in a peripheral circuit of YDA147, the maximum
current that can be driven will be IDDA.
●LC Filter
YDA147 adopts the modulation method that reduces speaker loss sufficiently at mute state by the use of only an inductance
the speaker has, and this allows for direct connection to a speaker without an LC filter.
When an LC filter is used, use the LC filter circuits shown below. At this time, the following constant should be used
according to an impedance of a speaker. Using these constants makes a low-pass filter with a cut-off frequency of 50kHz or
so, Q=0.7 or so.
LC filter constants:
RL L1 C1 C2
4Ω 10μH 0.33μF 0.22μF
8Ω 22μH 0.22μF 0.1μF
C1
C2 C2
RL
L1
L1
C1
C2 C2
RL
L1
L1
LC Filter circuit (Stereo) LC Filter circuit (Monaural)
* With use of LC filters, if there is a possibility of not using a speaker, audio signals within 20kHz should be input.
And, if its band limitation is not possible, remove the speaker under the following conditions: SLEEPN terminal = L or
MUTEN terminal = L, or PVDD = Power Off.
●Speaker Inductance
In the following cases, use a speaker with an inductance of 20µH or more (at around the switching frequency (fCKIN or fCK)).
1. Direct connection of a speaker to an output pin of the digital amplifier without an LC filter.
2. Connection of a speaker to a position after components for EMI measures such as ferrite beads etc. (filterless).
With an inductance of less than 20µH, power loss in the speaker and this device may increase.
YDA147
18 CATALOG No.:LSI-4DA147A61
●Protection Function
YDA147 has the following four digital amplifier protection functions: overcurrent protection function, high temperature
protection function, low voltage malfunction prevention function, and DC detection function.
Protection Functions PROTN
terminal
Output
PROTN
terminal
Latch
Digital Amplifier
Output State Protection Mode Cancel
Over current
Protection Function Low Latched WL*1) SLEEPN terminal=L or
PVDD shutdown
High Temperature
Protection Function
(High Temp. power limiter state) － Not latched
Power Limit
(-6dB)
SLEEPN terminal=L or
PVDD shutdown or
lower temperature
High Temperature
Protection Function
(High Temp. shutdown state) Low Not latched WL*1) SLEEPN terminal=L or
PVDD shutdown or
lower temperature
Low Voltage Malfunction
Prevention Function (Hi-Z) － WL*1) －
DC Detection Function Low Latched WL*1) SLEEPN terminal=L or
PVDD shutdown
*1: WL=Weak Low (a state grounded with a high resistance)
Use a circuit as shown below when pulling up PROTN terminal output externally.
1) Pull up the terminal to a voltage obtained by dividing the voltage between PVDD and GND with voltage-dividing
resistors.
Find values with reference to the following formula so that a voltage at the terminal becomes 3.3V or less when
PROTN terminal is in “H” output (Hi-Z).
2.0V ≦ (R2 / (R1 + R2)) × VDDP ≦ 3.3V ;however, R1 > 100kΩ, 10kΩ < R2 < 100kΩ
2) The pull-up should be performed to an external supply voltage lower than 3.3V. The pull-up resistor R3 should be a
value as follows. 40kΩ < R3 < 200kΩ (47kΩ is recommended.)
In each case, select these values so that 0.4mA or more current will not flow into the terminal while PROTN terminal is in
L state.
PROTN terminal Pull-Up Connection 1 (A pull-up to PVDD)
YDA147
CATALOG No.:LSI-4DA147A61 19
VCC(3.3V)
PROTN
R3
Error
Flag
PROTN terminal Pull-Up Connection 2 (A pull-up to 3.3V)
* If automatic return setting is given by connecting PROTN terminal to SLEEPN terminal, use a separate power supply
as VCC, not the same power supply as AVDD.
* When VCC is used as AVDD, see Startup Sequence (page 14 and 15).
YDA147
20 CATALOG No.:LSI-4DA147A61
・Digital Amplifier Over current Protection Function
This is the function to protect the device by detecting short-circuiting (to the supply voltage, to the ground, and between
terminals) at digital amplifier output terminals.
In the protection mode, PROTN terminal becomes L level and output terminals become Weak Low state (a state
grounded through a high resistance).
The protection mode can be cancelled by turning off the power supply or inputting an L level signal to SLEEPN terminal
momentarily.
And, when PROTN terminal is externally connected to SLEEPN terminal, automatic return mode is selected. At this time,
the protection mode is cancelled even if the protection mode is established by detecting an overcurrent state, and PROTN
terminal output is turned from L level into Hi-Z state and a normal operation state is given after a given standby time
(tWU). (Automatic Return Function)
The current value to detect a short-circuiting between terminals is 8A (typ,VDDP=12V), 10A (typ,VDDP=15V).
・High Temperature Protection Function
This is the function to protect the device by detecting an unusual temperature in YDA147.
The protection mode operates in the following two modes according to the temperature.
1) High Temperature Power Limiter State
If the temperature rises and reaches 155°C (typ.), the high temperature power limiter state is given. This state
decreases the power limit level by 6dB in order to limit the digital amplifier output power, and attempts to lower the
temperature.
In this way, when the temperature falls and lowers than 130°C (typ.), the high temperature power limiter state is
automatically cancelled and the gain is restored to the original setting value.
In the power limiter state, this does not affect on PROTN terminal.
2) High Temperature Shutdown State
If the temperature rises and reaches 165°C (typ.) during the high temperature power limiter state, the high temperature
cutoff state is given. This state outputs an L level signal from PROTN terminal and digital amplifier output terminals
become Weak Low state (a state grounded through a high resistance).
In this way, when the temperature goes down and lowers than 130°C (typ.), the high temperature shutdown state is
automatically cancelled.
And, even if the cutoff state is established by detecting an unusual temperature, when PROTN terminal is externally
connected to SLEEPN terminal, the cutoff state is cancelled and PROTN terminal output is turned from L into Hi-Z
state and a normal operation state is given if the temperature is sufficiently lowered after a given standby time (tWU).
(Automatic Return Function)
If the temperature is not sufficiently lowered, the high temperature protection mode will be established.
・Low Voltage Malfunction Prevention F unction
This is the function to protect the device when the supply voltage at PVDDREG terminal is unusually lowered.
In this protection mode, the digital amplifier output terminals become Weak Low state (a state grounded through a high
resistance).
This protection mode is given if the supply voltage at PVDDREG terminal becomes a voltage lower than PVDD
shutdown threshold voltage (VHUVLL).
When the supply voltage at PVDDREG terminal exceeds PVDD startup threshold voltage (VHUVLH), the protection mode
is cancelled and a normal operation mode is given after a given standby time (tWU). (Automatic Return Function)
YDA147
CATALOG No.:LSI-4DA147A61 21
・DC Detection Function
This is the function to protect the speaker connected to the digital amplifier output when a DC signal is continuously
output from the digital amplifier.
When MUTEN terminal=L, the DC detection function is disabled.
When a voltage in excess of a given time (tDCDET) and a given level (VDCDET) is output to the digital amplifier output, the
DC detection mode is given. This state outputs an L level signal from PROTN terminal and digital amplifier output
terminals become Weak Low state (a state grounded through a high resistance).
Once the DC detection mode is given, an L level signal keeps outputting from PROTN terminal even if the DC output
state is cancelled. The protection mode is cancelled by turning off the power supply or inputting an L level signal to
SLEEPN terminal momentarily.
And, even if DC protection mode is established by detecting a DC signal, when PROTN terminal is externally connected
to SLEEPN terminal, the protection mode is cancelled and PROTN terminal output is turned from L into Hi-Z state and a
normal operation state is given after a given standby time (tWU).
YDA147
22 CATALOG No.:LSI-4DA147A61
■Examples of Application Circuits
(Caution)
・A ceramic capacitor of 1µF should be used as a bypass capacitor between the following terminals: PVDDPL-PVSSL, PVDDML-PVSSL,
PVDDPR-PVSSR, and PVDDMR-PVSSR. Please mount the capacitor as close as possible to each terminal.
・A former-stage impedance of input terminals should be 10kΩ or less.
・Select resistor values so that a voltage becomes 2.0V to 3.3V when PROTN terminal is at H level and current becomes 0.4mA or less
when PROTN terminal is at L.
・For PLIMIT terminal setting, see page 8 and 9.
・For a pull-up resistor for PROTN terminal, see page 18 and 19.
VSSA
1uF 1uF
VDDPVDDP
1uF 1uF
VDDP VDDP
VSSP
VSSP
VDDP
0.1uF
1uF
Gain
Select
VCC
Error Flag
External Clock
Mute Control
Sleep Control
1uF
1uF
1uF
1uF
0.1uF
Lch Input-
Lch Input+
Rch Input-
Rch Input+
(open)
VDDP
220uF
Non-Clip/DRC1/DRC2
mode select
Single operation in stereo mode (differential-input, external clock operation)
SLEEPN
GAIN1
GAIN0
CKIN
CKOUT
PROTN
MUTEN
NCDRC1
AVDD
VREF
AVSS
INRP
INRM
INLP
PVDDREG
OUTPL
OUTML
PVSSL
PVDDML
PVDDPL
OUTML
OUTPL
PLIMIT
PVDDPR
PVDDMR
OUTPR
PVSSR
OUTMR
OUTPR
OUTMR
INLM NCDRC0
PVDDPL
OUTPL
PVSSL
OUTML
PVDDML
NC
NC
NC
NC
NC
NC
PVDDPR
OUTPR
PVSSR
OUTMR
PVDDMR
YDA147
CATALOG No.:LSI-4DA147A61 23
:
VDDP
0.1uF
1uF
1uF
1uF
1uF
1uF
0.1uF
Lch Input+
Rch Input+
Single operation in stereo mode (single-ended input, external clock operation)
1uF 1uF
VDDPVDDP
1uF 1uF
VDDP VDDP
VSSP
VSSP
Gain
Select
VCC
Error Flag
External Clock
Mute Control
Sleep Control
(open)
VDDP
220uF
Non-Clip/DRC1/DRC2
mode select
SLEEPN
GAIN1
GAIN0
CKIN
CKOUT
PROTN
MUTEN
NCDRC1
AVDD
VREF
AVSS
INRP
INRM
INLP
PVDDREG
OUTPL
OUTML
PVSSL
PVDDML
PVDDPL
OUTML
OUTPL
PLIMIT
PVDDPR
PVDDMR
OUTPR
PVSSR
OUTMR
OUTPR
OUTMR
INLM NCDRC0
PVDDPL
OUTPL
PVSSL
OUTML
PVDDML
NC
NC
NC
NC
NC
NC
PVDDPR
OUTPR
PVSSR
OUTMR
PVDDMR
VSSA
Single operation in stereo mode (differential-input, input signal level (externally set), external clock operation)
VDDP
0.1uF
1uF
1uF
1uF
1uF
1uF
0.1uF
Lch Input-
Lch Input+
Rch Input-
Rch Input+
1uF 1uF
VDDPVDDP
1uF 1uF
VDDP VDDP
VSSP
VSSP
Gain
Select
VCC
Error Flag
External Clock
Mute Control
Sleep Control
(open)
VDDP
220uF
Non-Clip/DRC1/DRC2
mode select
SLEEPN
GAIN1
GAIN0
CKIN
CKOUT
PROTN
MUTEN
NCDRC1
AVDD
VREF
AVSS
INRP
INRM
INLP
PVDDREG
OUTPL
OUTML
PVSSL
PVDDML
PVDDPL
OUTML
OUTPL
PLIMIT
PVDDPR
PVDDMR
OUTPR
PVSSR
OUTMR
OUTPR
OUTMR
INLM NCDRC0
PVDDPL
OUTPL
PVSSL
OUTML
PVDDML
NC
NC
NC
NC
NC
NC
PVDDPR
OUTPR
PVSSR
OUTMR
PVDDMR
VSSA
YDA147
24 CATALOG No.:LSI-4DA147A61
Single operation in stereo mode (single-ended input, input signal level (externally set), external clock operation)
VDDP
0.1uF
1uF
1uF
1uF
1uF
1uF
0.1uF
Lch Input+
Rch Input+
1uF 1uF
VDDPVDDP
1uF 1uF
VDDP VDDP
VSSP
VSSP
Gain
Select
VCC
Error Flag
External Clock
Mute Control
Sleep Control
(open)
VDDP
220uF
Non-Clip/DRC1/DRC2
mode select
SLEEPN
GAIN1
GAIN0
CKIN
CKOUT
PROTN
MUTEN
NCDRC1
AVDD
VREF
AVSS
INRP
INRM
INLP
PVDDREG
OUTPL
OUTML
PVSSL
PVDDML
PVDDPL
OUTML
OUTPL
PLIMIT
PVDDPR
PVDDMR
OUTPR
PVSSR
OUTMR
OUTPR
OUTMR
INLM NCDRC0
PVDDPL
OUTPL
PVSSL
OUTML
PVDDML
NC
NC
NC
NC
NC
NC
PVDDPR
OUTPR
PVSSR
OUTMR
PVDDMR
Single operation in monaural mode (differential-input, external clock operation)
VDDP
0.1uF
1uF
1uF
1uF
0.1uF
Lch Input-
Lch Input+
1uF 1uF
VDDPVDDP
1uF 1uF
VDDP VDDP
VSSP
Gain
Select
VCC
Error Flag
External Clock
Mute Control
Sleep Control
(open)
VDDP
220uF
Non-Clip/DRC1/DRC2
mode select
SLEEPN
GAIN1
GAIN0
CKIN
CKOUT
PROTN
MUTEN
NCDRC1
AVDD
VREF
AVSS
INRP
INRM
INLP
PVDDREG
OUTPL
OUTML
PVSSL
PVDDML
PVDDPL
OUTML
OUTPL
PLIMIT
PVDDPR
PVDDMR
OUTPR
PVSSR
OUTMR
OUTPR
OUTMR
INLM NCDRC0
PVDDPL
OUTPL
PVSSL
OUTML
PVDDML
NC
NC
NC
NC
NC
NC
PVDDPR
OUTPR
PVSSR
OUTMR
PVDDMR
VSSA
YDA147
CATALOG No.:LSI-4DA147A61 25
Single operation in stereo mode (differential-input, internal clock operation)
AVSS
1uF 1uF
VDDPVDDP
1uF 1uF
VDDP VDDP
VSSP
VSSP
VDDP
0.1uF
1uF
Gain
Select
VCC
Error Flag
Mute Control
Sleep Control
1uF
1uF
1uF
1uF
0.1uF
Lch Input-
Lch Input+
Rch Input-
Rch Input+
(open)
VDDP
220uF
Non-Clip/DRC1/DRC2
mode select
SLEEPN
GAIN1
GAIN0
CKIN
CKOUT
PROTN
MUTEN
NCDRC1
AVDD
VREF
AVSS
INRP
INRM
INLP
PVDDREG
OUTPL
OUTML
PVSSL
PVDDML
PVDDPL
OUTML
OUTPL
PLIMIT
PVDDPR
PVDDMR
OUTPR
PVSSR
OUTMR
OUTPR
OUTMR
INLM NCDRC0
PVDDPL
OUTPL
PVSSL
OUTML
PVDDML
NC
NC
NC
NC
NC
NC
PVDDPR
OUTPR
PVSSR
OUTMR
PVDDMR
VSSA
Single operation in stereo mode (differential-input, external clock operation, automatic return setting)
VDDP
VSSP
1uF 1uF
VDDPVDDP
1uF 1uF
VDDP VDDP
VSSP
VSSP
VDDP
0.1uF
1uF
Gain
Select
External Clock
Mute Control
1uF
1uF
1uF
1uF
0.1uF
Lch Input-
Lch Input+
Rch Input-
Rch Input+
(open)
VDDP
220uF
Non-Clip/DRC1/DRC2
mode select
SLEEPN
GAIN1
GAIN0
CKIN
CKOUT
PROTN
MUTEN
NCDRC1
AVDD
VREF
AVSS
INRP
INRM
INLP
PVDDREG
OUTPL
OUTML
PVSSL
PVDDML
PVDDPL
OUTML
OUTPL
PLIMIT
PVDDPR
PVDDMR
OUTPR
PVSSR
OUTMR
OUTPR
OUTMR
INLM NCDRC0
PVDDPL
OUTPL
PVSSL
OUTML
PVDDML
NC
NC
NC
NC
NC
NC
PVDDPR
OUTPR
PVSSR
OUTMR
PVDDMR
VSSA
YDA147
26 CATALOG No.:LSI-4DA147A61
M A STE R -SLA VE operation (differential-input, external clock operation)
Master
Slave1
Slave2
1uF 1uF
VDDPVDDP
1uF 1uF
VDDP VDDP
VSSP
VSSP
VDDP
0.1uF
1uF
Gain
Select
VCC
Error Flag
External Clock
Mute Control
Sleep Control
1uF
1uF
1uF
1uF
0.1uF
Lch Input-
Lch Input+
Rch Input-
Rch Input+
VDDP
220uF
Non-Clip/DRC1/DRC2
mode select
SLEEPN
GAIN1
GAIN0
CKIN
CKOUT
PROTN
MUTEN
NCDRC1
AVDD
VREF
AVSS
INRP
INRM
INLP
PVDDREG
OUTPL
OUTML
PVSSL
PVDDML
PVDDPL
OUTML
OUTPL
PLIMIT
PVDDPR
PVDDMR
OUTPR
PVSSR
OUTMR
OUTPR
OUTMR
INLM NCDRC0
PVDDPL
OUTPL
PVSSL
OUTML
PVDDML
NC
NC
NC
NC
NC
NC
PVDDPR
OUTPR
PVSSR
OUTMR
PVDDMR
1uF 1uF
VDDPVDDP
1uF 1uF
VDDP VDDP
VSSP
VSSP
VDDP
0.1uF
1uF
Gain
Select
VCC
Error Flag
Mute Control
Sleep Control
1uF
1uF
1uF
1uF
0.1uF
Lch Input-
Lch Input+
Rch Input-
Rch Input+
VDDP
220uF
Non-Clip/DRC1/DRC2
mode select
SLEEPN
GAIN1
GAIN0
CKIN
CKOUT
PROTN
MUTEN
NCDRC1
AVDD
VREF
AVSS
INRP
INRM
INLP
PVDDREG
OUTPL
OUTML
PVSSL
PVDDML
PVDDPL
OUTML
OUTPL
PLIMIT
PVDDPR
PVDDMR
OUTPR
PVSSR
OUTMR
OUTPR
OUTMR
INLM NCDRC0
PVDDPL
OUTPL
PVSSL
OUTML
PVDDML
NC
NC
NC
NC
NC
NC
PVDDPR
OUTPR
PVSSR
OUTMR
PVDDMR
1uF 1uF
VDDPVDDP
1uF 1uF
VDDP VDDP
VSSP
VSSP
VDDP
0.1uF
1uF
Gain
Select
VCC
Error Flag
(open )
Mute Control
Sleep Control
1uF
1uF
1uF
1uF
0.1uF
Lch Input-
Lch Input+
Rch Input-
Rch Input+
VDDP
220uF
Non-Clip/DRC1/DRC2
mode select
SLEEPN
GAIN1
GAIN0
CKIN
CKOUT
PROTN
MUTEN
NCDRC1
AVDD
VREF
AVSS
INRP
INRM
INLP
PVDDREG
OUTPL
OUTML
PVSSL
PVDDML
PVDDPL
OUTML
OUTPL
PLIMIT
PVDDPR
PVDDMR
OUTPR
PVSSR
OUTMR
OUTPR
OUTMR
INLM NCDRC0
PVDDPL
OUTPL
PVSSL
OUTML
PVDDML
NC
NC
NC
NC
NC
NC
PVDDPR
OUTPR
PVSSR
OUTMR
PVDDMR
VSSA
VSSA
VSSA
YDA147
CATALOG No.:LSI-4DA147A61 27
MASTER-SLAVE operation (differential-input, external clock operation, automatic return setting)
VSSP
VDDP
Master
Slave1
Slave2
1uF 1uF
VDDPVDDP
1uF 1uF
VDDP VDDP
VSSP
VSSP
VDDP
0.1uF
1uF
Gain
Select
External Clock
Mute Control
1uF
1uF
1uF
1uF
0.1uF
Lch Input-
Lch Input+
Rch Input-
Rch Input+
VDDP
220uF
Non-Clip/DRC1/DRC2
mode select
SLEEPN
GAIN1
GAIN0
CKIN
CKOUT
PROTN
MUTEN
NCDRC1
AVDD
VREF
AVSS
INRP
INRM
INLP
PVDDREG
OUTPL
OUTML
PVSSL
PVDDML
PVDDPL
OUTML
OUTPL
PLIMIT
PVDDPR
PVDDMR
OUTPR
PVSSR
OUTMR
OUTPR
OUTMR
INLM NCDRC0
PVDDPL
OUTPL
PVSSL
OUTML
PVDDML
NC
NC
NC
NC
NC
NC
PVDDPR
OUTPR
PVSSR
OUTMR
PVDDMR
1uF 1uF
VDDPVDDP
1uF 1uF
VDDP VDDP
VSSP
VSSP
VDDP
0.1uF
1uF
Gain
Select
Mute Control
1uF
1uF
1uF
1uF
0.1uF
Lch Input-
Lch Input+
Rch Input-
Rch Input+
VDDP
220uF
Non-Clip/DRC1/DRC2
mode select
SLEEPN
GAIN1
GAIN0
CKIN
CKOUT
PROTN
MUTEN
NCDRC1
AVDD
VREF
AVSS
INRP
INRM
INLP
PVDDREG
OUTPL
OUTML
PVSSL
PVDDML
PVDDPL
OUTML
OUTPL
PLIMIT
PVDDPR
PVDDMR
OUTPR
PVSSR
OUTMR
OUTPR
OUTMR
INLM NCDRC0
PVDDPL
OUTPL
PVSSL
OUTML
PVDDML
NC
NC
NC
NC
NC
NC
PVDDPR
OUTPR
PVSSR
OUTMR
PVDDMR
1uF 1uF
VDDPVDDP
1uF 1uF
VDDP VDDP
VSSP
VSSP
VDDP
0.1uF
1uF
Gain
Select
Mute Control
1uF
1uF
1uF
1uF
0.1uF
Lch Input-
Lch Input+
Rch Input-
Rch Input+
VDDP
220uF
Non-Clip/DRC1/DRC2
mode select
SLEEPN
GAIN1
GAIN0
CKIN
CKOUT
PROTN
MUTEN
NCDRC1
AVDD
VREF
AVSS
INRP
INRM
INLP
PVDDREG
OUTPL
OUTML
PVSSL
PVDDML
PVDDPL
OUTML
OUTPL
PLIMIT
PVDDPR
PVDDMR
OUTPR
PVSSR
OUTMR
OUTPR
OUTMR
INLM NCDRC0
PVDDPL
OUTPL
PVSSL
OUTML
PVDDML
NC
NC
NC
NC
NC
NC
PVDDPR
OUTPR
PVSSR
OUTMR
PVDDMR
(open)
VSSA
VSSA
VSSA
YDA147
28 CATALOG No.:LSI-4DA147A61
■Electrical Characteristics
●Absolute Maximum Ratings *1)
Parameter Symbol Min. Max. Unit
Power Supply terminal (PVDD) Voltage Range VDDP -0.3 20 V
Input Terminal Voltage Range VIN -0.3 4 V
PROTN Terminal Voltage Range VPROTN -0.3 4 V
Power Dissipation (Ta=25°C) PD25 6.5*2) W
Power Dissipation (Ta=70°C) PD70 4.21*2) W
4 layers
Power Dissipation (Ta=85°C) PD85 3.4*2) W
Power Dissipation (Ta=25°C) PD25 3.72*3) W
Power Dissipation (Ta=70°C) PD70 2.38*3) W
SQFP48
2 layers
Power Dissipation (Ta=85°C) PD85 1.93*3) W
Power Dissipation (Ta=25°C) PD25 2.67*4) W
Power Dissipation (Ta=70°C) PD70 1.70*4) W
LQFP48 1 layer
Power Dissipation (Ta=85°C) PD85 1.38*4) W
Junction Temperature TJMAX 150 °C
Storage Temperature TSTG -40 150 °C
Note) *1: Absolute Maximum Ratings is values which must not be exceeded to guarantee device reliability and life,
and when using a device in excess even a moment, it may immediately cause damage to device or may
significantly deteriorate its reliability.
*2: A value based on the following implementation conditions:
Board Layer: 4 layers (FR-4), Board Size: 136 [mm] × 85 [mm], Board Copper Foil Thickness: 35 [µm],
Wiring Density: 379%, Exposed stage: soldering on the board
Through Hole for heat radiation: 25 (5×5) holes from a point just below the exposed stage to the inner layer (VSS)
and B layer.
*3: A value based on the following implementation conditions:
Board Layer: 2 layers (FR-4), Board Size: 136 [mm] × 85 [mm], Board Copper Foil Thickness: 35 [µm],
Wiring Density: 187%, Exposed stage: soldering on the board
Through Hole for heat radiation: 25 (5×5) holes from a point just below the exposed stage to B layer.
*4: 1 layer board, Copper Foil Thickness: 35 [µm], Wiring Density: 80%, Board Size: 114.3 [mm] × 76.2 [mm]
●Recommended O perating Condition
Parameter Symbol Min. Typ. Max. Unit
Power Supply Voltage (PVDD) VDDP 8 - 16.5 V
Digital terminals*1) H level input voltage VIN 2.52 3.3 3.6 V
SLEEPN terminal H level input voltage VIN 2.0 3.3 3.6 V
Operating Ambient Temperature Ta -40 25 85 °C
Speaker Impedance (Stereo) RL 3.6 4 - Ω
Speaker Impedance (Monaural) *2) R
L 3.6 4 - Ω
Note) *1: This specification is applicable to MUTEN, CKIN, NCDRC0, NCDRC1, GAIN0, and GAIN1(CMOS I/F) pins
*2: Connect terminals between OUTPL and OUTPR and between OUTML and OUTMR before use.
YDA147
CATALOG No.:LSI-4DA147A61 29
●DC Characteristics (VSS=0V , VDDP=8V to 16.5V, Ta=-40°C to 85°C, CKIN=1MHz, unless otherwise sp ecified.)
Parameter Symbol Conditions Min. Typ. Max. Unit
PVDD Startup threshold voltage VHUVLH - - 6.5 - V
PVDD Shutdown threshold voltage VHUVLL - - 6.0 - V
DC Detection Voltage VDCDET PVDD=15V - 4 - V
DC Detection Time tDCDET - - 0.5 - s
Digital terminal*1) H level input voltage VIH - 2.52 - - V
Digital terminal*1) L level input voltage VIL - - - 0.9 V
Digital terminal *1) Input Impedance RIN_D - 3.3 - - MΩ
SLEEPN terminal H level input voltage VIH_SLPN - 2.0 - - V
SLEEPN terminal L level input voltage VIL_SLPN - - - 0.8 V
SLEEPN terminal Input Impedance RIN_ SLPN - 3.3 - - MΩ
CKOUT Output Voltage VOL I
OL=4mA - - 0.4 V
CKOUT Output Voltage VOH I
OH=-4mA 2.4 - - V
PROTN Output Voltage VOL I
OL=0.4mA - - 0.4 V
INLP, INLM, INRP, INRM terminals
Input impedance RIN - - 18.8 - kΩ
AVDD Output Voltage VDDA 3.0 3.3 3.6 V
AVDD Output Current IDDA - - 1 mA
VREF Output Voltage VREF - VDDA /2 - V
PVDD Consumption Current IDDP V
DDP=12V, no-load - 32 - mA
PVDD consumption current
during power-down mode (SLEEPN=L) ISLEEP V
DDP=15V, Ta=25°C - 20 - µA
PVDD consumption current
during Mute state (MUTEN=L) IMUTE V
DDP=15V, Ta=25°C - 16 - mA
PVDD consumption current
during no signal input INOSIG V
DDP=15V, Ta=25°C - 32 - mA
Note) *1: This specification is applicable to MUTEN, CKIN, NCDRC0, NCDRC1, GAIN0, and GAIN1 (CMOS I/F) terminals.
YDA147
30 CATALOG No.:LSI-4DA147A61
●AC characteristics (VSS=0V, VDDP=8V to 16.5V, Ta=-40°C to 85°C, CKIN=1MHz, unless otherwise specified.)
Parameter Symbol Min. Typ. Max. Unit
CKIN Input Frequency fCKIN 0.9 1,0 1.1 MHz
CKIN Input Duty DTCKEXT 40 - 60 %
Self-excited Clock Frequency fCK - 1.0 - MHz
Sleep Recovery Time tWU - 1 1.5 s
Mute Recovery Time tMRCV - - 1 ms
●Analog Characteristics
(VSS=0V, VDDP=12V, Ta=25°C, GAIN[1:0]=L,L, NCDRC[1:0]=L,L, CKIN= CKIN = L*2), unless otherwi se specified.)
Parameter Symbol Conditions Min. Typ. Max. Unit
RL=4Ω, VDDP=12V, THD+N=10% 15 W
RL=8Ω, VDDP=15V, THD+N=10% 15 W
Maximum momentary Output
(stereo) Po
RL=4Ω, VDDP=14V, THD+N=10%, 20 W
RL=4Ω, VDDP=12V, THD+N=10% 20 W
Maximum momentary Output
(monaural) Po RL=4Ω, VDDP=15V, THD+N=10% 30 W
GAIN[1:0]=L,L 22 dB
GAIN[1:0]=L,H 28 dB
GAIN[1:0]=H,L 34 dB
Voltage Gain AV
GAIN[1:0]=H,H 16 dB
Total Harmonic Distortion Rate
(stereo) (BW::20kHz) THD+N RL=4Ω,PO=0.1W 0.01 %
Total Harmonic Distortion Rate
(monaural) (BW::20kHz) THD+N RL=4Ω,PO=0.2 W 0.02 %
Signal /Noise Ratio (stereo)
(BW::20kHz A-Filter) SNR RL=4Ω,GAIN[1:0]=H,H 105 dB
Signal /Noise Ratio monaural)
(BW::20kHz A-Filter) SNR RL=4Ω,GAIN[1:0]=H,H 105 dB
Residual Noise (stereo)
(BW::20kHz A-Filter) Vn RL=4Ω,GAIN[1:0]=H,H 48 µVrms
Residual Noise (monaural)
(BW::20kHz A-Filter) Vn RL=4Ω,GAIN[1:0]=H,H 48 µVrms
Channel Separation Ratio CS 1kHz 80 dB
Power Supply Rejection Ratio (stereo)
(PVDD applied) PSRR Vripple=200mV, f=1kHz 60 dB
Power Supply Rejection Ratio
(monaural) (PVDD applied) PSRR Vripple=200mV, f=1kHz 60 dB
Common Mode Rejection Ratio
(stereo) CMRR f=1kHz 41 dB
Common Mode Rejection Ratio
(monaural) CMRR f=1kHz 41 dB
RL=4Ω 88 %
Maximum Efficiency (stereo) η RL=8Ω 92 %
RL=4Ω, 20W output 93 %
Maximum Efficiency (monaural) η RL=8Ω, 10W output 93 %
Output Offset Voltage (stereo) *1) |Vo| 5 15 mV
Output Offset Voltage (monaural) *1) |Vo| 5 15 mV
f=20Hz -1 0 1 dB
Frequency characteristics fRES f=20kHz -1 0 1 dB
Note) *1: The offset voltage is denoted by considering a typical value and the maximum value as σ and 3σ, respectively.
*2: The same specification is applied to the external clock mode and internal clock (spread clock mode).
All the values of analog characteristics were obtained in our evaluation circumstance.
Depending upon pattern layout etc., characteristics may vary.
The measurement is performed with an 8Ω or 4Ω resistor connected in series with a 30µH coil as an output load.
YDA147
CATALOG No.:LSI-4DA147A61 31
● Example of typical characteristics
(VSS=0V, VDDP=12V, Ta=25°C, GAIN[1:0]=L,L, NCDRC[1:0]=L,L, CKIN=1MHz, unless otherwise specified)
POWER vs THD+N (YDA147, RL=4Ω)
(Freq=1kHz, with 20kHz filter)
0.01%
0.10%
1.00%
10.00%
100.00%
0.0001 0.001 0.01 0.1 1 10 100
Power [W]
THD+N
Lch
Rch
POWER vs THD+N (YDA147, RL=8Ω)
(Freq=1kHz, with 20kHz filter)
0.01%
0.10%
1.00%
10.00%
100.00%
0.0001 0.001 0.01 0.1 1 10 100
Power [W]
THD+N
Lch
Rch
POWER vs THD+N (YDA147, RL=4Ω)
(Freq=1kHz, with 20kHz filter)
0.01%
0.10%
1.00%
10.00%
100.00%
0.0001 0.001 0.01 0.1 1 10 100
Power [W]
THD+N
Mono
POWER vs THD+N (YDA147, RL=8Ω)
(Freq=1kHz, with 20kHz filter)
0.01%
0.10%
1.00%
10.00%
100.00%
0.0001 0.001 0.01 0.1 1 10 100
Power [W]
THD+N
Mono
FREQ vs THD+N (YDA147)
(Po=0.1W with 20kHz filter)
0.01%
0.10%
1.00%
10.00%
100.00%
100 1000 10000 100000
FREQ [Hz］
THD+N
Lch
Rch
Noise FFT (YDA147)
-160
-140
-120
-100
-80
-60
-40
-20
0
10 100 1000 10000 100000
Freq [Hz]
Noise Level [dBV]
Lch
Rch
Frequency Responce (YDA147)
0
10
20
30
10 100 1000 10000 100000
FREQ [Hz]
Gain [dBV]
Lch
Rch
Power vs Efficiency (YDA147,PVDD=12V)
50
55
60
65
70
75
80
85
90
95
100
051015
Power [W]
Efficiency [%]
4Ω
8Ω
YDA147
32 CATALOG No.:LSI-4DA147A61
PVDD VS Max-Power (YDA147 stereo)
0
5
10
15
20
25
30
35
40
5101520
PVDD [V]
Max Power [W]
4Ω THD+N=1%
4Ω THD+N=10%
8Ω THD+N=1%
8Ω THD+N=10%
PVDD VS Max-Power (YDA147 mono)
0
5
10
15
20
25
30
35
40
5101520
PVDD [V]
Max Power [W]
4Ω THD+N=1%
4Ω THD+N=10%
8Ω THD+N=1%
8Ω THD+N=10%
Power Dissipation vs Output Power
(YDA147 stereo)
0
2
4
6
8
0 2 4 6 8 101214161820
Output Power [W]
Power Dissipation [W]
12V_8Ω_25℃
12V_8Ω_70℃
Power Dissipation vs Output Power
(YDA147 stereo)
0
2
4
6
8
0 2 4 6 8 10 12 14 16 18 20
Output Power [W]
Power Dissipation [W]
15V_8Ω_25℃
15V_8Ω_70℃
Power Dissipation vs Output Power
(YDA147 stereo)
0
2
4
6
8
02468101214161820
Output Power [W]
Power Dissipation [W]
12V_4Ω_25℃
12V_4Ω_70℃
Power Dissipation vs Output Power
(YDA147 stereo)
0
2
4
6
8
02468101214161820
Output Power [W]
Power Dissipation [W]
15V_4Ω_25℃
15V_4Ω_70℃
YDA147
CATALOG No.:LSI-4DA147A61 33
■Package Outline
< SQFP48 >
YDA147
34 CATALOG No.:LSI-4DA147A61
< LQFP48 >
YDA147
CATALOG No.:LSI-4DA147A61 35
YDA147
The specifications of this product are subject to improvement changes without prior notice.
Notice
