ROHM CO., LTD .
Description
Features
Applications
Product lineup
Single-output High-frequency Step-down
Switching Regulator(Controller type)
Dual-output Step-up, Negative, Step-down
Switching Regulator(Controller type)
TECHNICAL NOTE
BD9851EFV
BD9850FVM
Large Current External FET Controller Type Switching Regulators
Sep. 2008
Now available
ESD
Resistance
High temperature
operating
Now available
The BD9850FVM is a 1-channel DC/DC step-down switching regulator controller, while the BD9851EFV is a 2-channel DC/DC
step-down switching regulator controller. The BD9850FVM is adaptable for a maximum switching frequency of 2 MHz and the
BD9851EFV for that of 3 MHz. Both provide space saving in all applications.
TFT panel, TA/ Router, digital consumer electronics, PC, and portable CD/DVD/DVC
1) Adaptable for 2-MHz switching frequency (externally variable) (BD9850FVM)
Adaptable for 3-MHz switching frequency (externally variable) (BD9851EFV)
2) FET direct drive
3) High-accuracy reference voltage (Accuracy: ±1%)
4) Built-in Under Voltage Lock Out circuit (UVLO)
5) Built-in Thermal Shutdown circuit (TSD)
6) The BD9851EFV provides two channels:
Channel 1 available for selection of step-down/step-up switching
Channel 2 available for selection of step-down/inverting switching.
7) Compact MSOP8 package (BD9850FVM) / HTSSOP-B20 package (BD9851EFV)
Input range
Oscillation frequency range
External synchronization
Standby function
Operating temperature
Package
BD9850FVM
4V to 9V
100kHz to 2MHz
Not provided
Not provided
–40˚C to 85˚C
MSOP8
BD9851EFV
4V to 18V
10kHz to 3MHz
Not provided
Provided
–40˚C to 85˚C
HTSSOP-B20
Absolute maximum ratings (Ta=25˚C)
Recommended operating range
2/16
BD9850FVM
Item
Power supply voltage
Storage temperature
Operating temperature
Power dissipation
Maximum junction temperature
Vcc
Tstg
Topr
Pd
Tjmax
V
ºC
ºC
mW
ºC
Symbol Rating Unit
*Reduce by 4.7 mW/ºC over 25ºC (When mounted on PCB of 70mm×70mm ×1.6mm)
10
–55 to +150
–40 to +85
587
+150
*
BD9851EFV
Symbol Rating Unit
(*)Reduce by 8.0 mW/ºC over 25ºC (When mounted on PCB of 70mm×70mm ×1.6mm)
Item
Power supply voltage
(Between
Vcc and GND)
Between VREF and GND
Between OUT1 and PVcc1
Between OUT2 and PVcc2
Between OUT1, OUT2 and PGND
Power dissipation
Operating temperature
Maximum junction temperature
Storage temperature
Vcc
VREF
Vouth
Voutl
Pd
Topr
Tjmax
Tstg
20
7
20
20
1000
–40 to +85
+150
–55 to +150
(*)
V
V
V
V
mW
ºC
ºC
ºC
Vcc
fosc
Topr
Item
Power supply voltage
Oscillation frequency
Operating temperature
Symbol Limits
Typ. max.min. Unit
BD9850FVM
V
kHz
ºC
9
2000
+85
4
100
–40
7
–
–
BD9851EFV
Vcc
fosc
RRT
CCT
Item
Power supply voltage
Oscillation frequency
Timing resistor
Timing capacitor
Symbol Limits
Typ. max.min. Unit
V
kHz
kΩ
pF
18
3000
10000
47
4
10
3.3
33
12
300
–
–
3/16
BD9850FVM
Electrical characteristics (Unless otherwise specied, Ta=25˚C, Vcc=7V, fosc=600kHz)
Conditions
[Oscillator block]
Oscillation frequency
Frequency regulation
Oscillator amplitude voltage
[Soft start/SW block]
CTL/ SS pin sink current
CTL/ SS pin clamp voltage
[PWM comparator block]
0% threshold voltage
100% threshold voltage
[Error Amp block]
Threshold voltage
Frequency bandwidth
Voltage gain
Input bias current
Maximum output voltage
Minimum output voltage
Output source current
Output sink current
[VREF block]
VREF output voltage
FREF load regulation
VREF current capacitance
[Total device]
Standby current
Average supply current
[Output block]
ON resistance
Output transient time
[Under voltage lockout block]
Threshold voltage
Hysteresis width
*Design guarantee
*Not designed to be radiation-resistant.
Item Symbol Limits
Typ. max.min. Unit
CTL threshold voltage
fosc
FDV
Vpptr
ISS
VSS
D0
D100
VIN
BW
Av
IIB
VCH
VCL
IOl
IOO
VREF
ΔVREFl0
IVREF
ICCS
ICCA
RON
Tr/ Tf
VUT
VUThy
VCTLTH
510
–5
–
–1.90
2.2
1.5
2.0
0.98
1.5
–
–150
2.3
–
–3.1
12
2.475
–
–45
420
3.4
0.9
–
3.7
0.05
1.2
600
0
0.5
–1.00
2.4
1.6
2.1
1.00
3.0
70
–70
2.4
0.03
–1.6
50
2.500
–
–16
610
5.0
2.5
20
3.8
0.10
1.3
690
5
–
1.00
2.6
1.7
2.2
1.02
–
–
–
2.6
0.20
–1.0
125
2.525
10
–1
960
7.8
8.0
–
3.9
0.15
1.4
kHz
%
V
μA
V
V
V
V
MHz
dB
hA
V
V
mA
mA
V
mV
mA
μA
mA
Ω
nsec
V
V
V
RRT = 24kΩ
Vcc = 4V to 9V
*
*
*
*
VCTL/SS = 1.5V
fosc = 600kHz
fosc = 600kHz
AV = 0dB
VFB = 1.0V
VFB = 1.0V
IVREF = 0mA
IVREF = 0mA to –1mA
At no load
Cout = 1000pF
Vcc sweep down
4/16
*Design guarantee
*Design guarantee
BD9851EFV
Electrical characteristics (Unless otherwise specied, Ta=25˚C, Vcc=12V, fosc=300kHz, STB=3V)
Conditions
[Total device]
Standby mode circuit current
Operation mode circuit current
[Reference voltage block]
Output voltage
Input stability
Load stability
[Oscillator block]
Oscillation frequency
Oscillation frequency regulation
[Error Amp block]
Threshold voltage
Input oset voltage
Common-mode input voltage range
Input bias current
Voltage gain
Frequency bandwidth
Maximum output voltage
Minimum output voltage
Output sink current
Output source current
[PWM comparator block]
0% threshold voltage
100% threshold voltage
DTC bias current
[FET driver block]
ON resistance
SEL1 input voltage range
*Design guarantee
Item Symbol Limits
Typ. max.min. Unit
Short circuit mode output current
Iccst
Icc
DVli
VREF
DVlo
fosc
Dfosc
Vthea
Vofst
Vcm
Ibias
Av
Bw
Vfbh
Vfbl
Isource
Vth100
Isink
Vth0
Idtc
RONN
RONP
Vselh
Vsell
Vstb
Vtime
Vthscp
Vstscp
Vsoscp
Vuvlo
DVuvlo
Istb
Ios
–
1.5
–
2.475
–
270
–2
0.98
–10
0.3
–150
60
3
VREF–0.1
–
–260
1.74
1.6
1.21
–1
1.5
1
Vcc–0.2
0
0.6
2.2
1.4
–
–3.2
3.58
0.05
6
–45
–
2.5
–
2.500
–
300
0
1.00
0
–
–70
75
6
–
–
–160
1.84
6
1.31
–
3
2
–
–
1.5
2.3
1.5
10
–2.0
3.7
0.11
15
–12
5
4.1
10
2.525
10
330
2
1.02
10
2.0
–
90
13
VREF
0.1
–90
1.94
16
1.41
1
3
2
–
–
1.5
2.3
1.5
10
–2.0
3.7
0.11
15
–3
μA
mA
mV
V
mV
kHz
%
V
mV
V
nA
dB
MHz
V
V
μA
V
mA
V
μA
Ω
Ω
V
V
V
V
V
mV
μA
V
V
μA
mA
STB=0V
FB1, FB2=0V
Vcc=4Vto18V, Io=–0.1mA
Io=– 0.1mA
Io=– 0.1mA to –1mA
RRT=24kΩ, CCT=220pF
Vcc=4Vto18V
Ch1
Ch2
Ch2
DC
MHz
FB pin
FB voltage
FB pin
FB voltage
When OUT= Lo
When OUT=Hi
In step-down switching
In step-down switching
FB voltage
SCP voltage
SCP voltage
SCP= 0.75V
Vcc sweep down
STB=3V
[Control block]
Threshold voltage
Sink current
[Short circuit protection circuit (SCP) block]
Timer start voltage
Threshold voltage
Standby mode voltage
Source current
[Under voltage lockout block (UVLO)]
Threshold voltage
Hysteresis width
Characteristic data
(BD9850FVM)
5/16
Fig.1 Error Amp threshold voltage vs. Ambient temperature Fig.2 FB voltage vs. ON Duty
Fig.4 Output voltage vs. Output sink current
Fig.5 VREF vs. Ambient temperature Fig.6 Oscillation frequency vs. Ambient temperature
1.02
1.015
1.01
1.005
1
0.995
0.99
0.985
0.98
–40 –20 0 20 40 60 80
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
–40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
100
90
87
70
60
50
40
30
20
10
0
1.5 1.6 1.7 1.8 1.9 2 2.1 2.2
ERROR-AMP. THRESHOLD VOLTAGE : VINV(V)
AMBIENT TEMPERATURE : Ta(˚C) FB VOLTAGE : VFB(V)
ON DUTY : DON(%)
OUT SOURCE CURRENT : IOUT [mA]
(VCC-OUT)VOLTAGE : VO(V)
Fig.3 (Vcc-OUT) Voltage vs. Output source current
1000
900
800
700
600
500
400
300
200
100
0
2.53
2.52
2.51
2.5
2.49
2.48
2.47
1000
900
800
700
600
500
400
300
200
100
650
640
630
620
610
600
590
580
550
570
560
Vcc=10V
Vcc=7V
Vcc=4V
Vcc=10V
Vcc=7V
Vcc=4V
OUT VOLTAGE : VO(V)
OUT SINK CURRENT : IOUT [mA]
V
REF
VOLTAGE:V
REF
[V]
AMBIENT TEMPERATURE : Ta [˚C] AMBIENT TEMPERATURE : Ta [˚C]
OSCILLATING FREQUENCY : FOSC [kHz]
RT=24kΩ
(BD9851EFV)
6/16
Fig.7 Error Amp threshold voltage vs. Ambient temperature
1.02
1.015
1.01
1.005
1
0.995
0.99
0.985
0.98
–40 –20 0 20 40 60 80
–40 –20 0 20 40 60 80
1000
900
800
700
600
500
400
300
200
100
00 0.5 1 1.5 2 2.5 3 3.5 4
Vcc=20V
Vcc=12V
Vcc=4V
2.55
2.54
2.53
2.52
2.51
2.5
2.49
2.48
2.47
2.46
2.45
320
315
310
305
300
295
290
285
280
Fig.8 FB voltage vs. ON Duty
Fig.10 Output voltage vs. Output sink current
Fig.12 Oscillation frequency vs. Ambient temperature
–40 –20 0 20 40 60 80
1000
900
800
700
600
500
400
300
200
100
00 0.5 0 1.5 2 2.5 3 3.5 4
Vcc=20V
fosc=1MHz
fosc=300kHz
Vcc=12V
Vcc=4V
100
90
80
70
60
50
40
30
20
10
01.2 1.3 1.4 1.5 1.6 1.7 1.8 19
ERROR-AMP. THRESHOLD VOLTAGE : VEATH (V)
OUT SOURCE CURRENT : IOUT (mA)REFERENCE VOLTAGE : VREF (V)
OSCILLATING FREQUENCY : FOSC (kHz) OUT SINK CURRENT : IOUT (mA)
ON DUTY : DON (%)
AMBIENT TEMPERATURE : Ta(˚C)
(Vcc-OUT) VOLTAGE : VO(V)
AMBIENT TEMPERATURE : Ta(˚C) AMBIENT TEMPERATURE : Ta(˚C)
OUT VOLTAGE : VO (V)
DTC VOLTAGE : VDTC (V)
Fig.9 (Vcc-OUT) Voltage vs. Output source current
Fig.11 VREF vs. Ambient temperature
RRT=24kΩ
CCT=220pF
(BD9850FVM)
(BD9851EFV)
Fig.13 BD9850FVM Block diagram
7/16
Fig.14 BD9851EFV Block diagram
Vcc R T
OUT CTL / SS
GND FB
VREF INV
GND
STB
Vcc
VREF
INV1
FB1
SCP
DTC1
PVcc1
OUT1
SEL1
RT
CT
NON2
INV2
FB2
DTC2
PVcc2
OUT2
PGND
Pin No. Pin name Function
Power supply
Ground
Reference voltage (2.5V±1%) output
Error Amp inverting input
Error Amp output
Control/Soft start common
Oscillation frequency setting resistor connection
Pin No. Pin name Function
Block diagram / Pin assignment
Vcc
Vcc
Vcc
Vcc
Vo
OUT
PWM COMP
TRI
Clamper
U.V.L.O
INV 5
6
73
2
8
4
1
FB
1.0V
Error Amp
T.S.D
GND
CTL/SS
RTVREF
VREF
VREF
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
–
SEL1
RT
CT
NON2
INV2
FB2
DTC2
PVCC2
OUT2
PGND
OUT1
PVCC1
DTC1
SCP
FB1
INV1
VREF
VCC
STB
GND
FIN on
reverse
Vcc
OUT
GND
VREF
INV
FB
CTL/SS
RT
FET driver drive output
CH1 drive FET setting (Vcc short: P-ch drive, GND short: N-ch drive)
Oscillation frequency setting resistor connection
Oscillation frequency setting capacitor connection
Error Amp non-inverting input (CH2)
Error Amp inverting input (CH2)
Error Amp output (CH2)
Maximum duty/soft start setting (CH2)
FET driver block power supply input (CH2)
FET driver block output (CH2)
FET driver block ground
FET driver block output (CH1)
FET driver block power supply input (CH1)
Maximum duty/soft start setting (CH1)
Short circuit protection timer setting capacitor connection
Error Amp output (CH1)
Error Amp inverting input (CH1)
Reference voltage (2.5V±1%) output
Power supply input
ON/OFF control
Ground
Make FIN on the reverse open or ground to GND (pin 20)
(However, open FIN on the reverse will degrade radiation performance.)
18
17
15
13
6
5
4
2
7
3
14
19
1
12
11
10
8
9
Both channels
Vcc
VREF ON/OFF
STB
Vcc
Vcc
Vo1
Vo2
Vcc
PVcc2
GND
OUT2
PVcc1
OUT1
PGND
SEL1
VREF
(2.5V)
VREF
Vo1
Vo2 2.3V
FB1
INV1
INV1
NON2
DTC2
RT
CT
SCP
DTC1
FB2
1V
–
+–
–
+
–
+
–
–
+
–
+
+
Vcc
16
VREF
VREF
20
Tmer
Latch
OSC
8/16
Description of operations
Reference voltage block
The reference voltage block generates a constant voltage with temperature compensated through inputting the power supplied from
the Vcc pin. The output voltage is 2.5 V, with a ±1% accuracy. To cancel noises, insert a capacitor with a low ESR (several tens of mΩ)
between the VREF and GND pins. It is recommended to use a ceramic capacitor of 1μF for this purpose.
Triangular wave oscillator block
By connecting the resistor and capacitor of frequency settings to the RT and CT pins (only to RT pin on the BD9850FVM), a triangular
wave will be generated and then input to the PWM comparators of Channels 1 and 2.
Error Amp block
The Error Amp block detects the output voltage of the INV pin, amplies an error with the set output voltage, and then outputs the
error from the FB pin. The comparison voltage is 1 V, with a ±2% accuracy. (The Channel 2 of the BD9851EFV uses the NON pin input
voltage as a reference.)
Inserting a resistor and capacitor between the INV and FB pins will conduct phase compensation.
PWM comparator block
The PWM comparator block converts the output voltage (FB voltage) into a PWM waveform and outputs it to the FET driver.
<Dead time control> (Only available on the BD9851EFV)
Inputting a voltage, divided by resistance of the VREF pin in the DTC pin, will allow maximum ON duty setting.
<Soft start (BD9850FVM)>
Inserting a capacitor between the CTL/SS and GND pins will allow the soft start function to control the rising output voltage.
<Soft start (BD9851EFV)>
Inserting a capacitor between the DTC and GND pins will allow the soft start function to control the rising output voltage.
Furthermore, the overshoot of output voltage at startup can be derated. Adding a Schottky diode between the FB and DTC
pins will make it possible to suppress the overshoot rate (only available with step-down application).
FET driver block
This block is a push-pull type driver enabling direct drive of external MOS FET.
<Setting of step-down/step-up switching (Only available for Channel 1 of BD9851EFV)>
For the Channel 1, SEL1 pin setting will determine the application function.
Set the SEL1 pin to step-down (P-ch drive) mode for short-circuiting Vcc or to step-up (N-ch drive) mode for short-circuiting GND.
Furthermore, be sure to short-circuit the SEL1 pin to Vcc or GND pin.
Standby function
(BD9850FVM)
The CTL/SS pin allows for output ON/OFF control. Set the CTL/SS pin voltage to “H” to activate the output ON control.
(BD9851EFV)
The STB pin allows for output ON/OFF control. Set the STB pin voltage to “H” to activate the output ON control.
The standby mode circuit current should be set to less than 5 μA.
Short circuit protection circuit (SCP) (Only available on BD9851EFV)
The SCP is a timer-latch type short circuit protection circuit.
If the output voltage of either channel drops below the set voltage, the Error Amp will be activated to increase the FB voltage and
initiate charging the capacitor connected to the SCP pin with a 2 μA current. When the SCP pin voltage exceeds 1.5 V, the latch circuit
will be activated to x the output of both channels at OFF and, at the same time, the DTC pin at “L” level.
In order to rest the latch circuit, set the STB pin to “L” level once, and then to “H” level. Or, turn ON the power supply again.
Furthermore, if the short circuit protection circuit is not used, short-circuit the SCP pin to the GND pin.
Under Voltage Lock Out (UVLO) circuit
The UVLO is a protection circuit to prevent the IC from malfunctioning when the power supply turns ON or if an instantaneous power
interruption occurs.
When the Vcc voltage falls below 3.8 V (or 3.7 V on the BD9851EFV), the output of both channels will be xed at “OFF” and, at the same
time, the DTC pin at “L” level. Hysteresis width of 0.1 V (or 0.11 V on the BD9851EFV) is provided for the detection voltage and release
voltage of the UVLO in order to prevent malfunctions of the IC which may result from variations in the input voltage due to threshold
online.
Furthermore, if the latch circuit is activated through the short circuit protection circuit, the circuit will be reset by this UVLO.
Thermal shutdown circuit (TSD)
The TSD is a protection circuit to prevent the destruction of the IC due to abnormal heat generation.
If the TSD detects an abnormal heat generation (175˚C) on the chip, the output of both channels will be xed at “OFF” and, at the same
time, the DTC pin at “L” level. Hysteresis width (15˚C) is provided for the superheat detection and release temperatures in order to prevent
malfunctions of the IC which may result from variations in the input voltage due to threshold online.
Furthermore, if the latch circuit is activated through the short circuit protection circuit, the circuit will be reset by this TSD.
1)
2)
3)
4)
5)
6)
7)
8)
9)
• In startup/normal operation
(BD9850FVM)
(BD9851EFV)
Output short circuit
DTC
CT
FB
2.3V
Output voltage
waveform
Vcc pin voltage
waveform
3.8V
1.5V
9/16
Oscillator output
Soft start set voltage FB pin voltage
Control threshold
Vcc waveform
Output voltage
waveform
Timing chart
OUT pin waveform
Fig.15 BD9850FVM Timing chart
Fig.16 BD9851EFV Timing chart
SCP pin voltage
waveform
OUT pin voltage
waveform
• Setting of output voltage (BD9850FVM)
Setting of output voltage for the step-down application can be calculated by the formula below :
Fig.17 Setting procedure for BD9850FVM
oscillation frequency
RRT
RT (2)
Setting procedure Application
R1
R2
Vo
INV (5)
10/16
Setting procedure Application
Description of external components
Setting of output voltage (BD9851EFV)
Setting of oscillation frequency (BD9850FVM)
Vo = Vthea × (R1 + R2) / R2 [V]
(Vthea: Error Amp threshold voltage Typ. 1.0 [V])
• Step-down (CH1), Step-up (CH1)
Vo1 = Vthea × (R1 + R2) / R2 [V]
(Vthea: Error Amp threshold voltage Typ. 1.0 [V])
• Step-down (CH2)
Vo2 = VNON2 × (R1 + R2) / R2 [V]
VNON2 = 2.5 × R4 / (R3 + R4) [V]
However, set the NON2 pin voltage to 0.3 to 2.0 V.
• Inverting (CH2)
Vo2 = 2.5 – {(2.5 - VINV2) X (R1 + R2) / R1} [V]
VINV2 = 2.5 × R4 / (R3 + R4) [V]
However, set the INV2 pin voltage to 0.3 to 2.0 V
R1
R2
INV1 (16)
Vo1
R1
R2
INV2 (5)
NON2 (4)
VREF (17)
R3
R4
Vo2
R1
R2
Vo2
INV2 (5)
NON2 (4)
VREF (17)
R3
R4
Connecting a resistor to the RT pin (pin 2) allows for the setting of oscillation frequency.
Fig.18 RT vs. Oscillation frequency
10000
1000
100
1 10 100 1000
Oscillating frequency [kHz]
Timing resistance(RT) [kΩ]
• Setting of oscillation frequency (BD9851EFV)
• Setting of timer of short circuit protection circuit (BD9851EFV)
• Setting of maximum duty (BD9851EFV)
• Pin treatment of unused channels (BD9851EFV)
In order to use one channel, treat the pins of unused channel as shown above.
Setting procedure Application
CSCP
SCP (14)
Setting procedure Application
R1
R2
VREF (17)
DTC (13)(7)
11/165
(18)
Vcc
(18)
Vcc
(17)
VREF
SEL1
(1)
NON2
(4)
INV
(16)
(5)
FB
(15)
(6)
DTC
(13)
(7)
OUT
(9)
PVcc
(12) (11)
(8)
Upper : Pin No. to be treated when the CH1 is not used
Lower : Pin No. to be treated when the CH2 is not used
Fig. 22 Pin treatment procedure for unused channel on BD9851EFV
Connecting a resistor to the RT pin (pin 2) and a capacitor to the CT pin allows
for the setting of oscillation frequency.
Fig. 19 Setting procedure for BD9851EFV oscillation frequency
RRT
CCT
RT (2)
CT (3)
1000
1000
100
10 1 10 100
Oscillating Frequency (kHz)
Timing Resistance (kΩ)
Fig. 20 RT vs. Oscillation frequency
CCT=33pF
CCT=220pF
CCT=1200pF
1000
1000
100
1010 10 100 1000
Oscillating Frequency (kHz)
Timing Capacitance(pF)
Fig. 20 CT vs. Oscillation frequency
RRT=4.7kΩ
RRT=24kΩ
TSCP = 7.45 × 105 × CSCP
TSCP :
OSCP :
Time from output short circuit to latch stop [sec]
Capacitance of capacitor between the SCP and
GND pins [F]
DUTY(max.) = 100 × (VDTC – Vth0) / (Vth100 – Vth0)
VDTC = 2.5 × R2 / (R1 + R2)
DUTY(max.)
VDTC
Vth0
Vth100
: Maximum duty [%]
: DTC pin voltage [V]
: 0% duty threshold voltage [V]
: 100% duty threshold voltage [V]
Fig.23 BD9850FVM Reference application
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SEL1
RT
CT
NON2
INV2
FB2
DTC2
PVCC2
OUT2
PGND
GND
STB
VCC
VREF
INV1
FB1
SCP
DTC1
PVcc1
OUT1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SEL1
RT
CT
NON2
INV2
FB2
DTC2
PVcc2
OUT2
PGND
GND
STB
Vcc
VREF
INV1
FB1
SCP
DTC1
PVcc1
OUT1
STB
Vcc
GND
STB
Vcc
GND
Vo1
Vo2
Step-down VO1
Step-up
Vo2
Step-down
Fig.24 Step-down/Step-up application Fig.25 Step-up/Inverting application
Inverting
12/16
2PIN(OUT) 4PIN(VREF)5PIN(INV)
6PIN(FB) 7PIN(CTL/SS) 8PIN( RT)
Vcc
OUT
GND
250k
1.67k
Vcc
VREF
GND
200k
50k
193k
Vcc
INV
GND
GND
Vcc
FB
20p
200k
Vcc
CTL/SS
GND
20k 5k
VREF
RT
GND
500k
100k
1k
Fig.26 Equivalent circuit (BD9850FVM)
Application circuit / Directions for pattern layout
(BD9850FVM)
Equivalent circuit
(BD9850FVM)
In order to reduce ripple noises, set the shortest
distance between the VCC pin and the capacitor pin,
and the GND pin and the capacitor pin. Furthermore,
the OUT line may pass under the C1.
In order to reduce ripple noises, set the shortest
pattern between the VREF pin and the capacitor pin,
and the GND pin and the capacitor pin.
In order to stabilize the switching frequency, set the
smallest pattern area so that PCB parasitic
capacitance for the RT pin will be minimized.
C1:
C2:
R1:
Vo
Vcc Vcc
OUT
GND
VREF
RT
CTL/SS
FB
INV
C1
C2
1µF
*
*
R1
Vcc
Vcc
OUT
OUT
GND
GND VREF
VREF
RT
RT
R1
C1
C1
CT/SS
FB
INV
ON/OFF
[
H: OFF
]
L:ON
*
1PIN (SEL1) 7,13PIN (DTC2,DTC1)
9PIN (OUT2) 3PIN (CT) 4PIN (NON2)
11PIN (OUT1 ) 14PIN (SCP) 5,16PIN (INV2,INV1)
6,15PIN (FB2,FB1) 17PIN (VREF) 19PIN (STB)
Vcc Vcc
SEL1
Vcc
RT
VREF VREF Vcc Vcc
DTC
Vcc Vcc PVcc2
PGND
OUT2
VREF Vcc Vcc
NON2
VREF
Vcc Vcc
Fig.27 Equivalent circuit (BD9851EFV)
13/16
Vcc PVcc1
OUT1
Vcc Vcc Vcc
INV
VREF
Vcc
STB
VccVREF
FB
VccVREF VREF
Vcc
VREF VREF Vcc
SCP
VREF VREF VREF VREF VREF VREF
CT
VCC
BD9851EFV
Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices,
thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the
absolute maximum ratings, consider adding circuit protection devices, such as fuses.
GND potential
Ground-GND potential should maintain at the minimum ground voltage level. Furthermore, no terminals should be lower than the GND potential
voltage including an electric transients.
Thermal design
Use a thermal design that allows for a sucient margin in light of the power dissipation (Pd) in actual operating conditions.
Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if positive
and ground power supply terminals are reversed. The IC may also be damaged if pins are shorted together or are shorted to other circuitís power
lines.
Operation in strong electromagnetic eld
Use caution when using the IC in the presence of a strong electromagnetic eld as doing so may cause the IC to malfunction.
Thermal shutdown circuit (TSD circuit)
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC o
to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating
this circuit or use the IC in an environment where the operation of this circuit is assumed.
Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge
capacitors after each process or step. Always turn the IC's power supply o before connecting it to, or removing it from a jig or xture, during the
inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting and storing the IC.
1)
2)
3)
4)
5)
6)
7)
Cautions on use
2PIN (RT)
14/16
Fig. 29
Vcc
Output pin
Bypass diode
Backow prevention diode
Resistor Transistor (NPN)
IC pin input
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements to keep them isolated. Pin junctions are formed at the
intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the relation between each
potential is as follows:
When GND > Pin A and GND > Pin B, the Pin junction operates as a parasitic diode.
When Pin B > GND > Pin A, the PñN junction operates as a parasitic transistor.
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits,
operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the
GND (P substrate) voltage to an input pin, should not be used.
8)
Common impedance
The power supply and ground lines must be as short and thick as possible to reduce line impedance. Fluctuating voltage on the power ground
line may damage the device.
On the application shown below, Vcc is short-circuited to the Ground with external diode charged, internal circuits may be damaged.
recommended to insert a backow prevention diode in series with the Vcc or a bypass diode between each pin and Vcc.
9)
10)
Fig. 28 Typical simple construction of monolithic IC
(Pin B)
GND
GND
Parasitic element
P
NN
N
N
E
B
C
P+P+
Player
(Pin A)
Parasitic element
GND
P+P
NN
N
P+
Player
(Pin A)
Parasitic element
GND
Parasitic element
Other proximity element
GND
C
E
B
(Pin B)
Thermal derating characteristics
Selection of order type
15/16
Reel
No. 1 pin Pulling-out side
Package style
Quantity
Packaging
direction
Embossed carrier tape
3000 pieces/reel
TR
(When holding a reel in left hand and pulling out the tape with
right hand, No. 1 pin appears in the upper right of the reel.)
Reel
No. 1 pin Pulling-out side
12.34
12.34
12.34
12.34
12.34
12.34
12.34
12.34
Package style
<Package specications><Dimension>
HTSSOP-B20
Quantity
Packaging
direction
<Package specications><Dimension>
MSOP8
BD 9850 FVM TR
ROHM
model name
Product No. Package type
9850=10V
9851=20V
FVM=MSOP8
EFV=HTSSOP-B20
TR=Reel-type embossed carrier tape (MSOP8)
E2=Reel-type embossed carrier tape (HTSSOP-B20)
PD(W)
PD(W) HTSSOP-B20MSOP 8
Fig.31Fig.30
41
58
2.9 ± 0.1
0.475
0.22
0.65
4.0 ± 0.2
0.6 ± 0.2
0.29 ± 0.15
2.8 ± 0.1
0.75 ± 0.05
0.08 ± 0.05
0.9max.
0.08 S
+0.05
–0.04
0.145 +0.05
–0.03
0.08 M
1.0max.
101
20 11
0.17
0.65
S
0.08
+0.05
+0.04
+0.05
+0.03
0.2
6.4
±
0.2
0.5
±
0.15
1.0
±
0.2
6.5
±
0.1
4.4
±
0.1
0.85
±
0.05
0.08
±
0.05
0.325
S
AMBIENT TEMPERATURE : Ta [˚C] AMBIENT TEMPERATURE : Ta [˚C]
Embossed carrier tape (Moisture-proof specicatin)
2500 pieces/reel
E2
(When holding a reel in left hand and pulling out the tape with
right hand, No. 1 pin appears in the upper left of the reel.)
Although ROHM is condent that the example application circuit reects the best possible recommendations, be sure to verify circuit
characteristics for your particular application. Modication of constants for other externally connected circuits may cause variations in both static
and transient characteristics for external components as well as this Rohm IC. Allow for sucient margins when determining circuit constants.
Oscillation frequency setting resistor
For the oscillation frequency setting resistor to be inserted between the RT pin and the GND pin, mount this resistor close to the RT pin and
provide the shortest pattern routing.
11)
12)
0
0.2
0.4
0.6
0.8
0 25 50 75 100 125 150
POWER DISSIPATION : Pd [W]
(1) 0.30 W
(2) 0.59 W
Wiring width 0.4mm
Pd = 0.50 W
qjc = 200˚C/W
(1) : Single piece of IC
(2) : With ROHM standard PCB mounted
(Glass epoxy PCB of 70mmX70mmX1.6mm)
0
0
1
2
3
4
5
25 50 75 100 125 150
POWER DISSIPATION : Pd [W]
(1) 1.00W
(2) 1.45W
(3) 2.30W
(4) 3.20W
(1) : Single piece of IC
PCB size: 70mmX70mmX1.6 mm2 (PCB incorporates thermal via)
Copper foil area on the reverse side of PCB: 10.5X10.5mm2
(2) : 2-layer PCB (Copper foil area on the reverse side of PCB: 15mmX15mm
(3) : 2-layer PCB (Copper foil area on the reverse side of PCB: 70mmX70mm
(4) : 4-layer PCB (Copper foil area on the reverse side of PCB: 70mmX70mm
Taping type
(unit : mm)
(unit : mm)
Catalog No.08T67 9A '08.9 ROHM ©
Appendix-Rev4.0
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.
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FAX : +81-75-315-0172
Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM
CO.,LTD.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account
when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no re-
sponsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples
of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to
use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no re-
sponsibility whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment
or devices (such as audio visual equipment, office-automation equipment, communication devices, elec-
tronic appliances and amusement devices).
The Products are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your
use of any Product outside of the prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system
which requires an extremely high level of reliability the failure or malfunction of which may result in a direct
threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear
no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intend-
ed to be used for any such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.