CD74HCT259E96 - Texas Instruments

Data sheet acquired from Harris Semiconductor

SCHS173A

Features

• Buffered Inputs and Outputs

• Four Operating Modes

• Typical Propagation Delay of 15ns at VCC = 5V,

CL = 15pF, TA = 25oC

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating T emperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤1µA at VOL, VOH

Description

The ’HC259 and ’HCT259 Addressable Latch features the

low-power consumption associated with CMOS circuitry and

has speeds comparable to low-power Schottky.

This latches three active modes and one reset mode. When

both the Latch Enable (LE) and Master Reset (MR) inputs are

low (8-line Demultiplexer mode) the output of the addressed

latch follows the Data input and all other outputs are forced

low. When both MR and LE are high (Memory Mode), all

outputs are isolated from the Data input, i.e., all latches hold

the last data presented before the LE transition from low to

high. A condition of LE low and MR high (Addressable Latch

mode) allows the addressed latch’s output to follow the data

input; all other latches are unaffected. The Reset mode (all

outputs low) results when LE is high and MR is low.

Ordering Information

PART NUMBER TEMP. RANGE

(oC) PACKAGE

CD54HC259F3A -55 to 125 16 Ld CERDIP

CD74HC259E -55 to 125 16 Ld PDIP

CD74HC259M -55 to 125 16 Ld SOIC

CD54HCT259F3A -55 to 125 16 Ld CERDIP

CD74HCT259E -55 to 125 16 Ld PDIP

CD74HCT259M -55 to 125 16 Ld SOIC

NOTES:

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

2. Waferor diefor thispart numberis availablewhich meetsall elec-

trical specifications. Please contact your local TI sales office or

customer service for ordering information.

November 1997 - Revised May 2000

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC259,

CD54/74HCT259

High Speed CMOS Logic

8-Bit Addressable Latch

[ /Title

(CD74

HC259

CD74

HCT25

/Sub-

ject

(High

Speed

CMOS

Logic

8-Bit

Addres

sable

Latch)

Pinout

CD54HC259, CD54HCT259

(CERDIP)

CD74HC259, CD74HCT259

(PDIP, SOIC)

TOP VIEW

Functional Diagram

GND

VCC

LATCHES

1-OF-8

DECODER

GND = 8

VCC = 16

TRUTH TABLE

INPUTS OUTPUT OF

ADDRESS

LATCH EACH OTHER

OUTPUT FUNCTIONMR LE

HL D Q

io Addressable

Latch

HH Q

io Qio Memory

L L D L 8-Line

Demultiplexer

L H L L Reset

NOTE:

H = High Voltage Level

L = Low Voltage Level

D = The level at the data input

Qio = The level of Qi(i = 0, 1...7, as appropriate) before the indicated

steady-state input conditions were established.

LATCH SELECTION TABLE

SELECT INPUTS LATCH

ADDRESSEDA2 A1 A0

LLL 0

LLH 1

LHL 2

LHH 3

HLL 4

HLH 5

HHL 6

HHH 7

CD54/74HC259, CD54/74HCT259

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, IO

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input

Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input

Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

- - ---- - - -V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

- - ---- - - -V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC or

GND -6--±0.1 - ±1-±1µA

CD54/74HC259, CD54/74HCT259

Quiescent Device

Current ICC VCC or

GND 0 6 - - 8 - 80 - 160 µA

HCT TYPES

High Level Input

Voltage VIH - - 4.5 to

5.5 2--2 - 2 - V

Low Level Input

Voltage VIL - - 4.5 to

5.5 - - 0.8 - 0.8 - 0.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V

High Level Output

Voltage

TTL Loads

-4 4.5 3.98 - - 3.84 - 3.7 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC and

GND 0 5.5 - ±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 5.5 - - 8 - 80 - 160 µA

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

∆ICC VCC

-2.1 - 4.5 to

5.5 - 100 360 - 450 - 490 µA

NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) speciﬁcation is 1.8mA.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

A0 - A2, LE 1.5

D 1.2

MR 0.75

NOTE: Unit Load is ∆ICC limit speciﬁed in DC Electrical Table, e.g.,

360µA max at 25oC.

Prerequisite for Switching Speciﬁcations

PARAMETER SYMBOL VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

HC TYPES

Pulse Width tWL

LE 2 70 - - 90 - - 105 - - ns

4.5 14 - - 18 - - 21 - - ns

612--15- -18--ns

CD54/74HC259, CD54/74HCT259

MR tWL 2 70 - - 90 - - 105 - - ns

4.5 14 - - 18 - - 21 - - ns

612--15- -18--ns

Setup Time tSU

D to LE

A to LE 2 80 - - 100 - - 120 - - ns

4.5 16 - - 20 - - 24 - - ns

614--17- -20--ns

Hold Time tH

D to LE

A to LE 20--0--0--ns

4.5 0 - - 0 - - 0 - - ns

60--0--0--ns

HCT TYPES

Pulse Width

tWL 4.5 18 - - 23 - - 27 - - ns

Setup Time

D to LE

A to LE

tSU 4.5 17 - - 21 - - 26 - - ns

Hold Time

D to LE

A to LE

tH4.5 0 - - 0 - - 0 - - ns

Prerequisite for Switching Speciﬁcations (Continued)

PARAMETER SYMBOL VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

Switching Speciﬁcations CL = 50pF, Input tr, tf= 6ns

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC-40oC TO

85oC-55oC TO

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Propagation Delay tPHL CL = 50pF

D to Q 2 - - 185 - 230 - 280 ns

4.5 - - 37 - 46 - 56 ns

CL = 15pF 5 - 15 - - - - - ns

CL = 50pF 6 - - 31 - 39 - 48 ns

LE to Q tPHL CL = 50pF 2 - - 170 - 215 - 255 ns

4.5 - - 34 - 43 - 51 ns

CL = 15pF 5 - 14 - - - - - ns

CL = 50pF 6 - - 29 - 37 - 43 ns

CD54/74HC259, CD54/74HCT259

A to Q tPHL CL = 50pF 2 - - 185 - 230 - 280 ns

4.5 - - 37 - 46 - 56 ns

CL = 15pF 5 - 15 - - - - - ns

CL = 50pF 6 - - 31 - 39 - 48 ns

MR to Q tPHL, tPLH CL = 50pF 2 - - 155 - 195 - 235 ns

4.5 - - 31 - 39 - 47 ns

CL = 15pF 5 - 13 - - - - - ns

CL = 50pF 6 - - 26 - 33 - 40 ns

Output Transition Time tTHL, tTLH CL = 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Power Dissipation Capacitance

(Notes 4, 5) CPD CL = 15pF 5 - 21 - - - - - pF

Input Capacitance CICL = 50pF - 10 - 10 - 10 - 10 pF

HCT TYPES

Propagation Delay tPHL, tPLH

D to Q CL = 50pF 4.5 - - 39 - 49 - 59 ns

CL = 15pF 5 - 16 - - - - - ns

LE to Q CL = 50pF 4.5 - - 38 - 48 - 57 ns

CL = 15pF 5 - 16 - - - - - ns

A to Q CL = 50pF 4.5 - - 41 - 51 - 61 ns

CL = 15pF 5 - 17 - - - - - ns

MR to Q CL = 50pF 4.5 - - 39 - 49 - 59 ns

CL = 15pF 5 - 16 - - - - - ns

Power Dissipation Capacitance

(Notes 4, 5) CPD CL = 15pF 5 - 22 - - - - - pF

Input Capacitance CICL = 50pF - 10 - 10 - 10 - 10 pF

Output Transition Time tTHL, tTLH CL = 50pF 4.5 - - 15 - 19 - 22 ns

NOTES:

4. CPD is used to determine the dynamic power consumption, per package.

5. PD=C

PD VCC2fi+∑CLVCC2fOwhere fi= Input Frequency, fO= Output Frequency, CL= Output Load Capacitance,

VCC = Supply Voltage.

Switching Speciﬁcations CL = 50pF, Input tr, tf= 6ns (Continued)

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC-40oC TO

85oC-55oC TO

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

CD54/74HC259, CD54/74HCT259

Test Circuits and Waveforms

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

FIGURE 3. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

CLOCK 90% 50%

10% GND

VCC

trCLtfCL

50% 50%

tWL tWH

10%

tWL + tWH =fCL

CLOCK 2.7V 1.3V

0.3V GND

trCL= 6ns tfCL= 6ns

1.3V 1.3V

tWL tWH

0.3V

tWL + tWH =fCL

tPHL tPLH

tTHL tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns tf = 6ns

90%

tPHL tPLH

tTHL tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

tr = 6ns tf = 6ns

90%

trCLtfCL

GND

VCC

GND

VCC

50%

90%

10%

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

VCC 50%

50%

90%

10%

50%

90%

tREM

tPLH

tSU(H)

tTLH tTHL

tH(L)

tPHL

IC CL

50pF

tSU(L)

tH(H)

trCLtfCL

GND

1.3V

2.7V

0.3V

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

3V 1.3V

1.3V

90%

10%

1.3V

90%

tREM

tPLH

tSU(H)

tTLH tTHL

tH(L)

tPHL

IC CL

50pF

tSU(L)

1.3V

tH(H)

1.3V

CD54/74HC259, CD54/74HCT259

FIGURE 7. HC THREE-STATE PROPAGATION DELAY

WAVEFORM FIGURE 8. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto

VCC, CL = 50pF. FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

Test Circuits and Waveforms

(Continued)

50% 10%

90%

GND

VCC

10%

90% 50%

50%

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED OUTPUTS

DISABLED OUTPUTS

ENABLED

6ns 6ns

tPZH

tPHZ

tPZL

tPLZ

0.3

2.7

GND

10%

90%

1.3V

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED OUTPUTS

DISABLED OUTPUTS

ENABLED

tr6ns

tPZH

tPHZ

tPZL

tPLZ

6ns tf

1.3

IC WITH

THREE-

STATE

OUTPUT

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

VCC FOR tPLZ AND tPZL

GND FOR tPHZ AND tPZH

OUTPUT

RL = 1kΩ

50pF

CD54/74HC259, CD54/74HCT259

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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

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