ISL6536IBZ-T - RENESAS TECHNOLOGY

FN9114 Rev 3.00 Page 1 of 7

Jan 25, 2011

FN9114

Rev 3.00

Jan 25, 2011

ISL6536

Four Channel Supervisory IC

DATASHEET

The ISL6536 is a four channel supervisory IC designed to

monitor voltages >, = 0.7V. This IC bias range is from 2.7V

to 4V but can supervise any positive voltage using an

external resistor divider to translate to a lower voltage for

comparison to the internal 0.63V reference.

Once properly biased and enabled when all four voltage

monitor (VMON) inputs are satisfied the PGOOD output will

be immediately released to go high to signal that voltage is

valid on all four rails. Subsequently when the monitored

voltage on any rail drops below its user defined threshold

point, the PGOOD output is pulled low. Each rail’s VMON

point is independently adjustable with a resistor divider. The

PGOOD output is guaranteed to be valid with IC bias lower

than 1V. The VMON inputs will ignore 30µs transients on the

monitored supplies. The PGOOD output is an open-drain to

allow ORing of multiple signals and interfacing to a range of

logic levels. The ENABLE input provides for a reset of the

PGOOD output when it is pulled down below 0.5V. With an

internal 10uA pull-up to VDD it can be signalled with

common logic or pulled to ground with a push button switch.

Typical Application Schematic

Features

• Adjustable undervoltage lockout for each supply

• Active high PGOOD Output

• Guaranteed PGOOD Valid to Falling VDD < 1V

• VMON Glitch Immunity

•Pb-Free (RoHS Compliant)

Applications

• Graphics Cards

• Multi voltage DSPs and Processors

• µP Voltage Monitoring

• Embedded Control Systems

• Intelligent Instruments

• Medical Equipment

• Network Routers

• Portable Battery-Powered Equipment

• Set-Top Boxes

• Telecommunications Systems

GND

V1 in

V2 in

V3 in

VMON2

VMON3

VMON1

ISL6536

VMON4

V4 in

VDD

PGD

*OPT

Ordering Information

PART NUMBER

(Note 2)

PART

MARKING

TEMP. RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

ISL6536IBZ 6536 IBZ -40 to +85 8 Ld SOIC M8.15

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin

plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

ISL6536

FN9114 Rev 3.00 Page 2 of 7

Jan 25, 2011

Pin Descriptions

ISL6536 PIN NAME FUNCTION DESCRIPTION

1 VDD Bias IC from nominal 2.7V to 4V

2 PGOOD PGOOD is the boolean AND function of all the UV inputs being satisfied. This is an open drain output and

can be pulled high to the appropriate level with an external resistor. Additionally a 20k pull up to VDD is

provided internally.

3 ENABLE Enabling input for supervisory function. Has a 10µA pull-up to VDD

4 GND IC ground

5-8 VMON1

VMON2

VMON3

VMON4

These inputs provide for a programmable monitored voltage threshold referenced to an internal 0.63V

reference. These inputs have a 30µs glitch filter to prevent transient upsets from being recognized by

PGOOD.

VMON1

VMON2

VMON3

VMON4

20k

10µA

VDD

PGOOD

ISL6536

633mV

FALLING EDGE

GLITCH FILTER

ISL6536

FN9114 Rev 3.00 Page 3 of 7

Jan 25, 2011

Absolute Maximum Ratings Thermal Information

VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V

VMON, PGOOD, ENABLE. . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV (HBM)

Operating Conditions

VDD Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . +2.7V to +4V

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C

Thermal Resistance (Typical, Note 1) JA (°C/W)

8 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . .-65°C to 150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details.

2. All voltages are relative to GND, unless otherwise specified.

Electrical Specifications Nominal VDD = 3.3V, TA = TJ = -40°C - 85°C, Unless Otherwise Specified.

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 3) TYP

MAX

(Note 3) UNIT

BIAS

IC Supply Current IVDD VMON > VMON_L2H 165 1000 µA

VDD Power On VDD_L2H VDD low to high 2.6 V

VDD Power On Reset VDD_POR VDD high to low 2.4 V

PGOOD

Pull-Down Current PGpd VPGOOD = 0.5V 2 mA

Pull-Up Resistance PGpu 20 k

Output Low VPGl VDD = 1V 0.05 0.1 V

Delay from VMON Rising tPGdelVMON Last valid input = Vth to PG release 2 µs

Delay from EN Rising tPGdelENR EN high to PG release 0.05 µs

Delay from EN Falling tPGdelENF EN low to PG pulling low 0.015 µs

ENABLE

Rising Threshold VEN ENABLE Low to High Threshold 0.4VDD 0.5VDD 0.6VDD V

Threshold Hysteresis VEN_HYS 0.065 V

Pull-up Current IENpu VEN = 0.5V 10 µA

VMON Input

Falling Threshold 3.3VMON_H2L TJ = +25°C 0.623 0.633 0.643 V

Falling Threshold Temp Coeff. 3.3VMON_TC 100 uV/°C

Hysteresis VVMON_HYS -10-mV

Range VMON_RNG -8-mV

Glitch Filter Duration TFIL VMON glitch to PGOOD low Filter - 30 - µs

NOTE:

3. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

ISL6536

FN9114 Rev 3.00 Page 4 of 7

Jan 25, 2011

ISL6536 Description and Operation

The ISL6536 is a four channel supervisory IC designed to

monitor multiple voltages greater than 0.7V. This IC is

suitable for both microprocessors or industrial system

applications.

Upon VDD bias power up the PGOOD output is held low

with VDD as low as 0V. Once biased to 2.6V and enabled

the IC continuously monitors from one to four voltages

independently through external resistor dividers comparing

each VMON pin voltage to an internal 0.63V reference.

Once all VMON input voltages rise above 0.63V the PGOOD

(power good) output signal is released and is pulled high via

an external pull resistor to indicate that the power conditions

have been met. The PGOOD output is an open-drain to

allow ORing of the signals and interfacing to a wide range of

logic levels.

Once any VMON input falls below 0.63V the PGOOD output

is pulled low, the VMON inputs are designed to reject fast

transients (30µs).

If less than four voltages are being monitored, connect the

unused VMON pins to VDD.

The PGOOD pin has an internal 20k pull-up to VDD

making an external pull-up resistor unnecessary.

Figure 1 illustrates the operational timing diagram.

FIGURE 1. ISL6536 OPERATIONAL TIMING DIAGRAM

VTH

LAST EN/VMON INPUT

PGOOD OUTPUT

TFIL

4/5 EN/VMON INPUTS HIGH

<TFIL

ISL6536

FN9114 Rev 3.00 Page 5 of 7

Jan 25, 2011

Typical Performance Curves

FIGURE 2. VDD CURRENT vs. VDD VOLTAGE FIGURE 3. VMON THRESHOLD vs. VDD VOLTAGE

FIGURE 4. EN HIGH to PGOOD FIGURE 5. VMON HIGH to PGOOD

FIGURE 6. EN LOW to PGOOD FIGURE 7. VMON LOW to PGOOD

0.5

0.4

0.3

0.2

0.1

VDD BIAS VOLTAGE (V)

0.6

VDD BIAS CURRENT (mA)

2.6 3.0 3.33 3.66 4.0

VMON<VMON_L2H

VMON>VMON_L2H

0.645

0.642

0.639

0.636

0.633

0.627

VMON THRESHOLD (V)

VDD BIAS VOLTAGE (V)

3.32.6 3.9

0.630

3.7

3.5

PG = 1V/DIV

EN = 1V/DIV 1µs/DIV

PGOOD

PG = 2V/DIV

VMON = 1V/DIV 1µs/DIV

PGOOD

VMON

EN = 1V/DIV

PG = 1V/DIV 10nS/DIV

PGOOD

PGOOD = 2V/DIV

VMON = 1V/DIV 10µs/DIV

VMON

PGOOD

FN9114 Rev 3.00 Page 6 of 7

Jan 25, 2011

ISL6536

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

For additional products, see www.intersil.com/en/products.html

All trademarks and registered trademarks are the property of their respective owners.

FIGURE 8. EN LOW to PGOOD FIGURE 9. VMON LOW to PGOOD

Typical Performance Curves (Continued)

EN = 1V/DIV

PG = 1V/DIV 10nS/DIV

PGOOD

PGOOD = 2V/DIV

VMON = 1V/DIV 10µs/DIV

VMON

PGOOD

ISL6536

FN9114 Rev 3.00 Page 7 of 7

Jan 25, 2011

Package Outline Drawing

M8.15

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 2, 11/10

DETAIL "A"

TOP VIEW

INDEX

AREA

123

-C-

SEATING PLANE

x 45°

NOTES:

1. Dimensioning and tolerancing per ANSI Y14.5M-1982.

2. Package length does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

3. Package width does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

4. The chamfer on the body is optional. If it is not present, a visual index fea-

ture must be located within the crosshatched area.

5. Terminal numbers are shown for reference only.

6. The lead width as measured 0.36mm (0.014 inch) or greater above the seat-

ing plane, shall not exceed a maximum value of 0.61mm (0.024 inch).

7. Controlling dimension: MILLIMETER. Converted inch dimensions are not

necessarily exact.

8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.

SIDE VIEW “A

SIDE VIEW “B”

1.27 (0.050)

6.20 (0.244)

5.80 (0.228)

4.00 (0.157)

3.80 (0.150)

0.50 (0.20)

0.25 (0.01)

5.00 (0.197)

4.80 (0.189)

1.75 (0.069)

1.35 (0.053)

0.25(0.010)

0.10(0.004)

0.51(0.020)

0.33(0.013)

8°

0°

0.25 (0.010)

0.19 (0.008)

1.27 (0.050)

0.40 (0.016)

1.27 (0.050)

0.200

TYPICAL RECOMMENDED LAND PATTERN

2.41 (0.095)

0.76 (0.030)