TK28F010 1024K (128K X 8) CMOS FLASH MEMORY April 10, 2017 Product Overview Features o o Non-volatile Flash Memory Fast Read access Time =90 and -120 ns. o Flash Electrical Chip-Erase o General Description The Tekmos TK28F010 is a high speed 1M CMOS non-volatile flash memory arranged as 128K x 8. (131,072 x 8 bits) It is electrically erasable and reprogrammable. It is well suited for use in applications where codes are changed after the initial programming, during manufacture, final test or after sale. Memory contents can be changed in a test fixture, in a PROM programmer, or in system. 5 Second Typical Chip-Erase Quick Programming Algorithm 10 s Typical Byte-Program 2 Second Chip-Program o 12.0 V 5% VPP chip erase o 100,000 Erase/Program Cycles o 10 year data retention o CMOS Low Power Consumption 10 mA Typical Active Current 50 A Typical Standby Current o Command Register Architecture for Microprocessor/Microcontroller Compatible Write Interface o Great Noise Immunity Features The TK28F010 is manufactured to allow for low power consumption and immunity to noise. The device is designed to withstand 100,000 program/erase cycles without losing data integrity. Data retention is at least 10 years. Standby current maximum is 100 A providing significant power saving when the device is deselected. Access time of 90 ns provides zero wait state performance compatible with many microcontrollers and microprocessors. Electrical erasure of the entire memory is typically achieved in less than 5 seconds. 12 volt programming and erase voltage makes it compatible with similar devices. The erase procedure has a two-step process that ensures against accidental erasure of the contents of the memory. The erase command is actually written twice before it is executed. An integrated stop feature allows for automatic timing control eliminating the need for a maximum erase timing specification. 10% VCC Tolerance o -40oC to +85oC operation - Industrial -55oC to +125oC operation - Military o Safely abort Erase or Program sequence at any time including Integrated Program/Erase Stop Timer o Protection against inadvertent programming during power up. o JEDEC-Standard Pinouts 1 32-Pin Plastic Dip 32-Lead PLCC 32-Lead TSOP An Abort/Reset command is available to allow the user to safely abort an erase or program sequence. The abort/reset operation can interrupt at any time in a program or erase operation and the device is reset to the Read Mode. Protection against inadvertent programming during power up is provided. VPP and VCC may be powered up in any order, no sequencing is required. The TK28F010 is offered in 32-Pin Plastic DIP or 32Lead PLCC and 32-Lead TSOP packages. Conforming to JEDEC standards, it is pin for pin compatible with standard EPROM and EEPROM devices. The TK28F010 is often used as a drop in replacement in systems originally designed for other manufacturer's 28F010 devices. www.Tekmos.com 4/10/17 TK28F010 CMOS 1024K Flash Memory Pin Configurations PDIP Package PLCC Package 2 www.Tekmos.com 4/10/17 TK28F010 CMOS 1024K Flash Memory TSOP Pin Functions 3 DIP/ PCC Pin # TSOP Pin # Pin Name 1 9 VPP 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 VSS Type Function Program Erase Voltage Supply Input Address memory Input Address memory Input Address memory Input Address memory Input Address memory Input Address memory Input Address memory Input Address memory Input Address memory Input Address memory Input Address memory I/O Data Input/ Output I/O Data Input/ Output I/O Data Input/ Output Supply Ground Input DIP/ PCC Pin # TSOP Pin # Pin Name Type Function 17 25 I/O 3 Input Data Input/ Output 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 I/O 4 I/O 5 I/O 6 I/O 7 Input Input Input Input Input Input Input Input Input Input Input Input Input Supply Data Input/ Output Data Input/ Output Data Input/ Output Data Input/ Output Chip Enable Address memory Output Enable Address memory Address memory Address memory Address memory Data Input/ Output No Connection Data Input/ Output Voltage Supply www.Tekmos.com CE A10 OE A11 A9 A8 A13 A14 N/C WE VCC 4/10/17 TK28F010 CMOS 1024K Flash Memory Absolute Maximum Ratings* Temperature Under Bias Storage Temperature Voltage on Any Pin with Respect to Ground(1) Voltage on Pin A9 with Respect to Ground(1) VPP with Respect to Ground during Program/Erase(1) Package Power Dissipation Capability (TA = 25C) Lead Soldering Temperature (10 seconds) Output Short Circuit Current(2) -40C to +85C -55C to +150C -0.5V to +VCC + 0.5V -0.5V to +13.5V -0.5V to +14.0V 1.0 W 300C 100 mA Reliability Characteristics Symbol Parameter Units Test Method 100K Cycles/Byte MIL-STD-883, Test Method 1033 10 Years MIL-STD-883, Test Method 1008 ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 Latch-Up 100 mA NEND(3) Endurance TDR(3) Data Retention VZAP(3) ILTH(3)(4) Min Max JEDEC Standard 17 CAPACITANCE TA = 25C, f = 1.0 MHz Limits Symbol Max. Units Input Pin Capacitance 6 pF VIN = 0V COUT(3) Output Pin Capacitance 10 pF VOUT = 0V CVPP(3) VPP Supply Capacitance 25 pF VPP = 0V CIN(3) Test Min Conditions NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Other Notes: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V. 4 www.Tekmos.com 4/10/17 TK28F010 CMOS 1024K Flash Memory (VCC = +5V 10%, unless otherwise specified) D.C. Operating Characteristics Limits Symbol Parameter Min. Max. Unit Test Conditions ILI Input Leakage Current 1 A VIN = VCC or VSS VCC = 5.5V, OE = VIH ILO Output Leakage Current 1 A VOUT = VCC or VSS, VCC = 5.5V, OE = VIH ISB1 VCC Standby Current CMOS 100 A CE = VCC 0.5V, VCC = 5.5V ISB2 VCC Standby Current TTL 1 mA CE = VIH, VCC = 5.5V ICC1 VCC Active Read Current 30 mA VCC = 5.5V, CE = VIL, IOUT = 0mA, f = 6 MHz ICC2(1) VCC Programming Current 15 mA VCC = 5.5V, Programming in Progress ICC3 VCC Erase Current 15 mA VCC = 5.5V, Erasure in Progress ICC4 VCC Prog./Erase Verify Current 15 mA VCC = 5.5V, Program or Erase Verify in Progress IPPS VPP Standby Current 10 A VPP = VPPL IPP1 VPP Read Current 200 A VPP = VPPH (1) VPP Programming Current 30 mA VPP = VPPH, Programming in Progress (1) VPP Erase Current 30 mA VPP = VPPH, Erasure in Progress IPP4 (1) VPP Prog./Erase Verify Current 5 mA VPP = VPPH, Program or Erase Verify in Progress VIL Input Low Level TTL -0.5 0.8 V VILC Input Low Level CMOS -0.5 0.8 V VOL Output Low Level 0.45 V VIH Input High Level TTL 2 VCC+0.5 V VIHC Input High Level CMOS VCC*0.7 VCC+0.5 V VOH1 Output High Level TTL 2.4 V IOH = -2.5mA, VCC = 4.5V VOH2 Output High Level CMOS VCC-0.4 V IOH = -400A, VCC = 4.5V VID A9 Signature Voltage 13 V A9 = VID 200 A IPP2 IPP3 (1) 11.4 IID A9 Signature Current VLO VCC Erase/Prog. Lockout Voltage 2.5 IOL = 5.8mA, VCC = 4.5V V Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. 5 www.Tekmos.com 4/10/17 TK28F010 CMOS 1024K Flash Memory SUPPLY CHARACTERISTICS Limits Symbol Parameter VCC VCC Supply Voltage VPPL VPP During Read Operations VPPH VPP During Read/Erase/Program Min Max. Unit 4.5 5.5 V 0 Vcc+0.5 V 11.4 12.6 V A.C. CHARACTERISTICS, Read Operation VCC = +5V 10%, unless otherwise specified. Temperature -40oC to +85oC, unless otherwise specified. JEDEC Symbol Standard Symbol Parameter tAVAV tRC Read Cycle Time tELQV tCE Access Time tAVQV tACC tGLQV tOE tAXQX tOH Min Max Unit 90 ns 90 ns Address Access Time 90 ns Access Time 55 ns Output Hold from Address / Change 0 ns tGLQX tOLZ (1)(6) to Output in Low-Z 0 ns tELZX tLZ (1)(6) to Output in Low-Z 0 ns tGHQZ tDF(1)(2) High to Output High-Z 20 ns tEHQZ tDF(1)(2) High to Output High-Z 30 ns tWHGL(1) Write Recovery Time Before Read s 6 Figure 1. A.C. Testing Input / Output Waveforms(3)(4)(5) 2.4 V 2.0 V 0.8 V 0.45 V UNDER TEST CL = 100 pF CL Includes Jig Capacitance 51This parameter is tested initially and after a design or process change that affects the parameter. (1) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer. (2) Input Rise and Fall Times (10% to 90%) < 10 ns. 6 www.Tekmos.com 4/10/17 TK28F010 CMOS 1024K Flash Memory (3) (4) (5) (6) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V. Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V. Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid. For load and reference points, see Fig. 1 A.C. CHARACTERISTICS, Program/Erase Operation VCC = +5V 10%, unless otherwise specified. JEDEC Symbol Standard Symbol tAVAV tAVWL tWLAX tDVWH tWHDX tELWL tWHEH tWLWH tWHWL tWC tAS tAH tDS tDH tCS tCH tWP tWPH (2) - (2) - tWHWH1 tWHWH tWHGL tGHWL tVPEL - Parameter Min Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Setup Time Hold Time Pulse Width High Pulse Width Program Pulse Width Erase Pulse Width Write Recovery Time Before R d Recovery Time Before Read WPPit Setup Time to V Erase and Programming Performance Parameter Chip Erase Time (3) Chip Program Time (3)(4) Min Typ Max Unit 90 0 40 40 10 0 0 40 20 ns ns ns ns ns ns ns ns ns 10 s 9.5 ms 6 0 100 s s ns (1) Typ 0.5 2 Max 10 12.5 Unit Sec Sec Note: (1) Please refer to Supply characteristics for the value of VPPH and VPPL. The VPP supply can be either hardwired or switched. If VPP is switched, VPPL can be ground, less than VCC + 2.0V or a no connect with a resistor tied to ground. (2) Program and Erase operations are controlled by internal stop timers. (3) `Typicals' are not guaranteed, but based on characterization data. Data taken at 25C, 12.0V VPP. (4) Minimum byte programming time (excluding system overhead) is 16 s (10 s program + 6 s write recovery), while maximum is 400 s/ byte (16 s x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte. 7 www.Tekmos.com 4/10/17 TK28F010 CMOS 1024K Flash Memory Function Table(1) Pins Mode CE OE WE VPP I/O Read VIL VIL VIH VPPL DOUT Output Disable VIL VIH VIH X High-Z Standby VIH X X VPPL High-Z Signature (MFG) VIL VIL VIH X 31H A0 = VIL, A9 = 12V Signature (Device) VIL VIL VIH X B4H A0 = VIH, A9 = 12V Program/Erase VIL VIH VIL VPPH DIN See Command Table Write Cycle VIL VIH VIL VPPH DIN During Write Cycle Read Cycle VIL VIL VIH VPPH DOUT During Write Cycle Notes Write Command Table Commands are written into the command register in one or two write cycles. The command register can be altered . Write cycles also internally latch only when VPP is high and the instruction byte is latched on the rising edge of addresses and data required for programming and erase operations. Pins First Bus Cycle Second Bus Cycle Operation Address DIN Operation Address Set Read Write X 00H Read AIN DOUT Read Sig. (MFG) Write X 90H Read 00 31H Read Sig. (Device) Write X 90H Read 01 B4H Erase Write X 20H Write X Erase Verify Write AIN A0H Read X Program Write X 40H Write AIN Program Verify Write X C0H Read X Reset Write X FFH Write X Mode DIN 20H DOUT DIN DOUT FFH Note: (1) Logic Levels: X = Logic `Do not care' (VIH, VIL, VPPL, VPPH) 8 www.Tekmos.com DOUT 4/10/17 TK28F010 CMOS 1024K Flash Memory READ OPERATIONS Read Mode The conventional mode is entered as a regular READ mode by driving the and pins low (with high), and applying the required high voltage on address pin A9 while all other address lines are held at VIL. A Read operation is performed with both and low and with high. VPP can be either high or low, however, if VPP is high, the Set READ command has to be sent before reading data (see Write Operations). The data retrieved from the I/O pins reflects the contents of the memory location corresponding to the state of the 17 address pins. The respective timing waveforms for the read operation are shown in Figure 3. Refer to the AC Read characteristics for specific timing parameters. A Read cycle from address 0000H retrieves the binary code for the IC manufacturer on outputs I/O0 to I/O7: Tekmos Code = 0011 0100 (34H) A Read cycle from address 0001H retrieves the binary code for the device on outputs I/O0 to I/O7. Signature Mode 28F010 Code = 1011 0100 (B4H) The signature mode allows the user to identify the IC manufacturer and the type of device while the device resides in the target system. This mode can be activated in either of two ways; through the conventional method of applying a high voltage (12V) to address pin A9 or by sending an instruction to the command register (see Write Operations). Standby Mode With at a logic-high level, the TK28F010 is placed in a standby mode where most of the device circuitry is disabled, thereby substantially reducing power consumption. The outputs are placed in a high-impedance state. Figure 3. A.C. Timing for Read Operation POWER UP STANDBY DEVICE AND ADDRESS SELECTION ADDRESSES OUPUTS ENABLED DATA VALID STANDBY POWER DOWN ADDRESS STABLE tAVAV (tRC) CE (E) tEHQZt(DF) OE (G) tWHGL tGHQZ (tDF) tGLQV (tOE) WE (W) tGLQX (tOLZ) tELQX (tLZ) HIGH-Z tELQV (tCE) tAXQXt(OH) OUTPUT VALID DATA (I/O) HIGH-Z tAVQV (tACC) 9 www.Tekmos.com 4/10/17 TK28F010 CMOS 1024K Flash Memory WRITE OPERATIONS Signature Mode The following operations are initiated by observing the sequence specified in the Write Command Table. An alternative method for reading device signature (see Read Operations Signature Mode), is initiated by writing the code 90H into the command register while keeping VPP high. A read cycle from address 0000H with and low (and high) will output the device signature. Read Mode The device can be put into a standard READ mode by initiating a write cycle with 00H on the data bus. The subsequent read cycles will be performed similar to a standard EPROM or EEPROM Read. Tekmos Code = 0011 0100 (34H) A Read cycle from address 0001H retrieves the binary code for the device on outputs I/O0 to I/O7. 28F010 Code = 1011 0100 (B4H) 10 www.Tekmos.com 4/10/17 TK28F010 CMOS 1024K Flash Memory Note: (1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device 11 www.Tekmos.com 4/10/17 TK28F010 CMOS 1024K Flash Memory Erase Mode Erase-Verify Mode During the first Write cycle, the command 20H is written into the command register. In order to commence the erase operation, the identical command of 20H has to be written again into the register. This two-step process ensures against accidental erasure of the memory contents. The final erase cycle will be stopped at the rising edge of , at which time the Erase Verify command (A0H) is sent to the command register. During this cycle, the address to be verified is sent to the address bus and latched when goes low. An integrated stop timer allows for automatic timing control over this operation, eliminating the need for a maximum erase timing specification. Refer to AC Characteristics (Program/Erase) for specific timing parameters. The Erase-Verify operation is performed on every byte after each erase pulse to verify that the bits have been erased. 12 Programming Mode The programming operation is initiated using the programming algorithm of Figure 7. During the first write cycle, the command 40H is written into the command register. During the second write cycle, the address of the memory location to be programmed is latched on the falling edge of , while the data is latched on the rising edge of . The program operation terminates with the next rising edge of . An integrated stop timer allows for automatic timing control over this operation, eliminating the need for a maximum program timing specification. Refer to AC Characteristics (Program/Erase) for specific timing parameters. www.Tekmos.com 4/10/17 TK28F010 CMOS 1024K Flash Memory Note: (1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device 13 www.Tekmos.com 4/10/17 TK28F010 CMOS 1024K Flash Memory Program-Verify Mode A Program-Verify cycle is performed to ensure that all bits have been correctly programmed following each byte programming operation. The specific address is already latched from the write cycle just completed, and stays latched until the verify is completed. The Program-Verify operation is initiated by writing C0H into the command register. An internal reference generates the necessary high voltages so that the user does not need to modify VCC. Refer to AC Characteristics (Program/Erase) for specific timing parameters. Abort/Reset An Abort/Reset command is available to allow the user to safely abort an erase or program sequence. Two consecutive program cycles with FFH on the data bus will abort an erase or a program operation. The abort/ reset operation can interrupt at any time in a program or erase operation and the device is reset to the Read Mode. POWER UP/DOWN PROTECTION The TK28F010 offers protection against inadvertent programming during VPP and VCC power transitions. When powering up the device there is no power-on sequencing necessary. In other words, VPP and VCC may power up in any order. Additionally VPP may be hardwired to VPPH independent of the state of VCC and any power up/down cycling. The internal command register of the TK28F010 is reset to the Read Mode on power up. POWER SUPPLY DECOUPLING To reduce the effect of transient power supply voltage spikes, it is good practice to use a 0.1 F ceramic capacitor between VCC and VSS and VPP and VSS. These high-frequency capacitors should be placed as close as possible to the device for optimum decoupling. Ordering Information 14 www.Tekmos.com 4/10/17 TK28F010 CMOS 1024K Flash Memory Package Temperature Speed Order Number 32 Pin PLCC -40oC to +85oC 120 ns TK28F010NI-12 32 Pin PLCC -40oC to +85oC 90 ns TK28F010NI-90 32 Pin PLCC -55oC to +125oC 95 ns TK28F010NM-95 The PDIP and TSOP packages are available on request. Contact the factory for details. Part Marking Information Parts that have been screened to the military temperature range are marked with a gold dot. Contact Information The TK28F010 can be ordered directly from Tekmos: Tekmos, Inc. 7901 E Riverside Rd. Bldg. 2, Suite 150 Austin, TX 78744 512 342-9871 phone Sales@Tekmos.Com www.Tekmos.com Revision History Date 1/08/15 9/24/15 1/27/17 4/11/17 Revision 1.0 2.0 2.1 2.2 Description Initial Release Specification Data Added Ordering Information for 90ns added, Correct pin numbering. Make military part a -95 speed (c) 2017 Tekmos, Inc. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Tekmos Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Tekmos' products as critical components in life support systems is not authorized except with express written approval by Tekmos. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Tekmos logo and name are registered trademarks of Tekmos, Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. All rights reserved. Terms and product names in this document may be trademarks of others. 15 www.Tekmos.com 4/10/17