TK28F010 1024K (128K X 8)
CMOS FLASH MEMORY
April 10, 2017 Product Overview
1 www.Tekmos.com 4/10/17
Features
o Non-volatile Flash Memory
o Fast Read access Time =90 and -120 ns.
o Flash Electrical Chip-Erase
5 Second Typical Chip-Erase
o Quick Programming Algorithm
10 μs Typical Byte-Program
2 Second Chip-Program
o 12.0 V ±5% VPP chip erase
o 100,000 Erase/Program Cycles
o 10 year data retention
o CMOS Low Power Consumption
10 mA Typical Active Current
50 μA Typical Standby Current
o Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
o Great Noise Immunity Features
±10% VCC Tolerance
o -40
o
C to +85
o
C operation – Industrial
-55
o
C to +125
o
C operation - Military
o Safely abort Erase or Program sequence at any
time including Integrated Program/Erase Stop
Timer
o Protection against inadvertent programming
during power up.
o JEDEC-Standard Pinouts
32-Pin Plastic Dip
32-Lead PLCC
32-Lead TSOP
General Description
The Tekmos TK28F010 is a high speed 1M CMOS
non-volatile flash memory arranged as 128K x 8.
(131,072 x 8 bits) It is electrically erasable and
reprogrammable. It is well suited for use in
applications where codes are changed after the
initial programming, during manufacture, final test or
after sale. Memory contents can be changed in a test
fixture, in a PROM programmer, or in system.
The TK28F010 is manufactured to allow for low
power consumption and immunity to noise. The
device is designed to withstand 100,000
program/erase cycles without losing data integrity.
Data retention is at least 10 years.
Standby current maximum is 100 μA providing
significant power saving when the device is
deselected. Access time of 90 ns provides zero wait
state performance compatible with many
microcontrollers and microprocessors. Electrical
erasure of the entire memory is typically achieved in
less than 5 seconds. 12 volt programming and erase
voltage makes it compatible with similar devices.
The erase procedure has a two-step process that
ensures against accidental erasure of the contents
of the memory. The erase command is actually
written twice before it is executed. An integrated stop
feature allows for automatic timing control
eliminating the need for a maximum erase timing
specification.
An Abort/Reset command is available to allow the
user to safely abort an erase or program sequence.
The abort/reset operation can interrupt at any time in
a program or erase operation and the device is reset
to the Read Mode.
Protection against inadvertent programming during
power up is provided. V
PP
and V
CC
may be powered
up in any order, no sequencing is required.
The TK28F010 is offered in 32-Pin Plastic DIP or 32-
Lead PLCC and 32-Lead TSOP packages.
Conforming to JEDEC standards, it is pin for pin
compatible with standard EPROM and EEPROM
devices. The TK28F010 is often used as a drop in
replacement in systems originally designed for other
manufacturer’s 28F010 devices.
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Pin Configurations
PLCC Package
PDIP Package
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TSOP
Pin Functions
DIP/
PCC
Pin#
TSOP
Pin#
Pin
NameTypeFunction
DIP/
PCC
Pin#
TSOP
Pin#
Pin
NameTypeFunction
19V
PP
InputProgramErase
VoltageSupply1725I/O3InputDataInput/Output
210A16InputAddressmemory 1826I/O4InputDataInput/Output
311A15InputAddressmemory 1927I/O5InputDataInput/Output
412A12InputAddressmemory 2028I/O6InputDataInput/Output
513A7InputAddressmemory 2129I/O7InputDataInput/Output
614A6InputAddressmemory 2230InputChipEnable
715A5InputAddressmemory 2331A10InputAddressmemory
816A4InputAddressmemory 2432InputOutputEnable
917A3InputAddressmemory 251A11InputAddressmemory
1018A2InputAddressmemory 262A9InputAddressmemory
1119A1InputAddressmemory 273A8InputAddressmemory
1220A0InputAddressmemory 284A13InputAddressmemory
1321I/O0I/O DataInput/Output295A14InputDataInput/Output
1422I/O1I/O DataInput/Output306N/C ‐‐‐ NoConnection
1523I/O2I/O DataInput/Output317InputDataInput/Output
1624V
SS
SupplyGround328
V
CC
SupplyVoltageSupply
WE
OE
CE
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Absolute Maximum Ratings*
Temperature Under Bias -40C to +85C
Storage Temperature -55C to +150C
Voltage on Any Pin with Respect to Ground
(1)
-0.5V to +V
CC
+ 0.5V
Voltage on Pin A
9
with Respect to Ground
(1)
-0.5V to +13.5V
V
PP
with Respect to Ground during Program/Erase
(1)
-0.5V to +14.0V
Package Power Dissipation Capability (T
A
= 25C) 1.0 W
Lead Soldering Temperature (10 seconds) 300C
Output Short Circuit Current
(2)
100 mA
Reliability Characteristics
Symbol Parameter Min Max Units Test M ethod
N
END(3)
Endurance 100K
Cycles/Byte MIL-STD-883, Test Method 1033
T
DR(3)
Data Retention 10
Years MIL-STD-883, Test Method 1008
V
ZAP(3)
ESD Susceptibility 2000
Volts MIL-STD-883, Test Method 3015
I
LTH(3)(4)
Latch-Up 100
mA JEDEC Standard 17
CAPACITANCE TA = 25C, f = 1.0 MHz
Symbol
Test
Limits
Units
Conditions
Min Max.
C
IN(3)
Input Pin Capacitance
6 pF V
IN
= 0V
C
OUT(3)
Output Pin Capacitance
10 pF V
OUT
= 0V
C
VPP(3)
V
PP
Supply Capacitance
25 pF V
PP
= 0V
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of
those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and reliability.
Other Notes:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum
DC voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
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D.C. Operating Characteristics
(V
CC
= +5V 10%, unless otherwise specified)
Symbol
Parameter
Limits
Test Conditions
Min. Max. Unit
I
LI
Input Leakage Current
1 A V
IN
= V
CC
or V
SS
V
CC
= 5.5V, OE = V
IH
I
LO
Output Leakage Current
1 A V
OUT
= V
CC
or V
SS
,
V
CC
= 5.5V, OE = V
IH
I
SB1
V
CC
Standby Current CMOS
100 A CE = V
CC
0.5V,
V
CC
= 5.5V
I
SB2
V
CC
Standby Current TTL
1 mA
CE = V
IH
, V
CC
= 5.5V
I
CC1
V
CC
Active Read Current
30 mA
V
CC
= 5.5V, CE = V
IL
,
I
OUT
= 0mA, f = 6 MHz
I
CC2(1)
V
CC
Programming Current
15 mA
V
CC
= 5.5V,
Programming in Progress
I
CC3
V
CC
Erase Current
15 mA
V
CC
= 5.5V,
Erasure in Progress
I
CC4
V
CC
Prog./Erase Verify Current
15 mA
V
CC
= 5.5V, Program or
Erase Verify in Progress
I
PPS
V
PP
Standby Current
10 A V
PP
= V
PPL
I
PP1
V
PP
Read Current
200 A V
PP
= V
PPH
I
PP2
(1)
V
PP
Programming Current
30 mA
V
PP
= V
PPH
,
Programming in Progress
I
PP3
(1)
V
PP
Erase Current
30 mA
V
PP
= V
PPH
,
Erasure in Progress
I
PP4
(1)
V
PP
Prog./Erase Verify Current
5 mA
V
PP
= V
PPH
, Program or
Erase Verify in Progress
V
IL
Input Low Level TTL –0.5 0.8 V
V
ILC
Input Low Level CMOS –0.5 0.8 V
V
OL
Output Low Level
0.45 V I
OL
= 5.8mA, V
CC
= 4.5V
V
IH
Input High Level TTL 2 V
CC
+0.5 V
V
IHC
Input High Level CMOS V
CC
*0.7 V
CC
+0.5 V
V
OH1
Output High Level TTL 2.4
V I
OH
= –2.5mA, V
CC
= 4.5V
V
OH2
Output High Level CMOS V
CC
–0.4
V I
OH
= –400A, V
CC
= 4.5V
V
ID
A9
Signature Voltage 11.4 13 V A
9
= V
ID
I
ID
(1)
A9
Signature Current
200 A
V
LO
V
CC
Erase/Prog. Lockout Voltage 2.5
V
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter.
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UNDER
TEST
C
L
= 100 pF CL Includes
Jig Capacitance
SUPPLY CHARACTERISTICS
Symbol
Parameter
Limits
Unit
Min Max.
V
CC
V
CC
Supply Voltage 4.5 5.5 V
V
PPL
V
PP
During Read Operations 0 Vcc+0.5 V
V
PPH
V
PP
During Read/Erase/Program 11.4 12.6 V
A.C. CHARACTERISTICS,
Read Operation
VCC = +5V 10%, unless otherwise specified. Temperature -40
o
C to +85
o
C, unless otherwise specified.
JEDEC Sy mbol Standard Symbol Parameter Min Max Unit
t
AVAV
t
RC
Read Cycle Time 90
ns
t
ELQV
t
CE
Access Time
90 ns
t
AVQV
t
ACC
Address Access Time
90 ns
t
GLQV
t
OE
Access Time
55 ns
t
AXQX
t
OH
Output Hold from Address / Change 0
ns
t
GLQX
t
OLZ
(1)(6)
to Output in Low-Z 0
ns
t
ELZX
t
LZ
(1)(6)
to Output in Low-Z 0
ns
t
GHQZ
t
DF(1)(2)
High to Output High-Z
20 ns
t
EHQZ
t
DF(1)(2)
High to Output High-Z
30 ns
t
WHGL
(1)
Write Recovery Time Before Read 6
s
Figure 1. A.C. Testing Input / Output Waveforms
(3)(4)(5)
2.4 V
0.45 V
51
This parameter is tested initially and after a design or process change that affects the parameter.
(1) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(2) Input Rise and Fall Times (10% to 90%) < 10 ns.
2.0 V
0.8 V
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(3) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.
(4) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.
(5) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(6) For load and reference points, see Fig. 1
A.C. CHARACTERISTICS
, Program/Erase Operation
V
CC
= +5V ±10%, unless otherwise specified.
JEDEC
Symbol Standard
Symbol Parameter Min Typ Max Unit
t
AVAV
t
WC
Write Cycle Time 90
ns
t
AVWL
t
AS
Address Setup Time 0
ns
t
WLAX
t
AH
Address Hold Time 40
ns
t
DVWH
t
DS
Data Setup Time 40
ns
t
WHDX
t
DH
Data Hold Time 10
ns
t
ELWL
t
CS
Setup Time 0
ns
t
WHEH
t
CH
Hold Time 0
ns
t
WLWH
t
WP
Pulse Width 40
ns
t
WHWL
t
WPH
High Pulse Width 20
ns
t
WHWH1(2)
- Program Pulse Width 10
s
t
WHWH(2)
- Erase Pulse Width 9.5
ms
t
WHGL
-
Write Recovery Time Before
Rd
6
s
t
GHWL
-
Read Recovery Time Before
Wit
0
s
t
VPEL
-
V
PP
Setup Time to 100
ns
Erase and Programming Performance
(1)
Parameter Min Typ Max Unit
Chip Erase Time
(3)
0.5 10 Sec
Chip Program Time
(3)(4)
2 12.5 Sec
Note:
(1) Please refer to Supply characteristics for the value of V
PPH
and V
PPL
. The V
PP
supply can be either hardwired or switched. If
V
PP
is switched, V
PPL
can be ground, less than V
CC
+ 2.0V or a no connect with a resistor tied to ground.
(2) Program and Erase operations are controlled by internal stop timers.
(3) ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25C, 12.0V V
PP
.
(4) Minimum byte programming time (excluding system overhead) is 16 s (10 s program + 6 s write recovery), while maximum is
400 s/ byte (16 s x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming
algorithm since most bytes program significantly faster than the worst case byte.
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Function Table
(1)
Mode Pins
Notes
CE
OE
WE V
PP
I/O
Read V
IL
V
IL
V
IH
V
PPL
D
OUT
Output Disable V
IL
V
IH
V
IH
X High-Z
Standby V
IH
X X V
PPL
High-Z
Signature (MFG) V
IL
V
IL
V
IH
X 31H A
0
= V
IL
, A
9
= 12V
Signature (Device) V
IL
V
IL
V
IH
X B4H A
0
= V
IH
, A
9
= 12V
Program/Erase V
IL
V
IH
V
IL
V
PPH
D
IN
See Command Table
Write Cycle V
IL
V
IH
V
IL
V
PPH
D
IN
During Write Cycle
Read Cycle V
IL
V
IL
V
IH
V
PPH
D
OUT
During Write Cycle
Write Command Table
Commands are written into the command register in one or two write cycles. The command register can be altered
only when V
PP
is high and the instruction byte is latched on the rising edge of . Write cycles also internally latch
addresses and data required for programming and erase operations.
Mode
Pins
First Bus Cycle Second Bus Cy cle
Operation Address D
IN
Operation Address D
IN
D
OUT
Set Read Write X 00H Read A
IN
D
OUT
Read Sig. (MFG) Write X 90H Read 00
31H
Read Sig. (Device) Write X 90H Read 01
B4H
Erase Write X 20H Write X 20H
Erase Verify Write A
IN
A0H Read X
D
OUT
Program Write X 40H Write
A
IN
D
IN
Program Verify Write X C0H Read X
D
OUT
Reset Write X FFH Write X FFH
Note:
(1) Logic Levels: X = Logic ‘Do not care’ (V
IH
, V
IL
, V
PPL
, V
PPH
)
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READ OPERATIONS
Read Mode
A Read operation is performed with both and low
and with high. V
PP
can be either high or low,
however, if V
PP
is high, the Set READ command has to
be sent before reading data (see Write Operations). The
data retrieved from the I/O pins reflects the contents of
the memory location corresponding to the state of the 17
address pins. The respective timing waveforms for the
read operation are shown in Figure 3. Refer to the AC
Read characteristics for specific timing parameters.
Signature Mode
The signature mode allows the user to identify the IC
manufacturer and the type of device while the device
resides in the target system. This mode can be activated
in either of two ways; through the conventional method
of applying a high voltage (12V) to address pin A9
or by
sending an instruction to the command register (see
Write Operations).
The conventional mode is entered as a regular READ
mode by driving the and pins low (with high),
and applying the required high voltage on address pin A
9
while all other address lines are held at V
IL
.
A Read cycle from address 0000H retrieves the binary
code for the IC manufacturer on outputs I/O
0
to I/O
7
:
Tekmos Code = 0011 0100 (34H)
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O
0
to I/O
7
.
28F010 Code = 1011 0100 (B4H)
Standby Mode
With at a logic-high level, the TK28F010 is placed in
a standby mode where most of the device circuitry is
disabled, thereby substantially reducing power con-
sumption. The outputs are placed in a high-impedance
state.
Figure 3. A.C. Timing for Read Operation
POWER UP STANDBY DEVICE AND
ADDRESS SELECTION
OUPUTS
ENABLED
DATA VALID STANDBY POWER DOWN
ADDRESSES
CE (E)
ADDRESS STABLE
tAVAV (tRC)
tEHQZt(DF)
OE (G)
WE (W)
DATA (I/O)
HIGH-Z
tWHGL
tGLQX (tOLZ)
tELQX (tLZ)
tGLQV (tOE)
tGHQZ (tDF)
tELQV (tCE) tAXQXt(OH)
OUTPUT VALID
HIGH-Z
tAVQV (tACC)
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WRITE OPERATIONS
The following operations are initiated by observing the
sequence specified in the Write Command Table.
Read Mode
The device can be put into a standard READ mode by
initiating a write cycle with 00H on the data bus. The
subsequent read cycles will be performed similar to a
standard EPROM or EEPROM Read.
Signature Mode
An alternative method for reading device signature (see
Read Operations Signature Mode), is initiated by writing
the code 90H into the command register while keeping
V
PP
high. A read cycle from address 0000H with and
low (and high) will output the device signature.
Tekmos Code = 0011 0100 (34H)
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O
0
to I/O
7
.
28F010 Code = 1011 0100 (B4H)
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Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device
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Erase Mode
During the first Write cycle, the command 20H is written
into the command register. In order to commence the
erase operation, the identical command of 20H has to be
written again into the register. This two-step process
ensures against accidental erasure of the memory con-
tents. The final erase cycle will be stopped at the rising
edge of , at which time the Erase Verify command
(A0H) is sent to the command register. During this cycle,
the address to be verified is sent to the address bus and
latched when goes low. An integrated stop timer
allows for automatic timing control over this operation,
eliminating the need for a maximum erase timing speci-
fication. Refer to AC Characteristics (Program/Erase)
for specific timing parameters.
Erase-Verify Mode
The Erase-Verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.
Programming Mode
The programming operation is initiated using the pro-
gramming algorithm of Figure 7. During the first write
cycle, the command 40H is written into the command
register. During the second write cycle, the address of
the memory location to be programmed is latched on the
falling edge of , while the data is latched on the rising
edge of . The program operation terminates with the
next rising edge of . An integrated stop timer allows
for automatic timing control over this operation, eliminat-
ing the need for a maximum program timing specifica-
tion. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.
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Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device
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Program-Verify Mode
A Program-Verify cycle is performed to ensure that all
bits have been correctly programmed following each byte
programming operation. The specific address is already
latched from the write cycle just completed, and stays
latched until the verify is completed. The Program-Verify
operation is initiated by writing C0H into the command
register. An internal reference generates the necessary
high voltages so that the user does not need to modify
V
CC
. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.
Abort/Reset
An Abort/Reset command is available to allow the user
to safely abort an erase or program sequence. Two
consecutive program cycles with FFH on the data bus will
abort an erase or a program operation. The abort/ reset
operation can interrupt at any time in a program or erase
operation and the device is reset to the Read Mode.
POWER UP/DOWN PROTECTION
The TK28F010 offers protection against inadvertent
programming during V
PP
and V
CC
power transitions. When
powering up the device there is no power-on sequencing
necessary. In other words, V
PP
and V
CC
may power up in
any order. Additionally V
PP
may be hardwired to V
PPH
independent of the state of V
CC
and any power up/down
cycling. The internal command register of the TK28F010
is reset to the Read Mode on power up.
POWER SUPPLY DECOUPLING
To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1 μF ceramic
capacitor between V
CC
and V
SS
and V
PP
and V
SS
. These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.
Ordering Information
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Package Temperature Speed Order Number
32 Pin PLCC -40
o
C to +85
o
C 120 ns TK28F010NI-12
32 Pin PLCC -40
o
C to +85
o
C 90 ns TK28F010NI-90
32 Pin PLCC -55
o
C to +125
o
C 95 ns TK28F010NM-95
The PDIP and TSOP packages are available on request. Contact the factory for details.
Part Marking Information
Parts that have been screened to the military temperature range are marked with a gold dot.
Contact Information
The TK28F010 can be ordered directly from Tekmos:
Tekmos, Inc.
7901 E Riverside Rd.
Bldg. 2, Suite 150
Austin, TX 78744
512 342-9871 phone
Sales@Tekmos.Com
www.Tekmos.com
Revision History
Date Revision Description
1/08/15 1.0 Initial Release
9/24/15 2.0 Specification Data Added
1/27/17 2.1 Ordering Information for 90ns added,
4/11/17 2.2 Correct pin numbering. Make military part a -95 speed
© 2017 Tekmos, Inc.
Information contained in this publication regarding device applications and the like is intended for suggestion only
and may be superseded by updates. No representation or warranty is given and no liability is assumed by Tekmos
Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual
property rights arising from such use or otherwise. Use of Tekmos’ products as critical components in life support
systems is not authorized except with express written approval by Tekmos. No licenses are conveyed, implicitly
or otherwise, under any intellectual property rights. The Tekmos logo and name are registered trademarks of
Tekmos, Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective
companies. All rights reserved.
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