Application Note 22
Issue 1 May 1996
AN22 - 13
Application Note 22
Issue 1 May 1996
Input
Voltage
0V
Simple Inverter Switching Waveform
+5V
+5V
0V
0V
0mA
5mA
Voltage
Base
Current
Collector
Collector
Voltage
0.7V
-1.67V
td tr
ts
tf
Figure 23.
Bipolar Transistor Switching Waveforms
for the Inverter Circuit of Figure 22.
Q1
Cbe
R3
1k
R2
20k
R1
10k
+5V
Output
0V
-5V
Input
Cbc
Figure 22.
Bipolar Transistor Switching Circuit for
Illustration of Basic Switching Behaviour.
Appendix A
Bipolar Transistor Switching
Behaviour
In most switching circuits trigger
capacitors are required to differentiate
pulses and provide DC isolation between
stages, and speed-up capacitors are
needed to neutralise the stored charge
and junction capacitances of the
transistors. In most cases it is sufficient
to choose values small enough not to
interfere with the operation of the circuit
at its maximum frequency. These
capacitors do however have minimum
values depending on the type of
transistor used, the base and collector
currents, and the amplitude of the
waveforms involved.
In order to understand the requirement
for speed-up capacitors, consider the
simple inverter circuit shown in Figure
22, and the resultant switching
waveforms shown schematically in
Figure 23.
Initially Q1 is cut off with its base-emitter
(b-e) junction reverse biased to -1.67V
and its collector-base (c-b) reverse
biased by 6.67V. On the rising edge of
the input pulse the potential at point A
(VBE) rises exponentially as the junction
capacitances of the transistor charge,
until the VBE reaches 0.6-0.7V and the b-e
junction starts to conduct significant
current. The time before this occurs from
the start of the input pulse is termed the
delay time, td. As the base current (IB)
flows, charged carriers accumulate in
the base region, and the collector
current increases in proportion until it is
limited by the collector load resistance
R3. The time taken for the collector
current to rise from 10% to 90% of its
final value is the rise time, tr. As the
collector voltage approaches zero, the
c-b junction becomes forward biased
and conducts the excess base current.
The base now starts acting as an emitter
and begins to inject charge carriers into
the collector. This causes a considerable
accumulation of charge in the collector
region which must be removed, either
by recombination or by reverse base
current, before the device can begin to
turn off. The time taken for this excess
charge to be removed is called the
storage time (ts), and during this time the
transistor remains saturated. At the end
of the storage time all excess charge
carriers have been removed and the
base charge is simply that required to
maintain collector current. As this
charge is reduced further the collector
current falls in sympathy until the device
is cut off. The time taken for the collector
current to fall from 90% to 10% is called
the fall time, tf.
Due to the low leakage of silicon
transistors, it is not usually necessary to
reverse bias the base to ensure DC
stability. This does tend to reduce the
delay time, but increases the storage
and fall times as the stored charge can
only be dissipated by recombination
instead of by the reverse current
provided by R2. This can be overcome
by including a capacitor in parallel with
the base drive resistor, of such value that
the charge stored on it is sufficient to
neutralise the total charge in the
transistor. This value will be dependent
on the transistor type, the base and
collector currents and the amplitude of
the input or driving pulse. For practical
applications it is necessary to determine
the required capacitor values by
measurement, preferably using a worst
case version of the circuit. As a guide,
minimum values of turn-off charge have
been provided for small signal,
switching and high current low VCE(sat)
transistors, and are reproduced for
various DC conditions within Appendix
C. These charts were produced using
test circuits similar to that shown in
Figure 5. As carrier diffusion coefficients
and recombination are temperature
dependent, then storage time will also
possess this dependence to some
degree. Therefore in some
circumstances allowance must be made,
and component values adjusted
accordingly.
The mount of trigger charge necessary
for pulse applications can be considered
in a similar manner, and for obtaining
approximate values the circuit shown in
Figure 24 can be employed. The values
obtained are higher than for the
“speed-up” case as the trigger capacitor
not only has to remove the stored charge
but also has to overcome the DC bias
provided by RB. In a practical circuit,
there may well be additional
components, which will absorb some
fraction of the trigger charge. Therefore
it will usually be necessary to use a
higher value of capacitance than
measurement (or provided curves)
would suggest - it is advised to closely
breadboard/model the actual circuit as
closely as possible with worst case
component values. Figure 25 shows an
example oscillograph for the ZTX300
small signal device, and Figure 26
presents curves for the minimum trigger
AN22 - 12