FINAL
Publication# 11559 Rev: GAmendment/+1
Issue Date: April 1997
12.0 V Flash
Am28F010
1 Megabit (131,072 x 8-Bit) CMOS 12.0 Volt, Bulk Erase
Flash Memory
DISTINCTIVE CHARACTERISTICS
High performance
70 ns maximum access time
CMOS Low power consumption
30 mA maximum active current
100
µ
A maximum standby current
No data retention power consumption
Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts
32-pin PDIP
32-pin PLCC
32-pin TSOP
10,000 write/erase cycles minimum
Write and erase voltage 12.0 V
±
5%
Latch-up protected to 100 mA
from –1 V to V
CC
+1 V
Flasherase
Electrical Bulk Chip-Erase
One second typical chip-erase
Flashrite
Programming
10
µ
s typical byte-program
Two seconds typical chip program
Command register architecture for
microprocessor/microcontroller compatible
write interface
On-chip address and data latches
Advanced CMOS flash memory technology
Low cost single transistor memory cell
Automatic write/erase pulse stop timer
GENERAL DESCRIPTION
The Am28F010 is a 1 Megabit Flash memory orga-
nized as 128K bytes of 8 bits each. AMD’s Flash
memories offer the most cost-effective and reliable
read/write non-volatile random access memory. The
Am28F010 is packaged in 32-pin PDIP, PLCC, and
TSOP versions. It is designed to be reprogrammed
and erased in-system or in standard EPROM pro-
grammers. The Am28F010 is erased when shipped
from the factory.
The standard Am28F010 off ers access times as fast as
70 ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the Am28F010 has separate chip enab le (CE) and out-
put enable (OE) controls.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F010 uses a command register to manage this
functionality, while maintaining a JEDEC Flash Stan-
dard 32-pin pinout. The command register allows for
100% TTL level control inputs and fixed power supply
levels during erase and programming, while maintain-
ing maximum EPROM compatibility.
AMD’s Flash technology reliably stores memory con-
tents e ven after 10,000 erase and progr am cycles . The
AMD cell is designed to optimize the erase and pro-
gramming mechanisms . In addition, the combination of
advanced tunnel oxide processing and low internal
electric fields for erase and programming operations
produces reliable cycling. The Am28F010 uses a
12.0V
±
5% V
PP
high voltage input to perform the
Flasherase
and Flashrite
algorithms.
The highest degree of latch-up protection is achieved
with AMD’s propr ietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 milliamps on
address and data pins from –1 V to V
CC
+1 V.
The Am28F010 is byte programmable using 10 ms pro-
gramming pulses in accordance with AMD’s Flashrite
programming algorithm. The typical room temperature
programming time of the Am28F010 is two seconds.
The entire chip is bulk erased using 10 ms erase pulses
according to AMD’s Flasherase alrogithm. Typical era-
sure at room temperature is accomplished in less than
one second. The windowed package and the 15–20
2 Am28F010
minutes required for EPROM erasure using ultra-violet
light are eliminated.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as inputs to an internal state-machine
which controls the erase and programming circuitry.
During write cycles, the command register internally
latches address and data needed for the program-
ming and erase operations. For system design simpli-
fication, the Am28F010 is designed to suppor t either
WE or CE controlled writes. During a system write cy-
cle, addresses are latched on the falling edge of WE
or CE whichever occurs last. Data is latched on the
rising edge of WE or CE whichever occurs first. To
simplify the following discussion, the WE pin is used
as the write cycle control pin throughout the rest of
this text. All setup and hold times are with respect to
the WE signal.
AMD’s Flash technology combines years of EPROM
and EEPROM e xperience to produce the highest lev els
of quality, reliability, and cost effectiveness. The
Am28F010 electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are pro-
grammed one byte at a time using the EPROM pro-
gramming mechanism of hot electron injection.
BLOCK DIAGRAM
PRODUCT SELECTOR GUIDE
Family Part No: Am28F010
Ordering Part No:
±
10% V
CC
Tolerance
-70 -90 -120 -150 -200
Max Access Time (ns) 70 90 120 150 200
CE (E) Access (ns) 70 90 120 150 200
OE (G) Access (ns) 35 35 50 55 55
Erase Voltage
Switch Input/Output
Buffers
Data
Latch
Y-Gating
1,048,576 Bit
Cell Matrix
X-Decoder
Y-Decoder
Address Latch
Chip Enable
Output Enable
Logic
Program
Voltage Switch
State
Control
Command
Register
WE
CE
OE
A0–A16
DQ0–DQ7
VCC
VSS
11559G-1
Low VCC
Detector
Program/Erase
Pulse Timer
VPP
To Array
Am28F010 3
12.0 V Flash
CONNECTION DIAGRAMS
Note:
Pin 1 is marked for orientation.
3
4
5
2
1
9
10
11
12
13
27
26
25
24
23
7
8
22
21
6
32
31
20
14
30
29
28
15
16
19
18
17
A6
A5
A4
A3
A2
A1
A0
A16
DQ0
A15
A12
A7
DQ1
DQ2
VSS
A8
A9
A11
OE (G)
A10
CE (E)
DQ7
VCC
WE (W)
DQ6
NC
A14
A13
DQ5
DQ4
DQ3
VPP
11559G-2
PDIP
DQ6
NC
DQ5
DQ4
DQ3
131 30
2
3
4
5
6
7
8
9
10
11
12
13 17 18 19 2016
15
14
29
28
27
26
25
24
23
22
21
32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
OE (G)
A10
CE (E)
DQ7
A12
A15
A16
V
CC
WE (W)
NC
DQ1
DQ2
V
SS
PLCC
11559G-3
4 Am28F010
CONNECTION DIAGRAMS (continued)
LOGIC SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP
32-Pin TSOP—Standard Pinout
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
D7
D6
D5
D4
D3
VSS
D2
D1
D0
A0
A1
A2
A3
32-Pin TSOP—Reverse Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
D7
D6
D5
D4
D3
VSS
D2
D1
D0
A0
A1
A2
A3
11559G-4
17
8
DQ0–DQ7
A0–A16
CE (E)
OE (G)
WE (W)
11559G-5
Am28F010 5
12.0 V Flash
ORDERING INFORMATION
Standard Products
AMD standard products are av ailable in se v eral pac kages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific v alid combinations and
to check on newly released combinations.
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
P ACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 032)
F = 32-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR032)
DEVICE NUMBER/DESCRIPTION
Am28F010
1 Megabit (128 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory
AM28F010 -70 J C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
B
SPEED OPTION
See Product Selector Guide
and V alid Combinations
Valid Combinations
AM28F010-70
PC, PI, PE, PEB,
JC, JI, JE, JEB,
EC, EI, EE, EEB,
FC, FI, FE, FEB
AM28F010-90
AM28F010-120
AM28F010-150
AM28F010-200
6 Am28F010
PIN DESCRIPTION
A0–A16
A
ddress Inputs for memor y locations. Inter nal latches
hold addresses during write cycles.
CE (E)
Chip Enable active low input activates the chip’s con-
trol logic and input buffers. Chip Enable high will dese-
lect the device and operates the chip in stand-by mode.
DQ0–DQ7
Data Inputs during memory write cycles. Internal
latches hold data during write cycles. Data Outputs
during memory read cycles.
NC
No Connect-corresponding pin is not connected inter-
nally to the die.
OE (G)
Output Enable activ e lo w input gates the outputs of the
device through the data buffers during memory read
cycles. Output Enable is high during command se-
quencing and program/erase operations.
V
CC
P o wer supply f or device oper ation. (5.0 V
±
5% or 10%)
V
PP
Program voltage input. V
PP
must be at high voltage in
order to write to the command register. The command
register controls all functions required to alter the mem-
ory arra y contents . Memory contents cannot be altered
when V
PP
V
CC
+2 V.
V
SS
Ground
WE (W)
Write Enable activ e low input controls the write function
of the command register to the memor y array. The tar-
get address is latched on the falling edge of the Write
Enable pulse and the appropriate data is latched on the
rising edge of the pulse. Write Enable high inhibits writ-
ing to the device.
Am28F010 7
12.0 V Flash
BASIC PRINCIPLES
The Am28F010 uses 100% TTL-level control inputs
to manage the command register. Erase and repro-
gramming operations use a fixed 12.0 V
±
5% high
voltage input.
Read Only Memory
Without high V
PP
voltage, the Am28F010 functions as
a read only memory and operates like a standard
EPROM. The control inputs still manage traditional
read, standby, output disable, and Auto select modes.
Command Register
The command register is enabled only when high volt-
age is applied to the V
PP
pin. The erase and repro-
gramming operations are only accessed via the
register. In addition, two-cycle commands are required
for erase and reprogramming operations. The tradi-
tional read, standby, output disable, and Auto select
modes are available via the register.
The Am28F010’s command register is written using
standard microprocessor write timings. The register
controls an internal state machine that manages all de-
vice operations. For system design simplification, the
Am28F010 is designed to support either WE or CE
controlled writes. During a system write cycle, ad-
dresses are latched on the falling edge of WE or CE
whichever occurs last. Data is latched on the rising
edge of WE or CE whichever occur first. To simplify the
following discussion, the WE pin is used as the write
cycle control pin throughout the rest of this text. All
setup and hold times are with respect to the WE signal.
Overview of Erase/Program Operations
Flasherase
Sequence
A multiple step command sequence is required to
erase the Flash device (a two-cycle Erase command
and repeated one cycle verify commands).
Note:
The Flash memory array must be completely
programmed to 0’s prior to erasure. Refer to the
Flashrite
Programming Algorithm.
1.
Erase Setup:
Write the Setup Erase command to
the command register.
2.
Erase:
Write the Erase command (same as Setup
Erase command) to the command register again.
The second command initiates the erase operation.
The system software routines must now time-out
the erase pulse width (10 ms) prior to issuing the
Erase-verify command. An integrated stop timer
prevents any possibility of overerasure.
3.
Erase-Verify:
Write the Erase-verify command to
the command register. This command terminates
the erase operation. After the erase operation,
each byte of the arr ay must be verified. Address in-
formation must be supplied with the Erase-verify
command. This command verifies the margin and
outputs the addressed byte in order to compare the
array data with FFH data (Byte erased).
After successful data verification the Erase-verify
command is written again with new address infor-
mation. Each byte of the array is sequentially veri-
fied in this manner.
If data of the addressed location is not verified, the
Erase sequence is repeated until the entire array is
successfully verified or the sequence is repeated
1000 times.
Flashrite
Programming Sequence
A three step command sequence (a two-cycle Progr am
command and one cycle Verify command) is required
to program a b yte of the Flash arra y. Refer to the Flash-
rite
Algorithm.
1.
Program Setup:
Write the Setup Program com-
mand to the command register.
2.
Program:
Write the Progr am command to the com-
mand register with the appropriate Address and
Data. The system software routines must no w time-
out the program pulse width (10
µ
s) prior to issuing
the Program-verify command. An integrated stop
timer prevents any possibility of overprogramming.
3.
Program-Verify: Write the Program-verify com-
mand to the command register. This command ter-
minates the programming operation. In addition,
this command verifies the margin and outputs the
byte just prog rammed in order to compare the arra y
data with the original data programmed. After suc-
cessful data verification, the programming se-
quence is initiated again f or the next byte address to
be programmed.
If data is not verified successfully, the Program se-
quence is repeated until a successful comparison is
verified or the sequence is repeated 25 times.
Data Protection
The Am28F010 is designed to offer protection against
accidental erasure or programming caused by spurious
system le vel signals that ma y e xist during power transi-
tions. The Am28F010 powers up in its read only state.
Also, with its control register architecture, alteration of
the memory contents only occurs after successful com-
pletion of specific command sequences.
The device also incorporates several features to pre-
vent inadvertent write cycles resulting fromVCC po wer-
up and power-down transitions or system noise.
Low VCC Write Inhibit
To a void initiation of a write cycle during VCC pow er-up
and power-do wn, the Am28F010 loc ks out write cycles
for VCC < VLKO (see DC Characteristics section for
voltages). When VCC < VLKO, the command register is
8 Am28F010
disabled, all internal program/erase circuits are
disabled, and the device resets to the read mode. The
Am28F010 ignores all writes until VCC > VLKO. The user
must ensure that the control pins are in the correct logic
state when VCC > VLKO to prev ent uninitentional writes.
Write Pulse “Glitch” Protection
Noise pulses of less than 10 ns (typical) on OE, CE or
WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL,CE
= VIH or WE = VIH. To initiate a wr ite cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = VIL and OE =
VIH will not accept commands on the rising edge of
WE. The internal state machine is automatically reset
to the read mode on power-up.
FUNCTIONAL DESCRIPTION
Description of User ModesTable 1. Am28F010 User Bus Operations
Legend:
X = Don’t care, where Don’t Care is either V
IL
or V
IH
levels. V
PPL
= V
PP
V
CC
+ 2 V. See DC Characteristics for voltage levels
of V
PPH
. 0 V < An < V
CC
+ 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).
Notes:
1. V
PPL
ma y be grounded, connected with a resistor to g round, or < V
CC
+ 2.0 V. V
PPH
is the programming voltage specified f or
the device. Refer to the DC characteristics. When V
PP
= V
PPL
, memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.
3. 11.5 < V
ID
< 13.0 V. Minimum V
ID
rise time and fall time (between 0 and V
ID
voltages) is 500 ns.
4. Read operation with V
PP
= V
PPH
may access array data or the Auto select codes.
5. With V
PP
at high voltage, the standby current is I
CC
+ I
PP
(standby).
6. Refer to Table 3 for valid D
IN
during a write operation.
7. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either V
IL
or V
IH
levels. In the Auto select mode all
addresses except A9 and A0 must be held at V
IL
.
8. If V
CC
1.0 Volt, the voltage difference between V
PP
and V
CC
should not exceed 10.0 volts. Also, the Am28F010 has a V
PP
rise time and fall time specification of 500 ns minimum.
Operation CE (E)OE (G)WE (W)
VPP
(Note
(Note 1)) A0 A9 I/O
Read-Only
Read VIL VIL XV
PPL A0 A9 DOUT
Standby VIH XXV
PPL X X HIGH Z
Output Disable VIL VIH VIH VPPL X X HIGH Z
Auto-Select Manufacturer Code
(Note (Note 2)) VIL VIL VIH VPPL VIL
VID
(Note
(Note 3))
CODE
(01H)
Auto-Select Device Code (Note
(Note 2)) VIL VIL VIH VPPL VIH
VID
(Note
(Note 3))
CODE
(A7H)
Read/Write
Read VIL VIL VIH VPPH A0 A9 DOUT
(Note
(Note 4))
Standby (Note (Note 5)) VIH XXV
PPH X X HIGH Z
Output Disable VIL VIH VIH VPPH X X HIGH Z
Write VIL VIH VIL VPPH A0 A9 DIN
(Note
(Note 6))
Am28F010 9
12.0 V Flash
READ ONLY MODE
VPP < VCC + 2 V
Command Register Inactive
Read
The Am28F010 functions as a read only memory when
VPP < VCC + 2 V. The Am28F010 has two control func-
tions. Both must be satisfied in order to output data. CE
controls power to the device. This pin should be used
for specific device selection. OE controls the device
outputs and should be used to gate data to the output
pins if a device is selected.
Address access time tACC is equal to the delay from
stable addresses to valid output data. The chip enable
access time tCE is the dela y from stable addresses and
stable CE to valid data at the output pins. The output
enable access time is the dela y from the f alling edge of
OE to valid data at the output pins (assuming the ad-
dresses have been stable at least tACC–tOE).
Standby Mode
The Am28F010 has two standby modes. The CMOS
standby mode (CE input held at VCC ± 0.5 V), con-
sumes less than 100 µA of current. TTL standb y mode
(CE is held at VIH) reduces the current requirements
to less than 1mA. When in the standby mode the out-
puts are in a high impedance state, independent of the
OE input.
If the device is deselected during erasure, program-
ming, or program/erase verification, the device will
draw active current until the operation is terminated.
Output Disable
Output from the device is disabled when OE is at a logic
high le vel. When disab led, output pins are in a high im-
pedance state.
Auto Select
Flash memories can be programmed in-system or in a
standard PROM programmer. The device may be sol-
dered to the circuit board upon receipt of shipment and
programmed in-system. Alternatively, the device may
initially be programmed in a PROM programmer prior
to soldering the device to the board.
The Auto select mode allows the reading out of a binary
code from the device that will identify its manufacturer
and type. This mode is intended for the purpose
of automatically matching the device to be pro-
grammed with its corresponding programming algo-
rithm. This mode is functional over the entire
temperature range of the device.
Programming In A PROM Programmer
To activate this mode, the programming equipment
must force VID (11.5 V to 13.0 V) on address A9. Two
identifier bytes ma y then be sequenced from the device
outputs by toggling address A0 from VIL to VIH. All other
address lines must be held at VIL, and VPP must be less
than or equal to VCC + 2.0 V while using this Auto select
mode. Byte 0 (A0 = VIL) represents the manufacturer
code and byte 1 (A0 = VIH) the device identifier code.
For the Am28F010 these two bytes are given in the
table below. All identifiers for manufacturer and device
codes will exhibit odd parity with the MSB (DQ7) de-
fined as the parity bit.
(Ref er to the AUT O SELECT parag raph in the ERASE,
PROGRAM, and READ MODE section for program-
ming the Flash memory device in-system).
Table 2. Am28F010 Auto Select Code
Type A0 Code
(HEX) DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Manufacturer Code VIL 0100000001
Device Code VIH A710100111
10 Am28F010
ERASE, PROGRAM, AND READ MODE
VPP = 12.0 V ± 5%
Command Register Active
Write Operations
High voltage must be applied to the VPP pin in order to
activate the command register. Data written to the reg-
ister ser ves as input to the internal state machine. The
output of the state machine determines the operational
function of the device.
The command register does not occupy an address-
able memory location. The register is a latch that stores
the command, along with the address and data infor-
mation needed to execute the command. The register
is written by bringing WE and CE to VIL, while OE is at
VIH. Addresses are latched on the falling edge of WE,
while data is latched on the rising edge of the WE
pulse. Standard microprocessor write timings are used.
The de vice requires the OE pin to be VIH f or write oper-
ations. This condition eliminates the possibility for bus
contention during programming operations. In order to
write, OE must be VIH, and CE and WE must be VIL. If
any pin is not in the correct state a write command will
not be executed.
Refer to AC Write Characteristics and the Erase/Pro-
gramming Waveforms for specific timing parameters.
Command Definitions
The contents of the command register default to 00H
(Read Mode) in the absence of high voltage applied to
the VPP pin. The device operates as a read only mem-
ory. High voltage on the VPP pin enables the command
register . De vice operations are selected b y writing spe-
cific data codes into the command register. Table 3 de-
fines these register commands.
Read Command
Memory contents can be accessed via the read com-
mand when VPP is high. To read from the device, write
00H into the command register . Standard microproces-
sor read cycles access data from the memory. The de-
vice will remain in the read mode until the command
register contents are altered.
The command register defaults to 00H (read mode)
upon VPP power-up . The 00H (Read Mode) register de-
fault helps ensure that inadvertent alteration of the
memory contents does not occur during the VPP po wer
transition. Refer to the AC Read Characteristics and
Waveforms for the specific timing parameters.
Am28F010 11
12.0 V Flash
Table 3. Am28F010 Command Definitions
Notes:
1. Bus operations are defined in Table 1.
2. RA = Address of the memory location to be read.
EA = Address of the memory location to be read during erase-verify.
PA = Address of the memory location to be programmed.
X = Don’t care.
Addresses are latched on the falling edge of the WE pulse.
3. RD = Data read from location RA during read operation.
EVD = Data Read from location EA during erase-verify.
PD = Data to be programmed at location PA. Data latched on the rising edge of WE.
PVD = Data read from location PA during program-verify. PA is latched on the Program command.
4. Figure 1 illustrates the Flasherase Electrical Erase Algorithm.
5. Figure 3 illustrates the Flashrite Programming Algorithm.
6. Please reference Reset Command section.
FLASH MEMORY PROGRAM/ERASE
OPERATIONS
AMD’s Flasherase and Flashrite
Algorithms
Flasherase Erase Sequence
Erase Setup/Erase Commands
Erase Setup
Erase Setup is the first of a two-cycle er ase command.
It is a command-only operation that stages the device
for bulk chip erase. The array contents are not altered
with this command. 20H is written to the command reg-
ister in order to perform the Erase Setup operation.
Erase
The second two-cycle erase command initiates the
bulk erase operation. You must write the Erase com-
mand (20H) again to the register. The erase operation
begins with the rising edge of the WE pulse. The erase
operation must be terminated by writing a new com-
mand (Erase-verify) to the register.
This two step sequence of the Setup and Erase com-
mands helps to ensure that memory contents are not
accidentally erased. Also, chip erasure can only occur
when high voltage is applied to the VPP pin and all con-
trol pins are in their proper state. In absence of this high
voltage, memory contents cannot be altered. Refer to
AC Erase Characteristics and Waveforms for specific
timing parameters.
Note: The Flash memory device must be fully
programmed to 00H data prior to erasure. This
equalizes the charge on all memory cells ensuring
reliable erasure.
Erase-Verify Command
The erase operation erases all bytes of the array
in parallel. After the erase operation, all bytes must be
sequentially verified. The Erase-verify operation is initi-
ated by writing A0H to the register . The b yte address to
be verified must be supplied with the command. Ad-
dresses are latched on the f alling edge of the WE pulse
or CE pulse, whichever occurs later. The rising edge of
the WE pulse terminates the erase operation.
Command
First Bus Cycle Second Bus Cycle
Operation
(Note (Note
1))
Address
(Note (Note
2))
Data
(Note (Note
3))
Operation
(Note (Note
1))
Address
(Note (Note
2))
Data
(Note (Note
3))
Read Memory (Note (Note 6)) Write X 00H/FFH Read RA RD
Read Auto select Write X 80H or 90H Read 00H/01H 01H/A7H
Erase Setup/Erase Write (Note
(Note 4)) Write X 20H Write X 20H
Erase-Verify (Note 4) Write EA A0H Read X EVD
Program Setup/Program (Note
(Note 5)) Write X 40H Write PA PD
Program-Verify (Note (Note 5)) Write X C0H Read X PVD
Reset (Note (Note 6)) Write X FFH Write X 00H/FFH
12 Am28F010
Margin V erify
During the Erase-verify operation, the Am28F010
applies an internally generated margin voltage to the
addressed byte . Reading FFH from the addressed b yte
indicates that all bits in the byte are properly erased.
Verify Next Address
You must write the Erase-verify command with the ap-
propriate address to the register pr ior to verification of
each address. Each new address is latched on the fall-
ing edge of WE or CE pulse, whichever occurs later.
The process continues for each byte in the memory
array until a byte does not return FFH data or all the
bytes in the array are accessed and verified.
If an address is not verified to FFH data, the entire chip
is erased again (refer to Erase Setup/Erase). Erase
verification then resumes at the address that failed to
verify. Erase is complete when all bytes in the array
have been verified. The device is now ready to be pro-
grammed. At this point, the v erification operation is ter-
minated by writing a valid command (e.g. Program
Setup) to the command register. Figure 1 and Table 4,
the Flasherase electrical erase algorithm, illustrate how
commands and bus operations are combined to per-
f orm electrical erasure . Ref er to A C Er ase Characteris-
tics and Waveforms for specific timing parameters.
Figure 1. Flasherase Electrical Erase Algorithm
Start
Program All Bytes to 00H
Apply VPPH
Address = 00H
PLSCNT = 0
Write Erase Setup Command
Write Erase Command
Time out 10 ms
Write Erase V erify Command
Time out 6 µS
Read Data from Device
Data = FFH
Last Address
Write Reset Command
Apply VPPL
Erasure Completed
PLSCNT =
1000
Increment Address
Apply VPPL
Erase Error
No
Yes
No
11559G-6
Yes
Yes Yes
No
No
Increment
PLSCNT
Data = 00H
Am28F010 13
12.0 V Flash
Flasherase Electrical Erase Algorithm
This Flash memory device erases the entire array in
parallel. The erase time depends on VPP
, temperature,
and number of erase/program cycles on the device. In
general, reprogr amming time increases as the n umber
of erase/program cycles increases.
The Flasherase electrical erase algorithm employs an
interactive closed loop flow to simultaneously erase all
bits in the array. Erasure begins with a read of the
memory contents. The Am28F010 is erased when
shipped from the factory. Reading FFH data from the
de vice would immediately be followed by executing the
Flashrite programming algorithm with the appropriate
data pattern.
Should the device be currently programmed, data other
than FFH will be returned from address locations.
Follow the Flasherase algorithm. Uniform and reliable
erasure is ensured by first programming all bits in the
device to their charged state (Data = 00H). This is
accomplished using the Flashrite Programming
algorithm. Erasure then continues with an initial erase
operation. Erase verification (Data = FFH) begins at
address 0000H and continues through the array to the
last address, or until data other than FFH is
encountered. If a byte fails to verify, the device is
erased again. With each erase operation, an increasing
number of bytes verify to the erased state. Typically,
devices are erased in less than 100 pulses (one
second). Erase efficiency may be improved by storing
the address of the last byte that fails to verify in a
register . F ollowing the ne xt erase operation, verification
ma y start at the stored address location. A total of 1000
erase pulses are allowed per reprogram cycle, which
corresponds to approximately 10 seconds of
cumulative erase time. The entire sequence of erase
and byte verification is performed with high voltage
applied to the VPP pin. Figure 1 illustr ates the electrical
erase algorithm.
Table 4. Flasherase Electrical Erase Algorithm
Notes:
1. See AC and DC Characteristics for values of V
PP
parameters. The V
PP
power supply can be hard-wired to the device or
s witchable. When V
PP
is switched, V
PPL
may be ground, no connect with a resistor tied to ground, or less than V
CC
+ 2.0 V.
2. Erase V erify is perf ormed only after chip erasure. A final read compare ma y be performed (optional) after the register is written
with the read command.
3. The erase algorithm Must Be Followed to ensure proper and reliable operation of the device.
Bus Operations Command Comments
Entire memory must = 00H before erasure (Note (Note 3))
Note: Use Flashrite
programming algorithm (Figure 3) for
programming.
Standby
Wait for VPP Ramp to VPPH (Note (Note 1))
Initialize:
Addresses
PLSCNT (Pulse count)
Write Erase Setup Data = 20H
Erase Data = 20H
Standby Duration of Erase Operation (tWHWH2)
Write Erase-Verify (Note (Note 2)) Address = Byte to Verify
Data = A0H
Stops Erase Operation
Standby Write Recovery Time before Read = 6 µs
Read Read byte to verify erasure
Standby Compare output to FFH
Increment pulse count
Write Reset Data = FFH, reset the register for read operations
Standby Wait for VPP Ramp to VPPL (Note (Note 1))
14 Am28F010
Figure 2. AC Waveforms For Erase Operations
Analysis of Erase Timing Waveform
Note: This analysis does not include the requirement
to program the entire array to 00H data prior to erasure.
Refer to the Flashrite
Programming algorithm.
Erase Setup/Erase
This analysis illustrates the use of two-cycle erase
commands (section A and B). The first erase com-
mand (20H) is a Setup command and does not affect
the array data (section A). The second erase com-
mand (20H) initiates the erase operation (section B)
on the rising edge of this WE pulse. All bytes of the
memory arra y are erased in par allel. No address inf or-
mation is required.
The erase pulse occurs in section C.
Time-Out
A software timing routine (10 ms duration) must be ini-
tiated on the rising edge of the WE pulse of section B.
Note: An integrated stop timer pre v ents an y possibil-
ity of overerasure by limiting each time-out period of
10 ms.
Erase-Verify
Upon completion of the erase software timing routine,
the microprocessor must write the Erase-verify com-
mand (A0H). This command terminates the erase op-
eration on the rising edge of the WE pulse (section D).
The Erase-verify command also stages the device for
data verification (section F).
After each erase operation each byte must be verified.
The byte address to be ver ified must be supplied with
the Erase-verify command (section D). Addresses are
latched on the falling edge of the WE pulse.
Addresses
CE
OE
WE
Data
VPP
VCC
11559G-7
20H
20H
Section
A0H Data
Out
Bus Cycle Write Write Time-out Write Time-out Read Standby
Command 20H 20H N/A A0H N/A Compare
Data N/A
Function Erase
Setup Erase Erase
(10 ms) Erase-
Verify Transition
(6 µs) Erase
Verification
Proceed per
Erase
Algorithm
AB DEFCG
AB DEFCG
Am28F010 15
12.0 V Flash
Another software timing routine (6 µs dur ation) must be
e x ecuted to allo w f or gener ation of internal voltages f or
margin checking and read operation (section E).
During Erase-verification (section F) each address that
returns FFH data is successfully erased. Each address
of the arra y is sequentially verified in this manner by re-
peating sections D thru F until the entire array is ver i-
fied or an address fails to verify. Should an address
location fail to verify to FFH data, erase the device
again. Repeat sections A thru F. Resume verification
(section D) with the failed address.
Each data change sequence allows the device to use
up to 1,000 erase pulses to completely erase . Typically
100 erase pulses are required.
Note: All address locations must be programmed to
00H prior to erase. This equalizes the charge on all
memory cells and ensures reliable erasure.
Flashrite Programming Sequence
Program Setup/Program Command
Program Setup
The Am28F010 is programmed byte by byte. Bytes
may be programmed sequentially or at random. Pro-
gram Setup is the first of a two-cycle program com-
mand. It stages the device for byte programming. The
Program Setup operation is performed by writing 40H
to the command register.
Program
Only after the program Setup operation is completed
will the next WE pulse initiate the active programming
operation. The appropriate address and data for pro-
gramming must be available on the second WE pulse.
Addresses and data are internally latched on the falling
and rising edge of the WE pulse respectively. The rising
edge of WE also begins the programming operation.
You must write the Program-verify command to ter mi-
nate the programming operation. This two step se-
quence of the Setup and Program commands helps to
ensure that memory contents are not accidentally writ-
ten. Also, programming can only occur when high volt-
age is applied to the VPP pin and all control pins are in
their proper state. In absence of this high voltage,
memory contents cannot be programmed.
Ref er to AC Char acteristics and Wav ef orms f or specific
timing parameters.
Program V erify Command
Following each programming operation, the byte just
programmed must be verified.
Write C0H into the command register in order to initiate
the Program-verify operation. The rising edge of this
WE pulse terminates the programming operation. The
Program-v erify operation stages the de vice f or v erifica-
tion of the last byte prog rammed. Addresses were pre-
viously latched. No new information is required.
Margin V erify
During the Program-verify operation, the Am28F010
applies an internally generated margin voltage to the
addressed byte. A normal microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and the true data indicates that
the byte was successfully programmed. The original
programmed data should be stored for comparison.
Programming then proceeds to the next desired byte
location. Should the byte fail to verify, reprogram (refer
to Program Setup/Program). Figure 3 and Table 5 indi-
cate how instructions are combined with the bus oper-
ations to perform byte programming. Refer to AC
Programming Characteristics and Waveforms for spe-
cific timing parameters.
Flashrite Programming Algorithm
The Am28F010 Flashrite Programming algorithm em-
ploys an interactive closed loop flow to program data
byte by byte. Bytes may be programmed sequentially
or at random. The Flashrite Programming algorithm
uses 10 µs programming pulses. Each operation is fol-
lowed by a byte verification to determine when the ad-
dressed byte has been successfully programmed. The
program algorithm allows f or up to 25 progr amming op-
erations per b yte per reprog ramming cycle. Most bytes
verify after the first or second pulse. The entire se-
quence of programming and byte verification is per-
f ormed with high voltage applied to the VPP pin. Figure
3 and Table 5 illustrate the programming algorithm.
16 Am28F010
Figure 3. Flashrite Programming Algorithm
Start
Apply VPPH
PLSCNT = 0
Write Program Setup Command
Write Program Command (A/D)
Time out 10 µs
Write Program Verify Command
Time out 6 µS
Read Data from Device
Last Address
Write Reset Command
Apply VPPL
Programming Completed
PLSCNT =
25?
Increment Address
Apply VPPL
Device Failed
No
11559G-8
Yes
Yes
No No
Verify Byte Increment PLSCNT
Yes
Am28F010 17
12.0 V Flash
Table 5. Flashrite Programming Algorithm
Notes:
1. See AC and DC Characteristics for values of V
PP
parameters. The V
PP
power supply can be hard-wired to the device or
s witchable. When V
PP
is switched, V
PPL
may be ground, no connect with a resistor tied to ground, or less than V
CC
+ 2.0 V.
2. Program Verify is perf ormed only after byte prog ramming. A final read/compare may be perf ormed (optional) after the register
is written with the read command.
Bus Operations Command Comments
Standby Wait for VPP Ramp to VPPH (Note (Note 1))
Initialize Pulse counter
Write Program Setup Data = 40H
Program Valid Address/Data
Standby Duration of Programming Operation (tWHWH1)
Write Program-Verify (2) Data = C0H Stops Program Operation
Standby Write Recovery Time before Read = 6 µs
Read Read Byte to Verify Programming
Standby Compare Data Output to Data Expected
Write Reset Data = FFH, resets the register for read operations.
Standby Wait for VPP Ramp to VPPL (Note (Note 1))
18 Am28F010
Figure 4. AC Waveforms for Programming Operations
Analysis of Program Timing Waveforms
Program Setup/Program
Two-cycle write commands are required for program
operations (section A and B). The first program com-
mand (40H) is a Setup command and does not affect
the array data (section A).The second program com-
mand latches address and data required for program-
ming on the falling and rising edge of WE respectively
(section B). The rising edge of this WE pulse (section
B) also initiates the programming pulse. The device is
programmed on a b yte by byte basis either sequentially
or randomly.
The program pulse occurs in section C.
Time-Out
A software timing routine (10 µs dur ation) must be initi-
ated on the rising edge of the WE pulse of section B.
Note: An integrated stop timer pre v ents any possibility
of ov erprogramming b y limiting each time-out period of
10 µs.
Program-Verify
Upon completion of the program timing routine , the mi-
croprocessor must write the program-verify command
(C0H). This command terminates the programming op-
eration on the rising edge of the WE pulse (section D).
The program-verify command also stages the device
for data verification (section F). Another software timing
routine (6 µs duration) must be executed to allow for
Addresses
CE
OE
WE
Data
VPP
VCC
11559G-9
Data
In
20H
Section
A0H Data
Out
Bus Cycle Write Write Time-out Write Time-out Read Standby
Command 40H Program
Address,
Program Data N/A C0H
(Stops
Program) N/A Compare
Data N/A
Function Program
Setup
Program
Command
Latch
Address and
Data
Program
(10 µs) Program
Verify Transition
(6 µs) Program
Verification
Proceed per
Programming
Algorithm
AB DEFCG
A
B
DE FCG
Am28F010 19
12.0 V Flash
generation of internal voltages f or margin checking and
read operations (section E).
During program-verification (section F) each byte just
programmed is read to compare array data with original
program data. When successfully verified, the next de-
sired address is programmed. Should a b yte f ail to ver-
ify, reprogram the byte (repeat section A thr u F). Each
data change sequence allows the device to use up to
25 program pulses per byte. Typically , b ytes are verified
within one or two pulses.
Algorithm Timing Delays
There are four different timing delays associated with
the Flasherase and Flashrite algorithms:
1. The first delay is associated with the VPP rise-time
when VPP first turns on. The capacitors on the VPP
bus cause an RC ramp. After switching on the VPP,
the delay required is propor tional to the number of
devices being erased and the 0.1 mF/device. VPP
must reach its final value 100 ns before commands
are executed.
2. The second dela y time is the erase time pulse width
(10 ms). A software timing routine should be run by
the local microprocessor to time out the delay. The
erase operation must be terminated at the conclu-
sion of the timing routine or prior to executing any
system interrupts that may occur during the erase
operation. To ensure proper device operation, wr ite
the Erase-verify operation after each pulse.
3. A third dela y time is required for each programming
pulse width (10 ms). The programming algorithm is
interactive and verifies each byte after a program
pulse. The progr am operation must be terminated at
the conclusion of the timing routine or prior to exe-
cuting any system interrupts that may occur during
the programming operation.
4. A fourth timing delay associated with both the
Flasherase and Flashrite algorithms is the write re-
cov ery time (6 ms). During this time internal circuitry
is changing voltage levels from the erase/ program
level to those used for margin verify and read oper-
ations. An attempt to read the de vice during this pe-
riod will result in possible false data (it may appear
the device is not properly erased or programmed).
Note: Software timing routines should be written in
machine language f or each of the delays. Code written
in machine language requires knowledge of the appro-
priate microprocessor clock speed in order to accu-
rately time each delay.
Parallel Device Erasure
Many applications will use more than one Flash
memor y device. Total erase time may be minimized by
implementing a parallel erase algorithm. Flash
memories may erase at different rates. Therefore each
device must be verified separately. When a device is
completely erased and verified use a masking code to
pre vent further erasure. The other de vices will continue
to erase until verified. The masking code applied could
be the read command (00H).
Power-Up/Power-Down Sequence
The Am28F010 powers-up in the Read only mode.
Power supply sequencing is not required. Note that if
VCC 1.0 Volt, the voltage diff erence between VPP and
VCC should not exceed 10.0 Volts. Also, the
Am28F010 has VPP rise time and fall time specification
of 500 ns minimum.
Reset Command
The Reset command initializes the Flash memory de-
vice to the Read mode. In addition, it also provides the
user with a safe method to abor t any device operation
(including program or erase).
The Reset command must be written two consecutive
times after the setup Program command (40H). This
will reset the device to the Read mode.
Following any other Flash command write the Reset
command once to the de vice. This will saf ely abort any
previous operation and initialize the device to the
Read mode.
The Setup Program command (40H) is the only com-
mand that requires a two sequence reset cycle. The
first Reset command is interpreted as program data.
However, FFH data is considered null data during pro-
gramming operations (memory cells are only pro-
grammed from a logical “1” to “0”). The second Reset
command safely aborts the programming operation
and resets the device to the Read mode.
Memory contents are not altered in any case.
This detailed information is for your reference. It may
prove easier to always issue the Reset command two
consecutive times. This eliminates the need to deter-
mine if you are in the setup Program state or not.
Programming In-System
Flash memories can be programmed in-system or in a
standard PROM programmer. The device may be sol-
dered to the circuit board upon receipt of shipment and
programmed in-system. Alternatively, the device may
initially be programmed in a PROM programmer prior
to soldering the device to the board.
20 Am28F010
Auto Select Command
AMD’ s Flash memories are designed f or use in applica-
tions where the local CPU alters memory contents . Ac-
cordingly, manufacturer and device codes must be
accessible while the device resides in the target sys-
tem. PROM programmers typically access the signa-
ture codes by raising A9 to a high voltage. However,
multiplexing high voltage onto address lines is not a
generally desired system design practice.
The Am28F010 contains an Auto Select operation to
supplement traditional PROM programming methodol-
ogy. The operation is initiated by writing 80H or 90H
into the command register. Following this command, a
read cycle address 0000H retrieves the manufacturer
code of 01H. A read cycle from address 0001H returns
the de vice code A7H (see Table 2). To terminate the op-
eration, it is necessary to write another v alid command,
such as Reset (FFH), into the register.
Am28F010 21
12.0 V Flash
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .–55°C to + 125°C
Voltage with Respect To Ground
All pins except A9 and VPP (Note 1) .–2.0 V to +7.0 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +14.0 V
VPP (Note 2). . . . . . . . . . . . . . . . . . . –2.0 V to +14.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC v oltage on input or I/O pins is –0.5 V. During
voltage tr ansitions, inputs ma y overshoot V
SS
to –2.0 V f or
periods of up to 20 ns. Maximum DC voltage on input and
I/O pins is V
CC
+ 0.5 V. During voltage transitions, input
and I/O pins may overshoot to V
CC
+ 2.0V for periods up
to 20ns.
2. Minimum DC input voltage on A9 and V
PP
pins is -0.5 V.
During voltage transitions, A9 and V
PP
may overshoot V
SS
to –2.0 V for periods of up to 20 ns. Maximum DC input
voltage on A9 and V
PP
is +13.0 V which may overshoot to
14.0 V for periods up to 20 ns.
3. No more than one output shorted to ground at a time . Du-
ration of the short circuit should not be greater than one
second.
Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA). . . . . . . . . . . .0˚C to +70˚C
Industrial (I) Devices
Ambient Temperature (TA). . . . . . . . . .–40˚C to +85˚C
Extended (E) Devices
Ambient Temperature (TA). . . . . . . . .–55˚C to +125˚C
VCC Supply Voltages
VCC for Am28F010-70, -90,
-120, -150, -200 . . . . . . . . . . . . . . +4.50 V to +5.50 V
VPP V oltages
Read . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.6 V
Program, Erase, and Verify. . . . . . +11.4 V to +12.6 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
22 Am28F010
MAXIMUM OVERSHOOT
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
11559G-10
Maximum Negative Input Overshoot
20 ns
VCC + 0.5 V
2.0 V
20 ns 20 ns
VCC + 2.0 V
11559G-11
Maximum Positive Input Overshoot
11559G-12
Maximum VPP Overshoot
20 ns
13.5 V
VCC + 0.5 V
20 ns 20 ns
14.0 V
Am28F010 23
12.0 V Flash
DC CHARACTERISTICS over operating range unless otherwise specified
DC CHARACTERISTICS—TTL/NMOS COMPATIBLE
Notes:
1. Caution: The Am28F010 m ust not be remo ved from (or inserted into) a socket when V
CC
or V
PP
is applied. If V
CC
1.0 Volt,
the voltage difference between V
PP
and V
CC
should not exceed 10.0 Volts. Also, the Am28F010 has a V
PP
rise time and fall
time specification of 500 ns minimum.
2. I
CC1
is tested with OE = V
IH
to simulate open outputs.
3. Maximum active power usage is the sum of I
CC
and I
PP
..
4. Not 100% tested.
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
ILI Input Leakage Current VCC = VCC Max, VIN = VCC or VSS ±1.0 µA
ILO Output Leakage Current VCC = VCC Max, VOUT = VCC or VSS ±1.0 µA
ICCS VCC Standby Current VCC = VCC Max, CE = VIH 0.2 1.0 mA
ICC1 VCC Active Read Current VCC = VCC Max, CE = VIL, OE = VIH
IOUT = 0 mA, at 6 MHz 20 30 mA
ICC2 VCC Programming Current CE = VIL
Programming in Progress (Note (Note
4)) 20 30 mA
ICC3 VCC Erase Current CE = VIL
Erasure in Progress (Note (Note 4)) 20 30 mA
IPPS VPP Standby Current VPP = VPPL ±1.0 µA
IPP1 VPP Read Current VPP = VPPH 70 200 µA
VPP = VPPL ±1.0
IPP2 VPP Programming Current VPP = VPPH
Programming in Progress (Note (Note
4)) 10 30 mA
IPP3 VPP Erase Current VPP = VPPH
Erasure in Progress (Note (Note 4)) 10 30 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 2.0 VCC + 0.5 V
VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V
VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V
VID A9 Auto Select Voltage A9 = VID 11.5 13.0 V
IID A9 Auto Select Current A9 = VID Max, VCC = VCC Max 5 50 µA
VPPL VPP during Read-Only
Operations
Note: Erase/Program are inhibited
when V
PP
= V
PPL
0.0 VCC +2.0 V
VPPH VPP during Read/Write
Operations 11.4 12.6 V
VLKO Low VCC Lock-out Voltage 3.2 3.7 V
24 Am28F010
DC CHARACTERISTICS—CMOS COMPATIBLE
Notes:
1. Caution: The Am28F010 must not be removed from (or inserted into) a soc k et when V
CC
or V
PP
is applied. If V
CC
1.0 volt,
the voltage difference between V
PP
and V
CC
should not exceed 10.0 volts. Also, the Am28F010 has a V
PP
rise time and fall
time specification of 500 ns minimum.
2. I
CC1
is tested with OE = V
IH
to simulate open outputs.
3. Maximum active power usage is the sum of I
CC
and I
PP
..
4. Not 100% tested.
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
ILI Input Leakage Current VCC = VCC Max, VIN = VCC or VSS ±1.0 µA
ILO Output Leakage Current VCC = VCC Max, VOUT = VCC or VSS ±1.0 µA
ICCS VCC Standby Current VCC = VCC Max, CE = V CC + 0.5 V 15 100 µA
ICC1 VCC Active Read Current VCC = VCC Max, CE = VIL, OE = VIH
IOUT = 0 mA, at 6 MHz 20 30 mA
ICC2 VCC Programming Current CE = VIL
Programming in Progress (Note
(Note 4)) 20 30 mA
ICC3 VCC Erase Current CE = VIL
Erasure in Progress (Note (Note 4)) 20 30 mA
IPPS VPP Standby Current VPP = VPPL ±1.0 µA
IPP1 VPP Read Current VPP = VPPH 70 200 µA
IPP2 VPP Programming Current VPP = VPPH
Programming in Progress (Note
(Note 4)) 10 30 mA
IPP3 VPP Erase Current VPP = VPPH
Erasure in Progress (Note (Note 4)) 10 30 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 V CC VCC + 0.5 V
VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V
VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V
VOH2 IOH = –100 µA, VCC = VCC Min VCC –0.4
VID A9 Auto Select Voltage A9 = VID 11.5 13.0 V
IID A9 Auto Select Current A9 = VID Max, VCC = VCC Max 5 50 µA
VPPL VPPL during Read-Only
Operations
Note: Erase/Program are inhibited
when V
PP
= V
PPL
0.0 VCC + 2.0 V
VPPH VPP during Read/Write
Operations 11.4 12.6 V
VLKO Low VCC Lock-out Voltage 3.2 3.7 V
Am28F010 25
12.0 V Flash
Figure 5. Am28F010—Average ICC Active vs. Frequency
VCC = 5.5 V, Addressing Pattern = Minmax
Data Pattern = Checkerboar
ICC Active in mA
25
20
15
10
5
0
0123456789101112
Frequency in MHz 11559G-13
55°C
0°C
25°C
70°C
125°C
26 Am28F010
PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
SWITCHING CHARACTERISTICS over operating range unless otherwise specified
AC CHARACTERISTICS—Read Only Operation
Notes:
1. Output Load:
for -70: 1 TTL gate and C
L
= 30 pF
Input Rise and Fall Times:
10 ns
Input Pulse levels: 0 V to 3 V
Timing Measurement Reference Level: 1.5 V inputs and outputs.
for all others: 1 TTL gate and C
L
= 100 pF
Input Rise and Fall Times:
10 ns
Input Pulse levels: 0.45 V to 2.4 V
Timing Measurement Reference Level: 0.8 V and 2 V inputs and outputs
2. Guaranteed by design; not tested.
3. Not 100% tested.
Parameter
Symbol Parameter Description Test Conditions Typ Max Unit
CIN Input Capacitance VIN = 0 8 10 pF
COUT Output Capacitance VOUT = 0 8 12 pF
CIN2 VPP Input Capacitance VPP = 0 8 12 pF
Parameter
Symbols Am28F010 Speed Options (Note 1)
JEDEC Standard Parameter Description -70 -90 -120 -150 -200 Unit
tAVAV tRC Read Cycle Time (Note 3) Min 70 90 120 150 200 ns
tELQV tCE Chip Enable Access Time Max 70 90 120 150 200 ns
tAVQV tACC Address Access Time Max 70 90 120 150 200 ns
tGLQV tOE Output Enable Access Time Max 35 35 50 55 55 ns
tELQX tLZ Chip Enable to Output in Low Z
(Note 3) Min00000ns
t
EHQZ tDF Chip Disable to Output in High Z
(Note 2) Max 20 20 30 35 35 ns
tGLQX tOLZ Output Enable to Output in Low Z (Note 3) Min 00000ns
t
GHQZ tDF Output Disable to Output in High Z (Note 3) Max 20 20 30 35 35 ns
tAXQX tOH Output Hold Time From First Address, CE, or
OE change (Note 3) Min00000ns
t
WHGL Write Recovery Time before Read Min 66666µs
t
VCS VCC Set-up Time to Valid Read (Note 3) Min 50 50 50 50 50 µs
Am28F010 27
12.0 V Flash
AC CHARACTERISTICS—Write/Erase/Program Operations
Notes:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read Only operations.
2. All devices except Am28F010-70. Input Rise and Fall times:
10 ns; Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level: Inputs: 0.8 V and 2.0 V; Outputs: 0.8 V and 2.0 V
3. Am28F010-70. Input Rise and Fall times:
10 ns; Input Pulse Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level: Inputs and Outputs: 1.5 V
4. Maximum pulse widths not required because the on-chip program/erase stop timer will terminate the pulse widths internally
on the device.
5. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the Write Pulse Width (within a longer Write-Enable timing w avef orm) all set-up, hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
6. Not 100% tested.
Parameter Symbols Am28F010 Speed Options (Note 2)
JEDEC Standard Description -70 -90 -120 -150 -200 Unit
tAVAV tWC Write Cycle Time (Note 6) Min 70 90 120 150 200 ns
tAVWL tAS Address Setup Time Min 00000ns
t
WLAX tAH Address Hold Time Min 45 45 50 60 75 ns
tDVWH tDS Data Setup Time Min 45 45 50 50 50 ns
tWHDX tDH Data Hold Time Min 10 10 10 10 10 ns
tWHGL tWR Write Recovery Time Before Read Min 66666µs
t
GHWL Read Recovery TIme Before Write Min 00000µs
t
ELWL tCS CE Setup TIme Min 00000ns
t
WHEH tCH CE Hold TIme Min 00000ns
t
WLWH tWP Write Pulse Width Min 45 45 50 60 60 ns
tWHWL tWPH Write Pulse Width High Min 20 20 20 20 20 ns
tWHWH1 Duration of Programming Operation
(Note 4) Min 10 10 10 10 10 µs
tWHWH2 Duration of Erase Operation (Note 4) Typ 9.5 9.5 9.5 9.5 9.5 ms
tVPEL VPP Setup Time to Chip Enable Low (Note 6) Min 100 100 100 100 100 ns
tVCS VCC Setup Time to Chip Enable Low (Note 6) Min 50 50 50 50 50 µs
tVPPR VPP Rise Time (Note 6) 90% VPPH Min 500 500 500 500 500 ns
tVPPF VPP Fall Time (Note 6) 10% VPPL Min 500 500 500 500 500 ns
tLKO VCC < VLKO to Reset (Note 6) Min 100 100 100 100 100 ns
28 Am28F010
KEY TO SWITCHING WA VEFORMS
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
Does Not
Apply
Don’t Care,
Any Change
Permitted
Will Be
Steady
Will Be
Changing
from H to L
Will Be
Changing
from L to H
Changing,
State
Unknown
Center
Line is High-
Impedance
“Off” State
WAVEFORM INPUTS OUTPUTS
KS000010
Am28F010 29
12.0 V Flash
SWITCHING W A VEFORMS
Addresses
CE (E)
OE (G)
WE (W)
Data (DQ)
5.0 V
VCC
0 V
Power-up, Standby Device and
Address Selection Outputs
Enabled Data
Valid Standby, Power-down
Addresses Stable
High Z High Z
tWHGL
tAVQV (tACC)
tEHQZ
(tDF)
tGHQZ
(tDF)
tELQX (tLZ)
tGLQX (tOLZ)
tELQV (tCE)
tGLQV (tOE)
tAXQX (tOH)
Output V alid
tAVAV (tRC)
tVCS
11559G-14
Figure 6. AC Waveforms for Read Operations
30 Am28F010
SWITCHING W A VEFORMS
Figure 7. AC Waveforms for Erase Operations
DATA IN
= A0H VALID
DATA
OUT
Erase-Verify
Command Erase
Verification Standby,
Power-down
tWLAX (tAH)
tEHQZ (tDF)
tWHGL
tGHQZ (tDF)
tGLQX (tOLZ)
tGLQV (tOE)
tELQV (tCE)
11559G-15
tELQX (tLZ)
tAVAV (tRC)
tAXQX (tOH)
DATA IN
= 20H DATA IN
= 20H
Setup Erase
Command Erase
Command
Power-up ,
Standby
tAVWL (tAS)
tAVAV (tWC)
tELWL (tCS)
tGHWL (tOES)
tWHEH (tCH)
tWHWH2
tWHWL (tWPH)
tWHDX (tDH)
tWLWH (tWP)
tDVWH (tDS)
tVCS
tVPEL
Addresses
HIGH Z
CE (E)
OE (G)
WE (W)
Data (DQ)
5.0 V
VCC
0 V
VPPH
VPP
VPPL
Erasure
Am28F010 31
12.0 V Flash
SWITCHING W A VEFORMS
Figure 8. AC Waveforms for Programmings Operations
DATA IN
= C0H VALID
DATA
OUT
Verify
Command Programming
Verification Standby,
Power-down
tWLAX (tAH)
tGHQZ (tDF)
tWHGL
tGHQZ (tDF)
tGLQX (tOLZ)
tGLQV (tOE)
tELQV (tCE)
11559G-16
tELQX (tLZ)
tAVAV (tRC)
tAXQX (tOH)
DATA IN
= 40H DATA IN
Setup Program
Command
Program
Command
Latch Address
and Data
Power-up,
Standby
tAVWL (tAS)
tAVAV (tWC)
tELWL (tCS)
tGHWL (tOES)
tWHEH (tCH)
tWHWH1
tWHWL (tWPH)
tWHDX (tDH)
tWLWH (tWP)
tDVWH (tDS)
tVCS
tVPEL
Addresses
HIGH Z
CE (E)
OE (G)
WE (W)
Data (DQ)
5.0 V
VCC
0 V
VPPH
VPP
VPPL
Programming
32 Am28F010
SWITCHING TEST CIRCUIT
SWITCHING TEST WAVEFORMS
2.7 k
IN3064 or Equivalent
CL6.2 k
5.0 V
IN3064
or Equivalent
Device
Under
Test
IN3064 or Equivalent
IN3064 or Equivalent
Notes:
For -70 devices, CL = 30 pF, including jig capacitance
For all others, C
L
= 100 pF, including jig capacitance
11559G-17
11559G-18
3 V
0 V Input Output
1.5 V 1.5 V
Test Points
AC Testing for -70 devices: Inputs are driven at 3.0 V for a
logic “1” and 0 V for a logic “0”. Input pulse rise and fall times
are
10 ns.
2.4 V
0.45 V Input Output
Test Points
2.0 V 2.0 V
0.8 V
0.8 V
AC Testing (all speed options except -70): Inputs are driven at
2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse rise
and fall times are
10 ns.
Am28F010 33
12.0 V Flash
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. 25°C, 12 V V
PP
.
2. The Flasherase/Flashrite algorithms allows for 60 second erase time for military temperature range operations.
3. Maximum time specified is lower than worst case. Worst case is derived from the Flasherase/Flashrite pulse count
(Flasherase = 1000 max and Flashrite = 25 max). Typical worst case f or program and erase is significantly less than the actual
device limit.
LATCHUP CHARACTERISTICS
DATA RETENTION
Parameter
Limits
CommentsMin Typ Max
(Note 3) Unit
Chip Erase Time 1
(Note
(Note 1))
10
(Note
(Note 2)) sec Excludes 00H programming prior to erasure
Chip Programming Time (Note 2)
(Note
(Note 1)) 12.5 sec Excludes system-level overhead
Write/Erase Cycles 10,000 Cycles
Parameter Min Max
Input Voltage with respect to VSS on all pins except I/O pins (Including A9 and VPP) –1.0 V 13.5 V
Input Voltage with respect to VSS on all pins I/O pins –1.0 V VCC + 1.0 V
Current –100 mA +100 mA
Includes all pins except VCC. Test conditions: V CC = 5.0 V, one pin at a time.
Parameter Test Conditions Min Unit
Minimum Pattern Data Retention Time 150°C 10 Years
125°C 20 Years
34 Am28F010
REVISION SUMMARY FOR AM28F010
Distinctive Characteristics:
High Performance:
The fastest speed option available
is now 70 ns.
General Description:
Paragraph 2: Changed fastest speed option to 70 ns.
Product Selector Guide:
Added -70, deleted -95 and -250 speed options.
Ordering Information, Standard Products:
The -70 speed option is now listed in the example.
Valid Combinations:
Added -70, deleted -95 and -250
combinations.
Operating Ranges:
V
CC
Supply Voltages:
Added -70, deleted -95 and -250
speed options.
AC Characteristics:
Read Only Operations Characteristics:
Added the -70
column and test conditions.
Deleted -95 and -250 speed options.
AC Characteristics:
Write/Erase/Program Operations:
Added the -70 col-
umn. Deleted -95 and -250 speed options. Changed
speed option in Note 2 to -70.
Switching Test Waveforms:
In the 3.0 V waveform caption, changed -95 to -70.