AC performance complements the superb dc specifications. The AMP01 slews at 4.5 V/s into capacitive loads of up to 15 nF, settles in 50 s to 0.01% at a gain of 1000, and boasts a healthy 26 MHz gain-bandwidth product. These features make the AMP01 ideal for high speed data acquisition systems. Gain is set by the ratio of two external resistors over a range of 0.1 to 10,000. A very low gain temperature coefficient of 10 ppm/C is achievable over the whole gain range. Output voltage swing is guaranteed with three load resistances; 50 , 500 , and 2 k. Loaded with 500 , the output delivers 13.0 V minimum. A thermal shutdown circuit prevents destruction of the output transistors during overload conditions. The AMP01 can also be configured as a high performance operational amplifier. In many applications, the AMP01 can be used in place of op amp/power-buffer combinations. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 18 17 VIOS NULL -IN 3 16 VIOS NULL +IN VOOS NULL 4 15 RS VOOS NULL 5 14 RS TEST PIN* 6 13 +VOP SENSE 7 12 V+ REFERENCE 8 11 V- OUTPUT 9 10 -VOP AMP01 TOP VIEW (Not to Scale) *MAKE NO ELECTRICAL CONNECTION NC +IN 4 3 2 1 28 27 26 NC RG VIOS NULL AMP01 BTC/883 28-Terminal LCC NC 5 25 VIOS NULL VOOS NULL 6 24 NC NC 7 23 RS 22 RS AMP01 VOOS NULL 8 TOP VIEW (Not to Scale) NC 9 21 +VOP TEST PIN* 10 20 NC NC 11 19 V+ V- NC -VOP NC 12 13 14 15 16 17 18 NC = NO CONNECT OUT Input offset voltage is very low (20 V), which generally eliminates the external null potentiometer. Temperature changes have minimal effect on offset; TCVIOS is typically 0.15 V/C. Excellent low-frequency noise performance is achieved with a minimal compromise on input protection. Bias current is very low, less than 10 nA over the military temperature range. High common-mode rejection of 130 dB, 16-bit linearity at a gain of 1000, and 50 mA peak output current are achievable simultaneously. This combination takes the instrumentation amplifier one step further towards the ideal amplifier. RG 1 RG 2 -IN The AMP01 is a monolithic instrumentation amplifier designed for high-precision data acquisition and instrumentation applications. The design combines the conventional features of an instrumentation amplifier with a high current output stage. The output remains stable with high capacitance loads (1 F), a unique ability for an instrumentation amplifier. Consequently, the AMP01 can amplify low level signals for transmission through long cables without requiring an output buffer. The output stage may be configured as a voltage or current generator. 18-Lead Cerdip RG GENERAL DESCRIPTION PIN CONFIGURATIONS REF FEATURES Low Offset Voltage: 50 V Max Very Low Offset Voltage Drift: 0.3 V/C Max Low Noise: 0.12 V p-p (0.1 Hz to 10 Hz) Excellent Output Drive: 10 V at 50 mA Capacitive Load Stability: to 1 F Gain Range: 0.1 to 10,000 Excellent Linearity: 16-Bit at G = 1000 High CMR: 125 dB min (G = 1000) Low Bias Current: 4 nA Max May Be Configured as a Precision Op Amp Output-Stage Thermal Shutdown Available in Die Form SENSE a Low Noise, Precision Instrumentation Amplifier AMP01* *MAKE NO ELECTRICAL CONNECTION 20-Lead SOIC RG 1 20 RG TEST PIN* 2 19 TEST PIN* -IN 3 18 +IN VOOS NULL 4 17 VIOS NULL VOOS NULL 5 16 VIOS NULL TEST PIN* 6 SENSE AMP01 TOP VIEW 15 R S (Not to Scale) 14 RS 7 REFERENCE 8 13 +VOP OUTPUT 9 12 V+ 11 V- -VOP 10 *MAKE NO ELECTRICAL CONNECTION *Protected under U.S. Patent Numbers 4,471,321 and 4,503,381. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999 AMP01-SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ V = 15 V, R = 10 k, R = 2 k, T = +25C, unless otherwise noted) S S Parameter Symbol Conditions OFFSET VOLTAGE Input Offset Voltage VIOS TA = +25C -55C TA +125C -55C TA +125C TA = +25C -55C TA +125C RG = -55C TA +125C G = 1000 G = 100 G = 10 G=1 Input Offset Voltage Drift Output Offset Voltage TCVIOS VOOS Output Offset Voltage Drift TCVOOS Offset Referred to Input vs. Positive Supply V+ = +5 V to +15 V PSR Offset Referred to Input vs. Negative Supply V- = -5 V to -15 V PSR Input Offset Voltage Trim Range Output Offset Voltage Trim Range INPUT CURRENT Input Bias Current IB Input Bias Current Drift Input Offset Current TCIB IOS Input Offset Current Drift TCIOS INPUT Input Resistance RIN Input Voltage Range IVR Common-Mode Rejection CMR L Min A AMP01A Typ Max AMP01B Min Typ Max Units 40 60 0.3 2 6 100 150 1.0 6 10 V V V/C mV mV 50 120 120 100 80 120 110 100 90 70 V/C dB dB dB dB 130 130 110 90 125 105 85 65 110 100 90 70 105 90 70 50 120 120 100 80 115 95 75 60 dB dB dB dB dB dB dB dB 125 105 85 85 105 90 70 50 115 95 75 60 dB dB dB dB 20 40 0.15 1 3 50 80 0.3 3 6 20 130 130 110 90 50 120 110 95 75 -55C TA +125C G = 1000 G = 100 G = 10 G=1 G = 1000 G = 100 G = 10 G=1 120 110 95 75 105 90 70 50 -55C TA +125C G = 1000 G = 100 G = 10 G=1 105 90 70 50 VS = 4.5 V to 18 V 1 6 6 mV VS = 4.5 V to 18 V 1 100 100 mV TA = +25C -55C TA +125C -55C TA +125C TA = +25C -55C TA +125C -55C TA +125C 1 4 40 0.2 0.5 3 Differential, G = 1000 Differential, G 100 Common Mode, G = 1000 TA = +25C2 -55C TA +125C VCM = 10 V, 1 k Source Imbalance G = 1000 G = 100 G = 10 G=1 1 10 20 -55C TA +125C G = 1000 G = 100 G = 10 G=1 10.5 10.0 4 10 2 6 50 0.5 1.0 5 1.0 3.0 10.5 10.0 6 15 2.0 6.0 nA nA pA/C nA nA pA/C 1 10 20 G G G V V 125 120 100 85 130 130 120 100 115 110 95 75 125 125 110 90 dB dB dB dB 120 115 95 80 125 125 115 95 110 105 90 75 120 120 105 90 dB dB dB dB NOTES 1 VIOS and V OOS nulling has minimal affect on TCV IOS and TCV OOS respectively. 2 Refer to section on common-mode rejection. Specifications subject to change without notice. -2- REV. D AMP01 (@ VS = 15 V, RS = 10 k, RL = 2 k, TA = +25C, -25C TA +85C for E, F ELECTRICAL CHARACTERISTICS grades, 0C T +70C for G grade, unless otherwise noted) A Parameter OFFSET VOLTAGE Input Offset Voltage Symbol Conditions VIOS TA = +25C TMIN TA TMAX TMIN TA TMAX1 TA = +25C TMIN TA TMAX R G = 1 TMIN TA TMAX G = 1000 G = 100 G = 10 G=1 Input Offset Voltage Drift Output Offset Voltage TCVIOS VOOS Output Offset Voltage Drift TCVOOS Offset Referred to Input vs. Positive Supply V+ = +5 V to +15 V PSR Offset Referred to Input vs. Negative Supply V- = -5 V to -15 V Input Offset Voltage Trim Range Output Offset Voltage Trim Range INPUT CURRENT Input Bias Current PSR IB Input Bias Current Drift Input Offset Current TCIB IOS Input Offset Current Drift TCIOS INPUT Input Resistance RIN Input Voltage Range IVR Common-Mode Rejection CMR Min AMP01F/G Min Typ Max Units 40 60 0.3 2 6 100 150 1.0 6 10 V V V/C mV mV 50 120 120 100 80 120 110 100 90 70 V/C dB dB dB dB 130 130 110 90 125 105 85 65 110 100 90 70 105 90 70 50 120 120 100 80 115 95 75 60 dB dB dB dB dB dB dB dB 125 105 85 85 105 90 70 50 115 95 75 60 dB dB dB dB 20 40 0.15 1 3 50 80 0.3 3 6 20 130 130 110 90 100 120 110 95 75 TMIN TA TMAX G = 1000 G = 100 G = 10 G=1 G = 1000 G = 100 G = 10 G=1 120 110 95 75 110 95 75 55 TMIN TA TMAX G = 1000 G = 100 G = 10 G=1 110 95 75 55 VS = 4.5 V to 18 V 2 6 6 mV VS = 4.5 V to 18 V 2 100 100 mV TA = +25C TMIN TA TMAX TMIN TA TMAX TA = +25C TMIN TA TMAX TMIN TA TMAX 1 4 40 0.2 0.5 3 Differential, G = 1000 Differential, G 100 Common Mode, G = 1000 TA = +25C3 TMIN TA TMAX VCM = 10 V, 1 k Source Imbalance G = 1000 G = 100 G = 10 G=1 1 10 20 TMIN TA TMAX G = 1000 G = 100 G = 10 G=1 NOTES 1 Sample tested. 2 VIOS and V OOS nulling has minimal affect on TCVIOS and TCVOOS , respectively. 3 Refer to section on common-mode rejection. Specifications subject to change without notice. REV. D AMP01E Typ Max -3- 10.5 10.0 4 10 2 6 50 0.5 1.0 5 1.0 3.0 10.5 10.0 6 15 2.0 6.0 mV mV pA/C mV mV pA/C 1 10 20 G G G V V 125 120 100 85 130 130 120 100 115 110 95 75 125 125 110 90 dB dB dB dB 120 115 95 80 125 125 115 95 110 105 90 75 120 120 105 90 dB dB dB dB AMP01 ELECTRICAL CHARACTERISTICS (@ V = 15 V, R = 10 k, R = 2 k, T = +25C, unless otherwise noted) S Parameter S Symbol Conditions L Min A AMP01A/E Typ Max Min AMP01B/F/G Typ Max Units GAIN Gain Equation Accuracy G= 20 x RS RG 0.3 0.6 0.5 0.8 % Accuracy Measured from G = 1 to 1000 Gain Range Nonlinearity G Temperature Coefficient GTC OUTPUT RATING Output Voltage Swing VOUT Positive Current Limit Negative Current Limit Capacitive Load Stability Thermal Shutdown Temperature NOISE Voltage Density, RTI Noise Current Density, RTI Input Noise Voltage Input Noise Current DYNAMIC RESPONSE Small-Signal Bandwidth (-3 dB) Slew Rate Settling Time 0.1 10k 0.0007 0.005 0.005 0.005 0.010 5 10 0.1 10k 0.0007 0.005 0.005 0.007 0.015 5 15 V/V % % % % ppmC 13.0 13.0 2.5 12.0 12.0 60 60 13.8 13.5 4.0 13.8 13.5 100 120 90 120 13.0 13.0 2.5 12.0 12.0 60 60 13.8 13.5 4.0 13.8 13.5 100 120 90 120 V V V V V mA mA 0.1 1 0.1 1 F 165 165 C 5 10 59 540 0.15 5 10 59 540 0.15 nV/Hz nV/Hz nV/Hz nV/Hz pA/Hz 0.12 0.16 1.4 13 2 0.12 0.16 1.4 13 2 V p-p V p-p V p-p V p-p pA p-p 570 100 82 26 4.5 570 100 82 26 4.5 kHz kHz kHz kHz V/s 12 13 15 50 s s s s G = 10001 G = 1001 G = 101 G = 11 1 G 10001, 2 RL = 2 k RL = 500 RL = 50 RL = 2 k Over Temp. RL = 500 3 Output-to-Ground Short Output-to-Ground Short 1 G 1000 No Oscillations1 Junction Temperature en en en en en in en p-p en p-p en p-p en p-p en p-p in p-p BW SR tS fO = 1 kHz G = 1000 G = 100 G = 10 G=1 fO = 1 kHz, G = 1000 0.1 Hz to 10 Hz G = 1000 G = 100 G = 10 G=1 0.1 Hz to 10 Hz, G = 1000 G=1 G = 10 G = 100 G = 1000 G = 10 To 0.01%, 20 V step G=1 G = 10 G = 100 G = 1000 3.5 12 13 15 50 3.0 NOTES 1 Guaranteed by design. 2 Gain tempco does not include the effects of gain and scale resistor tempco match. 3 -55C TA +125C for A/B grades, -25C TA +85C for E/F grades, 0C TA 70C for G grades. Specifications subject to change without notice. -4- REV. D AMP01 ELECTRICAL CHARACTERISTICS (@ V = 15 V, R = 10 k, R = 2 k, T = +25C, unless otherwise noted) S Parameter Symbol Conditions SENSE INPUT Input Resistance Input Current Voltage Range RIN IIN REFERENCE INPUT Input Resistance Input Current Voltage Range Gain to Output RIN IIN S L Referenced to V- (Note 1) A AMP01A/E Min Typ Max AMP01B/F/G Min Typ Max 35 65 35 +15 -10.5 65 35 +15 -10.5 50 280 -10.5 35 Referenced to V- (Note 1) 50 280 -10.5 50 280 +15 50 280 1 65 65 +15 1 POWER SUPPLY -25C TA +85C for E/F Grades, -55C TA +125C for A/B Grades +V linked to +VOP 4.5 18 Supply Voltage Range VS -V linked to -VOP 4.5 18 VS +V linked to +VOP 3.0 4.8 Quiescent Current IQ IQ -V linked to -VOP 3.4 4.8 4.5 4.5 3.0 3.4 18 18 4.8 4.8 NOTE 1 Guaranteed by design. Specifications subject to change without notice. ORDERING GUIDE Model Temperature Range Package Description Package Option AMP01AX AMP01AX/883C AMP01BTC/883C AMP01BX AMP01BX/883C AMP01EX AMP01FX AMP01GBC AMP01GS AMP01GS-REEL AMP01NBC -55C to +125C -55C to +125C -55C to +125C -55C to +125C -55C to +125C -25C to +85C -25C to +85C 0C to +70C 0C to +70C 5962-8863001VA* -55C to +125C 5962-88630023A* -55C to +125C 5962-8863002VA* -55C to +125C 18-Lead Cerdip 18-Lead Cerdip 28-Terminal LCC 18-Lead Cerdip 18-Lead Cerdip 18-Lead Cerdip 18-Lead Cerdip Die 20-Lead SOIC 13" Tape and Reel Die Q-18 Q-18 E-28A Q-18 Q-18 Q-18 Q-18 18-Lead Cerdip 28-Terminal LCC 18-Lead Cerdip Q-18 E-28A Q-18 R-20 R-20 *Standard military drawing available. DICE CHARACTERISTICS Die Size 0.111 x 0.149 inch, 16,539 sq. mils (2.82 x 3.78 mm, 10.67 sq. mm) 1. 2. 3. 4. 5. 6. 7. 8. 9. RG RG -INPUT VOOS NULL VOOS NULL TEST PIN* SENSE REFERENCE OUTPUT 10. 11. 12. 13. 14. 15. 16. 17. 18. V- (OUTPUT) V- V+ V+ (OUTPUT) RS RS VIOS NULL VIOS NULL +INPUT * MAKE NO ELECTRICAL CONNECTION REV. D -5- Units k A V k A V V/V V V mA mA AMP01 WAFER TEST LIMITS (@ V = 15 V, R = 10 k, R = 2 k, T = +25C, unless otherwise noted) S S L Parameter Symbol Conditions Input Offset Voltage Output Offset Voltage Offset Referred to Input vs. Positive Supply VIOS VOOS PSR Offset Referred to Input vs. Negative Supply PSR Input Bias Current Input Offset Current Input Voltage Range Common Mode Rejection IB IOS IVR CMR Gain Equation Accuracy Output Voltage Swing Output Current Limit Output Current Limit Quiescent Current IQ AMP01NBC Limit V+ = +5 V to +15 V G = 1000 G = 100 G = 10 G=1 V- = -5 V to -15 V G = 1000 G = 100 G = 10 G=1 Guaranteed by CMR Tests VCM = 10 V G = 1000 G = 100 G = 10 G=1 G= VOUT VOUT VOUT A 20 x RS RG RL = 2 k RL = 500 RL = 50 Output to Ground Short Output to Ground Short +V Linked to +VOP -V Linked to -VOP AMP01GBC Limit Units 60 4 120 8 120 110 95 75 110 100 90 70 105 90 70 50 4 1 10 105 90 70 50 8 3 10 125 120 100 85 115 110 95 75 V max mV max dB min dB min dB min dB min dB min dB min dB min dB min dB min dB min nA max nA max V min dB min dB min dB min dB min dB min 0.6 0.8 % max 13 13 2.5 60 120 4.8 4.8 13 13 2.5 60 120 4.8 4.8 V min V min V min mA min mA max mA max mA max NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. V+ VIOS NULL +VOP A1 OUTPUT 250V -VOP -IN +IN 250V Q1 Q2 REFERENCE R1 47.5kV R3 47.5kV RGAIN A2 SENSE A3 RSCALE R2 2.5kV VOOS NULL R4 2.5kV V- Figure 1. Simplified Schematic CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AMP01 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -6- WARNING! ESD SENSITIVE DEVICE REV. D AMP01 ELECTRICAL CHARACTERISTICS (@ V = 15 V, R = 10 k, R = 2 k, T = +25C, unless otherwise noted) S Parameter Symbol Input Offset Voltage Drift Output Offset Voltage Drift Input Bias Current Drift Input Offset Current Drift Nonlinearity Voltage Noise Density TCVIOS TCVOOS TCIB TCIOS en Current Noise Density in Voltage Noise en p-p Current Noise in p-p Small-Signal Bandwidth (-3 dB) BW Slew Rate SR Settling Time tS S L A AMP01NBC Typical Conditions RG = G = 1000 G = 1000 fO = 1 kHz G = 1000 fO = 1 kHz G = 1000 0.1 Hz to 10 Hz G = 1000 0.1 Hz to 10 Hz G = 1000 G = 10 To 0.01%, 20 V Step G = 1000 AMP01GBC Typical Units 0.15 20 40 3 0.0007 0.30 50 50 5 0.0007 V/C V/C pA/C pA/C % 5 5 nV/Hz 0.15 0.15 pA/Hz 0.12 2 0.12 2 V p-p pA p-p 26 4.5 26 4.5 kHz V/s 50 50 s NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. REV. D -7- AMP01-Typical Performance Characteristics 8 50 30 20 10 0 -10 -20 -30 -40 -75 -50 -25 6 4 UNIT NO. 1 2 2 0 3 -2 4 -4 -6 0 25 50 75 100 125 150 TEMPERATURE - 8C Figure 2. Input Offset Voltage vs. Temperature 0 620 -0.5 65 610 615 620 625 POWER SUPPLY VOLTAGE - Volts TA = +258C 3 2 1 0 -0.2 -0.4 -0.6 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE - 8C Figure 8. Input Offset Current vs. Temperature COMMON-MODE REJECTION - dB 0.0 0.5 0 -0.5 -1.0 -2 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE - 8C -1.5 0 65 610 615 POWER SUPPLY VOLTAGE - Volts 620 Figure 7. Input Bias Current vs. Supply Voltage 140 140 0.2 1.0 -1 VS = 615V 0.4 -3 Figure 6. Input Bias Current vs. Temperature 0.8 0.6 -2 1.5 VS = 615V TA = +258C G = 1000 COMMON-MODE REJECTION - dB 0 0 -1 2.0 INPUT BIAS CURRENT - nA INPUT BIAS CURRENT - nA 0 1 Figure 4. Output Offset Voltage vs. Temperature 4 2.0 0.5 2 VS = 615V Figure 5. Output Offset Voltage Change vs. Supply Voltage INPUT OFFSET CURRENT - nA 65 610 615 POWER SUPPLY VOLTAGE - Volts 5 1.0 3 -4 TA = +258C 1.5 VS = 615V 4 -5 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE - 8C Figure 3. Input Offset Voltage vs. Supply Voltage 2.5 -1.0 OUTPUT OFFSET VOLTAGE - mV INPUT OFFSET VOLTAGE - mV INPUT OFFSET VOLTAGE - mV 40 OUTPUT OFFSET VOLTAGE CHANGE - mV 5 TA = +258C VS = 615V 130 120 110 120 G = 100 100 80 60 G = 10 40 G=1 VCM = 2V p-p VS = 615V TA = +258C 20 0 100 1 10 100 1k VOLTAGE GAIN - G 10k Figure 9. Common-Mode Rejection vs. Voltage Gain -8- 1 10 100 1k FREQUENCY - Hz 10k 100k Figure 10. Common-Mode Rejection vs. Frequency REV. D 140 VDM = 0 VS = 615V 14 12 10 VS = 610V 8 6 VS = 65V 4 2 120 100 G = 100 80 60 40 G = 10 20 1 100 G = 10 80 G=1 60 40 VS = 615V TA = +258C DVS = 61V 20 30 14 12 10 8 6 4 2 100 1k LOAD RESISTANCE - V G = 1000 60 G = 100 G = 10 20 G=1 0 -20 -40 1 10 100 1k 10k FREQUENCY - Hz 100k Figure 17. Closed-Loop Voltage Gain vs. Frequency REV. D 20 15 10 1M 1k 10k 100k FREQUENCY - Hz G = 1000 1.0 G=1 0.1 0.001 10 1M 100 1k 10k 100k FREQUENCY - Hz 1M Figure 16. Closed-Loop Output Impedance vs. Frequency 0.02 VS = 615V RL = 600V VOUT = 20V p-p 0.06 0.05 G = 1000 0.04 0.03 G = 10 G = 100 0.02 G=1 0.01 0 10 10 0.01 5 0.07 100k VS = 615V IOUT = 20mA p-p 0.08 VS = 615V TA = +258C 10k 100 VS = 615V RL = 2kV Figure 15. Maximum Output Swing vs. Frequency TOTAL HARMONIC DISTORTION - % 80 100 1k FREQUENCY - Hz 10 Figure 13. Negative PSR vs. Frequency 25 0 100 10k Figure 14. Maximum Output Voltage vs. Load Resistance 1 100k 10k OUTPUT IMPEDANCE - V PEAK-TO-PEAK AMPLITUDE - Volts VS = 615V 40 100 1k FREQUENCY - Hz Figure 12. Positive PSR vs. Frequency 16 10 10 100 1k FREQUENCY - Hz 10k Figure 18. Total Harmonic Distortion vs. Frequency -9- TOTAL HARMONIC DISTORTION - % 18 OUITPUT VOLTAGE - Volts G = 100 0 0 Figure 11. Common-Mode Voltage Range vs. Temperature VOLTAGE GAIN - dB G = 1000 120 G=1 0 25 50 75 100 125 150 -75 -50 -25 0 TEMPERATURE - 8C 0 140 VS = 615V TA = +258C DVS = 61V G = 1000 POWER SUPPLY REJECTION - dB 16 POWER SUPPLY REJECTION - dB COMMON-MODE INPUT VOLTAGE - Volts AMP01 VS = 615V G = 100 f = 1kHz VOUT = 20V p-p 0.01 0 100 1k LOAD RESISTANCE - V 10k Figure 19. Total Harmonic Distortion vs. Load Resistance AMP01 6 6 VS = 615V 5 4 3 2 1 4 3 2 1 0 1 10 100 VOLTAGE GAIN - G Figure 20. Slew Rate vs. Voltage Gain 10 100 1k FREQUENCY - Hz Figure 23. Voltage Noise Density vs. Frequency 100 10 10 100 VOLTAGE GAIN - G -5 -4 -3 -2 -1 0 65 620 610 615 POWER SUPPLY VOLTAGE - Volts Figure 26. Negative Supply Current vs. Supply Voltage 4 3 2 1 0 65 620 610 615 POWER SUPPLY VOLTAGE - Volts -6 VS = 615V NEGATIVE SUPPLY CURRENT - mA -6 POSITIVE SUPPLY CURRENT - mA -7 5 Figure 25. Positive Supply Current vs. Supply Voltage 6 TA = +258C 6 1k Figure 24. RTI Voltage Noise Density vs. Gain -8 7 0 1 1k TA = +258C 1 10k 10 100 VOLTAGE GAIN - G 8 POSITIVE SUPPLY CURRENT - mA VOLTAGE NOISE - nV/ Hz VOLTAGE NOISE - nV/ Hz 0 1 NEGATIVE SUPPLY CURRENT - mA 1 Figure 22. Settling Time to 0.01% vs. Voltage Gain VS = 615V f = 1kHz 5 30 1m 1k G = 1000 10 40 10 1n 10n 100n LOAD CAPACITANCE - F Figure 21. Slew Rate vs. Load Capacitance 15 50 20 0 100p 1k VS = 615V 20V STEP 60 SETTLING TIME - ms SLEW RATE - V/ms SLEW RATE - V/ms 5 0 70 VS = 615V 5 4 3 2 1 0 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE - 8C Figure 27. Positive Supply Current vs. Temperature -10- -5 VS = 615V VSENSE = VREF = 0V -4 -3 -2 -1 0 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE - 8C Figure 28. Negative Supply Current vs. Temperature REV. D AMP01 INPUT AND OUTPUT OFFSET VOLTAGES GAIN Instrumentation amplifiers have independent offset voltages associated with the input and output stages. While the initial offsets may be adjusted to zero, temperature variations will cause shifts in offsets. Systems with auto-zero can correct for offset errors, so initial adjustment would be unnecessary. However, many high-gain applications don't have auto zero. For these applications, both offsets can be nulled, which has minimal effect on TCVIOS and TCVOOS The AMP01 uses two external resistors for setting voltage gain over the range 0.1 to 10,000. The magnitudes of the scale resistor, RS, and gain-set resistor, RG, are related by the formula: G = 20 x RS/RG, where G is the selected voltage gain (refer to Figure 29). V+ RS The input offset component is directly multiplied by the amplifier gain, whereas output offset is independent of gain. Therefore, at low gain, output-offset errors dominate, while at high gain, input-offset errors dominate. Overall offset voltage, VOS, referred to the output (RTO) is calculated as follows; VOS (RTO) = (VIOS x G) + VOOS 14 -IN TCVOS (RTO) = (TCV IOS x G) + TCVOOS (2) where TCVIOS is the input offset voltage drift, and TCVOOS is the output offset voltage specification. Frequently, the amplifier drift is referred back to the input (RTI), which is then equivalent to an input signal change; TCVOS (RTI) = TCVIOS TCV OOS G (3) For example, the maximum input-referred drift of an AMP01 EX set to G = 1000 becomes; TCVOS (RTI ) = 0.3 V/C + 100 V /C = 0.4 V/C max 1000 INPUT BIAS AND OFFSET CURRENTS Input transistor bias currents are additional error sources that can degrade the input signal. Bias currents flowing through the signal source resistance appear as an additional offset voltage. Equal source resistance on both inputs of an IA will minimize offset changes due to bias current variations with signal voltage and temperature. However, the difference between the two bias currents, the input offset current, produces a nontrimmable error. The magnitude of the error is the offset current times the source resistance. 2 12 7 AMP01 3 VOLTAGE GAIN, G = 10 (20 R3 R ) S 9 8 11 REFERENCE OUTPUT V- G Figure 29. Basic AMP01 Connections for Gains 0.1 to 10,000 The magnitude of RS affects linearity and output referred errors. Circuit performance is characterized using RS = 10 k when operating on 15 volt supplies and driving a 10 volt output. RS may be reduced to 5 k in many applications particularly when operating on 5 volt supplies or if the output voltage swing is limited to 5 volts. Bandwidth is improved with RS = 5 k and this also increases common-mode rejection by approximately 6 dB at low gain. Lowering the value below 5 k can cause instability in some circuit configurations and usually has no advantage. High voltage gains between two and ten thousand would require very low values of RG. For RS = 10 k and AV = 2000 we get RG = 100 ; this value is the practical lower limit for RG. Below 100 , mismatch of wirebond and resistor temperature coefficients will introduce significant gain tempco errors. Therefore, for gains above 2,000, RG should be kept constant at 100 and RS increased. The maximum gain of 10,000 is obtained with RS set to 50 k. Metal-film or wirewound resistors are recommended for best results. The absolute values and TCs are not too important, only the ratiometric parameters. AC amplifiers require good gain stability with temperature and time, but dc performance is unimportant. Therefore, low cost metal-film types with TCs of 50 ppm/C are usually adequate for RS and R G. Realizing the full potential of the AMP01's offset voltage and gain stability requires precision metal-film or wirewound resistors. Achieving a 15 ppm/C gain tempco at all gains requires RS and RG temperature coefficient matching to 5 ppm/C or better. A current path must always be provided between the differential inputs and analog ground to ensure correct amplifier operation. Floating inputs, such as thermocouples, should be grounded close to the signal source for best common-mode rejection. REV. D SENSE 13 RG where VIOS and VOOS are the input and output offset voltage specifications and G is the amplifier gain. Input offset nulling alone is recommended with amplifiers having fixed gain above 50. Output offset nulling alone is recommended when gain is fixed at 50 or below. The overall offset voltage drift TCVOS, referred to the output, is a combination of input and output drift specifications. Input offset voltage drift is multiplied by the amplifier gain, G, and summed with the output offset drift; 15 1 (1) In applications requiring both initial offsets to be nulled, the input offset is nulled first by short-circuiting RG, then the output offset is nulled with the short removed. 18 +IN -11- AMP01 IVR is the data sheet specification for input voltage range; VOUT is the maximum output signal; G is the chosen voltage gain. For example, at +25C, IVR is specified as 10.5 volt minimum with 15 volt supplies. Using a 10 volt maximum swing output and substituting the figures in (4) simplifies the formula to: 1M VS = 615V RESISTANCE - V 100k 5 CMVR = 10.5 - G RS 10k (5) For all gains greater than or equal to 10, CMVR is 10 volt minimum; at gains below 10, CMVR is reduced. RG 1k ACTIVE GUARD DRIVE 100 1 10 100 VOLTAGE GAIN 1k 10k Figure 30. RG and RS Selection Gain accuracy is determined by the ratio accuracy of RS and RG combined with the gain equation error of the AMP01 (0.6% max for A/E grades). All instrumentation amplifiers require attention to layout so thermocouple effects are minimized. Thermocouples formed between copper and dissimilar metals can easily destroy the TCVOS performance of the AMP01 which is typically 0.15 V/C. Resistors themselves can generate thermoelectric EMF's when mounted parallel to a thermal gradient. "Vishay" resistors are recommended because a maximum value for thermoelectric generation is specified. However, where thermal gradients are low and gain TCs of 20 ppm-50 ppm are sufficient, general-purpose metal-film resistors can be used for RG and RS. COMMON-MODE REJECTION Ideally, an instrumentation amplifier responds only to the difference between the two input signals and rejects commonmode voltages and noise. In practice, there is a small change in output voltage when both inputs experience the same commonmode voltage change; the ratio of these voltages is called the common-mode gain. Common-mode rejection (CMR) is the logarithm of the ratio of differential-mode gain to commonmode gain, expressed in dB. CMR specifications are normally measured with a full-range input voltage change and a specified source resistance unbalance. The current-feedback design used in the AMP01 inherently yields high common-mode rejection. Unlike resistive feedback designs, typified by the three-op-amp IA, the CMR is not degraded by small resistances in series with the reference input. A slight, but trimmable, output offset voltage change results from resistance in series with the reference input. The common-mode input voltage range, CMVR, for linear operation may be calculated from the formula: |V OUT| CMVR = IVR - 2 G Rejection of common-mode noise and line pick-up can be improved by using shielded cable between the signal source and the IA. Shielding reduces pick-up, but increases input capacitance, which in turn degrades the settling-time for signal changes. Further, any imbalance in the source resistance between the inverting and noninverting inputs, when capacitively loaded, converts the common-mode voltage into a differential voltage. This effect reduces the benefits of shielding. AC common-mode rejection is improved by "bootstrapping" the input cable capacitance to the input signal, a technique called "guard driving." This technique effectively reduces the input capacitance. A single guard-driving signal is adequate at gains above 100 and should be the average value of the two inputs. The value of external gain resistor RG is split between two resistors RG1 and RG2; the center tap provides the required signal to drive the buffer amplifier (Figure 31). GROUNDING The majority of instruments and data acquisition systems have separate grounds for analog and digital signals. Analog ground may also be divided into two or more grounds which will be tied together at one point, usually the analog power-supply ground. In addition, the digital and analog grounds may be joined, normally at the analog ground pin on the A-to-D converter. Following this basic grounding practice is essential for good circuit performance (Figure 32). Mixing grounds causes interactions between digital circuits and the analog signals. Since the ground returns have finite resistance and inductance, hundreds of millivolts can be developed between the system ground and the data acquisition components. Using separate ground returns minimizes the current flow in the sensitive analog return path to the system ground point. Consequently, noisy ground currents from logic gates do not interact with the analog signals. Inevitably, two or more circuits will be joined together with their grounds at differential potentials. In these situations, the differential input of an instrumentation amplifier, with its high CMR, can accurately transfer analog information from one circuit to another. SENSE AND REFERENCE TERMINALS (4) The sense terminal completes the feedback path for the instrumentation amplifier output stage and is normally connected directly to the output. The output signal is specified with respect to the reference terminal, which is normally connected to analog ground. -12- REV. D AMP01 VOLTAGE GAIN, G = +15V C3 0.047mF (20R3 R ) S RS 10kV G1 * AV = 500 WITH COMPONENTS SHOWN 15 RS +15V 7 6 GUARD DRIVE 2 RG3 200V 3 RG2 200V 741 1 RG1 400V 4 -15V 3 -IN 6 * 12 RG 7 V+ RG R1 1MV R5 8 OUTPUT * 11 VOOS NULL VIOS NULL 9 V- 10 5 *SOLDER LINK 4 17 16 R2 1MV SENSE 13 AMP01 2 10mF 14 RS 18 +IN + C5 C1 0.047mF R4 NC * VR2 100kV VR1 100kV REFERENCE R3 * C4 0.047mF SIGNAL GROUND GROUND + C6 C2 0.047mF 10mF -15V Figure 31. AMP01 Evaluation Circuit Showing Guard-Drive Connection ANALOG POWER SUPPLY +15V DIGITAL POWER SUPPLY 0V -15V 0V +5V 4.7mF + C C C DIGITAL GROUND C 7 9 AMP01 SMP-11 SAMPLE AND HOLD C C C ANALOG GROUND DIGITAL GROUND ADC 8 OUTPUT REFERENCE HOLD CAPACITOR C = 0.047mF CERAMIC CAPACITORS Figure 32. Basic Grounding Practice REV. D -13- DIGITAL DATA OUTPUT AMP01 combination of these unique features in an instrumentation amplifier allows low-level transducer signals to be conditioned and directly transmitted through long cables in voltage or current form. Increased output current brings increased internal dissipation, especially with 50 loads. For this reason, the power-supply connections are split into two pairs; pins 10 and 13 connect to the output stage only and pins 11 and 12 provide power to the input and following stages. Dual supply pins allow dropper resistors to be connected in series with the output stage so excess power is dissipated outside the package. Additional decoupling is necessary between pins 10 and 13 to ground to maintain stability when dropper resistors are used. Figure 34 shows a complete circuit for driving 50 loads. If heavy output currents are expected and the load is situated some distance from the amplifier, voltage drops due to track or wire resistance will cause errors. Voltage drops are particularly troublesome when driving 50 loads. Under these conditions, the sense and reference terminals can be used to "remote sense" the load as shown in Figure 33. This method of connection puts the IxR drops inside the feedback loop and virtually eliminates the error. An unbalance in the lead resistances from the sense and reference pins does not degrade CMR, but will change the output offset voltage. For example, a large unbalance of 3 will change the output offset by only 1 mV. DRIVING 50 LOADS Output currents of 50 mA are guaranteed into loads of up to 50 and 26 mA into 500 . In addition, the output is stable and free from oscillation even with a high load capacitance. The V+ RS * IN4148 DIODES ARE OPTIONAL. DIODES LIMIT THE OUTPUT VOLTAGE EXCURSION IF SENSE AND/OR REFERENCE LINES BECOME DISCONNECTED FROM THE LOAD. 14 18 +IN 15 SENSE 12 1 13 * 7 RG 9 AMP01 2 -IN 10 8 REFERENCE REMOTE LOAD TWISTED PAIRS 11 3 * OUTPUT GROUND V- Figure 33. Remote Load Sensing POWER BANDWIDTH, G = 100, 130kHz POWER BANDWIDTH, G = 10, 200kHz T.H.D.~0.04% @ 1kHz, 2Vrms +15V R1 130V 1W RS 5kV 0.047mF C1 0.047mF 14 18 +IN 15 12 SENSE 13 1 7 8 2 10 11 VOLTAGE GAIN, G = R2 130V 1W 20 3 RS ( RG 50V LOAD REFERENCE C2 0.047mF 3 -IN VOUT 63V MAX 9 AMP01 RG 0.047mF -15V ) RESISTERS R1 AND R2 REDUCE IC DISSIPATION Figure 34. Driving 50 Loads -14- REV. D AMP01 HEATSINKING To maintain high reliability, the die temperature of any IC should be kept as low as practicable, preferably below 100C. Although most AMP01 application circuits will produce very little internal heat -- little more than the quiescent dissipation of 90 mW--some circuits will raise that to several hundred milliwatts (for example, the 4-20 mA current transmitter application, Figure 37). Excessive dissipation will cause thermal shutdown of the output stage thus protecting the device from damage. A heatsink is recommended in power applications to reduce the die temperature. Several appropriate heatsinks are available; the Thermalloy 6010B is especially easy to use and is inexpensive. Intended for dual-in-line packages, the heatsink may be attached with a cyanoacrylate adhesive. This heatsink reduces the thermal resistance between the junction and ambient environment to approximately 80C/W. Junction (die) temperature can then be calculated by using the relationship: Pd = TJ - TA JA External series resistors could be added to guard against higher voltage levels at the input, but resistors alone increase the input noise and degrade the signal-to-noise ratio, especially at high gains. Protection can also be achieved by connecting back-to-back 9.1 V Zener diodes across the differential inputs. This technique does not affect the input noise level and can be used down to a gain of 2 with minimal increase in input current. Although voltage-clamping elements look like short circuits at the limiting voltage, the majority of signal sources provide less than 50 mA, producing power levels that are easily handled by low-power Zeners. Simultaneous connection of the differential inputs to a low impedance signal above 10 V during normal circuit operation is unlikely. However, additional protection involves adding 100 current-limiting resistors in each signal path prior to the voltage clamp, the resistors increase the input noise level to just 5.4 nV/Hz (refer to Figure 35). Input components, whether multiplexers or resistors, should be carefully selected to prevent the formation of thermocouple junctions that would degrade the input signal. where TJ and TA are the junction and ambient temperatures respectively, JA is the thermal resistance from junction to ambient, and Pd is the device's internal dissipation. * OPTIONAL PROTECTION RESISTORS, SEE TEXT. +IN Instrumentation amplifiers invariably sit at the front end of instrumentation systems where there is a high probability of exposure to overloads. Voltage transients, failure of a transducer, or removal of the amplifier power supply while the signal source is connected may destroy or degrade the performance of an unprotected amplifier. Although it is impractical to protect an IC internally against connection to power lines, it is relatively easy to provide protection against typical system overloads. AMP01 noise level approaches the theoretical noise floor of the input stage which would be 4 nV/Hz at 1 kHz when the gain is set at 1000. Noise is the result of shot noise in the input devices and Johnson noise in the resistors. Resistor noise is calculated from the values of RG (200 at a gain of 1000) and the input protection resistors (250 ). Active loads for the input transistors contribute less than 1 nV/Hz of noise. The measured noise level is typically 5 nV/Hz. Diodes across the input transistor's base-emitter junctions, combined with 250 input resistors and RG, protect against differential inputs of up to 20 V for gains of up to 100. The diodes also prevent avalanche breakdown that would degrade the IB and IOS specifications. Decreasing the value of RG for gains above 100 limits the maximum input overload protection to 10 V. REV. D LINEAR INPUT RANGE, 65V MAXIMUM DIFFERENTIAL PROTECTION TO 630V 100V 1W* OVERVOLTAGE PROTECTION The AMP01 is internally protected against overloads for gains of up to 100. At higher gains, the protection is reduced and some external measures may be required. Limited internal overload protection is used so that noise performance would not be significantly degraded. +15V 9.1V 1W ZENERS -IN AMP01 VOUT 100V 1W* -15V Figure 35. Input Overvoltage Protection for Gains 2 to 10,000 POWER SUPPLY CONSIDERATIONS Achieving the rated performance of precision amplifiers in a practical circuit requires careful attention to external influences. For example, supply noise and changes in the nominal voltage directly affect the input offset voltage. A PSR of 80 dB means that a change of 100 mV on the supply, not an uncommon value, will produce a 10 V input offset change. Consequently, care should be taken in choosing a power unit that has a low output noise level, good line and load regulation, and good temperature stability. -15- AMP01 +15V COMPLIANCE, TYPICALLY 610V LINEARITY ~0.01% OUTPUT RESISTANCE AT 20mA ~5MV POWER BANDWIDTH (-3dB) ~60kHz INTO 500V LOAD 0.047mF 18 +IN ROUT TRIM 12 V+ 1 VIN 13 SENSE 7 9 RG RG 2kV AMP01 2 R2 200V R1 100V 6IOUT 8 RG 10 REFERENCE V- 11 RS 15 3 -IN RS IOUT = VIN 14 0.047mF G 3 R1 ) R1 = 100V FOR IOUT = 620mA VIN = 6100mV FOR 620mA FULL SCALE -15V RS 2kV 20 3 RS (R Figure 36. High Compliance Bipolar Current Source with 13-Bit Linearity ALL RESISTORS 1% METAL FILM +15V TO +30V RS 2kV +IN 18 0.047mF 14 RS 15 RS R3 100V 12 V+ 1 13 RG RG 2.75kV 7 9 AMP01 2 8 RG 10 R2 200V ROUT TRIM REF-02 R5 2.21kV 6 V- 11 -IN 3 R4 100V 2 4 R6 500V ZERO TRIM R1 100V IOUT 4mA TO 20mA 0V 0.047mF -5V COMPLIANCE OF IOUT, +20V WITH +30V SUPPLY (OUTPUT w.r.t. 0V) DIFFERENTIAL INPUT OF 100mV FOR 16mA SPAN OUTPUT RESISTANCE ~5MV AT IOUT = 20mA LINEARITY 0.01% OF SPAN Figure 37. 13-Bit Linear 4-20 mA Transmitter Constructed by Adding a Voltage Reference. Thermocouple Signals Can Be Accepted Without Preamplification. -16- REV. D AMP01 +15V + 10mF 0.047mF 10kV 14 RS 18 +IN 1 2N4921 15 RS 12 V+ 0.047mF 13 SENSE 7 9 RG AMP01 RG 2 VOUT (610V INTO 10V) 8 REFERENCE RG 10 V- 11 3 -IN 100V 2N4918 GND 0.047mF VOLTAGE GAIN, G = 100 POWER BANDWIDTH (-3dB), 60kHz QUIESCENT CURRENT, 4mA LINEARITY~0.01% @ FULL OUTPUT INTO 10V + -15V Figure 38. Adding Two Transistors Increases Output Current to 1 A Without Affecting the Quiescent Current of 4 mA. Power Bandwidth is 60 kHz. Q1, Q2...........J110 Q3, Q4, Q5....J107 IC1 ...............CMP-04 IC2 ...............OP15GZ RS 10kV 18 +IN 1 -IN 200kV 20kV 2kV 0.047mF 14 RS RG 15 RS 196V 9 AMP01 V- Q2 47kV VOOS NULL Q1 +15V 2 3 3 IC2 4 7 Q5 Q3 47kV RG VIOS NULL 1 14 10 11 27kV +15V 2.7kV + + + REFERENCE 5 GND 4 16 13 0.047mF -15V 3 4 6 8 10 OUT 8 17 2 2 SENSE 13 Q4 47kV 7 12 V+ 47kV 6 +15V 100kV + 100kV IC1 LINEARITY~0.005%, G = 10 AND 100 ~0.02%, G = 1 AND 1000 12 GAIN ACCURACY, UNTRIMMED~0.5% 5 7 G1 G10 9 G100 11 -15V G1000 SETTLING TIME TO 0.01%, ALL GAINS, LESS THAN 75ms GAIN SWITCHING TIME, LESS THAN 100ms TTL COMPATIBLE INPUTS Figure 39. The AMP01 Makes an Excellent Programmable-Gain Instrumentation Amplifier. Combined Gain-Switching and Settling Time to 13 Bits Falls Below 100 s. Linearity Is Better than 12 Bits over a Gain Range 1 to 1000. REV. D -17- AMP01 RS 10kV +15V 0.047mF 18 +IN *5kV RS 15 RS 1 *MATCHED TO 0.1% 0V 14 12 V+ 13 7 *5kV 9 AMP01 RG 2 1.5kV SENSE RG 2 470pF 8 RG 6 OP37 3 REFERENCE 10 V- 11 7 4 3 -IN 0.047mF 0V VOLTAGE GAIN, G = 20 3 RS ( RG -15V ) RL MAXIMUM OUTPUT, 20V p-p INTO 600V T.H.D. 0.01% @ 1kHz, 20V p-p INTO 600V, G = 10 + OUTPUT DIFFERENTIAL COMMON-MODE OUTPUT REFERENCE (65V MAX) Figure 40. A Differential Input Instrumentation Amplifier with Differential Output Replaces a Transformer in Many Applications. The Output will Drive a 600 Load at Low Distortion, (0.01%). +15V POWER BANDWIDTH (-3dB)~150kHz 8 18 REF 0.047mF 1 12 V+ 13 RG R1 390V 9 AMP01 2 10mF 7 SENSE VIN RG RS 3 RS 14 V- 11 VOUT 10 R2 4.95kV NC CL RL 15 0.047mF + NC 10mF -15V R3 50V CLOSED-LOOP VOLTAGE GAIN MUST BE GREATER THAN 50 FOR STABLE OPERATION NC = NO CONNECT TOTAL HARMONIC DISTORTION~0.006% @1kHz, 20V p-p INTO 500V // 1000pF + ( VOLTAGE GAIN, G = 1 + R2 R3 ) Figure 41. Configuring the AMP01 as a Noninverting Operational Amplifier Provides Exceptional Performance. The Output Handles Low Load Impedances at Very Low Distortion, 0.006%. -18- REV. D AMP01 NC R1 14 RS 3 VIN NC 15 RS 0.01mF 2 8 REF 9 AMP01 1 R3 7 SENSE RG R4 4.7kV R2 220kV RG V- 12 18 V- 11 10 20V p-p INTO 500V // 1000pF. TOTAL HARMONIC DISTORTION: <0.005% @ 1kHz, VOUT = 20V p-p G = 1 TO 1000 13 R1 = VOUT R2 GAIN (G) + 0.047mF 10mF R3 = R1 // R2 + R4 = 1.5kV @ G = 1 1.2kV @ G = 10 120V @ G = 100 AND 1000 +15V 10mF 0.047mF -15V Figure 42. The Inverting Operational Amplifier Configuration has Excellent Linearity over the Gain Range 1 to 1000, Typically 0.005%. Offset Voltage Drift at Unity Gain Is Improved over the Drift in the Instrumentation Amplifier Configuration. +15V R1 4.7kV 8 680pF 18 REF VIN + 7 SENSE 0.01mF 1 R3 330V 12 V+ POWER BANDWIDTH (-3dB)~60kHz TOTAL HARMONIC DISTORTION~0.001% @1kHz, 20V p-p INTO 500V // 1000pF NC = NO CONNECT 13 RG RG 3kV 9 AMP01 2 10mF 0.047mF RG RS 3 RS 14 V- 11 VOUT CL 10 RL R2 4.7kV 15 0.047mF NC + 10mF -15V NC Figure 43. Stability with Large Capacitive Loads Combined with High Output Current Capability make the AMP01 Ideal for Line Driving Applications. Offset Voltage Drift Approaches the TCVIOS Limit, (0.3 V/ C). REV. D -19- AMP01 V+ V- 16.2kV 1mF 13 18 12 1 R G RG 200kV 20kV 2kV 2 11 10 200V 1.82kV 7 G1 2 3 3 8 15 16.2kV 5 RS 14 1mF en (G = 1000) = 6 eOUT G1000 1000 3 G V- 1mF + 1/2 OP215 10kV en (G = 1, 10, 100) = V+ 1.62MV RS RG OUTPUT 4 + 8 8 RG G1000 1 1/2 OP215 9 AMP01 G100 G10 - 7 - 9.09kV G1,10,100 eOUT 100 3 G 100V 1kV Figure 44. Noise Test Circuit (0.1 Hz to 10 Hz) 200V 10T VIN 20V p-p 1.91kV 0.1% VOUT 2 3 HSCH-1001 10kV 0.1% G10 G1 14 RS 3 G100 1.1kV 0.1% G1000 102V 0.1% 2kV 0.1% 10kV 0.1% 1 R G RG 10V 0.1% 200kV 0.1% G1 20kV 0.1% G10 2kV 0.1% 15 RS 200V 0.1% G100 7 9 AMP01 8 8 RG G1000 10 2 RG 11 12 18 13 0.047mF 0.047mF V+ V- Figure 45. Settling-Time Test Circuit -20- REV. D AMP01 +15V RS 10kV 0.047mF 11 16 +IN 1 15 18 RS 1 15 RG 200V ANALOG SWITCH SENSE 7 9 13 AMP01 2 6 5 8 14 VOUT 7.5kV 8 4 S 12 V+ RG DG390 10 (20 R3 R ) G RS 3 9 -IN VOLTAGE GAIN, G = 14 RG 10 V- REFERENCE 11 15kV 3 13 61mA 13 14 4 DAC-08 1, 2 16 15 3 0.047mF R1 100V 0.01mF 7.5kV TTL INPUT "OFFSET" 0V TTL INPUT "ZERO" -15V Figure 46. Instrumentation Amplifier with Autozero +18V 10kV 0.047mF 14 18 1 10kV 2 3 RS 15 12 RS RG SENSE 13 7 9 AMP01 VOUT 8 RG 10 11 0.047mF -18V Figure 47. Burn-In Circuit REV. D -21- AMP01 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 18-Lead Cerdip (Q-18) 0.005 (0.13) MIN 18 C3103b-0-12/99 0.098 (2.49) MAX 10 0.310 (7.87) 0.220 (5.59) 1 9 0.320 (8.13) 0.290 (7.37) PIN 1 0.060 (1.52) 0.015 (0.38) 0.960 (24.38) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.78) SEATING 0.030 (0.76) PLANE 0.015 (0.38) 0.008 (0.20) 158 08 28-Terminal Ceramic Leadless Chip Carrier (E-28A) 0.075 (1.91) REF 0.100 (2.54) 0.064 (1.63) 0.458 (11.63) 0.442 (11.23) 0.458 SQ (11.63) MAX SQ 0.095 (2.41) 0.075 (1.90) 0.300 (7.62) BSC 0.150 (3.51) BSC 26 25 0.015 (0.38) MIN 4 28 5 1 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.088 (2.24) 0.054 (1.37) BOTTOM VIEW 19 18 0.055 (1.40) 0.045 (1.14) 12 11 0.200 (5.08) BSC 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC 458 TYP 20-Lead SOIC (R-20) 1 10 PIN 1 0.0118 (0.30) 0.0040 (0.10) 0.1043 (2.65) 0.0926 (2.35) PRINTED IN U.S.A. 11 0.4193 (10.65) 0.3937 (10.00) 20 0.2992 (7.60) 0.2914 (7.40) 0.5118 (13.00) 0.4961 (12.60) 0.0291 (0.74) 3 458 0.0098 (0.25) 88 0.0500 (1.27) 0.0500 0.0192 (0.49) 08 0.0157 (0.40) (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE BSC 0.0091 (0.23) -22- REV. D