DS90LV028AHMX - National Semiconductor

DS90LV028AH

High Temperature 3V LVDS Dual Differential Line

Receiver

General Description

The DS90LV028AH is a dual CMOS differential line receiver

designed for applications requiring ultra low power dissipa-

tion, low noise and high data rates. The device is designed to

support data rates in excess of 400 Mbps (200 MHz) utilizing

Low Voltage Differential Signaling (LVDS) technology.

The DS90LV028AH accepts low voltage (350 mV typical)

differential input signals and translates them to 3V CMOS

output levels. The DS90LV028AH has a flow-through design

for easy PCB layout.

The DS90LV028AH and companion LVDS line driver

DS90LV027AH provide a new alternative to high power

PECL/ECL devices for high speed point-to-point interface

applications.

Features

n-40˚C to +125˚C operating temperature range

n>400 Mbps (200 MHz) switching rates

n50 ps differential skew (typical)

n0.1 ns channel-to-channel skew (typical)

n2.5 ns maximum propagation delay

n3.3V power supply design

nFlow-through pinout

nPower down high impedance on LVDS inputs

nLow Power design (18mW @3.3V static)

nLVDS inputs accept LVDS/CML/LVPECL signals

nConforms to ANSI/TIA/EIA-644 Standard

nAvailable in SOIC package

Connection Diagram

SOIC

20162901

Order Number DS90LV028AHM

See NS Package Number M08A

Functional Diagram

20162902

Truth Table

INPUTS OUTPUT

+]−[R

−] R

OUT

≥0.1V H

≤−0.1V L

September 2005

DS90LV028AH High Temperature 3V LVDS Dual Differential Line Receiver

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

) −0.3V to +4V

Input Voltage (R

+, R

−) −0.3V to +3.9V

Output Voltage (R

OUT

) −0.3V to V

+ 0.3V

Maximum Package Power Dissipation @+25˚C

M Package 1025 mW

Derate M Package 8.2 mW/˚C above +25˚C

Storage Temperature Range −65˚C to +150˚C

Lead Temperature Range Soldering

(4 sec.) +260˚C

Maximum Junction Temperature +150˚C

ESD Rating (Note 4)

(HBM 1.5 kΩ, 100 pF) ≥7kV

(EIAJ 0Ω, 200 pF) ≥500 V

Recommended Operating

Conditions

Min Typ Max Units

Supply Voltage (V

) +3.0 +3.3 +3.6 V

Receiver Input Voltage GND 3.0 V

Operating Free Air

Temperature (T

) −40 25 +125 ˚C

Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3)

Symbol Parameter Conditions Pin Min Typ Max Units

Differential Input High Threshold V

= +1.2V, 0V, 3V (Note 12) R

+, +100 mV

Differential Input Low Threshold R

− −100 mV

Input Current V

= +2.8V V

= 3.6V or 0V −10 ±1 +10 µA

= 0V −10 ±1 +10 µA

= +3.6V V

= 0V -20 +20 µA

Output High Voltage I

= −0.4 mA, V

= +200 mV R

OUT

2.7 3.1 V

= −0.4 mA, Inputs terminated 2.7 3.1 V

= −0.4 mA, Inputs shorted 2.7 3.1 V

Output Low Voltage I

= 2 mA, V

= −200 mV 0.3 0.5 V

Output Short Circuit Current V

OUT

= 0V (Note 5) −15 −50 −100 mA

Input Clamp Voltage I

= −18 mA −1.5 −0.8 V

No Load Supply Current Inputs Open V

5.4 9 mA

Switching Characteristics

= +3.3V ±10%, T

= −40˚C to +125˚C (Notes 6, 7)

Symbol Parameter Conditions Min Typ Max Units

PHLD

Differential Propagation Delay High to Low C

= 15 pF 1.0 1.6 2.5 ns

PLHD

Differential Propagation Delay Low to High V

= 200 mV 1.0 1.7 2.5 ns

SKD1

Differential Pulse Skew |t

PHLD

−t

PLHD

| (Note 8) (Figure 1 and Figure 2) 0 50 650 ps

SKD2

Differential Channel-to-Channel Skew-same device (Note 9) 0 0.1 0.5 ns

SKD3

Differential Part to Part Skew (Note 10) 0 1.0 ns

SKD4

Differential Part to Part Skew (Note 11) 0 1.5 ns

TLH

Rise Time 325 800 ps

THL

Fall Time 225 800 ps

MAX

Maximum Operating Frequency (Note 13) 200 250 MHz

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise

specified (such as VID).

Note 3: All typicals are given for: VCC = +3.3V and TA= +25˚C.

Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) ≥7kV

EIAJ (0Ω, 200 pF) ≥500V

Note 5: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not

exceed maximum junction temperature specification.

Note 6: CLincludes probe and jig capacitance.

Note 7: Generator waveform for all tests unless otherwise specified:f=1MHz, ZO=50Ω,t

rand tf(0% to 100%) ≤3 ns for RIN.

Note 8: tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.

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Note 9: tSKD2 is the differential channel-to-channel skew of any event on the same device. This specification applies to devices having multiple receivers within the

integrated circuit.

Note 10: tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC

and within 5˚C of each other within the operating temperature range.

Note 11: tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the

recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.

Note 12: VCC is always higher than RIN+ and RIN− voltage. RIN+ and RIN− are allowed to have voltage range −0.05V to +3.05V. VID is not allowed to be greater

than 100 mV when VCM =0Vor3V.

Note 13: fMAX generator input conditions: tr=t

f<1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40% duty cycle,

VOL (max 0.4V), VOH (min 2.7V), load = 15 pF (stray plus probes).

Parameter Measurement Information

Typical Application

Applications Information

General application guidelines and hints for LVDS drivers

and receivers may be found in the following application

notes: LVDS Owner’s Manual (lit #550062-003), AN-808,

AN-977, AN-971, AN-916, AN-805, AN-903.

LVDS drivers and receivers are intended to be primarily used

in an uncomplicated point-to-point configuration as is shown

in Figure 3. This configuration provides a clean signaling

environment for the fast edge rates of the drivers. The re-

ceiver is connected to the driver through a balanced media

which may be a standard twisted pair cable, a parallel pair

cable, or simply PCB traces. Typically the characteristic

impedance of the media is in the range of 100Ω. A termina-

tion resistor of 100Ωshould be selected to match the media,

and is located as close to the receiver input pins as possible.

The termination resistor converts the driver output (current

mode) into a voltage that is detected by the receiver. Other

configurations are possible such as a multi-receiver configu-

ration, but the effects of a mid-stream connector(s), cable

20162903

FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit

20162904

FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms

Balanced System

20162905

FIGURE 3. Point-to-Point Application

DS90LV028AH

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Applications Information (Continued)

stub(s), and other impedance discontinuities as well as

ground shifting, noise margin limits, and total termination

loading must be taken into account.

The DS90LV028AH differential line receiver is capable of

detecting signals as low as 100 mV, over a ±1V common-

mode range centered around +1.2V. This is related to the

driver offset voltage which is typically +1.2V. The driven

signal is centered around this voltage and may shift ±1V

around this center point. The ±1V shifting may be the result

of a ground potential difference between the driver’s ground

reference and the receiver’s ground reference, the common-

mode effects of coupled noise, or a combination of the two.

The AC parameters of both receiver input pins are optimized

for a recommended operating input voltage range of 0V to

+2.4V (measured from each pin to ground). The device will

operate for receiver input voltages up to V

, but exceeding

will turn on the ESD protection circuitry which will clamp

the bus voltages.

POWER DECOUPLING RECOMMENDATIONS

Bypass capacitors must be used on power pins. Use high

frequency ceramic (surface mount is recommended) 0.1µF

and 0.01µF capacitors in parallel at the power supply pin

with the smallest value capacitor closest to the device supply

pin. Additional scattered capacitors over the printed circuit

board will improve decoupling. Multiple vias should be used

to connect the decoupling capacitors to the power planes. A

10µF (35V) or greater solid tantalum capacitor should be

connected at the power entry point on the printed circuit

board between the supply and ground.

PC BOARD CONSIDERATIONS

Use at least 4 PCB board layers (top to bottom): LVDS

signals, ground, power, TTL signals.

Isolate TTL signals from LVDS signals, otherwise the TTL

signals may couple onto the LVDS lines. It is best to put TTL

and LVDS signals on different layers which are isolated by a

power/ground plane(s).

Keep drivers and receivers as close to the (LVDS port side)

connectors as possible.

DIFFERENTIAL TRACES

Use controlled impedance traces which match the differen-

tial impedance of your transmission medium (ie. cable) and

termination resistor. Run the differential pair trace lines as

close together as possible as soon as they leave the IC

(stubs should be <10mm long). This will help eliminate

reflections and ensure noise is coupled as common-mode.

In fact, we have seen that differential signals which are 1mm

apart radiate far less noise than traces 3mm apart since

magnetic field cancellation is much better with the closer

traces. In addition, noise induced on the differential lines is

much more likely to appear as common-mode which is re-

jected by the receiver.

Match electrical lengths between traces to reduce skew.

Skew between the signals of a pair means a phase differ-

ence between signals which destroys the magnetic field

cancellation benefits of differential signals and EMI will re-

sult! (Note that the velocity of propagation,v=c/E

where c

(the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not

rely solely on the autoroute function for differential traces.

Carefully review dimensions to match differential impedance

and provide isolation for the differential lines. Minimize the

number of vias and other discontinuities on the line.

Avoid 90˚ turns (these cause impedance discontinuities).

Use arcs or 45˚ bevels.

Within a pair of traces, the distance between the two traces

should be minimized to maintain common-mode rejection of

the receivers. On the printed circuit board, this distance

should remain constant to avoid discontinuities in differential

impedance. Minor violations at connection points are allow-

able.

TERMINATION

Use a termination resistor which best matches the differen-

tial impedance or your transmission line. The resistor should

be between 90Ωand 130Ω. Remember that the current

mode outputs need the termination resistor to generate the

differential voltage. LVDS will not work correctly without re-

sistor termination. Typically, connecting a single resistor

across the pair at the receiver end will suffice.

Surface mount 1% - 2% resistors are the best. PCB stubs,

component lead, and the distance from the termination to the

receiver inputs should be minimized. The distance between

the termination resistor and the receiver should be <10mm

(12mm MAX).

INPUT FAILSAFE BIASING

External pull up and pull down resistors may be used to

provide enough of an offset to enable an input failsafe under

open-circuit conditions. This configuration ties the positive

LVDS input pin to VDD thru a pull up resistor and the

negative LVDS input pin is tied to GND by a pull down

resistor. The pull up and pull down resistors should be in the

5kΩto 15kΩrange to minimize loading and waveform dis-

tortion to the driver. The common-mode bias point ideally

should be set to approximately 1.2V (less than 1.75V) to be

compatible with the internal circuitry. Please refer to applica-

tion note AN-1194, “Failsafe Biasing of LVDS Interfaces” for

more information.

PROBING LVDS TRANSMISSION LINES

Always use high impedance (>100kΩ), low capacitance

(<2 pF) scope probes with a wide bandwidth (1 GHz)

scope. Improper probing will give deceiving results.

CABLES AND CONNECTORS, GENERAL COMMENTS

When choosing cable and connectors for LVDS it is impor-

tant to remember:

Use controlled impedance media. The cables and connec-

tors you use should have a matched differential impedance

of about 100Ω. They should not introduce major impedance

discontinuities.

Balanced cables (e.g. twisted pair) are usually better than

unbalanced cables (ribbon cable, simple coax) for noise

reduction and signal quality. Balanced cables tend to gener-

ate less EMI due to field canceling effects and also tend to

pick up electromagnetic radiation a common-mode (not dif-

ferential mode) noise which is rejected by the receiver.

For cable distances <0.5M, most cables can be made to

work effectively. For distances 0.5M ≤d≤10M, CAT 3

(category 3) twisted pair cable works well, is readily available

and relatively inexpensive.

DS90LV028AH

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Pin Descriptions

Pin No. Name Description

1, 4 R

- Inverting receiver input pin

2, 3 R

+ Non-inverting receiver input pin

6, 7 R

OUT

Receiver output pin

Power supply pin, +3.3V ±0.3V

5 GND Ground pin

Ordering Information

Operating Package Type/ Order Number

Temperature Number

−40˚C to +125˚C SOP/M08A DS90LV028AHM

Typical Performance Curves

Output High Voltage vs

Power Supply Voltage

Output Low Voltage vs

Power Supply Voltage

20162907 20162908

Output Short Circuit Current vs

Power Supply Voltage

Differential Transition Voltage vs

Power Supply Voltage

20162909 20162910

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Typical Performance Curves (Continued)

Power Supply Current

vs Frequency

Differential Propagation Delay vs

Power Supply Voltage

20162911

20162913

Differential Propagation Delay vs

Differential Input Voltage

Differential Propagation Delay vs

Common-Mode Voltage

20162917 20162918

Transition Time vs

Power Supply Voltage

Differential Skew vs

Power Supply Voltage

20162919 20162915

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Typical Performance Curves (Continued)

Differential Propagation Delay

vs Load

Differential Propagation Delay

vs Load

20162921 20162923

Transition Time

vs Load

Transition Time

vs Load

20162922 20162924

DS90LV028AH

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Physical Dimensions inches (millimeters) unless otherwise noted

8-Lead (0.150" Wide) Molded Small Outline Package, JEDEC

Order Number DS90LV028AHM

NS Package Number M08A

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

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device or system whose failure to perform can be reasonably

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DS90LV028AH High Temperature 3V LVDS Dual Differential Line Receiver