HEWLETT* PACKARD LG HCMOS Compatible, High CMR, 10 MBd Optocouplers Technical Data Features * HCMOS/LSTTL/TTL Performance Compatible * 1000 V/us Minimum Common Mode Rejection (CMR) at Voy = 50 V (HCPL- 261A Family) and 15 kV/Us Minimum CMR at Voy = 1000 V CHCPL-261N Family) * High Speed: 10 MBd Typical * AC and DC Performance Specified over Industrial Temperature Range -40C to +85C * Available in 8 Pin DIP, SOIC-8 Packages * Safety Approval UL Recognized per UL1577 2500 V rms for 1 minute and 5000 Vrms for 1 minute (Option 020) CSA Approved VDE 0884 Approved with ViorM = 6380 V peak for HCPL-261A/261N Option 060 Applications Low Input Current (3.0 mA) HCMOS Compatible Version of 6N137 Optocoupler * Isolated Line Receiver * Simplex/Multiplex Data Transmission Computer-Peripheral Interface * Digital Isolation for A/D, D/A Conversion Switching Power Supplies Instrumentation Input/Output Isolation Ground Loop Elimination Pulse Transformer Replacement Description The HCPL-261A family of optically coupled gates shown on this data sheet provide all the benefits of the industry standard 6N137 family with the added benefit of HCMOS Functional Diagram HCPL-261A/261N HCPL-061A/061N ne G] 8] Voc ANODE ak 7] Ve catHope [3 | ID Vo ne [4] 5 | GND 4 SHIELD TRUTH TABLE (POSITIVE LOGIC) LED | ENABLE | OUTPUT ON H L OFF H ON L OFF L ON NC OFF | _NC xl[rjxjzj=z CATHODE 4 al r yz Vor CATHODE 2 [3 | HCPL-261A HCPL-263A HCPL-261N HCPL-263N HCPL-061A HCPL-063A HCPL-061N HCPL-063N compatible input current. This allows direct interface to all common circuit topologies without additional LED buffer or drive components. The AlGaAs LED used allows lower drive currents and reduces degradation by using the latest LED technology. On the single channel parts, an enable output allows the detector to be strobed. The output of the detector IC is an open collector schottky- clamped transistor. The internal shield provides a minimum common mode transient immunity of 1000 V/us for the HCPL-261A family and 15000 V/us for the HCPL-261N family. HCPL-263A/263N HCPL-063A/063N Ta] Voc ANODE ; [1 +2] Vo2 -} | GND ANODE 2 [4 SHIELD TRUTH TABLE {POSITIVE LOGIC) LED | OUTPUT ON L OFF H The connection of a 0.1 pF bypass capacitor between pins 5 and 8 is required. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 1-166 5965-3593ESelection Guide Widebody i Minimum CMR Input 8-Pin DIP (300 Mil) Small-Outline SO-8 (400 Mil) Hermetic ee On- Single Dual Single Dual Single Single and Fa dv/dt Vom | Current | Output | Channel Channel | Channel Channel Channel | Dual Channel 8 (Vilis) Ww) (mA) Enable Package Package Package Package Package Packages h NA NA 5 YES 6N 13718 HCPL-0600(1! HCNW1 37111 io NO HCPL-263011! HCPL-0630!!1 5,000 50 YES HCPL-260 114 HCPL-0601!!1 HCNW2601!11 NO HCPL-263 11) HCPL-063 1!!! 10,000 1.000 YES HCPL-261 1U1 HCPL-0611148 HCNW261 14) NO HCPL-466 101 HCPL-0661!"1 1,000 50 YES HCPL-26021)1 3,500 300 YES HCPL-2612U1 1,000 50 3 YES HCPL-261A HCPL-0614 NO HCPL-2634 HCPL-063A 1.0002! 1,000 YES HCPL-261N HCPL-061N NO HCPL-263N HCPL-063N 1,000 50 12.5 [3] HCPL-193X01 HCPL-56XX!!1 HCPL-66XX!) Notes: 1. Technical data are on separate HP publications. 2. 15 kV/us with Voy = 1 kV can be achieved using HP application circuit. 3. Enable is available for single channel products only, except for HCPL-193X devices. Ordering Information Specify Part Number followed by Option Number (if desired). Example: HCPL-26 1LA#XXX tH 020 = 5000 V rms/1 minute UL Rating Option* t+ 060 = VDE 0884 Viorgy = 630 Vpeak Option** - 300 = Gull Wing Surface Mount Option*** 500 = Tape and Reel Packaging Option Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor for information. *For HCPL-261A4/261N/263A4/263N (8-pin DIP products) only. **For HCPL-2614/261N only. Combination of Option 020 and Option 060 is not available. HCPL-263A/263N HCPL-063A/063N lec y 89 y, 8 cc lor Vor ***Gull wing surface mount option applies to through hole parts only. Schematic HCPL-261A/261N 1 py HCPL-061A/061N Ip 1 ~ Ice $$ *0 y, Vv | 2+ 8 ec Fl ~ alo Yo - | \ 2 | | SHIELD Ve 4 3 ipg__+ | 2 @np 3 SHIELD 4 5 Veo ' lelo7z ~ VE { USE OF A 0.1 pF BYPASS CAPACITOR CONNECTED BETWEEN PINS 5 AND & IS RECOMMENDED (SEE NOTE 18). SHIELD =i 02 Voz -3 GND 1-167HCPL-261A/261N/263A/263N Outline Drawing Pin Location (for reference only) __ 240 fsa} ~ (fa (pe) Gl _- OPTION CODE* a eae TYPE NUMBER _| i 0.20 (0.008) - ~~ | .10 10.240 0.33 (0.013) HP XXXXZ L _~ DATE CODE | 8:10 (0.240) 80 (0.260} yrww 7.36 (0.290) 7.88 (0.310) i 5 TYP. = _+ Dla l3s) == pwone (TTI + a oad 1.78 (0.070) MAX. m -<~1,19 (0.047) MAX. OT 4.70 (0.185) MAX. wu _ __ Te 4.81 (0.020) MIN. 2.92 (0.115) MIN. yo 0.76 (0.030) eh + 0.65 (0.025) MAX. 1.40 (0.056) ~* 2 ~ .28 (0.080) 2.80 (0.110) Figure 1. 8-Pin Dual In-Line Package Device Outline Drawing. 9.65 0.25 (0.380 * 0.010) ba a DIMENSIONS IN MILLIMETERS AND (INCHES). * MARKING CODE LETTER FOR OPTION NUMBERS. L" = OPTION 020 V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED. 1.02 (0.040) ~~ 1.19 (0.047) OOo Qin T 4.83 (0.190)"*?- 6,360 + 0.25 il (0.250 + 0.010) 9.65 + 0.25 (0.380 + 0.010) iy ls pe Le Ge OCIf3 O74 ~ _ 0,38 (0.015) 1.19 (0.08) 0.64 (0.025) 1,78(0.07) woes _ _ _ 9.6520.26 __ ~~ 1.780 (0.380 = 0.010) 119 (0.070) 0.047) MAX. we 7.6240.25 yp MAX. (0.300 0.010) as 9,20 (0.008) . 933(0.013 (0.165) "4X: (0.013) - Vf Ld ! 1.080 20.320 4 ea 0.635 # 0.25 a (0.043 + 0.013) ~ = 10.025 = 0.010) 0.635 + 0.130 0-12" NOM 7 2.540 (0.025 + 0.005) : (0.100) BSC DIMENSIONS tN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 XX.XXX = 0.005 LEAD COPLANARITY MAXIMUM: 0.102 (0.004) Figure 2. Gull Wing Surface Mount Option #300, 1-168HCPL-061A/061N/063A/063N Outline Drawing 5.842 0.203 (0.236 + 0.008) 3.937 + 0.127 (0.155 = 0.005 TYPE NUMBER {LAST 3 DIGITS) oy DATE CODE 0.8t + 0.076 ONE so hes 2. Ke ete 4.270 (0.016 + 0.003) (0.050) 885 . + 0.432 5.0802 0.005, 45 X (0.200 2 0.005) (0.017) 3.175 20.127 | 0.228 0.025 0.125 + 0.005 ~ eee ( * ) 4520 [| (0.009 + 0.001) (0.060) J t P 7 0.152 + 0.051 (0.006 + 0.002) DIMENSIONS IN MILLIMETERS AND (INCHES), ~ -gy9)MIN. LEAD COPLANARITY = 0.10 mm (0.004 INCHES). Figure 3. 8-Pin Small Outline Package Device Drawing. Solder Reflow Temperature Profile GICPL-06XX and Gull Wing Surface Mount Option 300 Parts) TEMPERATURE - C 260 240 220 200 180 160 140 120 100 80 60 40 20 0 TIME MINUTES Note: Use of Nonchlorine Activated Fluxes is Recommended. Regulatory Information CSA The HCPL-2614 and HCPL-261N Approved under CSA Component families have been approved by Acceptance Notice #5, File CA the following organizations: 88324. UL VDE Recognized under UL 1577, Approved according to VDE Component Recognition 1884/06.92. (HCPL-261A/261N Program, File E55361. Option 060 only) OL MEOlOLOl maak) 1-169Insulation and Safety Related Specifications 8-Pin DIP (300 Mib | SO-8 Parameter Symbol Value Value | Units Conditions Minimum External Air L(101) 7.1 4.9 mm | Measured from input terminals to Gap (External output terminals, shortest distance Clearance) through air. Minimum External L(102) TA 4.8 mm | Measured from input terminals to Tracking (External output terminals, shortest distance Creepage) path along body. Minimum Internal Plastic 0.08 0.08 mm | Through insulation distance, conductor Gap (Internal Clearance) to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Tracking Resistance CTI 200 200 | Volts | DIN IEC 112/ VDE 0303 Part 1 (Comparative Tracking Index) Isolation Group Ia Ila Material Group (DIN VDE 0110, 1/89, Table 1) Option 300 surface mount classification is Class A in accordance with CECC 00802. VDE 0884 Insulation Related Characteristics (HCPL-261A/261N Option 060 ONLY) Description Symbol Characteristic | Units Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage < 300 V rms LIV for rated mains voltage < 450 V rms I-III Climatic Classification 55/85/21 Pollution Degree (DIN VDE 0110/1.89) 2 Maximum Working Insulation Voltage Viorm 630 V peak Input to Output Test Voltage, Method b* Viorm X 1.875 = Vpp, 100% Production Test with t,, = 1 sec, Vpr 1181 V peak Partial Discharge < 5 pC Input to Output Test Voltage, Method a* Viorm X 1.5 = Vpp, Type and sample test, t,, = 60 sec, PR 945 V peak Partial Discharge < 5 pC Highest Allowable Overvoltage* (Transient Overvoltage, t,,; = 10 sec) Viotm 6000 V peak Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure 18, Thermal Derating curve.) Case Temperature Ts 175 i @ Input Current Is input 230 mA Output Power Ps output 600 mW Insulation Resistance at Ts, Vig = 500 V Ry > 109 Q *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. 4-170Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature Ts -55 125 C Operating Temperature Ta -40 +85 C Average Input Current Tecave) 10 mA 1 Reverse Input Voltage Ve 3 Volts Supply Voltage Vec -0.5 7 Volts 2 Enable Input Voltage Ve -0.5 5.5 Volts Output Collector Current (Each Channel) Io 50 mA Output Power Dissipation (Each Channel) Po 60 mW 3 Output Voltage (Each channel) Vo -0.5 7 Volts Lead Solder Temperature 260C for 10s, 1.6 mm Below Seating Plane (Through Hole Parts Only) Solder Reflow Temperature Profile See Package Outline Drawings section (Surface Mount Parts Only) Recommended Operating Conditions Parameter Symbol Min Max. Units Input Voltage, Low Level Ve -3 0.8 Vv Input Current, High Level Irw 3.0 10 mA Power Supply Voltage Vec 4.5 5.5 Volts High Level Enable Voltage Ven 2.0 Vec Volts Low Level Enable Voltage Ve. 0 0.8 Volts Fan Qut (at Rp = 1 kQ) N 5 TTL Loads Output Pull-up Resistor R, 330 4k Q Operating Temperature Ts -40 85 C 1-171 OPTOCOUPLERSElectrical Specifications Over recommended operating temperature (T, = -40C to +85C) unless otherwise specified. Parameter Symbol | Min. | Typ.*| Max. | Units Test Conditions Fig. | Note High Level Output low 3.1 100 WA | Vec = 5.5 V, Vo = 5.5 V, 4 18 Current Vr = 0.8 V, Vp = 2.0V Low Level Output Voi 0.4 0.6 Vis Voc = 5.5 V, In, = 138 mA 5,8 | 4,18 Voltage (sinking), I; = 3.0 mA, Ve = 2.0V High Level Supply locu 7 10 mA | Ve = 0.5 V** Veo = 5.5V 4 Current 9 15 Dual Channel | Ir = 0 mA Products*** Low Level Supply Ice 8 13 mA | Ve =0.5 V** Veco = 5.5 V Current 12 21 Dual Channel | 1p = 3.0mA Products*** High Level Enable len -0.6 -1.6 mA |Vec = 5.5 V, Ve = 2.0V Current** Low Level Enable Tet -0.9 -1.6 mA |Voc = 5.5 V, Ve =0.5V Current** . Input Forward Ve 1.0 1.3 1.6 Vo {[lp=4mA 6 4 Voltage Temperature Co- AVp/AT, -1.25 mvV/C |Ip = 4 mA 4 efficient of Forward Voltage Input Reverse BVR 3 5 Vv Ip = 100 pA 4 Breakdown Voltage Input Capacitance Cw 60 pF |f = 1MHz,V>=0V *All typical values at T, = 25C, Voc = 5 V **Single Channel Products only (HCPL-26 14/26 1N/061A/061N) ***Duyal Channel Products only (HCPL-263A/263N/0634/063N) 1-172Switching Specifications Over recommended operating temperature (Ty = -40C to +85C) unless otherwise specified OPTOCOUPLERS Parameter Symbol | Min.| Typ.* | Max. | Units Test Conditions Fig. | Note Input Current Threshold Ira 1.5 3.0 mA | Voc = 5.5V,Vo =0.6V,| 7,10] 18 High to Low Ip >13 mA (Sinking) Propagation Delay teu 52 100 ns |Ip=3.5mA 9,11,} 4,9, Time to High Output Veco = 5.0 V, iz 18 Level Ve = Open, Propagation Delay tpHL 53 | 100 | ns |CL= 15 pF, 9, 11,} 4, 10, Time to Low Output R, = 350 2 12 18 Level Pulse Width Distortion PWD 11 45 ns 9,13] 17, 18 teen - tpun| Propagation Delay Skew tes 60 ns 24 |11,18 Output Rise Time tr 42 ns 9,14] 4,18 Output Fall Time te 12 ns 9,14] 4,18 Propagation Delay trae 19 ns [Ip = 3.5 mA 15, 12 Time of Enable Vee = 5.0 V, 16 from Ver to Ver VeL =OV, Veu =3V, Propagation Delay tea 30 ns | Ci = 15 pF, 15, 12 Time of Enable Ry = 350 Q 16 from Vg, to Vex *All typical values at Ty = 25C, Ver = 5 V. Common Mode Transient Immunity Specifications, All values at T, = 25C Parameter Device Symbol | Min.| Typ.| Max.| Units Test Conditions Fig.| Note Output High HCPL-261A | |CMy| 1 5 kV/us | Vey = 50 V loc = 5.0 V, 17 | 4, 13, Level Common | HCPL-061A R, = 350Q9, 15, 18 Mode Transient | HCPL-263A fp = 0 mA, Immunity HCPL-063A Ty = 25C HCPL-261N 1 5 kV/us| Vom = 1006 Vj Yormny = 2 V HCPL-061N HCPL-263N 15 25 kV/us Using HP App 20 | 4, 13, HCPL-063N Circuit 15 Output Low HCPL-2614 | |CM,] 1 5 kV/us} Voy = 50V | Vee = 5.0 V, 17 | 4,14, Level Common | HCPL-O61A R, = 350 Q, 15, 18 Mode Transient | HCPL-263A Tp = 3.5 mA, Immunity HCPL-063A Vormax) = 0.8 V HCPL-261N 1 5 kV/us| Voy = 1000 V| Ta = 25C HCPL-061N HCPL-263N 15 25 kV/Us Using HP App 20 | 4, 14, HCPL-063N Circuit 15 1-173Package Characteristics All Typicals at T, = 25C Parameter Sym. Package* Min. ; Typ.| Max.| Units | Test Conditions | Fig. | Note Input-Output Viso 2500 Vrms | RH < 50%, 5,6 Momentary With- t=1 min, stand Voltage** OPTO207 | 5000 Ty = 25C 5,7 Input-Output Rio 10 Q Vico = 500 Vde 4,8 Resistance Input-Output Cro 0.6 pF f = 1 MHz, 4,8 Capacitance Ty = 25C Input-Input I, | Dual Channel 0.005 HA | RH < 45%, 19 Insulation t=5s, Leakage Current Vi = 500 V Resistance R,; | Dual Channel 10!! Q 19 (nput-Input) Capacitance C,, | Dual 8-pin DIP 0.03 pF f= 1 MHz 19 (Input-Input) Dual SO-8 0.25 *Ratings apply to all devices except otherwise noted in the Package column. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification or HP Application Note 1074 entitled Optocoupler Input-Output Endurance Voltage. +For 8-pin DIP package devices (HCPL-261A/26 1 N/2634/26;3N) only. Notes: 1. Peaking circuits may be used which produce transient input currents up to 30 mA, 50 ns maximum pulse width, provided the average current does not exceed [0 mA. . | minute maximum. Ww 3. Derate linearly above 80C free-air temperature at a rate of 2.7 mW/FC for the SOIC-8 package. 4. Each channel. 5. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together. 6. In accordance with ULI577. each optocoupler is proof tested by applying an insulation test voltage 2 3000 Vpys for | second (leakage detection current limit. Ij.,< 5 WA). This test is performed before the 100% production test for partial discharge (method b) shown in the VDE 0884 Insulation Characteristics Table. if applicable. . In accordance with ULL577, each optocoupler is proof tested by applying an insulation test voltage 2 6000 Vays for | second (leakage detection current limit, [, <5 yA). 1 1-174 ao 10. = _ be . Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. . The tp, propagation delay is measured from the 1.75 mA point on the falling edge of the input pulse to the J.5 V point on the rising edge of the output pulse. The tpi, propagation delay is measured from the 1.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the output pulse. . Propagation delay skew (tps) is equal to the worst case difference in tpyy and/or tpy, that will be seen between any two units under the same test conditions and operating temperature. . Single channel products only CHCPL- 2614/26 LN/06 LA/O6 EN). . Common mode transient immunity in a Logic High level is the maximum tolerable |dV,-yy/dt| of the common mode puise, Voy, to assure that the output will remain in a Logic High state (iLe., Vo > 2.0 V). 14. 16. ~ =] Common mode transient immunity in a Logic Low level is the maximum tolerable |dVoy/dt| of the common mode pulse, Voy. to assure that the output will remain in a Logic Low state (i.e., V) < 0.8 V). . For sinusoidal voltages (JdVoyq/dt | max = mfoy Vomep-p)- Bypassing of the power supply line is required with a 0.1 wF ceramic disc capacitor adjacent to each optocoup- ler as shown in Figure 19. Total lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm. . Pulse Width Distortion (PWD) is defined as the difference between tp_y and tpy. for any given device. . No external pull up is required for a high logic state on the enable input of a single channel product. If the V; pin is not used, tying Ve to V- will result in improved CMR performance. . Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel parts only.lon ~ HIGH LEVEL OUTPUT CURRENT pA 0 -60 -40 Ta TEMPERATURE - C -20 0 Figure 4. Typical High Level Output Current vs. Temperature. Vo - OUTPUT VOLTAGE - V 0 0.5 Ip - FORWARD INPUT CURRENT ~ mA 1.0 1.5 Figure 7. Typical Output Voltage vs. Forward Input Current. 20 40 60 80 100 80 100.0 - -mA OPTOCOUPLERS i - INPUT FORWARD CURRENT | 0 J a. -60 -40 -20 0 20 40 60 80 100 Ta TEMPERATURE C io, - LOW LEVEL OUTPUT CURRENT - mA V1 Ve - FORWARD VOLTAGE - V 1.2 1.3 1.4 1.5 Figure 5. Low Level Output Current vs. Temperature. HCPL-261A fig 5 Figure 6. Typical Diode Input Forward Current Characteristic. 7 06 w Veo = 5.5 V g } > Ve s2 5 Ip =3.0 mA 3 os}--- S | Ig=16mA : k St 2 ig = 12.8 mA pe 2 04+-~> = = | 2 al we > WwW = 03h = 5 at I zg 0.2 20 3 -60 -40 -20 0 20 40 60 80 100 Ta ~ TEMPERATURE C Figure 8. Typical Low Level Output Voltage vs. Temperature. HCPL-261A/261N asy putsecen. | 'F By Voc re Zo= 502 tet, =5ne ' LoipF o L 2 ! 47] 7 Bypass $ RL I INPUT ; aN OUTPUT Vo MONITORING O| 3 r 16 MONITORING NODE 1 opp (NODE < 1 Rus [4] i____}5] GND *C, IS APPROXIMATELY 45 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. - ig =3.5mA INPUT lp ip = 1.75 mA >t ~~ ~ tpi PHL PLH Vo OUTPUT Vo SV el be. tise fat ~~ Figure 9. Test Circuit for tpg, and tpyy.- 1-175< = 2.0 ' e 2 @ = 15 5 3 a 3 2 1.0 a wi c Zz 5 0.5 | a ' Vee =5V z Vo = 0.6 V I : 1 x Oo L + 60 -40 -20 0 20 40 60 80 100 Ta TEMPERATURE - *C Figure 10. Typical Input Threshold Current vs. Temperature. 60 ha 50 Voc =5V 40 {p=3.5 MA o S ! 4 30 = a 20 RL = 1kQ 10 : Ry, = 350 0 0 -60 -40 -20 0 20 40 60 80 100 Ta, TEMPERATURE C Figure 13. Typical Pulse Width Distortion vs. Temperature. 1-176 120 a 1 100 > s m a0} - a 3 2 eo} ~ - 8 < 49 TPHL | |! 3 Ry = 350.0, 1 KO. 4 kQ xc : ' 1 & 9 _TPLH |. ' . Ry, = 350k Veo=5V | - [p= 3.5 mA | Q -60 -40 -20 0 20 40 60 80 100 Ta - TEMPERATURE - C Figure 11. Typical Propagation Delay vs. Temperature. > Qo ty ty - RISE, FALL TIME - ns nN o Ay = 350 0.1 KO, 4 kO 0 ~60 40 -20 0 20 40 60 80 100 Ta, TEMPERATURE - C Figure 14. Typical Rise and Fall Time vs. Temperature. 120 TPLH a e 1 > 5 iy 80F- : coon : TPLH 3 Rp =1 ko 60 ' 6 TPLH < ston te -- Rp = Q B40) typaii RAE c "RE = 350 61.1 kQ, 4 kQ a 1 1 . 1 70 iVeg=sv i a cc= ' - 0 | [Ta = 25C | 0 2 4 6 8 100 12 Ip - PULSE INPUT CURRENT mA Figure 12. Typical Propagation Delay vs. Pulse Input Current.PULSE GEN. Zq=500 ty=tp=Sne INPUT Ve MONITORING NODE HCPL-261A/261N sy [ Yeo We L0.1pF Sp Bypass Tel Tel TT Tel jh 1 ! ' t OUTPUT Vo * 0 MONITORING ! tcpcee (NODE ! i { "Cy IS APPROXIMATELY 15 pF WHICH INCLUDES = = PROBE AND STRAY WIRING CAPACITANCE. 30V INPUT Ve 18V ~ ten, = ~ tan 1 OUTPUT Yo SV Figure 15. Test Circuit for tey, and tgpy. HCPL-261A/261N O45 00.1 pF I~ Bypass $ 3500 OUTPUT Vo + MONITORING NODE | PULSEGEN. + Zo = 500! Vom (PEAK) Yom f/f \ i f/f ov SWITCH AT A: Ip=0 mA y Y SV tOooooT+1 chy Vo (min.) SWITCH AT B: Ip=3.5 mA - + VQ (max.) Yo IN Figure 17. Test Circuit for Common Mode Transient Immunity and Typical Waveforms. 8 8 OPTOCOUPLERS wy tue tery Ay = 1k2 | a o | 8 ELH: RL = 350 . | | fen, Re = 350.0. 1k O. 4 ka 0 60 -40 -20 @ 20 40 60 60 100 Ta TEMPERATURE - C te - ENABLE PROPAGATION DELAY - ns Figure 16. Typical Enable Propage- tion Delay vs. Temperature. HCPL- 261A/-261N/-061A/-061N Only. 0 HCPL-261A/261N OPTION 060 ONLY v1 Ps (mW) 700) Fm igmay 600 500 400 300 200 100 OUTPUT POWER - Pg, INPUT CURRENT - Is 0 0 25 50 75 100 125 150 175 200 Ts - CASE TEMPERATURE ~ C Figure 18. Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per VDE 0884. 1-177SINGLE CHANNEL PRODUCTS / GND BUS (BACK) ENABLE (IF USED} QUTPUT 1+ ENABLE (IF USED) QUTPUT 2 10 mm MAX. (SEE NOTE 16) DUAL CHANNEL PRODUCTS 1 GND BUS (BACK) > OUTPUT 1 ==) OUTPUT 2 |e 10 mm MAX. {SEE NOTE 16) Figure 19. Recommended Printed Circuit Board Layout. * HCPL-261A/261N Vee ao Fs] 0 Vec+ . 7 2350 t fs} p}- _+-v0 \ 74L804 j L OR ANY TOTEM-POLE OUTPUT LOGIC GATE weet ace eeeee a-[ 4 GND [4] SHIELD J L GND1 GND2 * HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS 1, 4 TO INPUT GROUND (GND1). Figure 20. Recommended Drive Circuit for HCPL-261A/-261N Families for High- CMR (Similar for HCPL-263A/-263N). *Higher CMR May Be Obtainable by Connecting Pins 1, 4 to Input Ground (Gnd1). 1-178 Application Information Common-Mode Rejection for HCPL-261A/HCPL-261N Families: Figure 20 shows the recom- mended drive circuit for the HCPL-261N/-261A for optimal common-mode rejection performance. Two main points to note are: 1. The enable pin is tied to Vec rather than floating (this applies to single-channel parts only). 2. Two LED-current setting resistors are used instead of one. This is to balance Ign variation during common- mode transients. If the enable pin is left floating, it is possible for common-mode transients to couple to the enable pin. resulting in common-mode failure. This failure mechanism only occurs when the LED is on and the output is in the Low State. It is identified as occurring when the transient output voltage rises above 0.8 V. Therefore, the enable pin should be connected to either V-c or logic-level high for best common-mode performance with the output low (CMR,). This failure mechanism is only present in single-channel parts (HCPL-261N, -261A, -061N, -061A) which have the enable function. Also, common-mode transients can capacitively couple from the LED anode (or cathode) to the output-side ground causing current to be shunted away from the LED (which can be bad if the LED is on) or conversely cause current to be injected into the LED (bad if the LED is meant to be off). Figure 21 shows the parasitic capacitances which exists between LEDanode/cathode and output ground (Cra and C,-). Also shown in Figure 21 on the input side is an AC-equivalent circuit. Table 1 indicates the directions of Ip and In flow depending on the direction of the common-mode transient. For transients occurring when the LED is on, common-mode rejec- tion (CMR,, since the output is in the low state) depends upon the amount of LED current drive (Ip). For conditions where Ip is close to the switching threshold (7). CMR, also depends on the extent which I,p and ILy balance each other. In other words, any condition where common-mode transients cause a momentary decrease in I}; (i.e. when dV-y/dt>0 and [Ipp| > [lex], referring to Table [) will cause common-mode failure for transients which are fast enough. Likewise for common-mode transients which occur when the LED is off (i.e. CMRy, since the output is high), if an imbalance between I, and I,y results in a transient I, equal to or greater than the switching threshold of the optocoupler, the transient signal may cause the output to spike below 2 V (which consti- tutes a CMR), failure). By using the recommended circuit in Figure 20, good CMR can be achieved. (In the case of the -261N families, a minimum CMR of 15 kV/us is guaranteed using this circuit.) The balanced ILep-setting resistors help equalize ILp and [x to reduce the amount by which {gp is modulated from transient coupling through Ca and Cie. CMR with Other Drive ~ircuits CMR performance with drive circuits other than that shown in Figure 20 may be enhanced by following these guidelines: 1. Use of drive circuits where current is shunted from the LED in the LED off state (as shown in Figures 22 and 23). This is beneficial for good CMRy. . Use of Ipy > 3.5 mA. This is good for high CMR,. in Using any one of the drive circuits in Figures 22-24 with fp = 10 mA will result in a typical CMR of 8 kV/us for the HCPL- 261N family, as long as the PC board layout practices are followed. Figure 22 shows a circuit which can be used with any totem-pole-output TTL/ LSTTL/HCMOS logic gate. The buffer PNP transistor allows the circuit to be used with logic devices which have low current- sinking capability. It also helps maintain the driving-gate power- supply current at a constant Jevel to minimize ground shifting for other devices connected to the input-supply ground. OPTOCOUPLERS When using an open-collector TTL or open-drain CMOS logic gate, the circuit in Figure 23 may be used. When using a CMOS gate to drive the optocoupler, the circuit shown in Figure 24 may be used. The diode in parallel with the Ry gy speeds the turn-off of the optocoupler LED. [4 18 -y Vect V2 FLED 10.01 pF 4 | 2 | 7 a $ 350 02 12 RLep rae S| fe} p+ v0 15 pF aS Cc fal |_S.e_] 5 GND SHIELD ilH a Vom WZ Figure 21. AC Equivalent Circuit for HCPL-261X. Voc $4200 S (MAX) 2N3906 (ANY PNP) HCPL-261X Figure 22. TTE Interface Circuit for the HCPL-261A/- 261LN Families. 1-179Veco 74HC00 [ (OR ANY OPEN-COLLECTOR/ OPEN-DRAIN LOGIC GATE) HCPL-261X Figure 23. TTL Open-Collector/Open Drain Gate Drive Circuit for HCPL-261A/-261N Families. Vee HCPL-261A/261N 74HC04 (OR ANY TOTEM-POLE OUTPUT LOGIC GATE) Figure 24. CMOS Gate Drive Circuit for HCPL-261A/- 261N Families. Table 1. Effects of Common Mode Pulse Direction on Transient I, pp If |Itp| < [Iinl; LED I, Current If [Ite] > [Iinl, LED I; Current If dVeu/ dt Is: then I,p Flows: and I, x Flows: Is Momentarily: Is Momentarily: anode through Cy, positive (>0) away from LED away from LED increased decreased anode through Ci, | cathode through Ci- negative (<0) | toward LED toward LED decreased increased cathode through Cy Propagation Delay, Pulse- Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propaga- tion delay from low to high (tpry) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tpy,) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 9). Pulse-width distortion (PWD) results when teu and teu differ in value. PWD is defined as the difference between tp_y and tpy, and often determines the 1-180 maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular appli- cation (RS232, RS422, T-1. etc.). Propagation delay skew, tpsx, is an important parameter to con- sider in parallel data applications where synchronization of signals on parallel data lines is a con- cern. If the parallel data is being sent through a group of opto- couplers, differences in propaga- tion delays will cause the data to arrive at the outputs of the opto- couplers at different times. If this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propaga- tion delays, either tp_y or tpy,, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 25, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tps, is the difference between the shortest propagation delay, either tppy or tpy,. and the longest propagation delay, either tpiy OF tpyp. As mentioned earlier, tpsx can determine the maximum paralleldata transmission rate. Figure 26 is the timing diagram of a typical paralle)] data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew repre- sents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 26 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncer- tainty not overlap, otherwise the clock signal might arrive betore all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considera- tions, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tps. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The tpsy specified optocouplers offer the advantages of guaran- teed specifications for propaga- tion delays, pulse-width distortion, and propagation delay skew over the recommended temperature, input current, and power supply ranges. fp) a [ee a ia a o oO oO EE Oo io) Vo 15V TPHL | i te \ 50% TPLH Yo 15V : = ipsk o> Figure 25. Illustration of Propagation Delay Skew - tpsx. | xX xX INPUTS CLOCK \ / EKA RAAK/ ) pave MM AYX XY CUTPUTS Tpsic cLocK i] \\ Figure 26. Paraliei Data Transmission Example. 1-181