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GS1662 HD/SD-SDI Serializer with Complete SMPTE
Video Support
Final Data Sheet Rev. 4
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HD/SD-SDI Serializer with Complete SMPTE Video Support
GS1662
www.semtech.com
Key Features
• Operation at 1.485Gb/s, 1.485/1.001Gb/s and 270Mb/s
• Supports SMPTE ST 292, SMPTE ST 259-C and DVB-ASI
• Integrated Cable Driver
• Integrated, low-noise VCO
•Integrated ClockCleaner™
• Ancillary data insertion
• Parallel data bus selectable as either 20-bit or 10-bit
• SMPTE video processing including TRS calculation and
insertion, line number calculation and insertion, line
based CRC calculation and insertion, illegal code
re-mapping, SMPTE ST 352 payload identifier
generation and insertion
•GSPI host interface
• +1.2V digital core power supply, +1.2V and +3.3V
analog power supplies, and selectable +1.8V or +3.3V
I/O power supply
• -20ºC to +85ºC operating temperature range
• Low power operation (typically at 330mW, including
Cable Driver)
• Small 11mm x 11mm 100-ball BGA package
• Pb-free and RoHS compliant
Applications
Description
The GS1662 is a complete SDI Transmitter, generating a
SMPTE ST 292, SMPTE ST 259-C or DVB-ASI compliant
serial digital output signal.
The integrated ClockCleaner™ allows the device to accept
parallel clocks with greater than 300ps input jitter and still
provide a SMPTE compliant serial digital output.
The device can operate in four basic user selectable modes:
SMPTE mode, DVB-ASI mode, Data-Through mode, or
Standby mode.
In SMPTE mode, the GS1662 performs SMPTE scrambling
and NRZ to NRZI coding. In addition, the device can insert
TRS words, calculate and insert line numbers and line
based CRC's, re-map illegal code words, map 8-bit TRS to
10-bit TRS, calculate and insert EDH CRC's and flags, and
insert SMPTE ST 352 payload identifier packets. All of the
processing features are optional, and may be disabled via
external control pins and/or via the Host Interface.
The GS1662 provides ancillary data insertion in SMPTE
mode as well. The entire ancillary packet is programmed
into internal registers through the GSPI Host Interface,
including the Ancillary Data Flag (ADF), Data Identification
words (DID and SDID) and checksum. The GS1662 then
recalculates the checksum and inserts the complete
ancillary packet into the video stream.
In DVB-ASI mode, the device will perform 8b/10b encoding
prior to transmission.
In Data-Through mode, all SMPTE and DVB-ASI processing
is disabled, and the device can be used as a simple parallel
to serial converter.
The device can also operate in a lower power Standby
mode. In this mode, no signal is generated at the output.
Parallel data inputs must be provided in 20-bit or 10-bit
multiplexed format for HD and SD video rates. The
associated Parallel Clock input signal operates at 148.5 or
148.5/1.001MHz (HD 10-bit multiplexed format), 74.25 or
74.25/1.001MHz (for HD 20-bit format), 27MHz (for SD
10-bit format) and 13.5MHz (for SD 20-bit format).
The GS1662 includes an integrated Cable Driver fully
compliant with SMPTE ST 259-C and SMPTE ST 292. It
features automatic dual slew-rate selection, depending on
HD or SD operational requirements.
HD-SDI
Application: Single Link (3G-SDI)
to Dual Link (HD-SDI) Converter
GS1662
Link A
Link B
HV F/PCLK
10-bit
3G-SDI GS2960
Semtech
EQ
GS1662
10-bit
HV F/PCLK
HD-SDI
2 of 71
GS1662 HD/SD-SDI Serializer with Complete SMPTE
Video Support
Final Data Sheet Rev. 4
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Functional Block Diagram
Figure A: GS1662 Functional Block Diagram
Input
Mux/
Demux
DIN[19:0]
SMPTE ST 352
Generation
and Insertion
ANC Data
Insertion
TRS , Line
Number
and CRC
Insertion
EDH
Packet
Insertion
DVB-ASI
8b/10b
Encoder
F/DE
V/VSYNC
H/HSYNC
TIM_861
Parallel to Serial
Converter
Mux
SMPTE
Cable
Driver
SDO
SDO
RSET
SDO_EN/DIS
PCLK
GSPI Host
Interface
HANC/
VANC
Blanking
PLL with Low Noise
VCO
ClockCleaner™
LOCKED
CS_TMS
SCLK_TCLK
SDIN_TDI
SDOUT_TDO
DVB_ASI
NRZ/NRZI
SMPTE
Scrambler
LF
VBG
RATE_SEL
CD_VDD
CD_GND
JTAG
CONTROLLER
TMS
TDI
TDO
JTAG/HOST
TCK
Dedicated JTAG pins
Shared JTAG and GSPI pins
(for Drop-in Compatibility
with GS1572/82)
CORE_VDD
CORE_GND
IO_VDD
IO_GND
RESET
STANDBY
20BIT/10BIT
ANC_BLANK
PLL_VDD
PLL_VDD
AVDD
AGND
VCO_GND
VCO_GND
IOPROC_EN/DIS
SMPTE_BYPASS
GS1662 HD/SD-SDI Serializer with Complete SMPTE
Video Support
Final Data Sheet Rev. 4
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Revision History
Version ECO PCN Date Changes and/or Modifications
4 014806−September 2013 Updates throughout the document.
3 155080 56060October 2010
Revised power rating in standby mode. Documented
CSUM behaviour in Section 4.7, Section 4.8.3 and
Configuration and Status Registers.
2 153743 −March 2010
Correction to ANC Data Insertion addresses 040h - 13Fh
in Table 4-16: Configuration and Status Registers.
Changed Reset Pulse width from 10ms to 1ms in Table
2-4: AC Electrical Characteristics and 4.16 Device Reset.
Changed Pin E4 to IO_GND.
1 153472 −January 2010 Converted to Data Sheet.
0 153210 −November 2009
Converted to Preliminary Data Sheet. Changed pin E4 to
RSV in Pin Assignment, Pin Descriptions and Typical
Application Circuit.
A 152910 −October 2009 New Document.
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Video Support
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Contents
Key Features ........................................................................................................................................................1
Applications.........................................................................................................................................................1
Description...........................................................................................................................................................1
Functional Block Diagram ..............................................................................................................................2
Revision History .................................................................................................................................................3
1. Pin Out...............................................................................................................................................................7
1.1 Pin Assignment ..................................................................................................................................7
1.2 Pin Descriptions ................................................................................................................................8
2. Electrical Characteristics ......................................................................................................................... 16
2.1 Absolute Maximum Ratings ....................................................................................................... 16
2.2 Recommended Operating Conditions .................................................................................... 16
2.3 DC Electrical Characteristics ..................................................................................................... 17
2.4 AC Electrical Characteristics ..................................................................................................... 18
3. Input/Output Circuits ............................................................................................................................... 20
4. Detailed Description.................................................................................................................................. 25
4.1 Functional Overview .................................................................................................................... 25
4.2 Parallel Data Inputs ....................................................................................................................... 25
4.2.1 Parallel Input in SMPTE Mode....................................................................................... 27
4.2.2 Parallel Input in DVB-ASI Mode................................................................................... 27
4.2.3 Parallel Input in Data-Through Mode......................................................................... 27
4.2.4 Parallel Input Clock (PCLK) ............................................................................................ 28
4.3 SMPTE Mode ................................................................................................................................... 29
4.3.1 H:V:F Timing ....................................................................................................................... 29
4.3.2 CEA 861 Timing.................................................................................................................. 30
4.4 DVB-ASI Mode ............................................................................................................................... 36
4.5 Data-Through Mode ..................................................................................................................... 36
4.6 Standby Mode ................................................................................................................................. 37
4.7 ANC Data Insertion ....................................................................................................................... 37
4.7.1 ANC Insertion Operating Modes .................................................................................. 38
4.7.2 HD ANC Insertion.............................................................................................................. 39
4.7.3 SD ANC Insertion............................................................................................................... 40
4.8 Additional Processing Functions .............................................................................................. 41
4.8.1 Video Format Detection .................................................................................................. 41
4.8.2 ANC Data Blanking........................................................................................................... 43
4.8.3 ANC Data Checksum Calculation and Insertion..................................................... 44
4.8.4 TRS Generation and Insertion ....................................................................................... 44
4.8.5 HD Line Number Calculation and Insertion............................................................. 44
4.8.6 Illegal Code Re-Mapping................................................................................................. 45
4.8.7 SMPTE ST 352 Payload Identifier Packet Insertion ................................................ 45
4.8.8 Line Based CRC Generation and Insertion (HD)...................................................... 45
4.8.9 EDH Generation and Insertion...................................................................................... 46
4.8.10 Processing Feature Disable .......................................................................................... 47
4.9 Serial Digital Output ..................................................................................................................... 47
4.9.1 Output Signal Interface Levels...................................................................................... 48
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Video Support
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4.9.2 Overshoot/Undershoot.................................................................................................... 49
4.9.3 Slew Rate Selection........................................................................................................... 49
4.9.4 Serial Digital Output Mute.............................................................................................. 49
4.10 Serial Clock PLL ........................................................................................................................... 50
4.10.1 PLL Bandwidth................................................................................................................. 50
4.10.2 Lock Detect........................................................................................................................ 51
4.11 GSPI Host Interface ..................................................................................................................... 52
4.11.1 Command Word Description...................................................................................... 53
4.11.2 Data Read or Write Access........................................................................................... 53
4.11.3 GSPI Timing....................................................................................................................... 54
4.12 Host Interface Register Maps .................................................................................................. 56
4.13 JTAG ID Codeword ..................................................................................................................... 65
4.14 JTAG Test Operation .................................................................................................................. 65
4.15 Device Power-Up ........................................................................................................................ 65
4.16 Device Reset .................................................................................................................................. 65
5. Application Reference Design ............................................................................................................... 66
5.1 Typical Application Circuit ........................................................................................................ 66
6. References & Relevant Standards ......................................................................................................... 67
7. Package & Ordering Information .......................................................................................................... 68
7.1 Package Dimensions ..................................................................................................................... 68
7.2 Packaging Data ............................................................................................................................... 69
7.3 Marking Diagram ........................................................................................................................... 69
7.4 Solder Reflow Profiles .................................................................................................................. 70
7.5 Ordering Information ................................................................................................................... 70
Table 7-2: Ordering Information ..................................................................................................... 70
List of Figures
Figure 3-1: Differential Output Stage (SDO/SDO) .............................................................................. 20
Figure 3-2: Digital Input Pin ........................................................................................................................ 20
Figure 3-3: Digital Input Pin with Schmitt Trigger (RESET) .............................................................. 21
Figure 3-4: Digital Input Pin with weak pull-down - maximum pull-down current ............... 21
Figure 3-5: Digital Input Pin with weak pull-up - maximum pull-up current ........................... 22
Figure 3-6: Bidirectional Digital Input/Output Pin with programmable drive strength......... 22
Figure 3-7: Bidirectional Digital Input/Output Pin with programmable drive strength ........ 23
Figure 3-8: VBG .............................................................................................................................................. 23
Figure 3-9: Loop Filter .................................................................................................................................. 24
Figure 4-1: GS1662 Video Host Interface Timing Diagrams ............................................................ 25
Figure 4-2: H:V:F Input Timing - HD 20-bit Input Mode ................................................................... 29
Figure 4-3: H:V:F Input Timing - HD 10-bit Input Mode ................................................................... 30
Figure 4-4: H:V:F Input Timing - SD 20-bit Mode ............................................................................... 30
Figure 4-5: H:V:F Input Timing - SD 10-bit Mode ............................................................................... 30
Figure 4-6: H:V:DE Input Timing 1280 x 720p @ 59.94/60 (Format 4) ........................................ 31
Figure 4-7: H:V:DE Input Timing 1920 x 1080i @ 59.94/60 (Format 5) ....................................... 32
Figure 4-8: H:V:DE Input Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) .......................... 33
Figure 4-9: H:V:DE Input Timing 1280 x 720p @ 50 (Format 19) .................................................. 33
Figure 4-10: H:V:DE Input Timing 1920 x 1080i @ 50 (Format 20) ............................................... 34
Figure 4-11: H:V:DE Input Timing 720 (1440) x 576 @ 50 (Format 21 & 22) .............................. 34
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Video Support
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Figure 4-12: H:V:DE Input Timing 1920 x 1080p @ 23.94/24 (Format 32) ................................. 35
Figure 4-13: H:V:DE Input Timing 1920 x 1080p @ 25 (Format 33) .............................................. 35
Figure 4-14: H:V:DE Input Timing 1920 x 1080p @ 29.97/30 (Format 34) ................................. 36
Figure 4-15: ORL Matching Network, BNC and Coaxial Cable Connection ............................... 48
Figure 4-16: GSPI Application Interface Connection ........................................................................ 52
Figure 4-17: Command Word Format ..................................................................................................... 53
Figure 4-18: Data Word Format ................................................................................................................ 53
Figure 4-19: Write Mode .............................................................................................................................. 54
Figure 4-20: Read Mode ............................................................................................................................... 54
Figure 4-21: GSPI Time Delay .................................................................................................................... 54
Figure 4-22: Reset Pulse ............................................................................................................................... 65
Figure 5-1: Typical Application Circuit .................................................................................................. 66
Figure 7-1: Package Dimensions ............................................................................................................... 68
Figure 7-2: Marking Diagram ..................................................................................................................... 69
Figure 7-3: Pb-free Solder Reflow Profile .............................................................................................. 70
List of Tables
Table 1-1: Pin Descriptions ............................................................................................................................ 8
Table 2-1: Absolute Maximum Ratings................................................................................................... 16
Table 2-2: Recommended Operating Conditions................................................................................ 16
Table 2-3: DC Electrical Characteristics ................................................................................................. 17
Table 2-4: AC Electrical Characteristics ................................................................................................. 18
Table 4-1: GS1662 Digital Input AC Electrical Characteristics ....................................................... 26
Table 4-2: GS1662 Input Video Data Format Selections................................................................... 26
Table 4-3: GS1662 PCLK Input Rates....................................................................................................... 28
Table 4-4: CEA861 Timing Formats ......................................................................................................... 31
Table 4-5: Supported Video Standards................................................................................................... 42
Table 4-6: IOPROC Register Bits................................................................................................................ 47
Table 4-7: Serial Digital Output - Serial Output Data Rate............................................................... 47
Table 4-8: RSET Resistor Value vs. Output Swing................................................................................. 48
Table 4-9: Serial Digital Output - Overshoot/Undershoot ............................................................... 49
Table 4-10: Serial Digital Output - Rise/Fall Time............................................................................... 49
Table 4-11: PCLK and Serial Digital Clock Rates ................................................................................. 50
Table 4-12: GS1662 PLL Bandwidth......................................................................................................... 50
Table 4-13: GS1662 Lock Detect Indication .......................................................................................... 51
Table 4-14: GSPI Time Delay ...................................................................................................................... 54
Table 4-15: GSPI AC Characteristics........................................................................................................ 55
Table 4-16: Configuration and Status Registers................................................................................... 56
Table 7-1: Packaging Data........................................................................................................................... 69
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Video Support
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1. Pin Out
1.1 Pin Assignment
132 45678910
A
B
C
D
E
F
G
H
J
K
VBG
DVB_ASI
20bit/
10bit
DIN18
SDO
LOCKED JTAG/
HOST
RESET
CORE
_GND
SDO
DIN17
SDO_
EN/DIS
F/DE H/HSYNC
VCO_
GND
PLL_
VDD A_GND
DETECT
_TRS
CORE
_VDD
CORE
_GND
CORE
_GND
CORE
_GND
VCO_
VDD
CORE
_VDD
CORE
_VDD
STANDBY
RSV A_VDD
LF
TDI
A_GND
CORE
_GND
IO_GND IO_VDD
CD_VDD
CD_GND
PLL_
GND
PLL_
GND
V/VSYNC
SDOUT_
TDO
CS_
TMS
SDIN_
TDI
SCLK_
TCK
SMPTE_
BYPASS
IO_GND
IO_VDD
ANC_
BLANK
PCLK
TIM_861
TCK
DIN15 DIN16 DIN19
DIN13 DIN14 DIN12
DIN11 DIN10
PLL_
GND
DIN9 DIN8
DIN7 DIN6
DIN5 DIN4
DIN3
DIN1
DIN0DIN2
CORE
_GND
CORE
_GND
CORE
_GND
CORE
_VDD
CORE
_GND
CD_GND
CD_GND
CD_GND
RSETTDO
TMS
PLL_
VDD
CORE
_GND RSV RSV RSV
CORE
_GND
RATE_
SEL IO_GND
RSV RSV RSV RSV
RSV
RSVRSVRSV
RSV
CORE
_GND
CORE
_GND
IOPROC
_EN/DIS
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1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number Name Timing Ty pe Description
B3, A2, A1,
B2, B1, C2,
C1, C3, D1,
D2
DIN[19:10] Input
PARALLEL DATA BUS
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
20-bit mode
20BIT/10BIT = HIGH
Luma data input in SMPTE mode
(SMPTE_BYPASS = HIGH)
Data input in data through mode
(SMPTE_BYPASS = LOW)
10-bit mode
20BIT/10BIT = LOW
Multiplexed Luma and Chroma data
input in SMPTE mode
(SMPTE_BYPASS = HIGH)
Data input in data through mode
(SMPTE_BYPASS = LOW)
DVB-ASI data input in DVB-ASI mode
(SMPTE_BYPASS = LOW)
(DVB_ASI = HIGH)
A3 F/DE
Synch-
ronous
with
PCLK
Input
PARALLEL DATA TIMING.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
TIM_861 = LOW:
Used to indicate the ODD / EVEN field of the video signal when
DETECT_TRS is set LOW. The device will set the F bit in all outgoing
TRS signals for the entire period that the F input signal is HIGH
(IOPROC_EN/DIS must also be HIGH).
The F signal should be set HIGH for the entire period of field 2 and
should be set LOW for all lines in field 1 and for all lines in
progressive scan systems.
The F signal is ignored when DETECT_TRS = HIGH.
TIM_861 = HIGH:
The DE signal is used to indicate the active video period when
DETECT_TRS is set LOW. DE is HIGH for active data and LOW for
blanking. See Section 4.3 and Section 4.3.2 for timing details.
The DE signal is ignored when DETECT_TRS = HIGH.
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Video Support
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A4 H/HSYNC
Synch-
ronous
with
PCLK
Input
PARALLEL DATA TIMING.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
TIM_861 is LOW:
The H signal is used to indicate the portion of the video line
containing active video data, when DETECT_TRS is set LOW.
Active Line Blanking
The H signal should be LOW for the active portion of the video line.
The signal goes LOW at the first active pixel of the line, and then
goes HIGH after the last active pixel of the line.
The H signal should be set HIGH for the entire horizontal blanking
period, including both EAV and SAV TRS words, and LOW otherwise.
TRS Based Blanking (H_CONFIG = 1h)
The H signal should be set HIGH for the entire horizontal blanking
period as indicated by the H bit in the received TRS ID words, and
LOW otherwise.
TIM_861 = HIGH:
The HSYNC signal indicates horizontal timing. See Section 4.3.
When DETECT_TRS is HIGH, this pin is ignored at all times.
If DETECT_TRS is set HIGH and TIM_861 is set HIGH, the DETECT_TRS
feature will take priority.
A5, E1, G10,
K8 CORE_VDD Input Power Power supply connection for digital core logic. Connect to +1.2V DC
digital.
A6, B6PLL_VDD Input Power Power supply pin for PLL. Connect to +1.2V DC analog.
A7 LF Analog
Output Loop Filter component connection.
A8 VBGOutput Bandgap voltage filter connection.
A9, D6, D7,
D8, H7, J4,
J5, J6, J7,
K4, K5, K6,
K7
RSV−These pins are reserved and should be left unconnected.
A10 A_VDD Input Power VDD for sensitive analog circuitry. Connect to +3.3VDC analog.
B4 PCLK Input
PARALLEL DATA BUS CLOCK.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
HD 20-bit modePCLK @ 74.25MHz
HD 10-bit modePCLK @ 148.5MHz
SD 20-bit modePCLK @ 13.5MHz
SD 10-bit modePCLK @ 27MHz
DVB-ASI modePCLK @ 27MHz
B5, C5, D5,
E2, E5, E6,
F4, F5, F6,
F7, G9, H5,
H6
CORE_GND Input Power Reserved. Connect to CORE_GND.
Table 1-1: Pin Descriptions (Continued)
Pin
Number Name Timing Ty pe Description
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B7 VCO_VDD Input Power
Power pin for VCO. Connect to +1.2V DC analog followed by an RC
filter (see Typical Application Circuit on page 66). VCO_VDD is
nominally 0.7V.
B8 VCO_GND Input Power Ground connection for VCO. Connect to analog GND.
B9, B10 A_GND Input Power GND pins for sensitive analog circuitry. Connect to analog GND.
C4V/VSYNC
Synch-
ronous
with
PCLK
Input
PARALLEL DATA TIMING.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
TIM_861 = LOW:
The V signal is used to indicate the portion of the video field/frame
that is used for vertical blanking, when DETECT_TRS is set LOW.
The V signal should be set HIGH for the entire vertical blanking
period and should be set LOW for all lines outside of the vertical
blanking interval.
The V signal is ignored when DETECT_TRS = HIGH.
TIM_861 = HIGH:
The VSYNC signal indicates vertical timing. See Section 4.3 for
timing details.
The VSYNC signal is ignored when DETECT_TRS = HIGH.
C6, C7, C8PLL_GND Input Power Ground connection for PLL. Connect to analog GND.
C9, D9, E9,
F9 CD_GND Input Power Ground connection for the serial digital cable driver. Connect to
analog GND.
C10, D10 SDO, SDO Output
Serial Data Output Signal.
Serial digital output signal operating at 1.485Gb/s, 1.485 /1.001Gb/s
or 270Mb/s.
The slew rate of the output is automatically controlled to meet
SMPTE ST 292 and ST 259 specifications according to the setting of
the RATE_SEL pin.
D3 STANDBY Input Standby input.
HIGH to place the device in Standby mode.
D4 SDO_EN/DISInput
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to enable or disable the serial digital output stage.
When SDO_EN/DIS is LOW, the serial digital output signals SDO and
SDO are disabled and become high impedance.
When SDO_EN/DIS is HIGH, the serial digital output signals SDO and
SDO are enabled.
Table 1-1: Pin Descriptions (Continued)
Pin
Number Name Timing Ty pe Description
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Video Support
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E3 RATE_SEL Input
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to configure the operating data rate.
E7 TDI Input
COMMUNICATION SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Dedicated JTAG pin.
Test data in.
This pin is used to shift JTAG test data into the device when the
JTAG/HOST pin is LOW.
E8 TMSInput
COMMUNICATION SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Dedicated JTAG pin.
Test mode start.
This pin is JTAG Test Mode Start, used to control the operation of
the JTAG test when the JTAG/HOST pin is LOW.
E10 CD_VDD Input Power Power for the serial digital cable driver. Connect to +3.3V DC analog.
F1, F2, H1,
H2, J1, J2,
K1, K2, J3,
K3
DIN[9:0] Input
PARALLEL DATA BUS.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
In 10-bit mode, these pins are not used.
20-bit mode
20BIT/10BIT = HIGH
Chroma data input in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in data through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
Not Used in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
10-bit mode
20BIT/10BIT = LOW Not used.
Table 1-1: Pin Descriptions (Continued)
Pin
Number Name Timing Ty pe Description
RATE_SEL Data Rate
0
1
1.485 or 1.485/1.001Gb/s
270Mb/s
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F3 DETECT_TRSInput
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select external HVF timing mode or TRS extraction timing
mode.
When DETECT_TRS is LOW, the device extracts all internal timing
from the supplied H:V:F or CEA-861 timing signals, dependent on
the status of the TIM861 pin.
When DETECT_TRS is HIGH, the device extracts all internal timing
from TRS signals embedded in the supplied video stream.
F8 TDO Output
COMMUNICATION SIGNAL OUTPUT.
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Dedicated JTAG pin.
JTAG Test Data Output.
This pin is used to shift results from the device when the JTAG/HOST
pin is LOW.
F10 RSET Input An external 1% resistor connected to this input is used to set the
SDO/SDO output signal amplitude.
G1, H10 IO_VDD Input Power Power connection for digital I/O. Connect to +3.3V or +1.8V DC
digital.
E4, G2, H9 IO_GND Input Power Ground connection for digital I/O. Connect to digital GND.
G3TIM_861 Input
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select external CEA-861 timing mode.
When DETECT_TRS is LOW and TIM-861 is LOW, the device extracts
all internal timing from the supplied H:V:F timing signals.
When DETECT_TRS is LOW and TIM-861 is HIGH, the device extracts
all internal timing from the supplied HSYNC, VSYNC, DE timing
signals.
When DETECT_TRS is HIGH, the device extracts all internal timing
from TRS signals embedded in the supplied video stream.
G420bit/10bit Input
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select the input bus width.
G5DVB_ASI Input
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to enable/disable the DVB-ASI data transmission.
When DVB_ASI is set HIGH and SMPTE_BYPASS is set LOW, then the
device will carry out DVB-ASI word alignment, I/O processing and
transmission.
When SMPTE_BYPASS and DVB_ASI are both set LOW, the device
operates in data-through mode.
Table 1-1: Pin Descriptions (Continued)
Pin
Number Name Timing Ty pe Description
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Video Support
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G6 SMPTE_BYPASS Input
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to enable / disable all forms of encoding / decoding,
scrambling and EDH insertion.
When set LOW, the device operates in data through mode
(DVB_ASI= LOW), or in DVB-ASI mode (DVB_ASI = HIGH).
No SMPTE scrambling takes place and none of the I/O processing
features of the device are available when SMPTE_BYPASS is set LOW.
When set HIGH, the device carries out SMPTE scrambling and I/O
processing.
G7IOPROC_EN/DISInput
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to enable or disable the I/O processing features.
When IOPROC_EN/DIS is HIGH, the I/O processing features of the
device are enabled. When IOPROC_EN/DIS is LOW, the I/O processing
features of the device are disabled.
Only applicable in SMPTE mode.
G8RESET Input
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to reset the internal operating conditions to default settings
and to reset the JTAG sequence.
Normal mode (JTAG/HOST = LOW).
When LOW, all functional blocks will be set to default conditions
and all input and output signals become high impedance.
When HIGH, normal operation of the device resumes.
JTAG test mode (JTAG/HOST = HIGH).
When LOW, all functional blocks will be set to default and the JTAG
test sequence will be reset.
When HIGH, normal operation of the JTAG test sequence resumes.
H3 ANC_BLANK Input
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
When ANC_BLANK is LOW, the Luma and Chroma input data is set
to the appropriate blanking levels during the H and V blanking
intervals.
When ANC_BLANK is HIGH, the blanking function is disabled.
Only applicable in SMPTE mode.
H4 LOCKED Output
STATUS SIGNAL OUTPUT.
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
PLL lock indication.
HIGH indicates PLL is locked.
LOW indicates PLL is not locked.
Table 1-1: Pin Descriptions (Continued)
Pin
Number Name Timing Ty pe Description
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Video Support
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H8 JTAG/HOSTInput
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select JTAG test mode or host interface mode.
When JTAG/HOST is HIGH, the host interface port is configured for
JTAG test.
When JTAG/HOST is LOW, normal operation of the host interface
port resumes and the separate JTAG pins become the JTAG port.
J8TCK Input
COMMUNICATION SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
JTAG Serial Data Clock Signal.
This pin is the JTAG clock when the JTAG/HOST pin is LOW.
J9SDOUT_TDO Output
COMMUNICATION SIGNAL OUTPUT.
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Shared JTAG/HOST pin. Provided for compatibility with the GS1582.
Serial Data Output/Test Data Output.
Host Mode (JTAG/HOST = LOW)
This pin operates as the host interface serial output, used to read
status and configuration information from the internal registers of
the device.
JTAG Test Mode (JTAG/HOST = HIGH)
This pin is used to shift test results and operates as the JTAG test
data output, TDO (for new designs, use the dedicated JTAG port).
Note: If the host interface is not being used leave this pin
unconnected.
IO_VDD = +3.3V
Drive Strength = 12mA
IO_VDD = +1.8V
Drive Strength = 4mA
J10 SCLK_TCK Input
COMMUNICATION SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Shared JTAG/HOST pin. Provided for pin compatibility with GS1582.
Serial data clock signal.
Host Mode (JTAG/HOST = LOW)
SCLK_TCK operates as the host interface burst clock, SCLK.
Command and data read/write words are clocked into the device
synchronously with this clock.
JTAG Test Mode (JTAG/HOST = HIGH)
This pin is the TEST MODE START pin, used to control the operation
of the JTAG test clock, TCK (for new designs, use the dedicated JTAG
port).
Note: If the host interface is not being used, tie this pin HIGH.
Table 1-1: Pin Descriptions (Continued)
Pin
Number Name Timing Ty pe Description
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Video Support
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K9 CS_TMSInput
COMMUNICATION SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Chip select / test mode start.
JTAG Test mode (JTAG/HOST = HIGH)
CS_TMS operates as the JTAG test mode start, TMS, used to control
the operation of the JTAG test, and is active HIGH (for new designs,
use the dedicated JTAG port).
Host mode (JTAG/HOST = LOW), CS_TMS operates as the host
interface Chip Select, CS, and is active LOW.
K10 SDIN_TDI Input
COMMUNICATION SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Shared JTAG/HOST pin. Provided for pin compatibility with GS1582.
Serial data in/test data in.
In JTAG mode, this pin is used to shift test data into the device (for
new designs, use the dedicated JTAG port).
In host interface mode, this pin is used to write address and
configuration data words into the device.
Table 1-1: Pin Descriptions (Continued)
Pin
Number Name Timing Ty pe Description
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
2.2 Recommended Operating Conditions
Table 2-1: Absolute Maximum Ratings
Parameter Value/Units
Supply Voltage, Digital Core (CORE_VDD) -0.3V to +1.5V
Supply Voltage, Digital I/O (IO_VDD) -0.3V to +3.6V
Supply Voltage, Analog +1.2V (PLL_VDD, VCO_VDD) -0.3V to +1.5V
Supply Voltage, Analog +3.3V (CD_VDD, A_VDD) -0.3V to +3.6V
Input Voltage Range (digital inputs) -2.0V to +5.25V
Operating Temperature Range-20°C to +85°C
Functional Temperature Range-40°C to +85°C
Storage Temperature Range-40°C to +125°C
Peak Reflow Temperature (JEDEC J-STD-020C)260°C
ESD Sensitivity, HBM (JESD22-A114) 2kV
Note: Absolute Maximum Ratings are those values beyond which damage may occur. Functional operation
outside of the ranges shown in Table 2-1 is not implied.
Table 2-2: Recommended Operating Conditions
Parameter Symbol Conditions Min Typ Max Units Notes
Operating Temperature Range,
Ambient TA–-20−85 °C−
Supply Voltage, Digital Core CORE_VDD – 1.14 1.2 1.26V−
Supply Voltage, Digital I/O IO_VDD
+1.8V mode 1.71 1.8 1.89 V −
+3.3V mode 3.13 3.3 3.47 V −
Supply Voltage, PLL PLL_VDD – 1.14 1.2 1.26V–
Supply Voltage, VCOVCO_VDD – −0.7 −V1
Supply Voltage, AnalogA_VDD – 3.13 3.3 3.47 V –
Supply Voltage, CDCD_VDD – 3.13 3.3 3.47 V –
Operating Temperature Range– – -20 – 85 °C2
Functional Temperature Range– – -40 – 85 °C2
Notes:
1. This is 0.7V rather than 1.2V because there is a voltage drop across an external 105Ω resistor. See Typical Application Circuit on page 66.
2. Operating Temperature Range guarantees the parameters given in the DC Electrical Characteristics and AC Electrical Characteristics.
Functional Temperature Range guarantees a device start-up.
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2.3 DC Electrical Characteristics
Table 2-3: DC Electrical Characteristics
VCC = +3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Notes
System
+1.2V Supply Current I1V2
10/20bit HD −90 150 mA −
10/20bit SD−75 120 mA −
DVB_ASI−75 120 mA −
+1.8V Supply Current I1V8
10/20bit HD −10 25 mA −
10/20bit SD−310mA−
DVB_ASI−310mA−
+3.3V Supply Current I3V3
10/20bit HD −80 100 mA −
10/20bit SD−70 90 mA −
DVB_ASI−70 90 mA −
Total Device Power
(IO_VDD = +1.8V) P1D8
10/20bit HD −330 490 mW −
10/20bit SD−300 450 mW −
DVB_ASI−300 410 mW −
Reset −200 −mW −
Standby−100 180 mW 1
Total Device Power
(IO_VDD = +3.3V) P3D3
10/20bit HD −370 500 mW −
10/20bit SD−320 450 mW −
DVB_ASI−320 450 mW −
Reset −230 −mW −
Standby−110 180 mW −
Digital I/O
Input Logic LOW VIL +3.3V or +1.8V operation IO_VSS-0.3 −0.3 x IO_VDD V −
Input Logic HIGHVIH +3.3V or +1.8V operation 0.7 x
IO_VDD −IO_VDD+0.3 V −
Output Logic LOW VOL
IOL=5mA, +1.8V operation −− 0.2 V −
IOL=8mA, +3.3V operation −− 0.4 V −
Output Logic HIGHVOH
IOH=-5mA, +1.8V operation 1.4 −–V−
IOH=-8mA, +3.3V operation 2.4 −–V−
Serial Output
Serial Output
Common Mode
Voltage
VCMOUT 75Ω load, RSET = 750Ω
SD and HD mode−CD_VDD -
(VSDD/2) −V−
Notes:
1. Devices manufactured prior to April 1, 2011 consume 150mW of power in Standby mode.
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2.4 AC Electrical Characteristics
Table 2-4: AC Electrical Characteristics
VCC = +3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Notes
System
Device Latency
–HD bypass
(PCLK = 74.25MHz) –54–PCLK –
–HD SMPTE
(PCLK = 74.25MHz) –95–PCLK –
–SD bypass
(PCLK = 27MHz)
–54 PCLK –
–SD SMPTE
(PCLK = 27MHz) – 112 PCLK –
–DVB-ASI–52–PCLK –
Reset Pulse Width treset –1––ms–
Parallel Input
Parallel Clock FrequencyfPCLK – 13.5 – 148.5 MHz –
Parallel Clock Duty Cycle DCPCLK –40– 60% –
Input Data Setup Time tsu 50% levels;
+3.3V or +1.8V
operation
1.2 – – ns 1
Input Data Hold Time tih 0.8 – – ns 1
Serial Digital Output
Serial Output Data Rate DRSDO
– – 1.485 – Gb/s –
– – 1.485/1.001 – Gb/s –
– – 270 – Mb/s –
Serial Output SwingVSDD RSET = 750Ω
75Ω load 750 800 850 mVpp –
Serial Output Rise/Fall Time
20% ~ 80%
trfSDO HD mode – 120 135 ps –
trfSDO SD mode 400 660800ps –
Mismatch in rise/fall time Δtr , Δtf–––35ps–
Duty Cycle Distortion – – – – 5 % 2
Overshoot –HD mode–510%2
–SD mode–38%2
Output Return Loss ORL 5 MHz - 1.485 GHz – -18 – dB3
Serial Output Intrinsic Jitter
tOJ
Pseudorandom and
SMPTE Colour Bars
HD signal
–5095ps4, 6
tOJ
Pseudorandom and
SMPTE Colour Bars
SD signal
– 200 400 ps 5
GSPI
GSPI Input Clock FrequencyfSCLK
50% levels
+3.3V or +1.8V
operation
––80MHz–
GSPI Input Clock Duty Cycle DCSCLK 40 50 60% –
GSPI Input Data Setup Time – 1.5 – – ns –
GSPI Input Data Hold Time – 1.5 – – ns –
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GSPI Output Data Hold Time – 15pF load1.5 – – ns –
CS low before SCLK rising
edget0
50% levels
+3.3V or +1.8V
operation
1.5 – – ns –
Time between end of
command word (or data in
Auto-Increment mode) and
the first SCLK of the
following data word - write
cycle
t4
50% levels
+3.3V or +1.8V
operation
PCLK
(MHz) ns
––ns–
unlocked445
13.5 74.2
27.0 37.1
74.25 13.5
148.5 6.7
Time between end of
command word (or data in
Auto-Increment mode) and
the first SCLK of the
following data word - read
cycle
t5
50% levels
+3.3V or +1.8V
operation
PCLK
(MHz) ns
––ns–
unlocked1187
13.5 297
27.0 148.4
74.25 53.9
148.5 27
CS high after SCLK falling
edget7
50% levels
+3.3V or +1.8V
operation
PCLK
(MHz) ns
––ns–
unlocked445
13.5 74.2
27.0 37.1
74.25 13.5
148.5 6.7
Notes:
1. Input setup and hold time is dependent on the rise and fall time on the parallel input. Parallel clock and data with rise time or fall time greater
than 500ps require larger setup and hold times.
2. Single Ended into 75Ω external load.
3. ORL depends on board design.
4. Alignment Jitter = measured from 100kHz to serial data rate/10.
5. Alignment Jitter = measured from 1kHz to 27MHz.
6. This is the maximum jitter for a BER of 10-12. The equivalent jitter value as per RP184 is 40ps max.
Table 2-4: AC Electrical Characteristics (Continued)
VCC = +3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Notes
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Video Support
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3. Input/Output Circuits
Figure 3-1: Differential Output Stage (SDO/SDO)
Figure 3-2: Digital Input Pin (20bit/10bit, ANC_BLANK, DETECT_TRS, DVB_ASI,
RATE_SEL, SMPTE_BYPASS, TIM_861, F/DE, H/HSYNC, PCLK, V/VSYNC)
I
REF
CD_VDD
SDO SDO
IO_VDD
200Ω
Input Pin
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Video Support
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Figure 3-3: Digital Input Pin with Schmitt Trigger (RESET)
Figure 3-4: Digital Input Pin with weak pull-down - maximum pull-down
current <110µA (JTAG/HOST, STANDBY, SCLK_TCK, SDIN_TDI, TCK, TDI)
IO_VDD
200Ω
Input Pin
IO_VDD
200Ω
Input Pin
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Figure 3-5: Digital Input Pin with weak pull-up - maximum pull-up current
<110µA (CS_TMS, SDO_EN/DIS, TMS)
Figure 3-6: Bidirectional Digital Input/Output Pin with programmable drive
strength. These pins are configured to input at all times except in test mode.
(DIN0, DIN2, DIN3, DIN4, DIN5, DIN6, DIN7, DIN8, DIN9, DIN10, DIN11, DIN12,
DIN13, DIN14, DIN15, DIN16, DIN17, DIN18, DIN19, DIN1)
200Ω
Input Pin
IO_VDD IO_VDD
IO_VDD
200Ω
Output Pin
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Figure 3-7: Bidirectional Digital Input/Output Pin with programmable drive
strength. These pins are configured to output at all times except in reset
mode. (LOCKED, SDOUT_TDO, TDO)
Figure 3-8: VBG
IO_VDD
200Ω
Output Pin
VBG
50Ω
2kΩ
A_VDD
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4. Detailed Description
4.1 Functional Overview
The GS1662 is a multi-rate Transmitter with integrated SMPTE digital video processing
and an integrated Cable Driver. It provides a complete transmit solution at 1.485Gb/s,
1.485/1.001Gb/s or 270Mb/s.
The device has four basic modes of operation that must be set through external device
pins: SMPTE mode, DVB-ASI mode, Data-Through mode and Standby mode.
In SMPTE mode, the device will accept 10-bit multiplexed or 20-bit demultiplexed
SMPTE compliant data. By default, the device's additional processing features will be
enabled in this mode.
In DVB-ASI mode, the GS1662 will accept an 8-bit parallel DVB-ASI compliant transport
stream on DIN[17:10]. The serial output data stream will be 8b/10b encoded with
stuffing characters added as per the standard.
Data-Through mode allows for the serializing of data not conforming to SMPTE or
DVB-ASI streams. No additional processing will be done in this mode.
In addition, the device may be put into Standby, to reduce power consumption.
The serial digital output features a high-impedance mode and adjustable signal swing.
The output slew rate is automatically set by the RATE_SEL pin setting.
The GS1662 provides several data processing functions; including generic ANC
insertion, SMPTE ST 352 and EDH data packet generation and insertion, automatic video
standards detection, and TRS, CRC, ANC data checksum, and line number calculation
and insertion. These features are all enabled/disabled collectively using the external I/O
processing pin, but may be individually disabled via internal registers accessible
through the GSPI host interface.
Finally, the GS1662 contains a JTAG interface for boundary scan test implementations.
4.2 Parallel Data Inputs
Data signal inputs enter the device on the rising edge of PCLK, as shown in Figure 4-1.
Figure 4-1: GS1662 Video Host Interface Timing Diagrams
data_1
transition zone data_1
data_0
transition zone
PCLK
PCLK peri od
DIN[19:0], F_DE,
H_HSYNC, V_VSYNC
data_0
T
H
Luma/Chroma is launched on the positive edge of PCLK
by the source chip to the GS1662
T
SU
T
H
T
SU
T
H
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The GS1662 is a high performance HD/SD capable transmitter. In order to optimize the
output jitter performance across all operating conditions, input levels and overshoot at
the parallel video data inputs of the device need to be controlled. In order to do this,
source series termination resistors should be used to match the impedance of the PCB
data trace line. IBIS models can be used to simulate the board effects and then optimize
the output drive strength and the termination resistors to allow for the best transition
(one that produces minimal overshoot). If this is not viable, Semtech recommends
matching the source series resistance to the trace impedance, and then adjusting the
output drive strength to the minimum value that will give zero errors.
The above also applies to the PCLK input line. HVF should also be well terminated,
however due to the lower data rates and transition density, it is not as critical.
Table 4-1: GS1662 Digital Input AC Electrical Characteristics
Parameter Symbol Conditions Min Typ Max Units
Input data set-up time tSU50% levels;
+1.8V operation
1.2 −− ns
Input data hold time tIH 0.8 −− ns
Input data set-up time tSU50% levels;
+3.3V operation
1.3 −− ns
Input data hold time tIH 0.8 −− ns
Table 4-2: GS1662 Input Video Data Format Selections
Input Data Format
Pin/Register Bit Settings
DIN[9:0] DIN[19:10]
20BIT
/10BIT
RATE
_SEL
SMPTE
_BYPASS DVB_ASI
20-bit demultiplexed HD
format HIGHLOW HIGHLOW Chroma Luma
20-bit data Input
HD format HIGHLOW LOW LOW DATA DATA
20-bit demultiplexed SD
format HIGHHIGHHIGHLOW Chroma Luma
20-bit data input
SD format HIGHHIGHLOW LOW DATA DATA
10-bit multiplexed
HD format LOW LOW HIGHLOWHigh ImpedanceLuma/Chroma
10-bit data input
HD format LOW LOW LOW LOW High ImpedanceDATA
10-bit multiplexed
SD format LOW HIGHHIGHLOWHigh ImpedanceLuma/
Chroma
10-bit multiplexed
SD format LOW HIGHLOW LOWHigh ImpedanceDATA
10-bit ASI input
SD format LOW HIGHLOW HIGHHigh ImpedanceDVB-ASI data
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4.2.1 Parallel Input in SMPTE Mode
When the device is operating in SMPTE mode (SMPTE_BYPASS = HIGH), data must be
presented to the input bus in either multiplexed or demultiplexed form, depending on
the setting of the 20BIT/10BIT pin.
When operating in 20-bit mode (20BIT/10BIT = HIGH), the input data format must be
word aligned, demultiplexed Luma and Chroma data (SD or HD).
When operating in 10-bit mode (20BIT/10BIT = LOW), the input data format must be
multiplexed Luma (Y) and Chroma (C) data (SD, HD). C words precede Y words. In this
mode, the data must be presented on the DIN[19:10] pins. The DIN[9:0] inputs are
ignored.
4.2.1.1 Input Data Format in SDTI Mode
SDTI and HD-SDTI are a sub-set of SDI and HD-SDI formats. They may contain SDTI data
on any line in the frame. Those lines which contain SDTI or HD-SDTI data are identified
with an SDTI or HD-SDTI header packet in the HANC space.
The GS1662 does not differentiate between a signal carrying video and a signal carrying
SDTI or HD-SDTI data in SD or HD formats. The user is responsible for ensuring that the
headers and data are not corrupted.
4.2.2 Parallel Input in DVB-ASI Mode
The GS1662 is in DVB-ASI mode when the SMPTE_BYPASS pin is set LOW, the DVB_ASI
pin is set HIGH, and the RATE_SEL0 pin is set HIGH. In this mode, all SMPTE processing
features are disabled.
When operating in DVB-ASI mode, the device must be set to 10-bit mode by setting the
20BIT/10BIT pin LOW. The device will accept 8-bit data words on DIN[17:10], where
DIN17 = HIN is the most significant bit of the encoded transport stream data and
DIN10 = AIN is the least significant bit. In addition, DIN19 and DIN18 will be configured
as the DVB-ASI control signals INSSYNCIN and KIN respectively.
DIN19 = INSSYNCIN
DIN18 = KIN
DIN17~10 = HIN ~ AIN where AIN is the least significant bit of the transport stream data.
4.2.3 Parallel Input in Data-Through Mode
Data-Through mode is enabled when the SMPTE_BYPASS pin and the DVB_ASI pin are
LOW.
In this mode, data at the input bus is serialized without any encoding, scrambling or
word alignment taking place.
The input data width is controlled by the setting of the 20BIT/10BIT pin as shown in
Table 4-2 above.
Note: When in HD 10-bit mode, asserting the SMPTE_BYPASS LOW to put the device in
SMPTE-BYPASS mode will create video errors. If the user desires to use the device as a
simple serializer in HD 10-bit mode, all video processing features may be disabled by
setting the IOPROC_EN/DIS pin LOW.
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4.2.4 Parallel Input Clock (PCLK)
The frequency of the PCLK input signal of the GS1662 is determined by the input data
format and operating mode selection.
Table 4-3 below lists the input PCLK rates and input signal formats according to the
external selection pins for the GS1662.
Table 4-3: GS1662 PCLK Input Rates
Input Data Format
Pin Settings
PCLK Rate
20BIT/10BIT RATE_
SEL
SMPTE_
BYPASS DVB-ASI
20-bit demultiplexed
HD format HIGHLOWHIGH X 74.25 or 74.25/1.001MHz
20-bit data input
HD format HIGH LOW LOW LOW 74.25 or 74.25/1.001MHz
20-bit demultiplexed
SD format HIGHHIGHHIGHLOW 13.5MHz
20-bit data input
SD format HIGHHIGH LOW LOW 13.5MHz
10-bit multiplexed
HD format LOW LOW HIGH LOW 148.5 or 148.5/1.001MHz
10-bit data input
HD format LOW LOW LOW LOW 148.5 or 148.5/1.001MHz
10-bit multiplexed
SD format LOW HIGHHIGH X 27MHz
10-bit data input
SD format LOW HIGH LOW LOW 27MHz
10-bit ASI input
SD format LOW HIGHLOW HIGH 27MHz
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4.3 SMPTE Mode
The function of this block is to carry out data scrambling according to SMPTE ST 292, and
to carry out NRZ to NRZI encoding prior to presentation to the parallel to serial
converter.
These functions are only enabled when the SMPTE_BYPASS pin is HIGH.
In addition, the GS1662 requires the DVB_ASI pin to be set LOW to enable this feature.
4.3.1 H:V:F Timing
In SMPTE mode, the GS1662 can automatically detect the video standard and generate
all internal timing signals. The total line length, active line length, total number of lines
per field/frame and total active lines per field/frame are calculated for the received
parallel video.
When DETECT_TRS is LOW, the video standard and timing signals are based on the
externally supplied H_Blanking, V_Blanking, and F_Digital signals. These signals are
supplied by the H/HSYNC, V/VSYNC and F/DE pins respectively. When DETECT_TRS is
HIGH, the video standard timing signals will be extracted from the embedded TRS ID
words in the parallel input data. Both 8-bit and 10-bit TRS code words will be identified
by the device.
Note: I/O processing must be enabled for the device to remap 8-bit TRS words to the
corresponding 10-bit value for transmission.
The GS1662 determines the video standard by timing the horizontal and vertical
reference information supplied at the H/HSYNC, V/VSYNC, and F/DE input pins, or
contained in the TRS ID words of the received video data. Therefore, full
synchronization to the received video standard requires at least one complete video
frame.
Once synchronization has been achieved, the GS1662 will continue to monitor the
received TRS timing or the supplied H, V, and F timing information to maintain
synchronization. The GS1662 will lose all timing information immediately following loss
of H, V and F.
The H signal timing should also be configured via the H_CONFIG bit of the internal
IOPROC register as either active line based blanking or TRS based blanking.
Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this mode,
the H input should be HIGH for the entire horizontal blanking period, including the EAV
and SAV TRS words. This is the default H timing used by the device.
The timing of these signals is shown in Figure 4-2.
Figure 4-2: H:V:F Input Timing - HD 20-bit Input Mode
PCLK
LUM A DA TA IN PU T
CHROMA DATA INPUT
H
X Y Z (EAV)0000003FF
0000003FF
V
F
0000003FF
0000003FFX Y Z (EAV)
X Y Z (SAV)
X Y Z (SAV)
H SIGNAL TIMING:H_CONFIG = LOW H_CONFIG = HIGH
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Figure 4-3: H:V:F Input Timing - HD 10-bit Input Mode
Figure 4-4: H:V:F Input Timing - SD 20-bit Mode
Figure 4-5: H:V:F Input Timing - SD 10-bit Mode
4.3.2 CEA 861 Timing
The GS1662 extracts timing information from externally provided HSYNC, VSYNC, and
DE signals when CEA 861 timing mode is selected by setting DETECT_TRS = LOW and
TIM_861 = HIGH.
Horizontal sync (H), Vertical sync (V), and Data Enable (DE) timing must be provided via
the H/HSYNC, V/VSYNC and F/DE input pins. The host interface register bit H_CONFIG
is ignored in CEA 861 input timing mode.
The GS1662 determines the EIA/CEA-861 standard and embeds EAV and SAV TRS
words in the output serial video stream.
Video standard detection is not dependent on the HSYNC pulse width or the VSYNC
pulse width and therefore the GS1662 tolerates non-standard pulse widths. In addition,
the device can compensate for up to ±1 PCLK cycle of jitter on VSYNC with respect to
HSYNC and sample VSYNC correctly.
Note 1: The period between the leading edge of the HSYNC pulse and the leading edge
of Data Enable (DE) must follow the timing requirements described in the EIA/CEA-861
specification. The GS1662 embeds TRS words according to this timing relationship to
maintain compatibility with the corresponding SMPTE standard.
HVF TIMING AT SAV
0000003FF3FF 000000
PCLK
MULTIPLEXED Y'CbCr DA TA IN PU T
H
V
F
HVF TIMING AT EAV
PCLK
0000003FF3FF X Y Z (EAV)000000
MULTIPLEXED Y'CbCr DA TA IN PU T
H
V
F
X Y Z (EAV)
XYZ (SAV) X Y Z (SAV)
PCLK
CHROMA DATA INPUT
LUMA DATA INPUT
H
0003FF
X Y Z (EAV)000
V
F
0003FF
000
H SIGNAL TIMING:H_CONFIG = LOW H_CONFIG = HIGH
X Y Z (SAV)
MULTIPLEXED Y'CbCr DATA INPUT
PCLK
H
V
F
X Y Z (EAV)0000003FF 0000003FF X Y Z (SAV)
H SIGNAL TIMING:H_CONFIG = LOW H_CONFIG = HIGH
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Note 2: When CEA 861 standards 6 & 7 [720(1440)x480i] are presented to the GS1662,
the device embeds TRS words corresponding to the timing defined in SMPTE ST 125 to
maintain SMPTE compatibility.
CEA 861 standards 6 & 7 [720(1440)x480i] define the active area on lines 22 to 261 and
285 to 524 inclusive (240 active lines per field). SMPTE ST 125 defines the active area on
lines 20 to 263 and 283 to 525 inclusive (244 lines on field 1, 243 lines on field 2).
Therefore, in the first field, the GS1662 adds two active lines above and two active lines
below the original active image. In the second field, it adds two lines above and one line
below the original active image.
The CEA861 Timing Formats are summarized in Table 4-4. and are shown in Figure 4-6
to Figure 4-14.
Figure 4-6: H:V:DE Input Timing 1280 x 720p @ 59.94/60 (Format 4)
Table 4-4: CEA861 Timing Formats
Format Parameters
4 H:V:DE Input Timing 1280 x 720p @ 59.94/60Hz
5 H:V:DE Input Timing 1920 x 1080i @ 59.94/60Hz
6&7 H:V:DE Input Timing 720 (1440) x 480i @ 59.94/60Hz
19 H:V:DE Input Timing 1280 x 720p @ 50Hz
20 H:V:DE Input Timing 1920 x 1080i @ 50Hz
21&22 H:V:DE Input Timing 720 (1440) x 576 @ 50Hz
32 H:V:DE Input Timing 1920 x 1080p @ 23.94/24Hz
33 H:V:DE Input Timing 1920 x 1080p @ 25Hz
34 H:V:DE Input Timing 1920 x 1080p @ 29.97/30Hz
1660 Total Horizontal Clocks per line
1280 Clocks for Active Video
Data
Enable
220 clocks
40
370
110
HSYNC
Progressive Frame: 30 Vertical Blanking Lines 720 Active Vertical Lines
1650 clocks
Data
Enable
HSYNC
110
VSYNC
260
745 746 747 748 749 750 1 2 3 4 5 6 7 25 26745 746750
~
~
~
~
~
~
~
~
~
~
~
~
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Figure 4-7: H:V:DE Input Timing 1920 x 1080i @ 59.94/60 (Format 5)
148 clocks
1920 Clocks for Active Video280
Data
Enable
HSYNC
VSYNC
1123 1124 1125 1 2 3 4 5 6 7 8
Data
Enable
HSYNC
2200 Total Horizontal Clocks per line
44
88
Field 1: 22 Vertical Blanking Lines
2200 clocks
88
19 20 21 560 561 562
192
540 Active Vertical Lines per field
540 Active Vertical Lines per field
Field 2: 23 Vertical Blanking Lines
192
88
2200 clocks
1100
VSYNC
Data
Enable
HSYNC
560 561 562 563 564 565 566 567 568 569 570 582 583 584 1123 1124 1125
~~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
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Figure 4-8: H:V:DE Input Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7)
Figure 4-9: H:V:DE Input Timing 1280 x 720p @ 50 (Format 19)
1440 Clocks for Active Video
276
Data
Enable
1716 Total Horizontal Clocks per line
HSYNC
Data
Enable
HSYNC
VSYNC
Data
Enable
HSYNC
VSYNC
114 clocks
124
38
Field 1: 22 Vertical Blanking Lines
1716 clocks 238
240 Active Vertical Lines per field
~
~
~
~
38
240 Active Vertical Lines per field
Field 2: 23 Vertical Blanking Lines
~
~
524 525 1 2 3 4 5 6 7 8 9 21 22
~
~
~
~
238
38 1716 clocks 858
261 262 263 264 265 266 267 268 269 270 271 524 525 1284 285
261 262 263
220 clocks
1280 Clocks for Active Video
700
Data
Enable
HSYNC
VSYNC
745 746 747 748 749 750 1 2 3 4 5 6 7
Data
Enable
HSYNC
1980 Total Horizontal Clocks per line
40
440
Progressive Frame: 30 Vertical Blanking Lines
1980 clocks
440
745 746
260
720 Active Vertical Lines
~
~
~
~
~
~
~
25 26
~
~
~
~
750
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Figure 4-10: H:V:DE Input Timing 1920 x 1080i @ 50 (Format 20)
Figure 4-11: H:V:DE Input Timing 720 (1440) x 576 @ 50 (Format 21 & 22)
148 clocks
1920 Clocks for Active Video720
Data
Enable
HSYNC
2640 Total Horizontal Clocks per line
44
528
VSYNC
1123 1124 1125 1 2 3 4 5 6 7 8
Data
Enable
HSYNC
Field 1: 22 Vertical Blanking Lines
2640 clocks
528
19 20 21 560 561 562
192
540 Active Vertical Lines per field
540 Active Vertical Lines per field
Field 2: 23 Vertical Blanking Lines
192
528
2640 clocks
1320
VSYNC
Data
Enable
HSYNC
560 561 562 563 564 565 566 567 568 569 570 582 583 584 1123 1124 1125
~~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
1440 Clocks for Active Video
288
Data
Enable
1728 Total Horizontal Clocks per line
HSYNC
138 clocks
126
24
Data
Enable
HSYNC
VSYNC
Data
Enable
HSYNC
VSYNC
Field 1: 24 Vertical Blanking Lines
1728 clocks 264
288 Active Vertical Lines per field
~
~
~
~
24
288 Active Vertical Lines per field
Field 2: 25 Vertical Blanking Lines
~
~
623 624 625 1 2 3 4 5 6 7 22 23
~
~
~
~
264
24
1728 clocks
864
310 311 312 313 314 315 316 317 318 319 320 623 624 625335 336
310 311 312
~
~
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Figure 4-12: H:V:DE Input Timing 1920 x 1080p @ 23.94/24 (Format 32)
Figure 4-13: H:V:DE Input Timing 1920 x 1080p @ 25 (Format 33)
148 clocks
1920 Clocks for Active Video
720
Data
Enable
HSYNC
2640 Total Horizontal Clocks per line
44
528
VSYNC
1121 1122 1123 1124 1125 1 2 3 4 5 6 7
Data
Enable
HSYNC
Progressive Frame: 45 Vertical Blanking Lines
2640 clocks
528
1121 1122 1123 1124 1125
192
1080 Active Vertical Lines
~
~
~
~
~
~
41 42
~
~
~
148 clocks
1920 Clocks for Active Video
720
Data
Enable
HSYNC
2640 Total Horizontal Clocks per line
44
528
VSYNC
1121 1122 1123 1124 1125 1 2 3 4 5 6 7
Data
Enable
HSYNC
Progressive Frame: 45 Vertical Blanking Lines
2640 clocks
528
1121 1122 1123 1124 1125
192
1080 Active Vertical Lines
~
~
~
~
~
~
41 42
~
~
~
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Figure 4-14: H:V:DE Input Timing 1920 x 1080p @ 29.97/30 (Format 34)
4.4 DVB-ASI Mode
When operating in DVB-ASI mode, all SMPTE processing features are disabled, and the
device accepts 8-bit transport stream data and control signal inputs on the DIN[19:10]
port.
This mode is only enabled when SMPTE_BYPASS pin is LOW, DVB_ASI pin is HIGH and
the RATE_SEL pin is HIGH.
The interface consists of eight data bits and two control signals, INSSYNCIN and KIN.
When INSSYNCIN is set HIGH, the GS1662 inserts K28.5 sync characters into the data
stream. This function is used to assist system implementations where the GS1662 may
be preceded by a data FIFO.
The FIFO can be fed data at a rate somewhat less than 27MHz. The ‘FIFO empty’ signal
could be used to feed the INSSYNCIN pin, causing the GS1662 to pad the data up to the
transmission rate of 27MHz.
When KIN is set HIGH the data input is interpreted as a special character (such as a K28.5
sync character), as defined by the DVB-ASI standard. When KIN is set LOW the input is
interpreted as data.
After sync signal insertion, the GS1662 8b/10b encodes the data, generating a 10-bit
data stream for the parallel to serial conversion and transmission process.
4.5 Data-Through Mode
The GS1662 may be configured to operate as a simple parallel-to-serial converter. In this
mode, the device passes data to the serial output without performing any scrambling or
encoding.
Data-through mode is enabled only when both the SMPTE_BYPASS and DVB_ASI pins
are set LOW.
148 clocks
1920 Clocks for Active Video280
Data
Enable
HSYNC
2200 Total Horizontal Clocks per line
44
88
VSYNC
1121 1122 1123 1124 1125 1 2 3 4 5 6 7
Data
Enable
HSYNC
Progressive Frame: 45 Vertical Blanking Lines
2220 clocks
88
1121 1122 1123 1124 1125
192
1080 Active Vertical Lines
~
~
~
~
~
~
41 42
~
~
~
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4.6 Standby Mode
The STANDBY pin reduces power to a minimum by disabling all circuits except for the
register configuration. Upon removal of the signal to the STANDBY pin, the device
returns to its previous operating condition within 1 second, without requiring input
from the host interface.
In addition, the serial digital output signals becomes high-impedance when the device
is powered-down.
4.7 ANC Data Insertion
Horizontal or vertical ancillary data words may be inserted on up to four different lines
per video frame.
Up to 512 data words may be inserted per frame with all Data Words - including the ANC
packet ADF, DBN, DCNT, DID, SDID and CSUM words - being provided by the user via
host interface configuration.
The CSUM word is re-calculated and inserted by the ANC Data Checksum Calculation
and Insertion function.
Note that any value may be used for the CSUM word, provided that it is outside the
protected ranges from 000h to 003h and from 3FCh to 3FFh. If a CSUM value in either of
these ranges is used, it will not be corrected by the device.
The GS1662 does not provide error checking or correction to the ANC data provided by
user via the host interface. It is the responsibility of the user to ensure that all data
provided for insertion is fully standard compliant.
In HD mode, ANC data packets are inserted into the Y or C video stream, as selected via
the host interface. The default insertion will be in the Y stream. For Y or C, see Registers
026h, 028h, 02Ah and 02Ch.
In SD mode, the ANC data packets are inserted into the multiplexed CbYCr data stream.
ANC data insertion only takes place if the IOPROC_EN/DIS pin is HIGH and
SMPTE_BYPASS is HIGH.
In addition to this, the GS1662 requires the ANC_INS bit to be set LOW in the IOPROC
register.
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4.7.1 ANC Insertion Operating Modes
User selection of one of the two operating modes is provided through host interface
configuration, using the ANC_INS_MODE register bit (see Table 4-16: Configuration and
Status Registers).
The supported operating modes are Concatenated mode and Separate Line operating
mode.
By default (at power up or after system reset), the Separate Line operating mode is
enabled.
Ancillary data packets are programmed into the ANC_PACKET_BANK host register at
addresses 040h to 13Fh.
4.7.1.1 Separate Line Operating Mode
In Separate Line mode, it is possible to insert horizontal or vertical ancillary data on up
to four lines per video frame. In Separate Line mode, the ANC_PACKET_BANK bits are
separated in four sections. Each section consists of 64 x 16-bit registers.
ANC_PACKET_BANK_1 uses registers 040h to 07Fh. ANC_PACKET_BANK_2 uses
registers 080h to 0BFh. ANC_PACKET_BANK_3 uses registers 0C0h to 0FFh.
ANC_PACKET_BANK_4 uses registers 100h to 13Fh. HANC or VANC can be specified,
independently of each other, on a per-line basis. 025h FIRST_LINE_NUMBER, 027h
SECOND_LINE_NUMBER, 029h THIRD_LINE_NUMBER and 02Bh
FOURTH_LINE_NUMBER. For each of the four video lines, up to 128 8-bit HANC or
VANC data words can be inserted. Separate Line mode is selected by setting the
ANC_INS_MODE bit in the host interface LOW. By default, at power up, Separate Line
mode is selected.
The lines on which ancillary data is to be inserted is programmed in the host register
addresses 025h to 02Ch.
For HD formats, the stream into which the ancillary data is to be inserted (Luma or
Chroma) is also programmed in these register addresses.
The non-zero video line numbers on which to insert the ancillary data, the ancillary data
type (HANC or VANC), and the total number of words to insert per line must be provided
via the host interface (see Section 4.12). At power up, or after system reset, all ancillary
data insertion line numbers and total number of words default to zero.
If the total number of Data Words specified per line exceeds 128 only the first 128 Data
Words will be inserted, the rest will be ignored.
The data words are programmed as two 8-bit values per address, starting at host
interface address 040h in the ANC_PACKET_BANK register (see Table 4-16).
The device automatically converts the provided 8-bit Data Words into the 10-bit data,
formatted according to SMPTE ST 291 prior to insertion.
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4.7.1.2 Concatenated Operating Mode
In Concatenated mode, it is possible to insert up to 512 8-bit horizontal or vertical
ancillary Data Words on one line per video frame. Concatenated Line mode can be
selected by setting the ANC_INS_MODE bit in the host interface HIGH. By default, at
power up, Separate Line mode is selected.
In Concatenated mode, only the FIRST_LINE registers of the host interface need to be
programmed (addresses 025h and 026h). See Table 4-16.
The non-zero video line number on which to insert the ancillary data, the ancillary data
type (HANC or VANC), and the total number of words to insert must be provided via the
host interface. At power up, or after system reset, the ancillary data insertion line
number and total number of words default to zero.
If the total number of data words specified exceeds 512 only the first 512 Data Words
will be inserted, the rest will be ignored.
The data words are programmed as two 8-bit values per address, starting at host
interface address 040h in the ANC_PACKET_BANK register. See Table 4-16.
The device automatically converts the provided 8-bit data words into the 10-bit data
formatted according to SMPTE ST 291 prior to insertion.
4.7.2 HD ANC Insertion
When operating in HD mode (RATE_SEL = LOW), the GS1662 inserts VANC or HANC
data packets into either the Y data stream or C data stream.
By default (at power up or after system reset), all ANC data insertion takes place in the Y
data stream.
The user can select between Y or C data stream for insertion on a per line basis in
Separate Line mode. The Y data stream is selected when the STREAM_TYPE_0 bit is LOW
(default). The C data stream is selected when the STREAM_TYPE_0 bit is HIGH.
The user can select between Y or C data stream for insertion on a single line basis in
Concatenated mode. The Y data stream is selected when the STREAM_TYPE_0 bit is
LOW (default). The C data stream is selected when the STREAM_TYPE_0 bit is HIGH.
Horizontal Ancillary data (HANC), is inserted into the Y or C data stream on the video
line(s) defined by the user.
Data insertion starts at the first available location in the HANC space, following any
pre-existing arbitrary data packets. All Data Words identified by the user are inserted in
a contiguous fashion starting at the first available data space.
HANC data insertion terminates when all Data Words identified by the user have been
inserted; or by the start of the four word TRS SAV code, regardless of the number of Data
Words actually inserted.
Vertical Ancillary data (VANC), is inserted into the Y or C data stream on the video line(s)
defined by the user.
Data insertion starts at the first active pixel immediately following the last word of the
TRS SAV code. All Data Words identified by the user are inserted in a contiguous
fashion, starting at the first active pixel.
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VANC data insertion terminates when all Data Words identified by the user have been
inserted; or by the start of the four word TRS EAV code, regardless of the number of Data
Words actually inserted.
The total number of Data Words to be inserted and the line number on which ANC data
insertion takes place is provided by the user via the host interface as part of the
configuration of the ANC data insertion function.
The user data for insertion is provided via host interface configuration.
STREAM_TYPE_1 = address 02Dh, STREAM_TYPE_0 for the four lines of insertion is at
addresses 026h (bit 14), 028h (bit 14), 02Ah (bit 14) and 02Ch (bit 14).
4.7.3 SD ANC Insertion
When operating in SD mode (RATE_SEL = HIGH), the GS1662 inserts VANC or HANC
data packets into the multiplexed CbYCr data stream.
Horizontal Ancillary data (HANC), is inserted on the video line(s) defined by the user.
Data insertion starts at the first available location in the HANC space following any
pre-existing arbitrary data packets. All Data Words identified by the user are inserted in
a contiguous fashion, starting at the first available data space.
HANC data insertion terminates when all Data Words identified by the user have been
inserted; or by the start of the four word TRS SAV code, regardless of the number of Data
Words actually inserted.
For the case where HANC data insertion is required on the same line as the EDH packet,
data insertion is terminated by the start of the EDH packet, regardless of the number of
Data Words actually inserted.
Vertical Ancillary data (VANC), is inserted into the data stream on the video line(s)
defined by the user.
Data insertion starts at the first active Cb pixel immediately following the last word of
the TRS SAV code. All data words identified by the user are inserted in a contiguous
fashion, starting at the first active pixel.
VANC data insertion terminates when all Data Words identified by the user have been
inserted; or by the start of the four word TRS EAV code, regardless of the number of Data
Words actually inserted.
The total number of data words to be inserted and the line number on which ANC data
insertion takes place is provided by the user via the host interface as part of the
configuration of the ANC data insertion function.
The user data for insertion is provided via host interface configuration.
STREAM_TYPE_1 = address 02Dh, STREAM_TYPE_0 for the four lines of insertion is at
addresses 026h (bit 14), 028h (bit 14), 02Ah (bit 14) and 02Ch (bit 14).
ANC data checksum insertion only takes place if the IOPROC_EN/DIS pin is HIGH, the
SMPTE_BYPASS is HIGH and the ANC_CSUM_INS bit is set LOW in the IOPROC register.
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4.8 Additional Processing Functions
The GS1662 contains a number of signal processing features. These features are only
enabled in SMPTE mode of operation (SMPTE_BYPASS = HIGH), and when I/O
processing is enabled (IOPROC_EN/DIS = HIGH).
Signal processing features include:
• TRS generation and insertion
• Line number calculation and insertion
• Line based CRC calculation and insertion
• Illegal code re-mapping
• SMPTE ST 352 payload identifier packet insertion
• ANC checksum calculation and correction
• EDH generation and insertion
To enable these features in the GS1662, the SMPTE_BYPASS pin must be HIGH, the
IOPROC_EN/DIS pin must be HIGH and the individual feature must be enabled via bits
set in the IOPROC register of the host interface. By default, all of the processing features
are enabled.
4.8.1 Video Format Detection
By using the timing parameters extracted from the received TRS signals, or the supplied
external timing signals, the GS1662 calculates the video format.
The total samples per line, active samples per line, total lines per field/frame, and active
lines per field/frame are measured and reported to the user via the four
RASTER_STRUC_X registers in the host interface.
These line and sample count registers are updated once per frame at the end of line 12.
The RASTER_STRUC_X registers also contain two status bits: STD_LOCK and INT/PROG.
The STD_LOCK bit is set HIGH whenever the automatic video format detection circuit
has achieved full synchronization.
The INT/PROG bit is set LOW if the detected video standard is Progressive, and is set
HIGH if the detected video standard is Interlaced.
The Gennum video standard code (VD_STD), as used in the GS1582 and GS1572, is
included in Table 4-5 for reference purposes.
Note: If proper SMPTE video is applied and then removed from the input, the device
does not flag that the H_LOCK, V_LOCK, VD_SDT etc. has changed (been lost). This is the
case for either TRS detect or HVF modes. This problem occurs only when the video data
is removed, but not the PCLK. Usually, when a video signal is removed, it includes the
clock, the video data, as well as the H, V, F as a whole. So the scenario is not likely to
occur, but the user should be aware of this issue.
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Table 4-5: Supported Video Standards
SMPTE
STANDARD
ACTIVE
VIDEO
AREA
LENGTH
OF
HANC
LENGTH
OF ACTIVE
VIDEO
TOTAL
SAMPLES
SMPTE
ST 352
LINES
Gennum
VD_STD
[4:0]
RATE_
SEL1
ST 428.1 2048x1080/24 (1:1) 690 2048 2750 10 1Ch1
ST 428.1 2048x1080/25 (1:1) 580 2048 2640 10 1Ch1
ST 260 (HD) 1920x1035/60 (2:1) 268 1920 2200 10, 572 15h 0
ST 295 (HD) 1920x1080/50 (2:1) 444 1920 237610, 572 14h 0
ST 274 (HD)
1920x1080/60 (2:1)
or
1920x1080/30 (PsF)
268 1920 2200 10, 572 0Ah 0
1920x1080/50 (2:1)
or
1920x1080/25 (PsF)
708 1920 2640 10, 572 0Ch0
1920x1080/30 (1:1) 268 1920 2200 10 (18)10Bh 0
1920x1080/25 (1:1) 708 1920 2640 10 (18)10Dh 0
1920x1080/24 (1:1) 818 1920 2750 10 (18)110h 0
1920x1080/24 (PsF) 818 1920 2750 10, 572 11h 0
1920x1080/25 (1:1) –
EM 324 2304 2640 10 (18)10Eh 0
1920x1080/25 (PsF) –
EM 324 2304 2640 10, 572 0Fh 0
1920x1080/24 (1:1) –
EM 338 2400 2750 10 (18)112h 0
1920x1080/24 (PsF) –
EM 338 2400 2750 10, 572 13h 0
ST 296 (HD)
1280x720/30 (1:1) 2008 1280 3300 10 (13)102h 0
1280x720/30 (1:1) –
EM 408 2880 3300 10 (13)103h 0
1280x720/50 (1:1) 688 1280 1980 10 (13)104h 0
1280x720/50 (1:1) –
EM 240 1728 1980 10 (13)105h 0
1280x720/25 (1:1) 2668 1280 396010 (13)106h0
1280x720/25 (1:1) –
EM 492 3456396010 (13)107h 0
1280x720/24 (1:1) 2833 1280 4125 10 (13)108h 0
1280x720/24 (1:1) –
EM 513 3600 4125 10 (13)109h 0
1280x720/60 (1:1) 358 1280 1650 10 (13)100h 0
1280x720/60 (1:1) –
EM 198 1440 1650 10 (13)101h 0
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Note 1: The part may provide full or limited functionality with standards that are not
included in this table. Please consult a Semtech technical representative.
By default (at power up or after system reset), the four RASTER_STRUC_X, STD_LOCK
and INT/PROG registers are set to zero. These registers are also cleared when the
SMPTE_BYPASS pin is LOW, or the LOCKED pin is LOW.
Note 2: The Line Numbers in brackets refer to Version zero SMPTE ST 352 packet
locations, if they are different from the Version one locations.
4.8.2 ANC Data Blanking
The GS1662 can blank the video input data during the H and V blanking periods. This
function will be enabled by setting the ANC_BLANK pin LOW.
This function is only available when the device is operating in SMPTE mode
(SMPTE_BYPASS = HIGH).
In this mode, input video data in the horizontal and vertical blanking periods will be
replaced by SMPTE compliant blanking values.
The blanking function will operate only on the video input signal and will remove all
ancillary data already embedded in the input video stream.
In SD mode, SAV and EAV code words already embedded in the input video stream will
be protected and will not be blanked.
In HD mode, SAV and EAV code words, line numbers and line based CRC's already
embedded in the input video stream will be protected and will not be blanked.
The above two statements are really implementation specific, and are provided only to
ensure that the “Detect TRS” function for timing generation is supported by the device,
even when the blanking function is enabled.
ST 125 (SD)
1440x487/60 (2:1)
(Or dual link
progressive)
268 1440 171613, 27616hX
1440x507/60 (2:1) 268 1440 171613, 27617h X
525-line 487 generic−−171613, 27619h X
525-line 507 generic−−171613, 2761Bh X
ITU-R BT.656
(SD)
1440x576/50 (2:1)
(Or dual link
progressive)
280 1440 1728 9, 322 18h X
625-line generic
(EM) −−1728 9, 322 1Ah X
Unknown HD RATE_SEL = 0 −−−−1Dh
Unknown SD RATE_SEL = 1 −−−−1Eh X
Table 4-5: Supported Video Standards (Continued)
SMPTE
STANDARD
ACTIVE
VIDEO
AREA
LENGTH
OF
HANC
LENGTH
OF ACTIVE
VIDEO
TOTAL
SAMPLES
SMPTE
ST 352
LINES
Gennum
VD_STD
[4:0]
RATE_
SEL1
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From a system perspective, use of the input blanking function is not recommended
unless TRS, line number and CRC generation and insertion functions are enabled.
The active image area will not be blanked.
The input blanking function will not blank any of the ancillary data, TRS words, line
numbers, CRC's, EDH or SMPTE ST 352 payload identifiers inserted by the device itself.
4.8.3 ANC Data Checksum Calculation and Insertion
The GS1662 calculates checksums for all detected ancillary data packets presented to
the device.
ANC data checksum insertion only takes place if the IOPROC_EN/DIS pin is HIGH, the
SMPTE_BYPASS is HIGH and the ANC_CSUM_INS bit is set LOW in the IOPROC register.
Note: The device will correct any CSUM value outside the protected ranges from 000h
to 003h and from 3FCh to 3FFh. If a CSUM value in either of these ranges is presented to
the device, it will not be corrected.
4.8.4 TRS Generation and Insertion
The GS1662 is capable of generating and inserting TRS codes.
TRS word generation and insertion are performed in accordance with the timing
parameters generated by the timing circuits, which is locked to the externally provided
H:V:F or CEA-861 signals, or the TRS signals embedded in the input data stream. The
GS1662 will overwrite the TRS signals if they're already embedded.
10-bit TRS code words are inserted at all times.
The insertion of TRS ID words only take place if the IOPROC_EN/DIS pin is HIGH and the
SMPTE_BYPASS pin is HIGH.
In addition to this, the GS1662 requires the TRS_INS bit to be set LOW in the IOPROC
register.
If the TIM_861 pin is HIGH, then the timing circuits are locked to CEA-861 timing.
4.8.5 HD Line Number Calculation and Insertion
The GS1662 is capable of line number generation and insertion, in accordance with the
relevant HD video standard, as determined by the automatic video standard detector.
Line numbers are inserted into both the Y and C channels.
Note: Line number generation and insertion only occurs in HD mode (RATE_SEL =
LOW).
The insertion of line numbers only take place if the IOPROC_EN/DIS pin is HIGH and
SMPTE_BYPASS pin is HIGH.
In addition to this, the GS1662 requires the LNUM_INS bit to be set LOW in the IOPROC
register.
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4.8.6 Illegal Code Re-Mapping
The GS1662 detects and corrects illegal code words within the active picture area.
All codes within the active picture (outside the horizontal and vertical blanking periods),
between the values of 3FCh and 3FFh are re-mapped to 3FBh. All codes within the active
picture area between the values of 000h and 003h are remapped to 004h.
8-bit TRS code words and ancillary data preambles are also re-mapped to 10-bit values.
The illegal code re-mapping will only take place if the IOPROC_EN/DIS pin is HIGH and
SMPTE_BYPASS is HIGH.
In addition to this, the GS1662 requires the ILLEGAL_REMAP bit to be set LOW in the
IOPROC register.
Note: Due to the architecture of the GS1662 serializer, illegal code words appearing in
the middle of a line that look like TRS sequences will be treated as such by the device.
For example, any sequence in the middle of a line that produces 3FFh 000h 000h
followed by another 10-bit word will be treated as a TRS, even if that following word
does not match the XYZh code words allowed by SMPTE.
To avoid this issue, any groupings of words that look like TRS sequence must be kept out
of the active picture portion of the video line or it will not be remapped.
4.8.7 SMPTE ST 352 Payload Identifier Packet Insertion
When enabled by the 352M_INS bit in the IOPROC register, new SMPTE ST 352 payload
identifier packets are inserted into the data stream. These packets are supplied by the
user via the host interface. Setting the 352M_INS bit LOW enables this insertion.
The device will automatically calculate the checksum and generate Version One
compliant ST 352 ancillary data preambles: DID, SDID, DBN, DC.
The SMPTE ST 352 packet is inserted into the data stream according to the line number
and sample position rules defined in the 2002 standard.
For HDTV video systems the SMPTE ST 352 packet is placed in the Y channel only.
By default (at power up or after system reset), the four VIDEO_FORMAT_IN_DS1
registers and the four VIDEO_FORMAT_OUT_DS1 registers are set to zero.
4.8.8 Line Based CRC Generation and Insertion (HD)
When operating in HD mode (RATE_SEL pin = LOW), the GS1662 generates and inserts
line based CRC words into both the Y and C channels of the data stream.
The line based CRC insertion only takes place if the IOPROC_EN/DIS pin is HIGH and
SMPTE_BYPASS is HIGH.
In addition to this, the GS1662 requires the CRC_INS bit to be set LOW in the IOPROC
register.
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4.8.9 EDH Generation and Insertion
When operating in SD mode, the GS1662 generates and inserts EDH packets into the
data stream.
The EDH packet generation and insertion only takes place if the IOPROC_EN/DIS pin is
HIGH, SMPTE_BYPASS pin is HIGH, the RATE_SEL pin is HIGH and the EDH_CRC_INS
bit is set LOW in the IOPROC register.
Calculation of both Full Field (FF) and Active Picture (AP) CRCs is carried out by the
device.
EDH error flags EDH, EDA, IDH, IDA and UES for ancillary data, full field and active
picture are also inserted.
• When the EDH_CRC_UPDATE bit of the host interface is set LOW, these flags are
sourced from the ANC_EDH_FLAG, FF_EDH_FLAG and AP_EDH_FLAG registers of
the device, where they are programmed by the application layer
• When the EDH_CRC_UPDATE bit of the host interface is set HIGH, incoming EDH
flags are preserved and inserted in the outgoing EDH packets. In this mode the
ANC_EDH_FLAG, FF_EDH_FLAG and AP_EDH_FLAG registers contain the
incoming EDH flags, and will be read only
The GS1662 generates all of the required EDH packet data including all ancillary data
preambles: DID, DBN, DC, reserved code words and checksum.
The prepared EDH packet is inserted at the appropriate line of the video stream (in
accordance with RP165). The start pixel position of the inserted packet is based on the
SAV position of that line, such that the last byte of the EDH packet (the checksum) is
placed in the sample immediately preceding the start of the SAV TRS word.
Note 1: When the EDH_CRC_UPDATE bit of the host interface is set LOW, it is the
responsibility of the application interface to ensure that the EDH flag registers are
updated regularly (once per field).
Note 2: It is also the responsibility of the application interface to ensure that there is
sufficient space in the horizontal blanking interval for the EDH packet to be inserted.
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4.8.10 Processing Feature Disable
The GS1662 contains an IOPROC register. This register contains one bit for each
processing feature, allowing the user to enable/disable each process individually.
By default (at power up or after system reset), all of the IOPROC register bits are LOW.
To disable an individual processing feature, the application interface must set the
corresponding bit HIGH in the IOPROC register. To enable these features, the
IOPROC_EN/DIS pin must be HIGH, and the individual feature must be enabled by
setting bits LOW in the IOPROC register of the host interface.
The I/O processing functions supported by the GS1662 are shown in Table 4-6 below.
4.9 Serial Digital Output
The GS1662 has a single, low-impedance current mode differential output driver,
capable of driving at least 800mV into a 75Ω single-ended load.
The output signal amplitude, or swing, will be user-configurable using an external
resistor on the RSET pin.
The serial digital output data rate supports SMPTE ST 292 and SMPTE ST 259-C
operation. This is summarized in Table 4-7:
The SDO and SDO pins of the device provide the serial digital output.
Table 4-6: IOPROC Register Bits
I/O Processing Feature IOPROC Register Bit
TRS insertion TRS_INS (000h Bit 0)
Y and C line number insertion LNUM_INS (000h Bit 1)
Y and C line based CRC insertion CRC_INS (000h Bit 2)
Ancillary data checksum correction ANC_CSUM_INS (000h Bit 3)
EDH CRC error calculation and insertion EDH_ CRC_INS (000h Bit 4)
Illegal word re-mappingILLEGAL_WORD_REMAP (000h Bit 5)
SMPTE ST 352 packet insertion SMPTE_352M_INS (000h Bit 6)
Ancillary data insertion ANC_INS (000h Bit 11)
Table 4-7: Serial Digital Output - Serial Output Data Rate
Parameter Symbol Conditions Min Typ Max Units
Serial Output Data Rate BRSDO
SMPTE ST 292 signal −1.485, 1.485/1.001 −Gb/s
SMPTE ST 259-C signal −270 −Mb/s
DVB-ASI signal −270 −Mb/s
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Compliance with all requirements defined in Section 4.9.1 through Section 4.9.4 is
guaranteed when measured across a 75Ω terminated load at the output of 1m of Belden
1694A cable, including the effects of the Semtech recommended ORL matching
network, BNC and coaxial cable connection, except where otherwise stated.
Figure 4-15 illustrates this requirement, which is in accordance with the measurement
methodology defined in SMPTE ST 292 and SMPTE ST 259-C.
Figure 4-15: ORL Matching Network, BNC and Coaxial Cable Connection
4.9.1 Output Signal Interface Levels
The Serial Digital Output signals (SDO and SDO pins), of the device meet the amplitude
requirements as defined in SMPTE ST 292 for an unbalanced generator (single-ended).
The signal amplitude is controlled to better than +/-7% of the nominal level defined in
SMPTE ST 292, when an external 750Ω 1% resistor is connected between the RSET pin
of the device and VCC.
The output signal amplitude can be reduced to less than 1/10th of the nominal
amplitude, defined above, by increasing the value of the resistor connected between the
RSET pin of the device and VCC.
These requirements are met across all ambient temperature and power supply
operating conditions described in the Electrical Characteristics on page 16.
The output amplitude of the GS1662 can be adjusted by changing the value of the RSET
resistor as shown in Table 4-8. For a 800mVpp output a value of 750Ω is required. A ±1%
SMT resistor should be used.
The RSET resistor is part of the high speed output circuit of the GS1662. The resistor
should be placed as close as possible to the RSET pin. In addition, an anti-pad should be
used underneath the resistor.
DUT
GS1662
ORL
mat c hi n g
network
BNC
1m Belden 1694A 75ohm
coaxial cable
BNC
75 ohm
resistive
load
Measuring device
Table 4-8: RSET Resistor Value vs. Output Swing
RSET Resistor Values (Ω)Output Swing (mVpp)
995 608
824 734
750 800
680 884
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4.9.2 Overshoot/Undershoot
The serial digital output signal overshoot and undershoot is controlled to be less that 7%
of the output signal amplitude, when operating as an unbalanced generator
(single-ended).
This requirement is met for nominal signal amplitudes as defined by SMPTE ST 292.
This requirement is met regardless of the output slew rate setting of the device.
This requirement is met across all ambient temperature and power supply operating
conditions described in the Electrical Characteristics on page 16.
This requirement is summarized in Table 4-9:
4.9.3 Slew Rate Selection
The GS1662 supports two user-selectable output slew rates.
Control of the slew rate is determined by the setting of the RATE_SEL input pin.
When this pin is set HIGH, the output slew rate matches the requirements as defined by
the SMPTE ST 259-C standard.
When this pin is set LOW, the output slew rate is better than the requirements as defined
by the SMPTE ST 292 standard.
These requirements is met across all ambient temperature and power supply operating
conditions described in the Electrical Characteristics on page 16.
This requirement is summarized in Table 4-10:
4.9.4 Serial Digital Output Mute
When the SDO_EN/DIS pin is LOW, the serial digital output signals of the device become
high-impedance, reducing system power.
The serial digital output is also placed in the high-impedance state when the LOCKED
pin is LOW, or when the STANDBY pin is HIGH.
Table 4-9: Serial Digital Output - Overshoot/Undershoot
Parameter Symbol Conditions Min Ty p Max Units
Serial output overshoot /undershoot −−−07%
Table 4-10: Serial Digital Output - Rise/Fall Time
Parameter Symbol Conditions Min Typ Max Units
Serial Output Rise/Fall Time
20% ~ 80% SDOTR
SMPTE ST 292 signal −−135 ps
SMPTE ST 259-C signal 400 −800 ps
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4.10 Serial Clock PLL
An internal VCO provides the transmission clock rates for the GS1662.
The power supply to the VCO is provided to the VCO_VDD/VCO_GND pins of the
device.
This VCO is locked to the input PCLK via an on-chip PLL and Charge Pump.
Internal division ratios for the PCLK are determined by the setting of the RATE_SEL pin
and the 20BIT/10BIT pin as shown in Table 4-11:
As well as generating the serial digital output clock signals, the PLL is also responsible
for generating all internal clock signals required by the device.
4.10.1 PLL Bandwidth
Table 4-12 shows the GS1662 PLL loop bandwidth variations. PLL bandwidth is a
function of the external loop filter resistor and the charge pump current. We
recommend using a 200Ω loop filter resistor, however, this value can be varied from
100Ω to 380Ω, depending on application. Values other than 200Ω are not guaranteed.
As the resistor is changed, the bandwidth will scale proportionately (for example, a
change from a 200Ω to 300Ω resistor will cause a 50% increase in bandwidth). The
charge pump current is preset to 100μA and should not be changed. The external loop
filter capacitor does not affect the PLL loop bandwidth. The external loop filter capacitor
affects PLL loop settling time, phase margin and noise. It is selectable from 1μF to 33μF.
However, it should be kept at 10μF for optimal performance. A smaller capacitor results
in shorter lock time but less stability. A larger capacitor results in longer lock time but
more stability. Narrower loop bandwidths require a larger capacitor to be stable. In other
words, a small loop filter resistor requires a larger loop capacitor.
Table 4-11: PCLK and Serial Digital Clock Rates
External Pin Setting Supplied PCLK
Rate
Serial Digital
Output Rate
RATE_SEL 20BIT/10BIT
LOW HIGH74.25 or
74.25/1.001MHz
1.485 or
1.485/1.001Gb/s
LOW LOW 148.5 or
148.5/1.001MHz
1.485 or
1.485/1.001Gb/s
HIGHHIGH 13.5MHz 270Mb/s
HIGH LOW 27MHz 270Mb/s
Table 4-12: GS1662 PLL Bandwidth
Mode PCLK Frequency
(MHz)
Filter Resistor
(Ω)
Charge Pump
Current (μA)
Bandwidth
(kHz)
SD 13.50 200 100 4.78
SD 27.00 200 100 9.57
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4.10.2 Lock Detect
The Lock Detect block controls the serial digital output signal and indicates to the
application layer the lock status of the device.
The LOCKED output pin is provided to indicate the device operating status.
The LOCKED output signal is set HIGH by the lock detect block under the following
conditions (see Table 4-13):
Any other combination of signal states not included in the above table results in the
LOCKED pin being LOW.
Note: When the LOCKED pin is LOW, the serial digital output is in the muted state.
HD 74.25 200 100 26.32
HD 148.50 200 100 52.63
Table 4-12: GS1662 PLL Bandwidth (Continued)
Mode PCLK Frequency
(MHz)
Filter Resistor
(Ω)
Charge Pump
Current (μA)
Bandwidth
(kHz)
Table 4-13: GS1662 Lock Detect Indication
RESET PLL Lock SMPTE_BYPASS DVB_ASI RATE_SEL
HIGHHIGHHIGHLOWX
HIGHHIGHLOW HIGHHIGH
HIGHHIGHLOW LOWX
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4.11 GSPI Host Interface
Note: When using more than one Semtech serializer or deserializer (SerDes) in the same
design, carefully read this section to see how the GSPI ports of multiple ICs should be
connected to each other. Unlike some previous devices, the SDOUT pin of these SerDes
ICs is a non-clocked, loop-through of SDIN (allowing for multiple devices to be
connected to the GSPI chain). The SDOUT pins of multiple SerDes ICs should not be
bussed together, as was the case with some older generations of SerDes ICs.
The GSPI, or Gennum Serial Peripheral Interface, is a 4-wire interface provided to allow
the application layer to access additional status information through configuration
registers in the GS1662.
The GSPI comprises a Serial Data Input signal (SDIN), Serial Data Output signal (SDOUT),
an active low Chip Select (CS) and a Burst Clock (SCLK).
Because these pins can be shared with the JTAG interface port for compatibility with the
GS1582, an additional control signal pin JTAG/HOST is provided.
When JTAG/HOST is LOW, the GSPI interface is enabled. When JTAG/HOST is HIGH, the
JTAG interface is enabled.
When operating in GSPI mode, the SCLK, SDIN, and CS signals are provided by the
application interface. The SDOUT pin is a non-clocked loop-through of SDIN, and may
be connected to the SDIN of another device, allowing multiple devices to be connected
to the GSPI chain. The interface is illustrated in Figure 4-16 below.
Figure 4-16: GSPI Application Interface Connection
All read or write access to the GS1662 is initiated and terminated by the application host
processor. Each access always begins with a Command/Address Word followed by a
data read to or written from the GS1662.
Application Host
SCLK SCLK
SCLK
SDOUT SDIN
SDOUT
SDOUT
CS
SDIN
SDIN
GS1662
GS1662
CS1 CS
CS2
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4.11.1 Command Word Description
The Command Word consists of a 16-bit word transmitted MSB first and contains a
read/write bit, an Auto-Increment bit and a 12-bit address. Figure 4-17 shows the
command word format and bit configurations.
Command Words are clocked into the GS1662 on the rising edge of the Serial Clock
SCLK, which operates in a burst fashion.
When the Auto-Increment bit is set LOW, each Command Word must be followed by
only one Data Word to ensure proper operation. If the Auto-Increment bit is set HIGH,
the following Data Word will be written into the address specified in the Command
Word, and subsequent data words will be written into incremental addresses from the
previous Data Word. This facilitates multiple address writes without sending a
Command Word for each Data Word.
Figure 4-17: Command Word Format
4.11.2 Data Read or Write Access
Serial data is transmitted or received MSB first synchronous with the rising edge of the
Serial Clock, SCLK. The Chip Select (CS) signal must be active LOW a minimum of 1.5ns
(t0 in Figure 4-19) before the first clock edge to ensure proper operation.
During a Read sequence (Command Word R/W bit set HIGH), a wait state of 148ns (4 x
1/fPCLK, t5 in Figure 4-19) is required between writing the Command Word and reading
the following Data Word. The read bits are clocked out on the negative edges of SCLK.
Note 1: Where several devices are connected to the GSPI chain, only one CS_TMS may
be asserted during a read sequence.
During a Write sequence (Command Word R/W bit set LOW), a wait state of 37ns
(1 x 1/fPCLK, t4 in Figure 4-19) is required between the Command Word and the
following Data Word. This wait state must also be maintained between successive
Command Word/Data Word write sequences. When Auto-increment mode is selected
(AutoInc = 1), the wait state must be maintained between successive Data Words after
the initial Command Word/Data Word sequence.
During the write sequence, all command and following Data Words input at the SDIN
pin are output at the SDOUT pin as is.
When several devices are connected to the GSPI chain, data can be written
simultaneously to all the devices which have CS set LOW.
Note 2: If the application interface performs a Read or Write access after power-up,
prior to the application of a valid serial video input signal, the SCLK frequency must not
exceed 10MHz.
Figure 4-18: Data Word Format
A0A1A2A3A4A5A6A7A8A9A11
MSB LSB
A10R/W RSVRSV AutoInc
D15 D14 D13 D12 D0D1D2D3D4D5D6D7D8D9D11 D10
MSB LSB
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4.11.3 GSPI Timing
Write and Read Mode timing for the GSPI interface is as shown in the following
diagrams:
Figure 4-19: Write Mode
Figure 4-20: Read Mode
Figure 4-21: GSPI Time Delay
SCLK_TCK
CS_TMS
SDIN_TDI
SDOUT_TDO
t
0
t
3
t
1
t
2
R/W
t
8
t
4
t
7
R/W Auto
_Inc
Auto
_Inc
A11
A11
A10
A10
A9
A9
A8
A8
A7
A7
A6
A6A5
A5 A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
D15
D15
D14
D14
D13
D13
D12
D12
D11
D11
D10
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
RSV
RSV
RSV
RSV
SCLK_TCK
CS_TMS
SDIN_TDI
SDOUT_TDO
R/W
R/W Auto
_Inc
Auto
_Inc
A11
A11
A10
A10
A9
A9
A8
A8
A7
A7
A6
A6A5
A5 A4
A4
A3
A3
A2
A2
A1
A1
A0
A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6D5 D4 D3 D2 D1 D0
RSV
RSV
RSV
RSV
t
6
t
5
SDIN_TDI data_0
SDIN_TDI to SDOUT_TDO combinational path for daisy chain connection of multiple GS1662 devices.
SDOUT_TDO data_0
T
DELAY
Table 4-14: GSPI Time Delay
Parameter Symbol Conditions Min Typ Max Units
Delay time tDELAY 50% levels;
+1.8V operation −−10.5 ns
Delay time tDELAY 50% levels;
+3.3V operation −−8.7
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Table 4-15: GSPI AC Characteristics
Parameter Symbol Conditions Min Typ Max Units
CS low before SCLK rising
edget0
50% levels; +3.3V or
+1.8V operation
1.5 −− ns
SCLK periodt112.5 −− ns
SCLK duty cycle t240 50 60%
Input data setup time t31.5 −− ns
Time between end of
Command Word (or data in
Auto-Increment mode) and
the first SCLK of the following
Data Word – write cycle.
t4
PCLK
(MHz) ns
−− ns
unlocked445
13.5 74.2
27.0 37.1
74.25 13.5
148.5 6.7
Time between end of
Command Word (or data in
Auto-Increment mode) and
the first SCLK of the following
Data Word – read cycle.
t5
PCLK
(MHz) ns
−− ns
unlocked1187
13.5 297
27.0 148.5
74.25 53.9
148.5 27
Output hold time (15pF load)t61.5 −− ns
CS HIGH after last SCLK falling
edget7
PCLK
(MHz) ns
−− ns
unlocked445
74.2 74.2
37.10 37.1
74.25 13.5
148.5 6.7
Input data hold time t81.5 −− ns
Note: If the application interface performs a Read or Write access after power-up, prior to the application of a valid serial video input
signal, the SCLK frequency must not exceed 10MHz.
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4.12 Host Interface Register Maps
Table 4-16: Configuration and Status Registers
Address Register Name Bit Name Bit Description R/W Default
000h IOPROC
RSVD 15 Reserved. R 0
DELAY_LINE_ENABLE 14 HIGH - enables the delay line
delay. R/W 0
RSVD 13 Reserved. R 0
EDH_CRC_UPDATE 12
HIGH - preserve incoming EDH
flags and insert into outgoing
EDH packets.
LOW - embed flags from 003 in
EDH packet.
R/W 0
ANC_INS11
HIGH - disable ancillary data
insertion.
LOW - enable ancillary data
insertion.
R0
RSVD 10-9 Reserved.R/W 0
H_CONFIG8
Chooses H configuration;
LOW - Active Picture timing
HIGH - SMPTE H timing
R/W 0
RSVD 7Reserved.R/W 0
SMPTE_352M_INS6
HIGH - disables insertion of
SMPTE ST 352 packets. R/W 0
ILLEGAL_WORD_REMAP 5 HIGH - disables illegal word
remapping.R/W 0
EDH_CRC_INS4HIGH - disables EDH CRC error
correction and insertion. R/W 0
ANC_CSUM_INS3HIGH - disables insertion of
ancillary data checksums. R/W 0
CRC_INS2HIGH - disables insertion of HD
CRC words. R/W 0
LNUM_INS1HIGH - disables insertion of HD
line numbers. R/W 0
TRS_INS0HIGH - disables insertion of TRS
words. R/W 0
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Video Support
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001h ERROR_STAT
RSVD 15-7 Reserved. R 0
TRS_PERR 6
TRS protection error.
LOW - No errors in TRS.
HIGH - Errors in TRS.
R0
Y1_EDH_CS_ERR 5
Same as CS_ERR but only updates
its state when packet being
inspected is an EDH packet.
R0
Y1_CS_ERR 4
HIGH indicates that a checksum
error is detected. It is updated
every time a CS word is present on
the output.
Note: This bit will not be set for
CSUM values in the protected
ranges (from 000h to 003h and
from 3FCh to 3FFh).
R0
FORMAT_ERR 3 HIGH indicates standard is not
recognized for 861D conversion. R0
TIMING_ERR 2
HIGH indicates that the RASTER
measurements do not line up with
the extracted ST 352 packet
information.
R0
NO_352M_ERR 1 HIGH indicates no ST 352 packet
embedded in incoming video. R0
LOCK_ERR 0 HIGH indicates PLL lock error
indication. R0
Table 4-16: Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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Video Support
Final Data Sheet Rev. 4
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002h EDH_FLAG_EXT
RSVD 15 Reserved. R 0
ANC_UES_EXT 14 Ancillary data - unknown error
status flag.R0
ANC_IDA_EXT 13 Ancillary data - internal error
detected already flag.R0
ANC_IDH_EXT 12 Ancillary data - internal error
detected here flag.R0
ANC_EDA_EXT 11 Ancillary data - error detected
already flag.R0
ANC_EDH_EXT 10 Ancillary data - error detected
here flag.R0
FF_UES_EXT 9 EDH Full Field - unknown error
status flag.R0
FF_IDA_EXT 8 EDH Full Field - internal error
detected already flag.R0
FF_IDH_EXT 7 EDH Full Field - internal error
detected here flag.R0
FF_EDA_EXT 6EDH Full Field - error detected
already flag.R0
FF_EDH_EXT 5 EDH Full Field - error detected
here flag.R0
AP_UES_EXT 4 EDH Active Picture - unknown
error status flag.R0
AP_IDA_EXT 3 EDH Active Picture - internal error
detected already flag.R0
AP_IDH_EXT 2 EDH Active Picture - internal error
detected here flag.R0
AP_EDA_EXT 1 EDH Active Picture - error
detected already flag.R0
AP_EDH_EXT 0 EDH Active Picture - error
detected here flag.R0
Table 4-16: Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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Video Support
Final Data Sheet Rev. 4
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003h EDH_FLAG_PGM
RSVD 15 Reserved. R 0
ANC_UES_PGM14
Ancillary data - unknown error
status flag.R0
ANC_IDA_PGM13
Ancillary data - internal error
detected already flag.R/W 0
ANC_IDH_PGM12
Ancillary data - internal error
detected here flag.R/W 0
ANC_EDA_PGM11
Ancillary data - error detected
already flag.R/W 0
ANC_EDH_PGM10
Ancillary data - error detected
here flag.R/W 0
FF_UES_PGM9
EDH Full Field - unknown error
status flag.R/W 0
FF_IDA_PGM8
EDH Full Field - internal error
detected already flag.R/W 0
FF_IDH_PGM7
EDH Full Field - internal error
detected here flag.R/W 0
FF_EDA_PGM6EDH Full Field - error detected
already flag.R/W 0
FF_EDH_PGM5
EDH Full Field - error detected
here flag.R/W 0
AP_UES_PGM4
EDH Active Picture - unknown
error status flag.R/W 0
AP_IDA_PGM3
EDH Active Picture - internal error
detected already flag.R/W 0
AP_IDH_PGM2
EDH Active Picture - internal error
detected here flag.R/W 0
AP_EDA_PGM1
EDH Active Picture - error
detected already flag.R/W 0
AP_EDH_PGM0
EDH Active Picture - error
detected here flag.R/W 0
004h DATA_FORMAT
RSVD 15-10 Reserved. R 0
VD_STD 9-5 Detected video standard.R0
INT_PROGB4
HIGH - interlaced signal
LOW - progressive signal R0
RSVD 3Reserved. R 0
STD_LOCK2
Standard lock indication. Active
HIGH. R0
V_LOCK1
Vertical lock indication. Active
HIGH. R0
H_LOCK0
Horizontal lock indication. Active
HIGH. R0
Table 4-16: Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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Video Support
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005h RSVD RSVD 15-0 Reserved. R 0
006hVSD_FORCE
RSVD 15-6Reserved. R 0
VSD_FORCE5
Use the CSR register STD value
rather than the flywheels STD
value. Active HIGH.
R/W 0
VID_STD_FORCE4-0Force VID STD CSR. R/W 0
007h EDH_STATUS
RSVD 15-2 Reserved. R 0
FF_CRC_V 1 Full Field extracted V bit. R 0
AP_CRC_V 0 Active Picture extracted V bit. R 0
008h FIRST_AVAIL_
POSITION
RSVD 15-1 Reserved. R 0
FIRST_AVAIL_POSITION 0
HIGH - ST 352 insertion occurs on
first available ANC space.
LOW - insert ST 352 packets right
after EAV/CRC1.
R/W 1
009h RSVD RSVD 15-0 Reserved. R 0
00Ah
VIDEO_FORMAT
_352_OUT_
WORD_1
VIDEO_FORMAT_OUT_DS1_
215-8 SMPTE ST 352 luma embedded
packet - byte 2. R/W 0
VIDEO_FORMAT_OUT_DS1_
17-0 SMPTE ST 352 luma embedded
packet - byte 1. R/W 0
00Bh
VIDEO_FORMAT
_352_OUT_
WORD_2
VIDEO_FORMAT_OUT_DS1_
415-8 SMPTE ST 352 luma embedded
packet - byte 4. R/W 0
VIDEO_FORMAT_OUT_DS1_
37-0 SMPTE ST 352 luma embedded
packet - byte 3. R/W 0
00Ch
VIDEO_FORMAT
_352_OUT_
WORD_3
VIDEO_FORMAT_OUT_DS2_
215-8 SMPTE ST 352 chroma embedded
packet - byte 2. R/W 0
VIDEO_FORMAT_OUT_DS2_
17-0 SMPTE ST 352 chroma embedded
packet - byte 1. R/W 0
00Dh
VIDEO_FORMAT
_352_OUT_
WORD_4
VIDEO_FORMAT_OUT_DS2_
415-8 SMPTE ST 352 chroma embedded
packet - byte 4. R/W 0
VIDEO_FORMAT_OUT_DS2_
37-0 SMPTE ST 352 chroma embedded
packet - byte 3. R/W 0
00Eh
VIDEO_FORMAT
_352_IN_
WORD_1
VIDEO_FORMAT_IN_DS1_2 15-8 SMPTE ST 352 luma extracted
packet - byte 2. R0
VIDEO_FORMAT_IN_DS1_1 7-0 SMPTE ST 352 luma extracted
packet - byte 1. R0
00Fh
VIDEO_FORMAT
_352_IN_
WORD_2
VIDEO_FORMAT_IN_DS1_4 15-8 SMPTE ST 352 luma extracted
packet - byte 4. R0
VIDEO_FORMAT_IN_DS1_3 7-0 SMPTE ST 352 luma extracted
packet - byte 3. R0
Table 4-16: Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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Video Support
Final Data Sheet Rev. 4
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010h
VIDEO_FORMAT
_352_IN_
WORD_3
VIDEO_FORMAT_IN_DS2_2 15-8 SMPTE ST 352 chroma extracted
packet - byte 2. R0
VIDEO_FORMAT_IN_DS2_1 7-0 SMPTE ST 352 chroma extracted
packet - byte 1. R0
011h
VIDEO_FORMAT
_352_IN_
WORD_4
VIDEO_FORMAT_IN_DS2_4 15-8 SMPTE ST 352 chroma extracted
packet - byte 4. R0
VIDEO_FORMAT_IN_DS2_3 7-0 SMPTE ST 352 chroma extracted
packet - byte 3. R0
012h RASTER_STRUC_
1
RSVD 15-11 Reserved. R 0
LINES_PER_FRAME 10-0 Total lines per frame. R 0
013h RASTER_STRUC_
2
RSVD 15-14 Reserved. R 0
WORDS_PER_LINE 13-0 Total words per line. R 0
014h RASTER_STRUC_
3
RSVD 15-13 Reserved. R 0
ACTIVE_WORDS_PER
_LINE 12-0 Words per active line. R 0
015h RASTER_STRUC_
4
RSVD 15-11 Reserved. R 0
ACTIVE_LINES_PER_FIELD 10-0 Active lines per frame. R 0
016h -
023h RSVD RSVD −Reserved. R 0
024h
FIRST_LINE_
NUMBER_
STATUS
RSVD 15-2 Reserved. R 0
PACKET_MISSED 1
ANC data packet could not be
inserted in its entirety.
HIGH - ANC packet cannot be
inserted in it’s entirety.
R0
RW_CONFLICT0
Same RAM address was read and
written to at the same time.
HIGH - one of the addresses from
040h to 13Fh was read and
written to at the same time.
R0
025h FIRST_LINE_
NUMBER
RSVD 15-12 Reserved. R 0
ANC_INS_MODE 11
ANC data insertion mode.
HIGH - Concatenate
LOW - Separate
R/W 0
FIRST_LINE_NUMBER 10-0 First line number to insert ANC
packet on. R/W 0
Table 4-16: Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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Video Support
Final Data Sheet Rev. 4
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026h
FIRST_LINE_
NUMBER_OF_
WORDS
FIRST_LINE_NUMBER_ANC_T
YPE 15
ANC region to insert packet in
HIGH - VANC,
LOW - HANC.
R/W 0
FIRST_LINE_NUMBER
_STREAM_TYPE 14
Stream to insert packet in HIGH - C
stream,
LOW - Y stream.
R/W 0
RSVD 13-10 Reserved. R 0
FIRST_LINE_NUMBER
_OF_WORDS9-0 Total number of words in ANC
packet to be inserted in first line. R/W 0
027h SECOND_LINE_
NUMBER
RSVD 15-11 Reserved. R 0
SECOND_LINE_NUMBER 10-0 Second line number to insert ANC
packet on in Separate Line mode. R/W 0
028h
SECOND_LINE_
NUMBER_OF_
WORDS
SECOND_LINE_NUMBER
_ANC_TYPE 15
ANC region to insert packet in
HIGH - VANC,
LOW - HANC.
R/W 0
SECOND_LINE_NUMBER
_STREAM_TYPE 14
Stream to insert packet in HIGH - C
stream,
LOW - Y stream.
R/W 0
RSVD 13-10 Reserved. R 0
SECOND_LINE_NUMBER
_OF_WORDS9-0
Total number of words in ANC
packet to be inserted in second
line.
R/W 0
029h THIRD_LINE_
NUMBER
RSVD 15-11 Reserved. R 0
THIRD_LINE_NUMBER 10-0 Third line number to insert ANC
packet on in Separate Line mode. R/W 0
02Ah
THIRD_LINE_
NUMBER_OF_
WORDS
THIRD_LINE_NUMBER
_ANC_TYPE 15
ANC region to insert packet in.
HIGH - VANC,
LOW - HANC.
R/W 0
THIRD_LINE_NUMBER
_STREAM_TYPE 14
Stream to insert packet in.
HIGH - C stream,
LOW - Y stream.
R/W 0
RSVD 13-10 Reserved. R 0
THIRD_LINE_NUMBER
_OF_WORDS9-0 Total number of words in ANC
packet to be inserted in third line. R/W 0
02Bh FOURTH_LINE_
NUMBER
RSVD 15-11 Reserved. R 0
FOURTH_LINE_NUMBER 10-0 Fourth line number to insert ANC
packet on in Seperate Line mode. R/W 0
Table 4-16: Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1662 HD/SD-SDI Serializer with Complete SMPTE
Video Support
Final Data Sheet Rev. 4
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02Ch
FOURTH_LINE_
NUMBER_OF_
WORDS
FOURTH_LINE_NUMBER
_ANC_TYPE 15
ANC region to insert packet in
HIGH - VANC,
LOW - HANC.
R/W 0
FOURTH_LINE_NUMBER
_STREAM_TYPE 14 Stream to insert packet in 1-C
stream, 0-Y stream. R/W 0
RSVD 13-10 Reserved. R 0
FOURTH_LINE_NUMBER
_OF_WORDS9-0
Total number of words in ANC
packet to be inserted in fourth
line.
R/W 0
02Dh STREAM_TYPE_
1
RSVD 15-5 Reserved. R 0
EDH_LINE_CHECK_EN 4
HIGH - ANC block will not insert
data into the EDH region of the
HANC space.
LOW - ANC block will insert data
into the EDH region.
R/W 1
STREAM_TYPE1_LINE_4 3
HIGH - data for the fourth line in
separate mode is inserted into the
Chroma Stream.
LOW - Luma Stream.
R/W 0
STREAM_TYPE1_LINE_3 2
HIGH - data for the third line in
separate mode is inserted into the
Chroma Stream.
LOW - Luma Stream.
R/W 0
STREAM_TYPE1_LINE_2 1
HIGH - data for the second line in
separate mode is inserted into the
Chroma Stream.
LOW - Luma Stream.
R/W 0
STREAM_TYPE1_LINE_1 0
HIGH - data for the first line in
separate mode is inserted into the
Chroma Stream.
LOW - Luma Stream.
R/W 0
02Eh -
03Fh RSVD RSVD 15-0 Reserved. R 0
040h -
07Fh
ANC_PACKET
_BANK_1 ANC_PACKET_BANK 15-0
First bank of user-defined 8-bit
ancillary data.
Bit 15 - 8: 2nd byte (MSB to LSB)
Bit 7 - 0: 1st byte (MSB to LSB)
See 4.7 ANC Data Insertion.
WO −
080h -
0BFh
ANC_PACKET
_BANK_2 ANC_PACKET_BANK 15-0
Second bank of user-defined 8-bit
ancillary data.
Bit 15 - 8: 2nd byte (MSB to LSB)
Bit 7 - 0: 1st byte (MSB to LSB)
See 4.7 ANC Data Insertion.
WO −
Table 4-16: Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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Video Support
Final Data Sheet Rev. 4
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0C0h -
0FFh
ANC_PACKET
_BANK_3 ANC_PACKET_BANK 15-0
Third bank of user-defined 8-bit
ancillary data.
Bit 15 - 8: 2nd byte (MSB to LSB)
Bit 7 - 0: 1st byte (MSB to LSB)
See 4.7 ANC Data Insertion.
WO −
100h -
13Fh
ANC_PACKET
_BANK_4 ANC_PACKET_BANK 15-0
Fourth bank of user-defined 8-bit
ancillary data.
Bit 15 - 8: 2nd byte (MSB to LSB)
Bit 7 - 0: 1st byte (MSB to LSB)
See 4.7 ANC Data Insertion.
WO −
140h -
209h RSVD RSVD −Reserved. R 0
20Ah SDTI_TDM
RSVD 15-8 Reserved. R 0
SDTI_TDM_DS27
HIGH indicates an SDTI type signal
on input for the Chroma Stream. R/W 0
SDTI_TDM_DS16HIGH indicates an SDTI type signal
on input for the Luma Stream. R/W 0
RSVD 5-0 Reserved. R 0
20Bh -
20Dh RSVD RSVD 15-0 Reserved. R 0
20Eh DRIVE_
STRENGTH
RSVD 15-4 Reserved.R/W 0
LOCKED_DS3-2
Drive strength value for LOCKED
pin.
00: 4mA;
01: 6mA;
10: 8mA(+1.8V), 10mA(+3.3V);
11: 10mA(+1.8V), 12mA(+3.3V)
R/W 0
SDOUT_TDO_DS1-0
Drive strength value for
SDOUT_TDO pin.
00: 4mA;
01: 6mA;
10: 8mA(+1.8V), 10mA(+3.3V);
11: 10mA(+1.8V), 12mA(+3.3V)
R/W 2
20Fh RSVD RSVD 15-0 Reserved.R/W 0
210h DRIVE_
STRENGTH2
TDO_DS15-14
Drive strength value for TDO pin.
00: 4mA;
01: 6mA;
10: 8mA(+1.8V), 10mA(+3.3V);
11: 10mA(+1.8V), 12mA(+3.3V)
R/W 0
RSVD 13-0 Reserved.R/W 0
211h -
232h RSVD RSVD 15-0 Reserved. R 0
Table 4-16: Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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Video Support
Final Data Sheet Rev. 4
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4.13 JTAG ID Codeword
The Platform ID for the GS16x2 family is 0Fh.
The part number field of the JTAG ID codeword for the GS1662 is set to 0F00h.
4.14 JTAG Test Operation
When the JTAG/HOST pin is HIGH, the GSPI host interface port is configured for JTAG
test operation.
In this mode the SCLK, SDIN, SDOUT and CS become TCK, TDI, TDO and TMS. In
addition, the TRST pin becomes active.
Boundary scan testing using the JTAG interface is enabled in this mode. When the
JTAG/HOST pin is LOW, the dedicated JTAG interface is used. In this mode the TCK, TDI,
TDO and TMS pins are active. This is the recommended mode for new designs.
4.15 Device Power-Up
Because the GS1662 is designed to operate in a multi-voltage environment, any
power-up sequence is allowed. The Charge Pump, Phase Detector, Core Logic, Serial
Digital Output and I/O Buffers can all be powered up in any order.
4.16 Device Reset
Note: At power-up, the device must be reset to operate correctly.
In order to initialize all internal operating conditions to their default states, hold the
RESET signal LOW for a minimum of treset = 1ms after all power supplies are stable. There
are no requirements for power supply sequencing.
When held in reset, all device outputs will be driven to a high-impedance state.
Figure 4-22: Reset Pulse
Supply Voltage
RESET
95% of Nominal Level
Nominal Level
Reset Reset
t
reset
t
reset
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Video Support
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5. Application Reference Design
5.1 Typical Application Circuit
Figure 5-1: Typical Application Circuit
SDO
SDO
TDO
TCK
TMS
TDI
PCLK
CD_VDD
GND_A
GND_A
+1.2V_A
GND_A
+1.2V IO_VDD
GND_A
+1.2V_A
GND_A
CD_VDD
GND_A
GND_A
+3.3V_A
Return Loss Compensation Network
SDI Output
Video Data, Clock & Timing Input
(SUBJECT TO CHANGE)
Notes:
1. DNP (Do Not Populate).
2. The value of the series resistors on video data, clock, and timing
connections should be determined by board signal integrity test. (See Section 4.1.1)
3. For analog power and ground isolation refer to PCB layout guide.
4. For impedance controlled signals refer to PCB layout guide.
Close to GS1662.
Close to
GS1662.
SDO
SDO
PCLK
VCO_VDD B7
VBG
A8
VCO_GND
B8
TDI E7
RSV
A9
TIM_861
G3
PCLK
B4
IO_VDD G1
DIN 18
A2 DIN 19
B3
LF
A7
A_VDD A10
B10
DIN 17
A1
CORE_VDD K8
H6
DETECT_TRS
F3
CORE_GND
E6
A_GND
B9
DIN 16
B2
CORE_VDD G10
PLL_VDD A6
PLL_VDD B6
D5
STANDBY
D3
K7
J7
J6
DIN 14
C2 DIN 15
B1
CORE_GND
C5 CORE_GND
B5
D6
D7
DVB_ASI
G5
LOCKED H4
H5
K6
DIN 12
C3 DIN 13
C1
D8
TMS E8
TDO F8
RATE_SEL
E3
CORE_GND
E5
CORE_VDD E1
K5
IO_VDD H10
DIN 10
D2 DIN 11
D1
F4
TCK J8
CORE_GND
G9
20bit/10bit
G4
CORE_GND
F5
CORE_VDD A5
J5
IO_GND
G2
DIN 8
F2 DIN 9
F1
F7
CD_GND
F9 CD_GND
E9
IOPROC_EN/DIS
G7
SMPTE_BYPASS
G6
RESET G8
J4
ANC_BLANK
H3
DIN 6
H2 DIN 7
H1
CD_GND
D9
CORE_GND
E2
H7
CS_TMS K9
SCLK_TCK J10
SDOUT_TDO J9
K4
H/HSYNC
A4
DIN 4
J2 DIN 5
J1
CORE_GND
F6
PLL_GND
C8 PLL_GND
C7 PLL_GND
C6
SDO_EN/DIS
D4
SDIN_TDI K10
V/VSYNC
C4
IO_GND
H9
DIN 2
K2 DIN 3
K1
RSET F10
CD_VDD E10
SDO C10
SDO D10
CD_GND
C9
JTAG/HOST H8
F/DE
A3
DIN 0
K3 DIN 1
J3
GS1662-IBE3
10µF
200
Ω
75
Ω
1µF
1
3
2
5.6nH
75
Ω
1
3
2
5.6nH
10nF
DNP
105
Ω
4.7µF
10nF
DNP
75
Ω
10n
10µF
100pF
75
Ω
750
Ω
10nF
DIN[19:0]
+1.2V_A
0Ω
10nF
+1.2V
10nF
10nF
10nF 10nF
IO_VDD
+1.2V
10nF
Power Filtering
10nF 10nF
GND_A
+3.3V_A
0Ω
10nF
10nF
GND_A
1µF
1µF
1µF
1µF
Power Decoupling
Place clos e to GS1662
1µF 1µF
IO_VDD
1µF
+3.3V CD_VD D
0Ω
10nF
10nF
GND_A
TIM_861
DETECT_TRS
STANDBY
DVB_ASI
RATE_SEL
LOCKED
RESET
CS_TMS
SCLK_TCK
SDOUT_TDO
SDIN_TDI
JTAG/HOST
H/HSYNC
V/VSYNC
F/DE
CD_VDD
IOPROC_EN/DIS
20BIT/10BIT
SDO_EN/DIS
SMPTE_BYPASS
0Ω
GND_A
GND_A
A_GND
ANC_BLANK
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
RSV
RSV
RSV
E4
IO_GND
4.7µF
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Video Support
Final Data Sheet Rev. 4
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6. References & Relevant Standards
SMPTE ST 125 Component video signal 4:2:2 – bit parallel interface
SMPTE ST 259 10-bit 4:2:2 Component and 4fsc Composite Digital Signals - Serial Digital
Interface
SMPTE ST 260 1125 / 60 high definition production system – digital representation and
bit parallel interface
SMPTE ST 267 Bit parallel digital interface – component video signal 4:2:2 16 x 9 aspect
ratio
SMPTE ST 272 Formatting AES/EBU Audio and Auxiliary Data into Digital Video Ancillary
Data Space
SMPTE ST 274 1920 x 1080 scanning analog and parallel digital interfaces for multiple
picture rates
SMPTE ST 291 Ancillary Data Packet and Space Formatting
SMPTE ST 292 Bit-Serial Digital Interface for High-Definition Television Systems
SMPTE ST 293 720 x 483 active line at 59.94Hz progressive scan production – digital
representation
SMPTE ST 2961280 x 720 scanning, analog and digital representation and analog
interface
SMPTE ST 305 Serial Data Transport Interface
SMPTE ST 348 High Data-Rate Serial Data Transport Interface (HD-SDTI)
SMPTE ST 352 Video Payload Identification for Digital Television Interfaces
SMPTE ST 372 Dual Link ST 292 Interface for 1920 x 1080 Picture Raster
SMPTE RP165 Error Detection Checkwords and Status Flags for Use in Bit-Serial Digital
Interfaces for Television
SMPTE RP168 Definition of Vertical Interval Switching Point for Synchronous Video
Switching
CEA 861Video Timing Requirements
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Video Support
Final Data Sheet Rev. 4
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7.2 Packaging Data
7.3 Marking Diagram
Figure 7-2: Marking Diagram
Table 7-1: Packaging Data
Parameter Value
Package Type 11mm x 11mm 100-ball LBGA
Package Drawing ReferenceJEDEC M0192 (with exceptions noted in
Package Dimensions on page 68).
Moisture Sensitivity Level 3
Junction to Case Thermal Resistance, θj-c10.4°C/W
Junction to Air Thermal Resistance, θj-a (at
zero airflow) 37.1°C/W
Junction to Board Thermal Resistance, θj-b26.4°C/W
Psi, ψ0.4°C/W
Pb-free and RoHS Compliant Yes
GS1662
XXXXXXE3
YYWW
Pin 1 ID
XXXXXX - Last 6 digits (excluding decimal)
of SAP Batch Assembly (FIN) as listed
on Packing Slip.
E3 - Pb-free & Green indicator
YYWW - Date Code
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Video Support
Final Data Sheet Rev. 4
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7.4 Solder Reflow Profiles
The GS1662 is available in a Pb-free package. It is recommended that the Pb-free
package be soldered with Pb-free paste using the reflow profile shown in Figure 7-3.
Figure 7-3: Pb-free Solder Reflow Profile
7.5 Ordering Information
25°C
150°C
200°C
217°C
260°C
250°C
Time
Temperature
8 min. max
60-180 sec. max
60-150 sec.
20-40 sec.
3°C/sec max
6°C/sec max
Table 7-2: Ordering Information
Part Number Package Pb-free Temperature Range
GS1662-IBE3 100-ball BGA Yes -20°C to 85°C
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DOCUMENT IDENTIFICATION
FINAL DATA SHEET
Information relating to this product and the application or design described
herein is believed to be reliable, however such information is provided as a
guide only and Semtech assumes no liability for any errors in this document, or
for the application or design described herein. Semtech reserves the right to
make changes to the product or this document at any time without notice.
GS1662 HD/SD-SDI Serializer with Complete SMPTE
Video Support
Final Data Sheet Rev. 4
GENDOC-053628 September 2013
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71
Contact Information
Semtech Corporation
Gennum Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A
STATIC-FREE WORKSTATION
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