This document is a general product descriptio n and is subject to change wit hout noti ce. Hyni x does no t assume an y respon sibilit y for
use of circuits described. No patent licenses are implied.
Rev. 0.0 / Feb. 2007 1
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
32Gb NAND FLASH
HY27UK08BGFM
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Document Title
32Gbit (4Gx8bit) NAND Flash Memory
Revision History
Revision
No. History Draft Date Remark
0.0 Initial Draft. Feb. 09. 2007 Initial
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V
: HY27UK08BGFM
Memory Cell Array
= (2K+ 64) Bytes x 64 Pages x 16,384 Blocks
PAGE SIZE
- x8 device : (2K + 64 spare) Bytes
: HY27UK08BGFM
BLOCK SIZE
- x8 device: (128K + 4K spare) Bytes
PAGE READ / PROGRAM
- Random access: 25us (max.)
- Sequential access: 30ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
CACHE PROGRAM MODE
- Internal Cache Register to improve the program
throughput
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
STATUS REGISTER
ELECTRONIC SIGNATURE
- 1st cycle: Manufacturer Code
- 2nd cycle: Device Code.
CHIP ENABLE DON'T CARE
- Simple interface with microcontroller
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
DATA INTEGRITY
- 100,000 Program/Erase cycles (with 1bit/512byte ECC)
- 10 years Data Retention
PACKAGE
- HY27UK08BGFM-TP
: 48-pin TSOP DSP (12 x 20 x 2.3 mm)
- HHY27UK08BGFM-TP (Lead Free)
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
1. SUMMARY DESCRIPTION
The HYNIX HY27UK08BGFM series is a 4Gx8bit capacity. The device is offered in 3.3V Vcc Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
data is erased.
The device contains 16,384 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells.
A program operation allows to write the 2112-byte pa ge in t ypical 200us an d an er as e op er ation can be perf orm ed in
typical 2ms on a 128K-byte block.
Data in the page mode can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interf ace allows a reduced pin count an d easy migr ation towards dif-
ferent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modifying can be locked using the WP input pin.
The output pin R/B (open drain buffer) signa ls the status of the d evice d uring each operation. In a system with multi-
ple memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27UK08BGFM extended reliability of 100K program/
erase cycles by providing ECC (E rror Correcting Code) with real time mapping-out algorithm.
The chip could be offered with the CE don’t care function. This function allows the direct download of the code from
the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: whe n a page progr am operat ion fails
the data can be directly programmed in another page inside the same arr ay section without the time consuming serial
data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the
flash array. This pipelined program operation improves the program throughput when long files are written inside the
memory.
A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-
secutive pages have to be streamed out.
This device includes also extra features like OTP/Unique ID area, Read ID2 extension.
The HY27UK08BGFM is available in 48 - TSOP1 - DSP 12 x 20 mm package.
1.1 Product List
PART NUMBER ORIZATION VCC RANGE PACKAGE
HY27UK08BGFM x8 2.7V - 3.6 Volt 48TSOP1
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Figure1: Logic Diagram
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CLE Command latch enable
ALE Address latch enable
CE Chip Enable
RE Read Enable
WE Write Enable
WP Write Protect
R/B Ready / Busy
Vcc Power Supply
Vss Ground
NC No Connection
Table 1: Signal Names
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
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Figure 2. 48TSOP1 - DSP Contactions, x8 Device (4CE)
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
1.2 PIN DESCRIPTION
Pin Name Description
IO0-IO7
DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read / program
operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to
High-Z when the device is deselected or the outputs are disabled.
CLE COMMAND LATCH ENABLE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Write Enable (WE).
ALE ADDRESS LAT CH ENABLE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of
Write Enable (WE).
CE1, CE2CHIP ENABLE
This input controls the selection of the device. When the device is busy CE1, CE2 low does not deselect
the memory.
CE3, CE4CHIP ENABLE
The input enable the second HY27UW08AG5M
WE WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE.
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE which also increments the internal column address counter by
one.
WP WRITE PROTECT
The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)
operations.
R/B1 / R/B2
R/B3 / R/B4READY BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VCC SUPPLY VOLTAGE
The VCC supplies the power for all the operations (Read, Write, Erase).
VSS GROUND
NC NO CONNECTION
Table 2: Pin Description
NOTE:
1. A 0.1uF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple
the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required
during program and erase operations.
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
FUNCTION 1st CYCLE 2nd CYCLE 3rd CYCLE Acceptable command
during busy
READ 1 00h 30h -
READ FOR COPY-BACK 00h 35h -
READ ID 90h - -
RESET FFh - - Yes
PAGE PROGRAM (start) 80h 10h -
COPY BACK PGM (start) 85h 10h -
CACHE PROGRAM 80h 15h -
BLOCK ERASE 60h D0h -
READ STATUS REGISTER 70h - - Yes
RANDOM DATA INPUT 85h - -
RANDOM DATA OUTPUT 05h E0h -
CACHE READ START 00h 31h -
CACHE READ EXIT 34h - -
Table 4: Command Set
Table 3: Address Cycle Map(4CE)
1. L must be set to Low.
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7
1st Cycle A0 A1 A2 A3 A4 A5 A6 A7
2nd Cycle A8 A9 A10 A11 L(1) L(1) L(1) L(1)
3rd Cycle A12 A13 A14 A15 A16 A17 A18 A19
4th Cycle A20 A21 A22 A23 A24 A25 A26 A27
5th Cycle A28 A29 A30 L(1) L(1) L(1) L(1) L(1)
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
CLE ALE CE WE RE WP MODE
H L L Rising H X Read Mode Command Input
L H L Rising H X Address Input(5 cycles)
H L L Rising H H Wri te Mode Command Input
L H L Rising H H Address Input(5 cycles)
LLLRisingHHData Input
LL
L(1) H Falling X Sequential Read and Data Output
L L L H H X During Read (Busy)
XXXXXHDuring Program (Busy)
XXXXXHDuring Erase (Busy)
XXXXXLWrite Protect
XXHXX0V/VccStand By
Table 5: Mode Selection
NOTE:
1. With the CE high during latency time does not stop the read operation
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitch es less than 5 ns o n Chip Enab le, W rite Enab le and R ead Ena ble ar e ignore d by the memo ry and do not
affect b us operations.
2.1 Command Input.
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Moreover for commands that starts a modifying operation (write/erase) the Write Protect pin
must be high. See figure 4 and table 12 for details of the timings requirements. Command codes ar e always applied on
IO7:0, disregarding the bus configuration.
2.2 Address Input.
Address Input bus op er ation allows the ins ertion of the memory addr ess. To insert the 30 addr esses needed to access
the 16Gbit 5 clock cycles are needed. Addresses are accepted with Chip Enable low, Address Latch Enable High, Com-
mand Latch Enable low and R ead Enable high and latche d on the rising edge of Write Enable. More over f or commands
that starts a modify operation (write/er ase) the W rite Protect pin must be high. See figure 5 and table 12 f or details of
the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration.
2.3 Data Input.
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and
timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command
Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enab le. See figure
6 and table 12 for details of the timings requirements.
2.4 Data Output.
Data Output bus operation allows to re ad data from the memory arr ay and to check the status register content, the ID
data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write Enable High, Address
Latch Enable low, and Command Latch Enable low. See figures 7,9,10 and table 12 for details of the timings require-
ments.
2.5 Write Protect.
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the pro-
tection even during the power up.
2.6 Standby.
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read.
Page read operation is initiated by writing 00h and 30h to the command register along with five address cycles. In two
consecutive read operations, the second one doesn’t’ need 00h command, which five address cycles and 30h com-
mand initiates that operation. Two types of operations are available : random read, serial page read. The random read
mode is enabled when the page address is changed. The 2112 bytes of data within the selected page are transferred
to the data registers in less than 25us(tR). The system controller may detect the completion of this data transfer (tR)
by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in
30ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device out-
put the data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data out-
put command.
The column address of next data, which is going to be out, may be cha nged to the address which follows r andom data
output command.
Random data output can be operated multiple times regardless of how many times it is done in a page.
3.2 Page Program.
The device is progr ammed basically by pa ge, but it does allow multiple par tial page pr ogr amming of a word or consec-
utive bytes up to 2112 , in a single page program cycle.
The number of consecutive partial page programming operation within the same page without an intervening erase
operation must not exceed 8; for example, 4 times for main array and 4 times for spare array.
The addressing should be done in sequential order in a block. A page program cycle consists of a serial data
loading period in which up to 2112bytes of data may be loaded into the data register, followed by a non-volatile pro-
gramming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle
address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The
device supports random data input in a page. The column address of next data, which will be entered, may be
changed to the address which follows random data input command (85h). Random data input may be opera ted multi-
ple times regardless of how many times it is done in a page.
The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously
entering the serial data will not initiate the pr ogr am ming process . The internal write s tate contro ller automatically ex e-
cutes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other
tasks. Once the progr am process starts, the R ead Status Regis ter command may be entered to read the status register.
The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/
O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write verify
detects only errors for "1"s that are not successfully programme d to "0"s . The command r egister r ema ins in Read Sta-
tus command mode until another valid command is written to the command register. Figure 13 details the sequence.
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
3.3 Block Erase.
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an
Erase Setup command (60h). Only address A18 to A30 is valid while A12 to A17 is ignored. The Erase Confirm com-
mand (D0h) f ollo wing the block add ress l oading in itiates the in ternal er asing pr ocess. This two-step sequence of setup
followed by execution command ensures that memory contents are not accidentally erased due to external noise con-
ditions. At the rising edge of WE after the er ase confirm command input, the internal write controller handles erase and
erase-verify. Once the erase proces s starts, the Read Status Regis ter com mand may be entered to r ead the status re g-
ister. The system controller can detect the completion of an erase by monitoring the R/B output, or the Status bit (I/O
6) of the Status Register. Only the Read Status command and Reset command are valid while erasing is in progress.
When the erase operation is completed, the Write Status Bit (I/O 0) may be checked.
Figure 18 details the sequence.
3.4 Copy-Back Program.
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an
external memory. Since the time-consuming cycles of serial access and re-loading cycles are remove d, the system per-
formance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block
also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a
sequential execution of page-read without serial access and copying-program with the address of destination page. A
read oper ation with "35h" command an d the address of the source page moves the whole 2112byte data into the inter-
nal data buffer. As soon as the device returns to Ready state, Copy Back command (85h) with the address cycles of
destination page may be writ ten. The Pr ogram Confirm command (10h) is required to actua lly begin the progra mming
operation. Data input cycle for modifying a portion or multiple distant portions of the source pa ge is allowed a s s hown
in Figure 15.
"When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if
Copy-Back operations are accumulated over time, bit e rror due to charge loss is not checked by external
error detection/correction scheme. For this reason, two bit error correction is recommended for the use
of Copy-Back operation."
Figure 15 shows the command sequence for the copy-back operation.
The Copy Back Program operation requires three steps:
1. The source page must be read using the Read A command (one bus write cycle to setup the command and then
5 bus write cy cles to inp ut the sour ce page address). This oper ation copies all 2KBytes from the page into the P a ge
Buffer.
2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is
given with the 5bus cycles to input the target page address. A30 must be the same fo r the Source and Target P ages.
3. Then the confirm command is issued to start the P/E/R Controller.
Note:
1. Copy-Back Program operation is allowed only within the same memory plane.
2. On the same plane, It’s prohibited to operate copy-back program from an odd address page (source page) to an
even address page (target page) or from an even address page (source page) to an odd address page (target page).
Therefore, the copy-back program is permitted just between odd address pages or even address pages.
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
3.5 Read Status Register.
The device contains a Status Register which ma y be read to find out whether rea d, progra m or erase oper ation is com-
pleted, and whether the progr am or er as e oper a tion is c omplet ed successf u lly. After writing 70h co mmand to the com-
mand register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE,
whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory
connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer
to table 13 for specific Status Register definitions. The command register remains in Status Read mode until further
commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command
(00h) should be given before starting read cycles. See figure 9 for details of the Read Status operation.
3.6 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an
address input of 00h. F our read cy cles sequentially output the manufacturer code (ADh), and the dev ice code and 3rd
cycle ID , 4th cycle ID, re spectively. The command register remains in Read ID mode until fu rther commands are issued
to it. Figure 19 shows the operation sequence, while tables 15 explain the byte meaning.
3.7 Reset.
The device offers a reset feature, executed by writing FFh to the command re gis ter. When the device is in Busy state
during random read, pr ogr am or er ase mode, the res et operation will abort these operations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is
cleared to wait for the next comm and, and the Status R egister is clear ed to value E0h when WP is high. Ref er to table
13 for device status after reset operation. If the device is already in reset state a new reset command will not be
accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer
to figure 24.
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
3.8 Cache Program.
Cache Program is an extension of P age Progr am, which is execute d with 2112byte data registers, and is a v ailable only
within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in
data register are programmed into memory cell. After writing the first set of data up to 2112byte into the selected
cache registers, Cache Program command (15h) instead of actual Page Pr ogram (10h) is input to make cache re gisters
free and to start internal program operation. To transfer data from cache registers to data registers, the device
remains in Busy state f or a short period of time (tCBSY) an d has its cache registers ready for the ne xt data-input while
the internal programming gets started with the data loaded into data registers. Read Status command (70h) may be
issued to find out when cache registers become ready by polling the Cache-Busy status bit (I/O 6). Pass/fail status of
only the previous page is available upon the return to Ready state. When the next set of data is input with the Cache
Program command, tCBSY is affected by the progress of pending internal programming. The programming of the
cache registers is initiated only when the pending program cycle is finished and the data registers are av ailable for the
transfer of data from cache registers. The status bit (I/O5) for internal Ready/Busy may be polled to identify the com-
pletion of internal programming.
If the system monitors the p rogress of pr ogr amming only with R/B , the last page of the target progr amming sequence
must be programmed with actual Page Program command (10h). If the Cache Program command (15h) is used
instead, status bit (I/O5) must be polled to find out when the last programming is actually finished before starting
other operat ions such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of the previous
page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true Ready
(returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is
checked. See figure 16 for more details.
NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program.
However, if the previous program cycle with the cache data has not finished, the actual program cycle of the
last page is initiated only after completion of the previous cycle, which can be expressed as the following
formula.
tPROG= Program time for the last page+ Progra m time for the ( last -1 )th page -
(Program command cycle time + Last page data loading time)
The value for A30 from second to the last page address must be same as the value given to A30 in first address.
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
3.9 Cache Read
Cache read ope ra tion allow s automatic dow nload of con secutiv e pages, up to the whole device. Immediately after 1st
latency end, while user can start reading out data, device internally starts reading following page.
Start address of 1st page is at page start (A<10:0>=00h), after 1st latency time (tr) , automatic data download will
be uninterrupted. In fact latency time is 25us, while download of a page require at least 100us for x8 device.
Cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache
read) user can check operation status using :
- R/B ( ‘0’ means latency ongoing, download not possible, ‘1’ means download of n page possible, even if device
internally is active on n+1 page
- Status register (SR<6> behave like R/B, SR<5> is ‘0’ when device is internally reading and ‘1’ when device is idle)
To exit cache read operation a cache read exit command (34h) must be issued. this command can be given any time
(both device idle and reading).
If device is active (SR<5>=0) it will go idle within 5us, while if it is not active, device itself will go busy for a time
shorter then tRBSY before becoming again idle and ready to accept any further commands.
If user arrives reading last byte/word of the memory array, then has to stop by giving a cache read exit command.
Random data output is not available in cache read.
Cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks.
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
4. OTHER FEATURES
4.1 Data Protection & Power on/off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal
voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is
recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is required
before internal circuit gets ready for any comma nd sequences as shown in Figure 25. The two -step command
sequence for program/erase provides additional software protection.
4.2 Ready/Busy.
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,
copy-back, cache progr am and random read completion. The R/B pin is normally high and goes to low when the device
is busy (after a reset, read, pr og ram, erase oper at ion). It re turns to high when the internal controller has finished the
operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up
resistor value is related to tr(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with
the following reference chart (Fig 26). Its value can be determined by the following guidance.
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Parameter Symbol Min Typ Max Unit
Valid Block Number NVB 32128 32768 Blocks
Table 6: Valid Blocks Number
NOTE:
1. The 1st block is guaranteed to be a va lid block up to 1K cycles with ECC. (1bit/512bytes)
Symbol Parameter Value Unit
TA
Ambient Operating Temperature (Commercial Temperature Range) 0 to 70 ℃
Ambient Operating Temperature (Extended Temperature Range) -25 to 85 ℃
Ambient Operating Temperature (Industry Temperature Range) -40 to 85 ℃
TBIAS Temperature Under Bias -50 to 125 ℃
TSTG Storage Temperature -65 to 150 ℃
VIO(2) Input or Output Voltage -0.6 to 4.6 V
Vcc Supply Voltage -0.6 to 4.6 V
Table 7: Absolute maximum ratings
NOTE:
1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute
Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of
the device at these or any other conditions abov e those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
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3$*(%8))(5
;
'
(
&
2
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(
5
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&(
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&/(
$/(
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Figure 3: Block Diagram
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Parameter Symbol Test Conditions Min Typ Max Unit
Operating
Current
Sequential
Read ICC1 tRC=30ns
CE=VIL, IOUT=0mA -2535mA
Program ICC2 - - 25 35 mA
Erase ICC3 - - 25 35 mA
Stand-by Current (TTL) ICC4 CE=VIH,
WP=0V/Vcc -3mA
Stand-by Current (CMOS) ICC5 CE=Vcc-0.2,
WP=0V/Vcc - 80 400 uA
Input Leakage Current ILI VIN=0 to Vcc (max) - - ±80 uA
Output Leakage Current ILO VOUT =0 to Vcc (max) - - ±80 uA
Input High Voltage VIH - Vccx0.8 - Vcc+0.3 V
Input Low Voltage VIL - -0.3 - Vccx0.2 V
Output High Voltage Level VOH IOH=-400uA 2.4 - - V
Output Low Vol t age Level VOL IOL=2.1mA - - 0.4 V
Output Low Current (R/B)IOL
(R/B)VOL=0.4V 8 10 - mA
Table 8: DC and Operating Characteristics
Parameter Value
Input Pulse Levels 0V to Vcc
Input Rise and Fall Times 5ns
Input and Output Timing Levels Vcc/2
Output Load (2.7V - 3.6V) 1 TTL GATE and CL=30pF
Table 9: AC Conditions
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Parameter Symbol Min Typ Max Unit
Program Time tPROG - 200 700 us
Dummy Busy Time for Cache Program tCBSY - 3 700 us
Dummy Busy Time for Cache Read tRBSY -5-us
Number of partial Program Cycles in the same page Main Array NOP - - 4 Cycles
Spare Arra y NOP - - 4 Cycles
Block Erase Time tBERS -23ms
Table 11: Program / Erase Characteristics
Item Symbol Test
Condition Min Max Unit
HY27UK08BGFM-T(P)
Input / Output Capacitance CI/O VIL=0V - 80 pF
Input Capacitance CIN VIN=0V - 80 pF
Table 10: Pin Capacitance (TA=25C, F=1.0MHz)
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Parameter Symbol Min Max Unit
CLE Setup time tCLS 15 ns
CLE Hold time tCLH 5 ns
CE setup time tCS 25 ns
CE hold time tCH 5 ns
WE pulse width tWP 15 ns
ALE setup time tALS 15 ns
ALE hold time tALH 5 ns
Data setup time tDS 15 ns
Data hold time tDH 5 ns
Write Cycle time tWC 30 ns
WE High hold time tWH 10 ns
Address to Data Loading Time tADL(2) 100 ns
Data Transfer from Cell to register tR 25 us
ALE to RE Dela y tAR 15 ns
CLE to RE Delay tCLR 15 ns
Ready to R E Low tRR 20 ns
RE Pulse Width tRP 15 ns
WE High to Busy tWB 100 ns
Read Cycle Time tRC 30 ns
RE Access Time tREA 25 ns
RE High to Output High Z tRHZ 50 ns
CE High to Output High Z tCHZ 50 ns
Cache read RE High tCRRH 100 ns
RE High to Output Hold tRHOH 15 ns
RE Low to Output Hold tRLOH 5 ns
CE High to Output Hold tCOH 15 ns
RE High Hold Time tREH 10 ns
Output High Z to RE low tIR 0 ns
CE Access Time tCEA 30 ns
WE High to RE low tWHR 60 ns
Device Resetting Time
(Read / Program / Copy-Back Program / Erase) tRST 5/10/40/500(1) us
Write Protection time tWW(3) 100 ns
Table 12: AC Timing Characteristics
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
3. Program / Erase Enable Operation : WP high to WE High.
Program / Erase Disable Operation : WP Low to WE High.
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
IO Page
Program Block
Erase Cache
Program Read Cache
Read CODING
0 Pass / Fail Pass / Fail Pass / Fail (N) NA Pass: ‘0’ Fail: ‘1’
1 NA NA Pass / Fail (N-1) NA Pass: ‘0’ Fail: ‘1’
(Only for Cache Progra m,
else Don’t care)
2NA NA NA NA -
3NA NA NA NA -
4NA NA NA NA -
5 Ready/Busy Ready/Busy P/E/R
Controller Bit Ready/Busy P/E/R
Controller Bit Active: ‘0’ Idle: ‘1’
6 Ready/Busy Ready/Busy Cache Register
Free Rea dy/ Bu sy Read y/ Busy Busy: ‘0’ Rea dy’: ‘1’
7 Write Protect Write Protect W rite Protec t Write Protect Protected: ‘0’
Not Protected: ‘1’
Table 13: Status Register Coding
DEVICE IDENTIFIER CYCLE DESCRIPTION
1st Manufacturer Code
2nd Device Identifier
3rd Internal chip number, cell Type, Number of Simultaneously Programmed pages.
4th Page Size, Block Size, Spare Size, Organization
Table 14: Device Identifier Coding
Part Number Voltage Bus Width 1st cycle
(Manufacture Code) 2nd cycle
(Device Code) 3rd Cycle 4th Cycle
HY27UK08BGFM 3.3V x8 ADh D3h C1h 95h
Table 15: Read ID Data Table
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Description IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
Internal Chip Number
1
2
4
8
0 0
0 1
1 0
1 1
Cell Type
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
0 0
0 1
1 0
1 1
Number of
Simultaneously
Programmed Pages
1
2
4
8
0 0
0 1
1 0
1 1
Interle a ve Program
Belween multiple chips Not Support
Support 0
1
Cache Program Not Support
Support 0
1
Table 16. 3rd Byte of Device Identifier Description
Description IO7 IO6 IO5-4 IO3 IO2 IO1-0
Page Size
(Without Spare Area)
1K
2K
Reserved
Reserved
0 0
0 1
1 0
1 1
Spare Area Size
(Byte / 512Byte) 8
16 0
1
Serial Access Time
50ns/30ns
25ns
Reserved
Reserved
0
1
0
1
0
0
1
1
Block Size
(Without Spare Area)
64K
128K
256K
Reserved
0 0
0 1
1 0
1 1
Organization X8
X16 0
1
Table 17: 4th Byte of Device Identifier Description
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Figure 4: Command Latch Cycle
W&/
6
W&6
W:3
&RPPDQG
&/(
&(
:(
$/(
,2[
W'+W'6
W$/6 W$/+
W&/+
W&+
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
1&
1&
1&
1&
1&
5%
5%
5(
&(
&(
1&
9FF
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&RO$GG
W$/+ W$/+ W$/+ W$/+
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Figure 5: Address Latch Cycle
Figure 6: In put Data Latch Cycle
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&(
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:(
1RWHV',1ILQDOPHDQV
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Figure 7: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L)
W5&
&(
5(
,2[
5%
W5($
W55
'RXW 'RXW 'RXW
1RWHV7UDQVLWLRQLVPHDVXUHGP9IURPVWHDG\VWDWHYROWDJHZLWKORDG
7KLVSDUDPHWHULVVDPSOHGDQGQRWWHVWHGW&+=W5+=
W5/2+LVYDOLGZKHQIUHTXHQF\LVKLJKHUWKDQ0+]
W5+2+VWDUWVWREHYDOLGZKHQIUHTXHQF\LVORZHUWKDQ0+]
W5($
W5+= W5+=
W5($
W&+=
W&2+
W5+2+
W5(+
W5&
W53 W5(+
W5($
W&($ W5/2+
W55
W5($
W&+=
W&2+
W5+=
W5+2+
'RXW'RXW
&(
5(
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5%
1RWHV7UDQVLWLRQLVPHDVXUHGP9IURPVWHDG\VWDWHYROWDJHZLWKORDG
7KLVSDUDPHWHULVVDPSOHGDQGQRWWHVWHGW&+=W5+=
W5/2+LVYDOLGZKHQIUHTXHQF\LVKLJKHUWKDQ0+]
W5+2+VWDUWVWREHYDOLGZKHQIUHTXHQF\LVORZHUWKDQ0+]
Figure 8: Sequential Out Cycle after Read (EDO Type CLE=L, WE=H, ALE=L)
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Figure 9: Status Read Cycle
W&/6
W&/5
W&/+
W&6
W&+
W:3
W:+5
W&($
W'6 W5($
W&+=
W&2+
W5+=
W5+2+
KRU%K 6WDWXV2XWSXW
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&(
:(
,2
[
&/(
5(
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55
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&RO$GG 5RZ$GG 5RZ$GG
%XV\
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W
:%
W
$5
W
5
W
5&
W
5+=
5RZ$GG
Figure 10: Read1 Operation (Read One Page)
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
W:%
W$5
W&+=
W&2+
W5&
W5
W55
%XV\
K K 'RXW
1'RXW
1 'RXW
1
&RO
$GG &RO
$GG 5RZ
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5(
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Figure 11: Read1 Operation intercepted by CE
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
&/(
$/(
&(
5(
5%
,2[
:(
W&/5
K
&ROXPQ$GGUHVV 5RZ$GGUHVV
%XV\
K K (K
'RXW1 'RXW0
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&RO$GG 5RZ$GG 5RZ$GG 5RZ$GG
&RO$GG
&ROXPQ$GGUHVV
&RO$GG &RO$GG
W5 W5&
W:%
W$5
W55
W:+5
W5($
W5+:
Figure 12 : Random Data output
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Figure 13: Page Program Operation
&/(
$/(
&(
5(
5%
,2[
:(
W:&
K &RO
$GG
6HULDO'DWD
,QSXW&RPPDQG &ROXPQ$GGUHVV 5RZ$GGUHVV 5HDG6WDWXV
&RPPDQG
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,2R 6XFFHVVIXO3URJUDP
,2R (UURULQ3URJUDP
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&RO
$GG 5RZ
$GG 5RZ
$GG 5RZ
$GG 'LQ
1'LQ
0K K ,2R
W:&
W:% W352*
W:&
W$'/
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
&/(
$/(
&(
5(
5%
,2[
:(
W:&
K 'LQ
1'LQ
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.
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,QSXW&RPPDQG
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&RPPDQG
5HDG6WDWXV
&RPPDQG
W:&
W$'/ W$'/
Figure 14: Random Data In
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
%XV\
W:%
W:%
W$'/
W352*
W:&
&/(
&(
:(
5(
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5%
$/(
&ROXPQ$GGUHVV
K K K 'DWD 'DWD1 K ,2[%KK
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$GG 5RZ
$GG 5RZ
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$GG &RO
$GG 5RZ
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$GG
5RZ$GGUHVV &ROXPQ$GGUHVV 5RZ$GGUHVV
W5
%XV\
&RS\%DFN'DWD
,QSXW&RPPDQG
Figure 15: Copy Back Program
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
&/(
$/(
&(
5(
5%
,2[
:(
5%
,2[
([&DFKH3URJUDP
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'DWD,QSXW $GGUHVV
'DWD,QSXW
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W:% W352*
W:% W&%6<
Figure 16: Cache Program
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
K $GG $GG $GG $GG $GG K ' '' '' '' '
W&55+
5HDGVWSDJH 5HDGQGSDJH
' '
&/(
$/(
,2;
5%
5(
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Figure 17 : Cache Read RE high
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
W:&
&/(
&(
:(
$/(
5(
,2[
5%
W:% W%(56
%86<
K ,2'K
5RZ
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K
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5RZ$GGUHVV
Figure 18: Block Erase Operation (Erase One Block)
K
&/(
&(
:(
$/(
5(
,2[ K
W5($
5HDG,'&RPPDQG $GGUHVVF\FOH 0DNHU&RGH'HYLFH&RGH
$'K
WK&\FOHUG&\FOH
'K &K K
W$5
Figure 19: Read ID Operation
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
'K
'
5HDGVWSDJH
5HDGQGSDJH
5HDGUGSDJH 5HDGWKSDJH
,GOH ,GOH
' ' ' ' ' ' ' ' ' '' '
$GG $GG $GG $GG $GG K
V V V
V
V V V
&/(
$/(
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,QWHUQDORSHUDWLRQ
6WDWXV5HJLVWHU
65!
Figure 20: start address at page start :after 1st latency uninterrupted data flow
'
,GOH ,GOH
VW5%6<
QSDJH
QSDJH
5HDGQSDJH
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UHDG
V
V
,QWHUUXSWHG
5HDG
QSDJH
Figure 21: exit from cache read in 5us when device internally is reading
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
System Interface Using CE don’t care
To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below.
So, it is possible to connect NAND Fl ash to a micro porcess or. The only function that was removed fr om standard NAND
Flash to make CE don’t care read operation was disabling of the automatic sequential read function.
&(GRQ¶WFDUH
K 6WDUW$GG&\FOH 'DWD,QSXW K'DWD,QSXW
&/(
&(
:(
$/(
,2[
Figure 22: Program Operation with CE don’t-care.
,IVHTXHQWLDOURZUHDGHQDEOHG
&(PXVWEHKHOGORZGXULQJW5 &(GRQ¶WFDUH
K K
&/(
&(
5(
$/(
5%
:(
,2[
6WDUW$GG&\FOH 'DWD2XWSXWVHTXHQWLDO
W5
Figure 23: Read Operation with CE don’t-care.
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Figure 24: Reset Operation
))K
W567
:(
$/(
&/(
5(
,2[
5%
:3
:(
9FF
XV
W
97+
Figure 25: Power On and Data Protection Timing
VTH = 2.5 Volt for 3.3 Volt Supply devices
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
5SYDOXHJXLGHQFH
5SPLQ9SDUW
ZKHUH,/LVWKHVXPRIWKHLQSXWFXUUQWVRIDOOGHYLFHVWLHGWRWKH5%SLQ
5SPD[LVGHWHUPLQHGE\PD[LPXPSHUPLVVLEOHOLPLWRIWU
#9FF 97D &&
/
S)
9FF0D[9
2/0D[ 9
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5S LEXV\
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/
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92+
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92/
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9FF
Q P
N N N N
Q P
Q P
*1'
'HYLFH
RSHQGUDLQRXWSXW
5%
Figure 26: Ready/Busy Pin electrical specifications
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Figure 27: page programming within a block
mGGsziGGGtziG
kh{hGpuGaGkGOXP kGO][P
kG
wG]Z
wGZX
wGY
wGX
wGW
O][P
a
OZYP
a
OZP
OYP
OXP
lUPGyGGGOwP
kh{hGpuGaGkGOXP kGO][P
kG
wG]Z
wGZX
wGY
wGX
wGW
O][P
a
OXP
a
OZP
OZYP
OXP
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the
blocks are v alid. A Bad Block does not affect the perf ormance of valid blocks because it is isolated f rom the bit line and
common source line by a select transistor. The devices are supplied with all the locations inside valid blocks
erased(FFh). The Bad Block Inf ormation is writ ten pr ior to shipp ing. An y block whe re th e 1st Byte in the spare ar ea of
the 1st or 2nd page(if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be
read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recog-
nize the Bad Blocks based on the original information it is recom mended to create a Bad Block table following the flow-
chart shown in Figure 28. The 1st block, which is placed on 00h block address is guaranteed to be a valid block.
Bad Replacement
Over the lifetime of the device additional Bad Blocks may deve lop. In this case the block has to be replaced by copying
the data to a va lid block. These additional Bad Blocks can be identified as attempts to progr am or er ase them will give
errors in the Status Register.
As the failure of a page program operation does not aff ect the data in other pages in the same block, the block can be
replaced by re-programming the current data and copying the rest of the replaced block to an available valid block.
The Copy Back Program command can be used to copy the data to a valid block.
See the “Copy Back Program” section for more details.
Refer to Table 18 for the recommended procedure to follow if an error occurs during an operation.
Operation Recommended Procedure
Erase Block Replacement
Program Block Replacement or ECC (with 1bit/512byte)
Read ECC (with 1bit/512byte)
Table 18: Block Failure
<HV
<HV
1R
1R
67$57
%ORFN$GGUHVV
%ORFN
'DWD
))K"
/DVW
EORFN"
(1'
,QFUHPHQW
%ORFN$GGUHVV
8SGDWH
%DG%ORFNWDEOH
Figure 28: Bad Block Management Flowchart
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Write Protect Operation
The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations
are enabled and disabled as follows (Figure 29~32)
::
W
K K
:(
,2[
:3
5%
K K
W::
:(
,2[
:3
5%
Figure 29: Enable Programming
Figure 30: Disable Programming
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
K
W
'K
::
:(
,2[
:3
5%
K
W::
'K
:(
,2[
:3
5%
Figure 31: Enable Erasing
Figure 32: Disable Erasing
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
5. APPENDIX : Extra Features
5.1 Addressing for program operation
Within a block, the pages must be programmed consecutively fr om LSB (least sign ificant bit) page of the block to MSB
(most signif ica nt bit) page of the block. Random address programming is prohibited.
5.2 Stacked Devices Access
A small logic inside the devices allows the possibilit y to stack up to 4 devices in a single pack age without changing the
pinout of the memory. To do this the internal address register can store up to 30 addresses(512Mb yte addressing field)
and basing on the 2 MSB pattern each device inside the package can decide if remain active (1 over 4 ) or “hang up”
the connection entering the Stand-By.
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
Figure 33. 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
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Table 19: 48-TSOP1 - 48-lead Plastic Thin Small Outline,
12 x 20mm, Package Mechanical Data
Symbol millimeters
Min Typ Max
A2.300
A1 0.050 0.150
B 0.170 0.250
C 0.100 0.200
CP 0.100
D 11.910 12.000 12.120
E 19.900 20.000 20.100
E1 18.300 18.400 18.500
e 0.500
L 0.500 0.680
alpha 0 5
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
MARKING INFORMATION - TSOP1
Packag M arking Exam ple
TSOP1
K O R
H Y 2 7 U K 0 8 B G F M
x x x x Y W W x x
- hynix
- K O R
- H Y27UK08BG FM xxxx
HY : HYNIX
2 7 : NAND Flash
U : Power Supply
K : Classification
0 8 : B it O rg a niza tio n
B G: Density
F : Mode
M: Version
x : Package Type
x : Package Material
x : Operating Tem perature
x : Bad Block
- Y : Year (ex: 5= year 2005, 06= year 2006)
- ww: Work W eek (ex: 12= work w eek 12)
- x x: Process C ode
Note
- C ap ita l L ette r
- Sma ll L e tt e r
: H yn ix Symbol
: O rigin Country
: U (2.7V ~ 3.6V )
: S in g le L e v el Ce ll+D S P +L a rg e B lo c k
: 08(x8)
: 32G bit
: F (4nC E & 4R/nB; Sequential Row Read D isable)
: 1 st G en eration
: T(4 8-T SO P 1)
: Blank(Norm al), P(Lead Free)
: C (0℃~70℃), E(-25 ℃~85℃)
M(-30℃~85℃), I(-40 ℃~85℃)
: B(Included Bad Block), S(1~ 5 Bad Block),
P (A ll G o o d B lo ck )
: Fixed Item
: N on-fixed Item
: Pa rt N umber
