®
INA111
1
©1992 Burr-Brown Corporation PDS-1143E Printed in U.S.A. March, 1998
INA111
A
1
A
2
A
3
(12)
(11)
6
(10)
10kΩ10kΩ
25kΩ
25kΩ
10kΩ10kΩ
(13)7
(7)4
(5)
3
(15)
8
(2)
1
(4)
2
V
IN
V
IN
R
G
V+
V–
INA111
DIP (SOIC)
Ref
Feedback
V
O
G = 1 + 50kΩ
R
G
–
+5
DIP Connected
Internally
High Speed FET-Input
INSTRUMENTATION AMPLIFIER
FEATURES
●FET INPUT: IB = 20pA max
●HIGH SPEED: TS = 4µs (G = 100, 0.01%)
●LOW OFFSET VOLTAGE: 500µV max
●LOW OFFSET VOLTAGE DRIFT:
5µV/°C max
●HIGH COMMON-MODE REJECTION:
106dB min
●8-PIN PLASTIC DIP, SOL-16 SOIC
APPLICATIONS
●MEDICAL INSTRUMENTATION
●DATA ACQUISITION
DESCRIPTION
The INA111 is a high speed, FET-input instrumenta-
tion amplifier offering excellent performance.
The INA111 uses a current-feedback topology provid-
ing extended bandwidth (2MHz at G = 10) and fast
settling time (4µs to 0.01% at G = 100). A single
external resistor sets any gain from 1 to over 1000.
Offset voltage and drift are laser trimmed for excellent
DC accuracy. The INA111’s FET inputs reduce input
bias current to under 20pA, simplifying input filtering
and limiting circuitry.
The INA111 is available in 8-pin plastic DIP, and
SOL-16 surface-mount packages, specified for the
–40°C to +85°C temperature range.
®
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
INA111
INA111
SBOS015
®
INA111 2
SPECIFICATIONS
ELECTRICAL
At TA = +25°C, VS = ±15V, RL = 2kΩ, unless otherwise noted.
✻ Specification same as INA111BP.
NOTE: (1) Temperature coefficient of the “50kΩ” term in the gain equation.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
INA111BP, BU INA111AP, AU
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
INPUT
Offset Voltage, RTI
Initial TA = +25°C±100 ± 500/G ±500 ± 2000/G ±200 ± 500/G ±1000 ± 5000/G µV
vs Temperature TA = TMIN to TMAX ±2 ± 10/G ±5 ± 100/G ±2 ± 20/G ±10 ± 100/G µV/°C
vs Power Supply VS = ±6V to ±18V 2 +10/G 30 + 100/G ✻✻µV/V
Impedance, Differential 1012 || 6 ✻Ω || pF
Common-Mode 1012 || 3 ✻Ω || pF
Input Common-Mode Range VDIFF = 0V ±10 ±12 ✻✻ V
Common-Mode Rejection VCM = ±10V, ∆RS = 1kΩ
G = 1 80 90 75 ✻dB
G = 10 96 110 90 ✻dB
G = 100 106 115 100 ✻dB
G = 1000 106 115 100 ✻dB
BIAS CURRENT ±2±20 ✻✻pA
OFFSET CURRENT ±0.1 ±10 ✻✻pA
NOISE VOLTAGE, RTI G = 1000, RS = 0Ω
f = 100Hz 13 ✻nV/√Hz
f = 1kHz 10 ✻nV/√Hz
f = 10kHz 10 ✻nV/√Hz
fB = 0.1Hz to 10Hz 1 ✻µVp-p
Noise Current
f = 10kHz 0.8 ✻fA/√Hz
GAIN
Gain Equation 1 + (50kΩ/RG)✻V/V
Range of Gain 1 10000 ✻✻V/V
Gain Error G = 1, RL = 10kΩ±0.01 ±0.02 ✻0.05 %
G = 10, RL = 10kΩ±0.1 ±0.5 ✻✻%
G = 100, RL = 10kΩ±0.15 ±0.5 ✻±0.7 %
G = 1000, RL = 10kΩ±0.25 ±1✻±2%
Gain vs Temperature G = 1 ±1±10 ✻✻ppm/°C
50kΩ Resistance(1) ±25 ±100 ✻✻ppm/°C
Nonlinearity G = 1 ±0.0005 ±0.005 ✻✻% of FSR
G = 10 ±0.001 ±0.005 ✻±0.01 % of FSR
G = 100 ±0.001 ±0.005 ✻±0.01 % of FSR
G = 1000 ±0.005 ±0.02 ✻±0.04 % of FSR
OUTPUT
Voltage IO = 5mA, TMIN to TMAX ±11 ±12.7 ✻✻ V
Load Capacitance Stability 1000 ✻pF
Short Circuit Current +30/–25 ✻mA
FREQUENCY RESPONSE
Bandwidth, –3dB G = 1 2 ✻MHz
G = 10 2 ✻MHz
G = 100 450 ✻kHz
G = 1000 50 ✻kHz
Slew Rate VO = ±10V, G = 2 to 100 17 ✻V/µs
Settling Time, 0.01% G = 1 2 ✻µs
G = 10 2 ✻µs
G = 100 4 ✻µs
G = 1000 30 ✻µs
Overload Recovery 50% Overdrive 1 ✻µs
POWER SUPPLY
Voltage Range ±6±15 ±18 ✻✻ ✻ V
Current VIN = 0V ±3.3 ±4.5 ✻✻mA
TEMPERATURE RANGE
Specification –40 85 ✻✻°C
Operating –40 125 ✻✻°C
θ
JA 100 ✻°C/W
®
INA111
3
PIN CONFIGURATIONS ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap-
propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
Top View DIP
Top View SOL-16 Surface Mount
NC
R
G
NC
V
–IN
V
+IN
NC
V–
NC
NC
R
G
NC
V+
Feedback
V
O
Ref
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RG
V–IN
V+IN
V–
RG
V+
VO
Ref
1
2
3
4
8
7
6
5
ORDERING INFORMATION
PRODUCT PACKAGE TEMPERATURE RANGE
INA111AP 8-Pin Plastic DIP –40°C to +85°C
INA111BP 8-Pin Plastic DIP –40°C to +85°C
INA111AU SOL-16 Surface-Mount –40°C to +85°C
INA111BU SOL-16 Surface-Mount –40°C to +85°C
Supply Voltage .................................................................................. ±18V
Input Voltage Range.......................................... (V–) –0.7V to (V+) +15V
Output Short-Circuit (to ground) .............................................. Continuous
Operating Temperature ................................................. –40°C to +125°C
Storage Temperature..................................................... –40°C to +125°C
Junction Temperature.................................................................... +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: Stresses above these ratings may cause permanent damage.
ABSOLUTE MAXIMUM RATINGS(1)
PACKAGE INFORMATION
PACKAGE DRAWING
PRODUCT PACKAGE NUMBER(1)
INA111AP 8-Pin Plastic DIP 006
INA111BP 8-Pin Plastic DIP 006
INA111AU 16-Pin Surface Mount 211
INA111BU 16-Pin Surface Mount 211
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
®
INA111 4
SETTLING TIME vs GAIN
100
10
11 10 100 1000
Gain (V/V)
Settling Time (µs)
0.01%
0.1%
POWER SUPPLY REJECTION vs FREQUENCY
Frequency (Hz)
Power Supply Rejection (dB)
120
100
80
60
40
20
010 100 1k 10k 100k 1M
G = 1k
G = 100
G = 10
G = 1
INPUT COMMON-MODE VOLTAGE RANGE
vs OUTPUT VOLTAGE
Output Voltage (V)
Common-Mode Voltage (V)
–15 –10 0 5 15–5
15
10
5
0
–5
–10
–15 10
Limited by A1
+ Output Swing
A3 – Output
Swing Limit A3 + Output
Swing Limit
Limited by A
2
– Output Swing
Limited by A
1
– Output Swing
Limited by A
2
+ Output Swing
VD/2
–
+
–
+
V
CM
V
O
(Any Gain)
VD/2
COMMON-MODE REJECTION vs FREQUENCY
Frequency (Hz)
Common-Mode Rejection (dB)
120
100
80
60
40
20
010 100 1k 10k 100k 1M
G = 1k
G = 100
G = 10
G = 1
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±15V, unless otherwise noted.
GAIN vs FREQUENCY
Gain (V/V)
Frequency (Hz)
10k
1k
100
10
1
0.1 1k 10k 100k 1M 10M
G = 1k
G = 100
G = 10
G = 1
INPUT-REFERRED NOISE VOLTAGE vs FREQUENCY
Frequency (Hz)
1k
100
10
11 10 100 1k 10k
Input-Referred Noise Voltage (nV/√Hz)
G = 1
G = 10
G = 100, 1k
®
INA111
5
OUTPUT CURRENT LIMIT vs TEMPERATURE
50
40
30
20
10
0–75 –50 –25 0 25 50 75 100 125
Temperature (°C)
Short-Circuit Current (mA)
–I
CL
+I
CL
MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY
30
25
20
15
10
5
01k 10k 100k 1M 10M
Frequency (Hz)
Peak-to-Peak Amplitude (V)
–15.7V
+15.7V
INPUT BIAS CURRENT
vs COMMON-MODE INPUT VOLTAGE
Common-Mode Voltage (V)
–10m
–1m
–100µ
–10µ
+1p
+10p
Input Bias Current (A)
–20 –15 –10 –5 0 5 10 15 20
G = 100G = 10 G = 1kG = 1
G = 1
G = 100
G = 10
G = 1k +15.7V
–15.7V
INPUT BIAS CURRENT
vs DIFFERENTIAL INPUT VOLTAGE
–10m
–1m
–100µ
–10µ
+1p
+10p
+100p–20 –15 –10 –5 0 5 10 15 20
Differential Overload Voltage (V)
NOTE: One input grounded.
Input Bias Current (A)
OFFSET VOLTAGE WARM-UP vs TIME
75
50
25
0
–25
–50
–75
G = 1
Referred-to-Input V
OS
Change (µV)
300
200
100
0
–100
–200
–300
Referred-to-Input V
OS
Change (µV)
Time From Power Supply Turn-On (Minutes)
012345
G ≥ 10
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
INPUT BIAS CURRENT vs TEMPERATURE
10n
1n
100p
10p
1p
0.1p
0.01p
Input Bias Current (A)
–75 –50 –25 0 25 50 75 100 125
Temperature (°C)
I
OS
I
b
®
INA111 6
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
Frequency (Hz)
1
0.1
0.01
0.001
0.0001
THD + N (%)
20 100 1k 10k 20k
Single-Ended Drive G = 1
Differential Drive G = 1
G = 1k
G = 100
G = 10
V
O
= 3Vrms, R
L
= 2kΩ
Measurement BW = 80kHz
QUIESCENT CURRENT vs TEMPERATURE
3.5
3.4
3.3
3.2
3.1
3.0–75 –50 –25 0 25 50 75 100 125
Temperature (°C)
Quiescent Current (mA)
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
+10
–10
0
10 200 Time (µs)
+10
–10
10 200 Time (µs)
0
+0.1
–0.1
0
+0.1
–0.1
0
10 200 Time (µs)
10 200 Time (µs)
SMALL SIGNAL RESPONSE, G = 1
LARGE SIGNAL RESPONSE, G = 100
SMALL SIGNAL RESPONSE, G = 1LARGE SIGNAL RESPONSE, G = 100
®
INA111
7
APPLICATION INFORMATION
Figure 1 shows the basic connections required for operation
of the INA111. Applications with noisy or high impedance
power supplies may require decoupling capacitors close to
the device pins as shown.
The output is referred to the output reference (Ref) terminal
which is normally grounded. This must be a low-impedance
connection to assure good common-mode rejection. A resis-
tance of 2Ω in series with the Ref pin will cause a typical
device with 90dB CMR to degrade to approximately 80dB
CMR (G = 1).
SETTING THE GAIN
Gain of the INA111 is set by connecting a single external
resistor, RG:
Commonly used gains and resistor values are shown in
Figure 1.
The 50kΩ term in equation 1 comes from the sum of the two
internal feedback resistors. These are on-chip metal film
resistors which are laser trimmed to accurate absolute val-
ues. The accuracy and temperature coefficient of these
resistors are included in the gain accuracy and drift specifi-
cations of the INA111.
The stability and temperature drift of the external gain
setting resistor, RG, also affects gain. RG’s contribution to
gain accuracy and drift can be directly inferred from the gain
equation (1). Low resistor values required for high gain can
make wiring resistance important. Sockets add to the wiring
resistance, which will contribute additional gain error (pos-
sibly an unstable gain error) in gains of approximately 100
or greater.
DYNAMIC PERFORMANCE
The typical performance curve “Gain vs Frequency” shows
that the INA111 achieves wide bandwidth over a wide range
of gain. This is due to the current-feedback topology of the
INA111. Settling time also remains excellent over wide
gains.
FIGURE 1. Basic Connections
DESIRED RGNEAREST 1% RG
GAIN (Ω)(Ω)
1 No Connection No Connection
2 50.00k 49.9k
5 12.50k 12.4k
10 5.556k 5.62k
20 2.632k 2.61k
50 1.02k 1.02k
100 505.1 511
200 251.3 249
500 100.2 100
1000 50.05 49.9
2000 25.01 24.9
5000 10.00 10
10000 5.001 4.99
G=1+50kΩ
R
G
(1)
A
1
A
2
A
3
6
10kΩ10kΩ
10kΩ10kΩ
7
4
3
8
1
2
V
IN
V
IN
R
G
V+
V–
INA111
G = 1 + 50kΩ
R
G
–
+5
25kΩ
25kΩLoad
V
O
= G • (V
IN
– V
IN
)
+–
0.1µF
0.1µF
Pin numbers are
for DIP package.
+
–
V
O
INA111
R
G
Also drawn in simplified form:
V
O
Ref
V
IN
–
V
IN
+
Ref
®
INA111 8
The INA111 exhibits approximately 6dB rise in gain at
2MHz in unity gain. This is a result of its current-feedback
topology and is not an indication of instability. Unlike an op
amp with poor phase margin, the rise in response is a
predictable +6dB/octave due to a response zero. A simple
pole at 700kHz or lower will produce a flat passband
response (see Input Filtering).
The INA111 provides excellent rejection of high frequency
common-mode signals. The typical performance curve,
“Common-Mode Rejection vs Frequency” shows this be-
havior. If the inputs are not properly balanced, however,
common-mode signals can be converted to differential sig-
nals. Run the VIN and VIN connections directly adjacent each
other, from the source signal all the way to the input pins. If
possible use a ground plane under both input traces. Avoid
running other potentially noisy lines near the inputs.
NOISE AND ACCURACY PERFORMANCE
The INA111’s FET input circuitry provides low input bias
current and high speed. It achieves lower noise and higher
accuracy with high impedance sources. With source imped-
ances of 2kΩ to 50kΩ the INA114 may provide lower offset
voltage and drift. For very low source impedance (≤1kΩ),
the INA103 may provide improved accuracy and lower
noise.
OFFSET TRIMMING
The INA111 is laser trimmed for low offset voltage and
drift. Most applications require no external offset adjust-
ment. Figure 2 shows an optional circuit for trimming the
output offset voltage. The voltage applied to Ref terminal is
summed at the output. Low impedance must be maintained
at this node to assure good common-mode rejection. The op
amp shown maintains low output impedance at high fre-
quency. Trim circuits with higher source impedance should
be buffered with an op amp follower circuit to assure low
impedance on the Ref pin.
INPUT BIAS CURRENT RETURN PATH
The input impedance of the INA111 is extremely high—
approximately 1012Ω. However, a path must be provided for
the input bias current of both inputs. This input bias current
is typically less than 10pA. High input impedance means
that this input bias current changes very little with varying
input voltage.
Input circuitry must provide a path for this input bias current
if the INA111 is to operate properly. Figure 3 shows various
provisions for an input bias current path. Without a bias
current return path, the inputs will float to a potential which
exceeds the common-mode range of the INA111 and the
input amplifiers will saturate.
If the differential source resistance is low, the bias current
return path can be connected to one input (see the thermo-
couple example in Figure 3). With higher source impedance,
using two resistors provides a balanced input with possible
advantages of lower input offset voltage due to bias current
and better high-frequency common-mode rejection.
INA111
1MΩ1MΩ
INA111
10kΩ
Thermocouple
INA111
Center-tap provides
bias current return.
Crystal or
Ceramic
Transducer
FIGURE 3. Providing an Input Common-Mode Current Path.
FIGURE 2. Optional Trimming of Output Offset Voltage.
INPUT COMMON-MODE RANGE
The linear common-mode range of the input op amps of the
INA111 is approximately ±12V (or 3V from the power
supplies). As the output voltage increases, however, the
linear input range will be limited by the output voltage swing
of the input amplifiers, A1 and A2. The common-mode range
is related to the output voltage of the complete amplifier—
see performance curve “Input Common-Mode Range vs
Output Voltage”.
INA111
V
IN
V
IN
R
G
–
+
10kΩ
(1)
V
O
OPA177
Ref
±10mV
Adjustment Range
100Ω
(1)
100Ω
(1)
100µA
1/2 REF200
100µA
1/2 REF200
V+
V–
NOTE: (1) For wider trim range required
in high gains, scale resistor values larger
+–
®
INA111
9
A combination of common-mode and differential input
voltage can cause the output of A1 or A2 to saturate. Figure
4 shows the output voltage swing of A1 and A2 expressed in
terms of a common-mode and differential input voltages.
For applications where input common-mode range must be
maximized, limit the output voltage swing by connecting the
INA111 in a lower gain (see performance curve “Input
Common-Mode Voltage Range vs Output Voltage”). If
necessary, add gain after the INA111 to increase the voltage
swing.
Input-overload often produces an output voltage that appears
normal. For example, consider an input voltage of +14V on
one input and +15V on the other input will obviously exceed
the linear common-mode range of both input amplifiers.
Since both input amplifiers are saturated to the nearly the
same output voltage limit, the difference voltage measured
by the output amplifier will be near zero. The output of the
INA111 will be near 0V even though both inputs are
overloaded.
INPUT PROTECTION
Inputs of the INA111 are protected for input voltages from
0.7V below the negative supply to 15V above the positive
power supply voltages. If the input current is limited to less
than 1mA, clamp diodes are not required; internal junctions
will clamp the input voltage to safe levels. If the input source
can supply more than 1mA, use external clamp diodes as
shown in Figure 5. The source current can be limited with
series resistors R1 and R2 as shown. Resistor values greater
than 10kΩ will contribute noise to the circuit.
A diode formed with a 2N4117A transistor as shown in
Figure 5 assures low leakage. Common signal diodes such as
the 1N4148 may have leakage currents far greater than the
input bias current of the INA111 and are usually sensitive to
light.
INPUT FILTERING
The INA111’s FET input allows use of an R/C input filter
without creating large offsets due to input bias current.
Figure 6 shows proper implementation of this input filter to
preserve the INA111’s excellent high frequency common-
mode rejection. Mismatch of the common-mode input ca-
pacitance (C1 and C2), either from stray capacitance or
FIGURE 5. Input Protection Voltage Clamp.
FIGURE 4. Voltage Swing of A1 and A2.
INA111 V
O
V+
V+
V
IN
–
V
IN
+
D
1
D
3
D
2
D
4
Diodes: =2N4117A
1pA Leakage
R
G
R
1
R
2
A
1
A
2
A
3
10kΩ10kΩ
10kΩ10kΩ
R
G
V+
V–
INA111
V
O
= G • V
D
G = 1 + 50kΩ
R
G
25kΩ
25kΩ
V
CM
– G • V
D
2
V
D
2
V
D
2
V
CM
V
CM
+ G • V
D
2
®
INA111 10
FIGURE 7. Bridge Transducer Amplifier.
mismatched values, causes a high frequency common-mode
signal to be converted to a differential signal. This degrades
common-mode rejection. The differential input capacitor,
C3, reduces the bandwidth and mitigates the effects of
mismatch in C1 and C2. Make C3 much larger than C1 and
C2. If properly matched, C1 and C2 also improve CMR.
OUTPUT VOLTAGE SENSE
(SOL-16 Package Only)
The surface-mount version of the INA111 has a separate
output sense feedback connection (pin 12). Pin 12 must be
connected, usually to the output terminal, pin 11, for proper
operation. (This connection is made internally on the DIP
version of the INA111.)
The output feedback connection can be used to sense the
output voltage directly at the load for best accuracy. Figure 8
shows how to drive a load through series interconnection
resistance. Remotely located feedback paths may cause
instability. This can be generally be eliminated with a high
frequency feedback path through C1.
FIGURE 6. Input Low-Pass Filter.
FIGURE 8. Remote Load and Ground Sensing.
INA111
R
G
100ΩV
O
+10V
Bridge G = 500
Ref
INA111 V
O
V
IN
–
V
IN
+
R
1
R
2
C
3
C
1
C
2
R
1
= R
2
C
1
= C
2
C
3
≈ 10C
1
Ref
INA111
R
G
V
IN
–
V
IN
+
Load
Equal resistance here preserves
g
ood common-mode re
j
ection.
C
1
1000pF
Feedback
Ref
Surface-mount package
version only.
FIGURE 9. High-Pass Input Filter.
INA111
C
1
C
2
R
1
R
2
V
O
2πR
1
C
1
1
f
c
=
NOTE: To preserve good low frequency CMR,
make R
1
= R
2
and C
1
= C
2
.
R
G
Ref
f
−3dB
=1
4πR
1
C
3
+C
1
2
FIGURE 10. Galvanically Isolated Instrumentation
Amplifier.
INA111 ISO122
±6V to ±18V
Isolated Power
±15V
Ref
V
IN
–
V
IN
+
V
O
Isolated
Common
V+ V–
®
INA111
11
FIGURE 12. Voltage Controlled Current Source.FIGURE 11. AC-Coupled Instrumentation Amplifier.
FIGURE 13. Shield Driver Circuit.
FIGURE 14. Multiplexed-Input Data Acquisition System.
INA111
R
G
V
O
C
1
0.1µF
OPA602
Ref R
1
1MΩ
f
–3dB
= 1
2πR
1
C
1
= 1.59Hz
V
IN
+
–
INA111
V
IN
+
–
V
IN
+
–
Channel 8
Channel 1
MPC800
MUX ADS574
+5V
12 Bits
Out
R
G
Ref
INA111
OPA177
C1
50nF
RGR2
RG
Make G ≤ 10 where G = 1 + 50k Load
VIN
G • R2
IL =
R1
10kΩ
VIN
Ref
INA111
V
IN
–
V
IN
+
OPA602
511Ω
22.1kΩ
22.1kΩ
Ref
V
O
For G = 100
R
G
= 511Ω // 2(22.1kΩ)
effective R
G
= 505Ω
100Ω
NOTE: Driving the shield minimizes CMR degradation
due to unequally distributed capacitance on the input
line. The shield is driven at approximately 1V below
the common-mode input voltage.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Jan-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
INA111AP ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Contact TI Distributor
or Sales Office
INA111APG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Contact TI Distributor
or Sales Office
INA111AU ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Contact TI Distributor
or Sales Office
INA111AU/1K ACTIVE SOIC DW 16 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
INA111AU/1KE4 ACTIVE SOIC DW 16 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
INA111AU/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
INA111AUE4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Contact TI Distributor
or Sales Office
INA111BP ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Contact TI Distributor
or Sales Office
INA111BPG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Contact TI Distributor
or Sales Office
INA111BU ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Contact TI Distributor
or Sales Office
INA111BUE4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Contact TI Distributor
or Sales Office
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Jan-2011
Addendum-Page 2
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
INA111AU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
INA111AU/1K SOIC DW 16 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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