SCAS301R - JANUARY 1993 - REVISED MARCH 2005 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK All Ports (5-V Input/Output Voltage With 3.3-V VCC) Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) 1D 2D 3D 4D 5D 6D 7D 8D 20 19 1Q 3 18 2Q 4 17 3Q 16 4Q 15 5Q 5 6 8 14 6Q 13 7Q 9 12 8Q 7 10 11 3D 4D 5D 6D 7D 1Q 1 2 SN54LVC574A . . . FK PACKAGE (TOP VIEW) 2D 1D OE VCC SN74LVC574A . . . RGY PACKAGE (TOP VIEW) VCC OE 1D 2D 3D 4D 5D 6D 7D 8D GND D CLK SN54LVC574A . . . J OR W PACKAGE SN74LVC574A . . . DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW) D OE D D -40C to 125C, and -55C to 125C Max tpd of 7 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25C GND D D D Support Mixed-Mode Signal Operation on 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2Q 3Q 4Q 5Q 6Q 8D GND CLK 8Q 7Q D Operate From 1.65 V to 3.6 V D Inputs Accept Voltages to 5.5 V D Specified From -40C to 85C, description/ordering information The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2005, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ '*%$"# $')!" " 12 !)) '!!&"&# !& "&#"&* %)&## ",&.#& "&*+ !)) ",& '*%$"# '*%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCAS301R - JANUARY 1993 - REVISED MARCH 2005 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE TA QFN - RGY Reel of 1000 SN74LVC574ARGYR VFBGA - GQN -40C -40 C to 85 85C C PDIP - N Reel of 1000 LC574A SN74LVC574AZQNR Tube of 20 SN74LVC574AN Tube of 25 SN74LVC574ADW Reel of 2000 SN74LVC574ADWR SOP - NS Reel of 2000 SN74LVC574ANSR LVC574A SSOP - DB Reel of 2000 SN74LVC574ADBR LC574A Tube of 70 SN74LVC574APW Reel of 2000 SN74LVC574APWR Reel of 250 SN74LVC574APWT TVSOP - DGV Reel of 2000 SN74LVC574ADGVR LC574A CDIP - J Tube of 20 SNJ54LVC574AJ SNJ54LVC574AJ CFP - W Tube of 85 SNJ54LVC574AW SNJ54LVC574AW LCCC - FK Tube of 55 SNJ54LVC574AFK SOIC - DW TSSOP - PW -55C -55 C to 125 125C C LC574A SN74LVC574AGQNR VFBGA - ZQN (Pb-free) -40C -40 C to 125 125C C TOP-SIDE MARKING SN74LVC574AN LVC574A LC574A SNJ54LVC574AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. GQN OR ZQN PACKAGE (TOP VIEW) 1 2 3 terminal assignments 4 1 2 3 4 A A 1D OE 1Q B B 3D 3Q VCC 2D C C 5D 4D 5Q 4Q D D 7D 7Q 6D 6Q E E GND 8D CLK 8Q FUNCTION TABLE (each flip-flop) INPUTS 2 OE CLK D OUTPUT Q L H H L L L L L X Q0 H X X Z POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2Q SCAS301R - JANUARY 1993 - REVISED MARCH 2005 logic diagram (positive logic) OE CLK 1 11 C1 1D 2 19 1Q 1D To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92C/W (see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W (see Note 3): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78C/W (see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Power dissipation, Ptot (TA = -40C to 125C) (see Notes 5 and 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. 5. For the DW package: above 70C the value of Ptot derates linearly with 8 mW/K. 6. For the DB, DGV, N, NS, and PW packages: above 60C the value of Ptot derates linearly with 5.5 mW/K. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SCAS301R - JANUARY 1993 - REVISED MARCH 2005 recommended operating conditions (see Note 7) SN54LVC574A -55 TO 125C MIN MAX 2 3.6 Operating VCC Supply voltage VIH VIL High-level input voltage VI Input voltage Data retention only VO Output voltage IOH High-level output current IOL Low-level output current t/v Input transition rise or fall rate V 1.5 VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V Low-level input voltage UNIT 2 V 0.8 V 0 5.5 V High or low state 0 3-state 0 VCC 5.5 V VCC = 2.7 V VCC = 3 V -12 VCC = 2.7 V 12 VCC = 3 V 24 -24 6 mA mA ns/V NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. recommended operating conditions (see Note 7) SN74LVC574A Operating VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage VO IOH Output voltage High-level output current Data retention only TA = 25C MIN MAX MIN MAX MIN MAX 1.65 1.65 3.6 1.65 3.6 3.6 -40 TO 85C -40 TO 125C V 1.5 1.5 1.5 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 0.65 x VCC 0.65 x VCC 0.65 x VCC 1.7 1.7 1.7 VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V 2 2 2 0.35 x VCC VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0.35 x VCC 0.7 V 0.35 x VCC 0.7 0.8 UNIT 0.7 0.8 V 0.8 0 5.5 0 5.5 0 5.5 V High or low state 0 0 0 VCC 5.5 0 3-state VCC 5.5 VCC 5.5 V 0 0 VCC = 1.65 V VCC = 2.3 V -4 -4 -4 -8 -8 -8 VCC = 2.7 V VCC = 3 V -12 -12 -12 -24 -24 -24 VCC = 1.65 V VCC = 2.3 V 4 4 4 8 8 8 VCC = 2.7 V VCC = 3 V 12 12 12 24 24 24 6 6 6 IOL Low-level output current t/v Input transition rise or fall rate mA mA ns/V NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCAS301R - JANUARY 1993 - REVISED MARCH 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LVC574A PARAMETER TEST CONDITIONS VCC IOH = -100 A VOH 2.7 V to 3.6 V 2.7 V VCC - 0.2 2.2 3V 2.4 3V 2.2 IOH = -12 mA IOH = -24 mA IOL = 100 A -55 TO 125C MIN TYP MAX UNIT V 2.7 V to 3.6 V 0.2 IOL = 12 mA IOL = 24 mA 2.7 V 0.4 3V 0.55 II IOZ VI = 5.5 V or GND VO = 0 to 5.5 V 3.6 V 5 A 3.6 V 15 A ICC VI = VCC or GND 3.6 V VI 5.5 V VOL ICC Ci 10 IO = 0 One input atVCC - 0.6 V, Other inputs at VCC or GND VI = VCC or GND Co VO = VCC or GND TA = 25C This applies in the disabled state only. POST OFFICE BOX 655303 3.6 V 10 2.7 V to 3.6 V 500 V A A A 3.3 V 4 pF 3.3 V 5.5 pF * DALLAS, TEXAS 75265 5 SCAS301R - JANUARY 1993 - REVISED MARCH 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN74LVC574A PARAMETER TEST CONDITIONS IOH = -100 A IOH = -4 mA VOH VCC 1.65 V to 3.6 V IOH = -8 mA IOH = -12 mA IOH = -24 mA IOL = 100 A TA = 25C MIN TYP -40 TO 85C MAX MIN MAX -40 TO 125C MIN 1.65 V VCC - 0.2 1.29 VCC - 0.2 1.2 VCC - 0.2 1.2 2.3 V 1.9 1.7 1.7 2.7 V 2.2 2.2 2.2 3V 2.4 2.4 2.4 3V 2.3 2.2 UNIT MAX V 2.2 1.65 V to 3.6 V 0.1 0.2 0.2 IOL = 4 mA IOL = 8 mA 1.65 V 0.24 0.45 0.45 2.3 V 0.3 0.7 0.7 IOL = 12 mA IOL = 24 mA 2.7 V 0.4 0.4 0.4 3V 0.55 0.55 0.55 II Ioff VI = 5.5 V or GND VI or VO = 5.5 V 3.6 V 1 5 5 A 0 4 10 10 A IOZ VI = 0 to 5.5 V VI = VCC or GND 3.6 V VI 5.5 V 3.6 V A VOL ICC IO = 0 ICC One input at VCC - 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND Co VO = VCC or GND This applies in the disabled state only. 3.6 V 2.7 V to 3.6 V 1 10 10 1.5 10 10 1.5 10 10 500 500 500 V A A A 3.3 V 4 pF 3.3 V 5.5 pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVC574A VCC -55 TO 125C MIN 6 fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time, data before CLK th Hold time, data after CLK POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2.7 V 150 3.3 V 0.3 V 150 2.7 V 3.3 3.3 V 0.3 V 3.3 2.7 V 2 3.3 V 0.3 V 2 2.7 V 2 3.3 V 0.3 V 2 UNIT MAX MHz ns ns ns SCAS301R - JANUARY 1993 - REVISED MARCH 2005 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVC574A PARAMETER FROM (INPUT) TO (OUTPUT) -55 TO 125C VCC MIN fmax 2.7 V 150 3.3 V 0.3 V 150 CLK Q ten OE Q tdis OE Q MHz 8 2.7 V tpd UNIT MAX 3.3 V 0.3 V 1 7 1 7.5 0.5 6.4 ns 9 2.7 V 3.3 V 0.3 V 7 2.7 V 3.3 V 0.3 V ns ns timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC574A VCC fclock tw tsu th Clock frequency Pulse duration, CLK high or low Setup time, data before CLK Hold time, data after CLK TA = 25C MIN TYP MAX -40 TO 85C MIN MAX -40 TO 125C MIN 1.8 V 0.15 V 55 55 40 2.5 V 0.2 V 95 95 80 2.7 V 150 150 150 3.3 V 0.3 V 150 150 150 1.8 V 0.15 V 9 9 2.5 V 0.2 V 4 4 4 2.7 V 3.3 3.3 3.3 3.3 V 0.3 V 3.3 3.3 3.3 6 6 6 2.5 V 0.2 V 4 4 4 2.7 V 2 2 2 3.3 V 0.3 V 2 2 2 1.8 V 0.15 V 4 4 4 2.5 V 0.2 V 2 2 2 2.7 V 1.5 1.5 1.5 3.3 V 0.3 V 1.5 1.5 1.5 * DALLAS, TEXAS 75265 MHz 9 1.8 V 0.15 V POST OFFICE BOX 655303 UNIT MAX ns ns ns 7 SCAS301R - JANUARY 1993 - REVISED MARCH 2005 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC574A PARAMETER FROM (INPUT) TO (OUTPUT) VCC 1.8 V 0.15 V fmax tpd CLK ten OE tdis OE Q Q Q TA = 25C MIN TYP MAX 55 -40 TO 85C MIN MAX 55 MIN UNIT MAX 40 2.5 V 02 V 95 95 80 2.7 V 150 150 150 3.3 V 0.3 V 150 150 150 1.8 V 0.15 V 1.0 7.1 21.5 1 21.6 1.0 21.6 2.5 V 0.2 V 1.0 4.9 10.0 1 10.5 1.0 10.5 2.7 V 1.0 5.0 7.8 1 8 1.0 8.0 3.3 V 0.3 V 2.2 4.6 6.8 2.2 7 2.2 7.0 1.8 V 0.15 V 1.0 6.6 19.0 1 19.5 1.0 19.5 2.5 V 0.2 V 1.0 4.8 10.0 1 10.5 1.0 10.5 2.7 V 1.0 5.5 8.3 1 8.5 1.0 8.5 MHz 3.3 V 0.3 V 1.5 4.4 7.3 1.5 7.5 1.5 7.5 1.8 V 0.15 V 1.0 5.4 18.3 1 18.8 1.0 18.8 2.5 V 0.2 V 1.0 3.0 7.3 1 7.8 1.0 7.8 2.7 V 1.0 4.0 6.8 1 7 1.0 7.3 3.3 V 0.3 V 1.7 3.9 6.2 1.7 6.4 1.7 6.6 3.3 V 0.3 V tsk(o) -40 TO 125C 1 1 ns ns ns ns operating characteristics, TA = 25C TEST CONDITIONS PARAMETER Outputs enabled Cpd Power dissipation capacitance per flip-flop f = 10 MHz Outputs disabled 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 VCC TYP 1.8 V 25 2.5 V 29 3.3 V 30 1.8 V 9 2.5 V 9 3.3 V 11 UNIT pF SCAS301R - JANUARY 1993 - REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 2.7 V 3.3 V 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL V VCC/2 VCC/2 1.5 V 1.5 V 2 x VCC 2 x VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 k 500 500 500 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPLZ tPZL VLOAD/2 VM VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V VOL tPHZ tPZH VOH Output VI Output Control VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SCAS301R - JANUARY 1993 - REVISED MARCH 2005 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9757601Q2A ACTIVE LCCC FK 20 1 TBD 5962-9757601QRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type 1 TBD Call TI N / A for Pkg Type TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type 5962-9757601QSA ACTIVE CFP W 20 SN74LVC574ADBLE OBSOLETE SSOP DB 20 SN74LVC574ADBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574ADGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574ADGVRG4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574ADW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574ADWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574AGQNR NRND GQN 20 1000 TBD SNPB Level-1-240C-UNLIM SN74LVC574AN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74LVC574ANE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74LVC574ANSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574ANSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574APW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574APWLE OBSOLETE TSSOP PW 20 TBD Call TI BGA MI CROSTA R JUNI OR Addendum-Page 1 Call TI PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 Orderable Device Status (1) Package Type Package Drawing SN74LVC574APWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574APWT ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574APWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574APWTG4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC574ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74LVC574ARGYRG4 ACTIVE VQFN RGY 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74LVC574AZQNR ACTIVE ZQN 20 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SNJ54LVC574AFK ACTIVE LCCC FK 20 1 TBD SNJ54LVC574AJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type SNJ54LVC574AW ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type BGA MI CROSTA R JUNI OR Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 OTHER QUALIFIED VERSIONS OF SN54LVC574A, SN74LVC574A : SN74LVC574A-Q1 * Automotive: * Enhanced Product: SN74LVC574A-EP NOTE: Qualified Version Definitions: - Q100 devices qualified for high-reliability automotive applications targeting zero defects * Automotive * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 8.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.5 2.5 12.0 16.0 Q1 SN74LVC574ADBR SSOP DB 20 2000 330.0 16.4 SN74LVC574ADGVR TVSOP DGV 20 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 SN74LVC574ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74LVC574AGQNR BGA MI CROSTA R JUNI OR GQN 20 1000 330.0 12.4 3.3 4.3 1.6 8.0 12.0 Q1 SN74LVC574AGQNR BGA MI CROSTA R JUNI OR GQN 20 1000 330.0 12.4 3.3 4.3 1.5 8.0 12.0 Q1 SN74LVC574ANSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1 SN74LVC574APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LVC574ARGYR VQFN RGY 20 3000 180.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 SN74LVC574AZQNR BGA MI CROSTA R JUNI OR ZQN 20 1000 330.0 12.4 3.3 4.3 1.5 8.0 12.0 Q1 SN74LVC574AZQNR BGA MI CROSTA R JUNI ZQN 20 1000 330.0 12.4 3.3 4.3 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2009 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant OR *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC574ADBR SSOP DB 20 2000 346.0 346.0 33.0 SN74LVC574ADGVR TVSOP DGV 20 2000 346.0 346.0 29.0 SN74LVC574ADWR SOIC DW 20 2000 346.0 346.0 41.0 SN74LVC574AGQNR BGA MICROSTAR JUNIOR GQN 20 1000 340.5 338.1 20.6 SN74LVC574AGQNR BGA MICROSTAR JUNIOR GQN 20 1000 346.0 346.0 29.0 SN74LVC574ANSR SO NS 20 2000 346.0 346.0 41.0 SN74LVC574APWR TSSOP PW 20 2000 346.0 346.0 33.0 SN74LVC574ARGYR VQFN RGY 20 3000 190.5 212.7 31.8 SN74LVC574AZQNR BGA MICROSTAR JUNIOR ZQN 20 1000 346.0 346.0 29.0 SN74LVC574AZQNR BGA MICROSTAR JUNIOR ZQN 20 1000 340.5 338.1 20.6 Pack Materials-Page 2 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MLCC006B - OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MPDS006C - FEBRUARY 1996 - REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0-8 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. 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